Name		Name	Last commit message	Last commit date
parent directory ..
Makefile		Makefile
blink.v		blink.v
blink_tb.v		blink_tb.v
chip.v		chip.v
default.gtkw		default.gtkw
readme.md		readme.md
test.c		test.c
upduino_v2.pcf		upduino_v2.pcf

readme.md

Tasks

This example shows how to use tasks in verilog. Tasks can have any number of inputs and outputs.

Requirements

Yosys
Arachne-pnr
Project IceStorm

Usage

make

Builds chip.bin bitstream
make flash

Program the bitstream to the device.

Pretty loosly based on tomverbeure/upduino