diff --git a/ip/clk/globalclk.qsys b/ip/clk/globalclk.qsys
index 59826ce..90adfc8 100644
--- a/ip/clk/globalclk.qsys
+++ b/ip/clk/globalclk.qsys
@@ -44,7 +44,6 @@
type="conduit"
dir="end">
-
-
+
diff --git a/ip/clk/globalclk.sopcinfo b/ip/clk/globalclk.sopcinfo
index 4c561dc..3aa8425 100644
--- a/ip/clk/globalclk.sopcinfo
+++ b/ip/clk/globalclk.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1586444192
+ 1588892645
false
true
false
@@ -107,7 +107,7 @@ the requested settings for a module instance. -->
boolean
- true
+ false
false
true
true
@@ -185,12 +185,6 @@ parameters are a RESULT of the module parameters. -->
1
inclk
-
- ena
- Input
- 1
- ena
-
-
+
com.altera.sopcmodel.ensemble.EClockAdapter
@@ -53,7 +53,7 @@
int
- 1586444192
+ 1588892645
false
true
true
@@ -189,7 +189,7 @@ the requested settings for a module instance. -->
boolean
- true
+ false
false
true
true
@@ -267,12 +267,6 @@ parameters are a RESULT of the module parameters. -->
1
inclk
-
- ena
- Input
- 1
- ena
-
19.1
19.1 670
- 005056C00008000001715F714CC9
+ 5CE0C587F67700000171F161BA18
diff --git a/ip/clk/globalclk/synthesis/globalclk.qip b/ip/clk/globalclk/synthesis/globalclk.qip
index 33887df..ca597bc 100644
--- a/ip/clk/globalclk/synthesis/globalclk.qip
+++ b/ip/clk/globalclk/synthesis/globalclk.qip
@@ -2,7 +2,7 @@ set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_NAM
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "globalclk" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../globalclk.sopcinfo"]
-set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1586444192"
+set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1588892645"
set_global_assignment -library "globalclk" -name MISC_FILE [file join $::quartus(qip_path) "../globalclk.cmp"]
set_global_assignment -library "globalclk" -name SLD_FILE [file join $::quartus(qip_path) "globalclk.debuginfo"]
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@ set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONEN
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4NjQ0NDE5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4ODg5MjY0NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQ00xNTNDOEc=::QXV0byBERVZJQ0U="
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -28,7 +28,7 @@ set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -nam
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
-set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::dHJ1ZQ==::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
+set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
set_global_assignment -library "globalclk" -name VERILOG_FILE [file join $::quartus(qip_path) "globalclk.v"]
diff --git a/ip/clk/globalclk/synthesis/globalclk.v b/ip/clk/globalclk/synthesis/globalclk.v
index 988b394..986876b 100644
--- a/ip/clk/globalclk/synthesis/globalclk.v
+++ b/ip/clk/globalclk/synthesis/globalclk.v
@@ -5,13 +5,11 @@
`timescale 1 ps / 1 ps
module globalclk (
input wire inclk, // altclkctrl_input.inclk
- input wire ena, // .ena
output wire outclk // altclkctrl_output.outclk
);
globalclk_altclkctrl_0 altclkctrl_0 (
.inclk (inclk), // altclkctrl_input.inclk
- .ena (ena), // .ena
.outclk (outclk) // altclkctrl_output.outclk
);
diff --git a/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v b/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v
index e3d51b6..abc12a2 100644
--- a/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v
+++ b/ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v
@@ -88,35 +88,28 @@ endmodule //globalclk_altclkctrl_0_sub
`timescale 1 ps / 1 ps
// synopsys translate_on
module globalclk_altclkctrl_0 (
- ena,
inclk,
outclk);
- input ena;
input inclk;
output outclk;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri1 ena;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
wire sub_wire0;
wire outclk;
wire sub_wire1;
- wire [3:0] sub_wire2;
- wire [2:0] sub_wire3;
+ wire sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [2:0] sub_wire4;
assign outclk = sub_wire0;
- assign sub_wire1 = inclk;
- assign sub_wire2[3:0] = {sub_wire3, sub_wire1};
- assign sub_wire3[2:0] = 3'h0;
+ assign sub_wire1 = 1'h1;
+ assign sub_wire2 = inclk;
+ assign sub_wire3[3:0] = {sub_wire4, sub_wire2};
+ assign sub_wire4[2:0] = 3'h0;
globalclk_altclkctrl_0_sub globalclk_altclkctrl_0_sub_component (
- .ena (ena),
- .inclk (sub_wire2),
+ .ena (sub_wire1),
+ .inclk (sub_wire3),
.outclk (sub_wire0));
endmodule
\ No newline at end of file
diff --git a/rtl/sys_ctl.sv b/rtl/sys_ctl.sv
index 7427bea..eae3e35 100644
--- a/rtl/sys_ctl.sv
+++ b/rtl/sys_ctl.sv
@@ -40,13 +40,11 @@ rst_sync sys_rst_n_sync(
globalclk global_clk(
.inclk(pll_200m),
- .ena(1'b1),
.outclk(sys_clk_out)
);
globalclk global_rst_n(
.inclk(sys_rst_n),
- .ena(1'b1),
.outclk(sys_rst_n_out)
);