From d6e2bf880384984acb3b9386033873ddac874461 Mon Sep 17 00:00:00 2001 From: Renaldas Zioma Date: Wed, 15 Nov 2023 14:36:27 +0100 Subject: [PATCH] Initial commit --- .github/workflows/docs.yaml | 17 +++ .github/workflows/gds.yaml | 38 ++++++ .github/workflows/test.yaml | 39 ++++++ .gitignore | 9 ++ LICENSE | 201 ++++++++++++++++++++++++++++++ README.md | 36 ++++++ info.yaml | 85 +++++++++++++ src/Makefile | 36 ++++++ src/cells.v | 102 +++++++++++++++ src/config.tcl | 78 ++++++++++++ src/decoder.v | 44 +++++++ src/tb.gtkw | 30 +++++ src/tb.v | 47 +++++++ src/test.py | 48 +++++++ src/tt_um_seven_segment_seconds.v | 60 +++++++++ 15 files changed, 870 insertions(+) create mode 100644 .github/workflows/docs.yaml create mode 100644 .github/workflows/gds.yaml create mode 100644 .github/workflows/test.yaml create mode 100644 .gitignore create mode 100644 LICENSE create mode 100644 README.md create mode 100644 info.yaml create mode 100644 src/Makefile create mode 100644 src/cells.v create mode 100644 src/config.tcl create mode 100644 src/decoder.v create mode 100644 src/tb.gtkw create mode 100644 src/tb.v create mode 100644 src/test.py create mode 100644 src/tt_um_seven_segment_seconds.v diff --git a/.github/workflows/docs.yaml b/.github/workflows/docs.yaml new file mode 100644 index 0000000..64cb271 --- /dev/null +++ b/.github/workflows/docs.yaml @@ -0,0 +1,17 @@ +name: docs + +on: + push: + workflow_dispatch: + +jobs: + docs: + runs-on: ubuntu-latest + steps: + - name: Checkout repo + uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Build docs + uses: TinyTapeout/tt-gds-action/docs@tt05 diff --git a/.github/workflows/gds.yaml b/.github/workflows/gds.yaml new file mode 100644 index 0000000..2c4b142 --- /dev/null +++ b/.github/workflows/gds.yaml @@ -0,0 +1,38 @@ +name: gds + +on: + push: + workflow_dispatch: + +jobs: + gds: + runs-on: ubuntu-latest + steps: + - name: checkout repo + uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Build GDS + uses: TinyTapeout/tt-gds-action@tt05 + + gl_test: + needs: gds + runs-on: ubuntu-latest + steps: + - name: checkout repo + uses: actions/checkout@v3 + with: + submodules: recursive + + - name: GL test + uses: TinyTapeout/tt-gds-action/gl_test@tt05 + + viewer: + needs: gds + runs-on: ubuntu-latest + permissions: + pages: write # to deploy to Pages + id-token: write # to verify the deployment originates from an appropriate source + steps: + - uses: TinyTapeout/tt-gds-action/viewer@tt05 diff --git a/.github/workflows/test.yaml b/.github/workflows/test.yaml new file mode 100644 index 0000000..cbe0aff --- /dev/null +++ b/.github/workflows/test.yaml @@ -0,0 +1,39 @@ +name: test +# either manually started, or on a schedule +on: [ push, workflow_dispatch ] +jobs: + test: + # ubuntu + runs-on: ubuntu-latest + steps: + # need the repo checked out + - name: checkout repo + uses: actions/checkout@v3 + + # install oss fpga tools + - name: install oss-cad-suite + uses: YosysHQ/setup-oss-cad-suite@v2 + with: + python-override: true + github-token: ${{ secrets.GITHUB_TOKEN }} + - run: | + yosys --version + iverilog -V + cocotb-config --libpython + cocotb-config --python-bin + + - name: test + run: | + cd src + make clean + make + # make will return success even if the test fails, so check for failure in the results.xml + ! grep failure results.xml + + - name: upload vcd + if: success() || failure() + uses: actions/upload-artifact@v3 + with: + name: test-vcd + path: src/tb.vcd + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..657dc9d --- /dev/null +++ b/.gitignore @@ -0,0 +1,9 @@ +.DS_Store +.idea +.vscode +*.vcd +runs +src/sim_build +src/__pycache__/ +src/results.xml +src/user_config.tcl diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/README.md b/README.md new file mode 100644 index 0000000..5f86ad8 --- /dev/null +++ b/README.md @@ -0,0 +1,36 @@ +![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) + +# What is Tiny Tapeout? + +TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip. + +To learn more and get started, visit https://tinytapeout.com. + +## Verilog Projects + +Edit the [info.yaml](info.yaml) and uncomment the `source_files` and `top_module` properties, and change the value of `language` to "Verilog". Add your Verilog files to the `src` folder, and list them in the `source_files` property. + +The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/). + +## How to enable the GitHub actions to build the ASIC files + +Please see the instructions for: + +- [Enabling GitHub Actions](https://tinytapeout.com/faq/#when-i-commit-my-change-the-gds-action-isnt-running) +- [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part) + +## Resources + +- [FAQ](https://tinytapeout.com/faq/) +- [Digital design lessons](https://tinytapeout.com/digital_design/) +- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/) +- [Join the community](https://discord.gg/rPK2nSjxy8) + +## What next? + +- Submit your design to the next shuttle [on the website](https://tinytapeout.com/#submit-your-design). The closing date is **November 4th**. +- Edit this [README](README.md) and explain your design, how it works, and how to test it. +- Share your GDS on your social network of choice, tagging it #tinytapeout and linking Matt's profile: + - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [matt-venn](https://www.linkedin.com/in/matt-venn/) + - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn) + - Twitter [#tinytapeout](https://twitter.com/hashtag/tinytapeout?src=hashtag_click) [@matthewvenn](https://twitter.com/matthewvenn) diff --git a/info.yaml b/info.yaml new file mode 100644 index 0000000..a3fbdaa --- /dev/null +++ b/info.yaml @@ -0,0 +1,85 @@ +--- +# Tiny Tapeout project information +project: + wokwi_id: 0 # If using wokwi, set this to your project's ID + +# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. +# Source files must be in ./src and you must list each source file separately + source_files: + - tt_um_seven_segment_seconds.v + - decoder.v + top_module: "tt_um_seven_segment_seconds" # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username + +# How many tiles your design occupies? A single tile is about 167x108 uM. + tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 8x2 + +# Keep a track of the submission yaml +yaml_version: 4 + +# As everyone will have access to all designs, try to make it easy for someone new to your design to know what +# it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip. +# +# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml +documentation: + author: "Matt Venn" # Your name + title: "7 segment seconds (Verilog Demo)" # Project title + language: "Verilog" # other examples include Verilog, Amaranth, VHDL, etc + description: "Count up to 10, one second at a time." # Short description of what your project does + +# Longer description of how the project works. You can use standard markdown format. + how_it_works: | + Uses a set of registers to divide the clock, and then some combinational logic + to convert from binary to decimal for the display. + + Puts the bottom 8 bits of the counter on the bidirectional outputs. + + With all the inputs set to 0, the internal 24 bit compare is set to 10,000,000. This means the + counter will increment by one each second. + + If any inputs are non zero, then the input will be used as an bits 11 to 18 of the 24 bit compare register. + Example: setting the inputs to 00010000 will program 16384 into the compare register. + With a 10MHz clock the counter will increment ~610 times per second. + +# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed + how_to_test: | + After reset, the counter should increase by one every second with a 10MHz input clock. + Experiment by changing the inputs to change the counting speed. + +# A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc). + inputs: + - compare bit 11 + - compare bit 12 + - compare bit 13 + - compare bit 14 + - compare bit 15 + - compare bit 16 + - compare bit 17 + - compare bit 18 +# A description of what the outputs do (e.g. status LED, SPI MISO, etc) + outputs: + - segment a + - segment b + - segment c + - segment d + - segment e + - segment f + - segment g + - dot +# A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc) + bidirectional: + - second counter bit 0 + - second counter bit 1 + - second counter bit 2 + - second counter bit 3 + - second counter bit 4 + - second counter bit 5 + - second counter bit 6 + - second counter bit 7 + +# The following fields are optional + tag: "timer, test" # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator, + external_hw: "" # Describe any external hardware needed + discord: "mattvenn" # Your discord handle, used for communication and automatically assigning tapeout role after a submission + doc_link: "" # URL to longer form documentation, eg the README.md in your repository + clock_hz: 10000000 # Clock frequency in Hz (if required) + picture: "" # relative path to a picture in your repository (must be 512kb or less) diff --git a/src/Makefile b/src/Makefile new file mode 100644 index 0000000..2a6db2d --- /dev/null +++ b/src/Makefile @@ -0,0 +1,36 @@ +# Makefile +# See https://docs.cocotb.org/en/stable/quickstart.html for more info + +# defaults +SIM ?= icarus +TOPLEVEL_LANG ?= verilog + +# normal simulation +ifneq ($(GATES),yes) + +# this is the only part you should need to modify: +VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_seven_segment_seconds.v $(PWD)/decoder.v + +else + +# gate level simulation requires some extra setup, you shouldn't need to touch this +COMPILE_ARGS += -DGL_TEST +COMPILE_ARGS += -DFUNCTIONAL +COMPILE_ARGS += -DUSE_POWER_PINS +COMPILE_ARGS += -DSIM +COMPILE_ARGS += -DUNIT_DELAY=\#1 +VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v +VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v + +# this gets copied in by the GDS action workflow +VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/gate_level_netlist.v +endif + +# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file +TOPLEVEL = tb + +# MODULE is the basename of the Python test file +MODULE = test + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/cells.v b/src/cells.v new file mode 100644 index 0000000..772fb21 --- /dev/null +++ b/src/cells.v @@ -0,0 +1,102 @@ +/* +This file provides the mapping from the Wokwi modules to Verilog HDL + +It's only needed for Wokwi designs + +*/ +`define default_netname none + +module buffer_cell ( + input wire in, + output wire out + ); + assign out = in; +endmodule + +module and_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a & b; +endmodule + +module or_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a | b; +endmodule + +module xor_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a ^ b; +endmodule + +module nand_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = !(a&b); +endmodule + +module not_cell ( + input wire in, + output wire out + ); + + assign out = !in; +endmodule + +module mux_cell ( + input wire a, + input wire b, + input wire sel, + output wire out + ); + + assign out = sel ? b : a; +endmodule + +module dff_cell ( + input wire clk, + input wire d, + output reg q, + output wire notq + ); + + assign notq = !q; + always @(posedge clk) + q <= d; + +endmodule + +module dffsr_cell ( + input wire clk, + input wire d, + input wire s, + input wire r, + output reg q, + output wire notq + ); + + assign notq = !q; + + always @(posedge clk or posedge s or posedge r) begin + if (r) + q <= 0; + else if (s) + q <= 1; + else + q <= d; + end +endmodule diff --git a/src/config.tcl b/src/config.tcl new file mode 100644 index 0000000..4a525a1 --- /dev/null +++ b/src/config.tcl @@ -0,0 +1,78 @@ +# DO NOT EDIT THIS FILE before reading the comments below: + +# This is the default configuration for Tiny Tapeout projects. It should fit most designs. +# If you change it, please make sure you understand what you are doing. We are not responsible +# if your project fails because of a bad configuration. + +# !!! DO NOT EDIT THIS FILE unless you know what you are doing !!! + +# If you get stuck with this config, please open an issue or get in touch via the discord. + +# Here are some of the variables you may want to change: + +# PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302. +# Users have reported that values up to 0.8 worked well for them. +set ::env(PL_TARGET_DENSITY) 0.6 + +# CLOCK_PERIOD - Increase this in case you are getting setup time violations. +# The value is in nanoseconds, so 20ns == 50MHz. +set ::env(CLOCK_PERIOD) "20" + +# Hold slack margin - Increase them in case you are getting hold violations. +set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1 +set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.05 + +# RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended! +set ::env(RUN_LINTER) 1 +set ::env(LINTER_INCLUDE_PDK_MODELS) 1 + +# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html + +# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +# !!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!! +# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +# Load configuration auto-generated by tt-support-tools +set script_dir [file dirname [file normalize [info script]]] +source $::env(DESIGN_DIR)/user_config.tcl + +# Save some time +set ::env(RUN_KLAYOUT_XOR) 0 +set ::env(RUN_KLAYOUT_DRC) 0 + +# Don't put clock buffers on the outputs +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 + +# Allow use of specific sky130 cells +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +# Reduce wasted space +set ::env(TOP_MARGIN_MULT) 1 +set ::env(BOTTOM_MARGIN_MULT) 1 +set ::env(LEFT_MARGIN_MULT) 6 +set ::env(RIGHT_MARGIN_MULT) 6 + +# Absolute die size +set ::env(FP_SIZING) absolute + +set ::env(PL_BASIC_PLACEMENT) {0} +set ::env(GRT_ALLOW_CONGESTION) "1" + +set ::env(FP_IO_HLENGTH) 2 +set ::env(FP_IO_VLENGTH) 2 + +# Use alternative efabless decap cells to solve LI density issue +set ::env(DECAP_CELL) "\ + sky130_fd_sc_hd__decap_3 \ + sky130_fd_sc_hd__decap_4 \ + sky130_fd_sc_hd__decap_6 \ + sky130_fd_sc_hd__decap_8 \ + sky130_ef_sc_hd__decap_12" + +# Clock +set ::env(RUN_CTS) 1 +set ::env(CLOCK_PORT) {clk} + +# Don't use power rings or met5 layer +set ::env(DESIGN_IS_CORE) 0 +set ::env(RT_MAX_LAYER) {met4} diff --git a/src/decoder.v b/src/decoder.v new file mode 100644 index 0000000..e2e3d5b --- /dev/null +++ b/src/decoder.v @@ -0,0 +1,44 @@ + +/* + -- 1 -- + | | + 6 2 + | | + -- 7 -- + | | + 5 3 + | | + -- 4 -- +*/ + +module seg7 ( + input wire [3:0] counter, + output reg [6:0] segments +); + + always @(*) begin + case(counter) + // 7654321 + 0: segments = 7'b0111111; + 1: segments = 7'b0000110; + 2: segments = 7'b1011011; + 3: segments = 7'b1001111; + 4: segments = 7'b1100110; + 5: segments = 7'b1101101; + 6: segments = 7'b1111101; + 7: segments = 7'b0000111; + 8: segments = 7'b1111111; + 9: segments = 7'b1101111; + 10: segments = 7'b1110111; + 11: segments = 7'b1111100; + 12: segments = 7'b0111001; + 13: segments = 7'b1011110; + 14: segments = 7'b1111001; + 15: segments = 7'b1110001; + default: + segments = 7'b0000000; + endcase + end + +endmodule + diff --git a/src/tb.gtkw b/src/tb.gtkw new file mode 100644 index 0000000..259ce74 --- /dev/null +++ b/src/tb.gtkw @@ -0,0 +1,30 @@ +[*] +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Fri Jul 21 10:59:05 2023 +[*] +[dumpfile] "/home/matt/work/asic-workshop/shuttle-2309C/tt04-verilog-demo/src/tb.vcd" +[dumpfile_mtime] "Fri Jul 21 10:58:31 2023" +[dumpfile_size] 4298151 +[savefile] "/home/matt/work/asic-workshop/shuttle-2309C/tt04-verilog-demo/src/tb.gtkw" +[timestart] 0 +[size] 2286 698 +[pos] -1 -1 +*-33.900002 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] tb. +[sst_width] 343 +[signals_width] 414 +[sst_expanded] 1 +[sst_vpaned_height] 190 +@28 +tb.rst_n +tb.clk +@22 +tb.segments[6:0] +tb.uio_out[7:0] +tb.tt_um_seven_segment_seconds.compare[23:0] +@28 +tb.tt_um_seven_segment_seconds.rst_n +@22 +tb.ui_in[7:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/src/tb.v b/src/tb.v new file mode 100644 index 0000000..d347d54 --- /dev/null +++ b/src/tb.v @@ -0,0 +1,47 @@ +`default_nettype none +`timescale 1ns/1ps + +/* +this testbench just instantiates the module and makes some convenient wires +that can be driven / tested by the cocotb test.py +*/ + +// testbench is controlled by test.py +module tb (); + + // this part dumps the trace to a vcd file that can be viewed with GTKWave + initial begin + $dumpfile ("tb.vcd"); + $dumpvars (0, tb); + #1; + end + + // wire up the inputs and outputs + reg clk; + reg rst_n; + reg ena; + reg [7:0] ui_in; + reg [7:0] uio_in; + + wire [6:0] segments = uo_out[6:0]; + wire [7:0] uo_out; + wire [7:0] uio_out; + wire [7:0] uio_oe; + + tt_um_seven_segment_seconds tt_um_seven_segment_seconds ( + // include power ports for the Gate Level test + `ifdef GL_TEST + .VPWR( 1'b1), + .VGND( 1'b0), + `endif + .ui_in (ui_in), // Dedicated inputs + .uo_out (uo_out), // Dedicated outputs + .uio_in (uio_in), // IOs: Input path + .uio_out (uio_out), // IOs: Output path + .uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output) + .ena (ena), // enable - goes high when design is selected + .clk (clk), // clock + .rst_n (rst_n) // not reset + ); + +endmodule diff --git a/src/test.py b/src/test.py new file mode 100644 index 0000000..fb76b0e --- /dev/null +++ b/src/test.py @@ -0,0 +1,48 @@ +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer, ClockCycles + + +segments = [ 63, 6, 91, 79, 102, 109, 125, 7, 127, 111 ] + +@cocotb.test() +async def test_7seg(dut): + dut._log.info("start") + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + # reset + dut._log.info("reset") + dut.rst_n.value = 0 + # set the compare value + dut.ui_in.value = 1 + await ClockCycles(dut.clk, 10) + dut.rst_n.value = 1 + + # the compare value is shifted 10 bits inside the design to allow slower counting + max_count = dut.ui_in.value << 10 + dut._log.info(f"check all segments with MAX_COUNT set to {max_count}") + # check all segments and roll over + for i in range(15): + dut._log.info("check segment {}".format(i)) + await ClockCycles(dut.clk, max_count) + assert int(dut.segments.value) == segments[i % 10] + + # all bidirectionals are set to output + assert dut.uio_oe == 0xFF + + # reset + dut.rst_n.value = 0 + # set a different compare value + dut.ui_in.value = 3 + await ClockCycles(dut.clk, 10) + dut.rst_n.value = 1 + + max_count = dut.ui_in.value << 10 + dut._log.info(f"check all segments with MAX_COUNT set to {max_count}") + # check all segments and roll over + for i in range(15): + dut._log.info("check segment {}".format(i)) + await ClockCycles(dut.clk, max_count) + assert int(dut.segments.value) == segments[i % 10] + diff --git a/src/tt_um_seven_segment_seconds.v b/src/tt_um_seven_segment_seconds.v new file mode 100644 index 0000000..5ac8f26 --- /dev/null +++ b/src/tt_um_seven_segment_seconds.v @@ -0,0 +1,60 @@ +`default_nettype none + +module tt_um_seven_segment_seconds #( parameter MAX_COUNT = 24'd10_000_000 ) ( + input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches + output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display + input wire [7:0] uio_in, // IOs: Bidirectional Input path + output wire [7:0] uio_out, // IOs: Bidirectional Output path + output wire [7:0] uio_oe, // IOs: Bidirectional Enable path (active high: 0=input, 1=output) + input wire ena, // will go high when the design is enabled + input wire clk, // clock + input wire rst_n // reset_n - low to reset +); + + wire reset = ! rst_n; + wire [6:0] led_out; + assign uo_out[6:0] = led_out; + assign uo_out[7] = 1'b0; + + // use bidirectionals as outputs + assign uio_oe = 8'b11111111; + + // put bottom 8 bits of second counter out on the bidirectional gpio + assign uio_out = second_counter[7:0]; + + // external clock is 10MHz, so need 24 bit counter + reg [23:0] second_counter; + reg [3:0] digit; + + // if external inputs are set then use that as compare count + // otherwise use the hard coded MAX_COUNT + wire [23:0] compare = ui_in == 0 ? MAX_COUNT: {6'b0, ui_in[7:0], 10'b0}; + + always @(posedge clk) begin + // if reset, set counter to 0 + if (reset) begin + second_counter <= 0; + digit <= 0; + end else begin + // if up to 16e6 + if (second_counter == compare) begin + // reset + second_counter <= 0; + + // increment digit + digit <= digit + 1'b1; + + // only count from 0 to 9 + if (digit == 9) + digit <= 0; + + end else + // increment counter + second_counter <= second_counter + 1'b1; + end + end + + // instantiate segment display + seg7 seg7(.counter(digit), .segments(led_out)); + +endmodule