From 08c566b47f758f87cc7d4f7c8d0bc083e072695e Mon Sep 17 00:00:00 2001 From: Kiva Date: Fri, 29 Dec 2023 15:59:47 +0800 Subject: [PATCH] [Clang][XTHeadVector] Add wrapper macros that forwards intrinsic calls from 1.0 to xtheadvector (#46) * [Clang][XTHeadVector] Add intrinsic wrapper macros in order to compatible with RVV 1.0 * [Clang][XTHeadVector] Test intrinsic wrapper macros --- .../clang/Basic/riscv_vector_xtheadv.td | 289 ++++++++++++++++ .../wrappers/vlb.c | 166 +++++++++ .../wrappers/vlbu.c | 166 +++++++++ .../wrappers/vle16.c | 126 +++++++ .../wrappers/vle32.c | 126 +++++++ .../wrappers/vle64.c | 126 +++++++ .../wrappers/vle8.c | 86 +++++ .../wrappers/vlh.c | 167 +++++++++ .../wrappers/vlhu.c | 166 +++++++++ .../wrappers/vlw.c | 166 +++++++++ .../wrappers/vlwu.c | 166 +++++++++ .../wrappers/vsb.c | 327 ++++++++++++++++++ .../wrappers/vse16.c | 126 +++++++ .../wrappers/vse32.c | 126 +++++++ .../wrappers/vse64.c | 126 +++++++ .../wrappers/vse8.c | 86 +++++ .../wrappers/vsh.c | 326 +++++++++++++++++ .../wrappers/vsw.c | 326 +++++++++++++++++ 18 files changed, 3193 insertions(+) create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlb.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlbu.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlh.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlhu.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlw.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlwu.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsb.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsh.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsw.c diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv.td b/clang/include/clang/Basic/riscv_vector_xtheadv.td index eaaa66009a4e56a..935a0e264dd8f79 100644 --- a/clang/include/clang/Basic/riscv_vector_xtheadv.td +++ b/clang/include/clang/Basic/riscv_vector_xtheadv.td @@ -173,6 +173,295 @@ let HasBuiltinAlias = false, // 7. Vector Loads and Stores //===----------------------------------------------------------------------===// +let HeaderCode = +[{ +// Vector Unit-stride loads +#define __riscv_vlb_v_i8m1(base, vl) __riscv_th_vlb_v_i8m1(base, vl) +#define __riscv_vlb_v_i8m2(base, vl) __riscv_th_vlb_v_i8m2(base, vl) +#define __riscv_vlb_v_i8m4(base, vl) __riscv_th_vlb_v_i8m4(base, vl) +#define __riscv_vlb_v_i8m8(base, vl) __riscv_th_vlb_v_i8m8(base, vl) +#define __riscv_vlb_v_i16m1(base, vl) __riscv_th_vlb_v_i16m1(base, vl) +#define __riscv_vlb_v_i16m2(base, vl) __riscv_th_vlb_v_i16m2(base, vl) +#define __riscv_vlb_v_i16m4(base, vl) __riscv_th_vlb_v_i16m4(base, vl) +#define __riscv_vlb_v_i16m8(base, vl) __riscv_th_vlb_v_i16m8(base, vl) +#define __riscv_vlb_v_i32m1(base, vl) __riscv_th_vlb_v_i32m1(base, vl) +#define __riscv_vlb_v_i32m2(base, vl) __riscv_th_vlb_v_i32m2(base, vl) +#define __riscv_vlb_v_i32m4(base, vl) __riscv_th_vlb_v_i32m4(base, vl) +#define __riscv_vlb_v_i32m8(base, vl) __riscv_th_vlb_v_i32m8(base, vl) +#define __riscv_vlb_v_i64m1(base, vl) __riscv_th_vlb_v_i64m1(base, vl) +#define __riscv_vlb_v_i64m2(base, vl) __riscv_th_vlb_v_i64m2(base, vl) +#define __riscv_vlb_v_i64m4(base, vl) __riscv_th_vlb_v_i64m4(base, vl) +#define __riscv_vlb_v_i64m8(base, vl) __riscv_th_vlb_v_i64m8(base, vl) +#define __riscv_vlh_v_i8m1(base, vl) __riscv_th_vlh_v_i8m1(base, vl) +#define __riscv_vlh_v_i8m2(base, vl) __riscv_th_vlh_v_i8m2(base, vl) +#define __riscv_vlh_v_i8m4(base, vl) __riscv_th_vlh_v_i8m4(base, vl) +#define __riscv_vlh_v_i8m8(base, vl) __riscv_th_vlh_v_i8m8(base, vl) +#define __riscv_vlh_v_i16m1(base, vl) __riscv_th_vlh_v_i16m1(base, vl) +#define __riscv_vlh_v_i16m2(base, vl) __riscv_th_vlh_v_i16m2(base, vl) +#define __riscv_vlh_v_i16m4(base, vl) __riscv_th_vlh_v_i16m4(base, vl) +#define __riscv_vlh_v_i16m8(base, vl) __riscv_th_vlh_v_i16m8(base, vl) +#define __riscv_vlh_v_i32m1(base, vl) __riscv_th_vlh_v_i32m1(base, vl) +#define __riscv_vlh_v_i32m2(base, vl) __riscv_th_vlh_v_i32m2(base, vl) +#define __riscv_vlh_v_i32m4(base, vl) __riscv_th_vlh_v_i32m4(base, vl) +#define __riscv_vlh_v_i32m8(base, vl) __riscv_th_vlh_v_i32m8(base, vl) +#define __riscv_vlh_v_i64m1(base, vl) __riscv_th_vlh_v_i64m1(base, vl) +#define __riscv_vlh_v_i64m2(base, vl) __riscv_th_vlh_v_i64m2(base, vl) +#define __riscv_vlh_v_i64m4(base, vl) __riscv_th_vlh_v_i64m4(base, vl) +#define __riscv_vlh_v_i64m8(base, vl) __riscv_th_vlh_v_i64m8(base, vl) +#define __riscv_vlw_v_i8m1(base, vl) __riscv_th_vlw_v_i8m1(base, vl) +#define __riscv_vlw_v_i8m2(base, vl) __riscv_th_vlw_v_i8m2(base, vl) +#define __riscv_vlw_v_i8m4(base, vl) __riscv_th_vlw_v_i8m4(base, vl) +#define __riscv_vlw_v_i8m8(base, vl) __riscv_th_vlw_v_i8m8(base, vl) +#define __riscv_vlw_v_i16m1(base, vl) __riscv_th_vlw_v_i16m1(base, vl) +#define __riscv_vlw_v_i16m2(base, vl) __riscv_th_vlw_v_i16m2(base, vl) +#define __riscv_vlw_v_i16m4(base, vl) __riscv_th_vlw_v_i16m4(base, vl) +#define __riscv_vlw_v_i16m8(base, vl) __riscv_th_vlw_v_i16m8(base, vl) +#define __riscv_vlw_v_i32m1(base, vl) __riscv_th_vlw_v_i32m1(base, vl) +#define __riscv_vlw_v_i32m2(base, vl) __riscv_th_vlw_v_i32m2(base, vl) +#define __riscv_vlw_v_i32m4(base, vl) __riscv_th_vlw_v_i32m4(base, vl) +#define __riscv_vlw_v_i32m8(base, vl) __riscv_th_vlw_v_i32m8(base, vl) +#define __riscv_vlw_v_i64m1(base, vl) __riscv_th_vlw_v_i64m1(base, vl) +#define __riscv_vlw_v_i64m2(base, vl) __riscv_th_vlw_v_i64m2(base, vl) +#define __riscv_vlw_v_i64m4(base, vl) __riscv_th_vlw_v_i64m4(base, vl) +#define __riscv_vlw_v_i64m8(base, vl) __riscv_th_vlw_v_i64m8(base, vl) +#define __riscv_vlbu_v_u8m1(base, vl) __riscv_th_vlbu_v_u8m1(base, vl) +#define __riscv_vlbu_v_u8m2(base, vl) __riscv_th_vlbu_v_u8m2(base, vl) +#define __riscv_vlbu_v_u8m4(base, vl) __riscv_th_vlbu_v_u8m4(base, vl) +#define __riscv_vlbu_v_u8m8(base, vl) __riscv_th_vlbu_v_u8m8(base, vl) +#define __riscv_vlbu_v_u16m1(base, vl) __riscv_th_vlbu_v_u16m1(base, vl) +#define __riscv_vlbu_v_u16m2(base, vl) __riscv_th_vlbu_v_u16m2(base, vl) +#define __riscv_vlbu_v_u16m4(base, vl) __riscv_th_vlbu_v_u16m4(base, vl) +#define __riscv_vlbu_v_u16m8(base, vl) __riscv_th_vlbu_v_u16m8(base, vl) +#define __riscv_vlbu_v_u32m1(base, vl) __riscv_th_vlbu_v_u32m1(base, vl) +#define __riscv_vlbu_v_u32m2(base, vl) __riscv_th_vlbu_v_u32m2(base, vl) +#define __riscv_vlbu_v_u32m4(base, vl) __riscv_th_vlbu_v_u32m4(base, vl) +#define __riscv_vlbu_v_u32m8(base, vl) __riscv_th_vlbu_v_u32m8(base, vl) +#define __riscv_vlbu_v_u64m1(base, vl) __riscv_th_vlbu_v_u64m1(base, vl) +#define __riscv_vlbu_v_u64m2(base, vl) __riscv_th_vlbu_v_u64m2(base, vl) +#define __riscv_vlbu_v_u64m4(base, vl) __riscv_th_vlbu_v_u64m4(base, vl) +#define __riscv_vlbu_v_u64m8(base, vl) __riscv_th_vlbu_v_u64m8(base, vl) +#define __riscv_vlhu_v_u8m1(base, vl) __riscv_th_vlhu_v_u8m1(base, vl) +#define __riscv_vlhu_v_u8m2(base, vl) __riscv_th_vlhu_v_u8m2(base, vl) +#define __riscv_vlhu_v_u8m4(base, vl) __riscv_th_vlhu_v_u8m4(base, vl) +#define __riscv_vlhu_v_u8m8(base, vl) __riscv_th_vlhu_v_u8m8(base, vl) +#define __riscv_vlhu_v_u16m1(base, vl) __riscv_th_vlhu_v_u16m1(base, vl) +#define __riscv_vlhu_v_u16m2(base, vl) __riscv_th_vlhu_v_u16m2(base, vl) +#define __riscv_vlhu_v_u16m4(base, vl) __riscv_th_vlhu_v_u16m4(base, vl) +#define __riscv_vlhu_v_u16m8(base, vl) __riscv_th_vlhu_v_u16m8(base, vl) +#define __riscv_vlhu_v_u32m1(base, vl) __riscv_th_vlhu_v_u32m1(base, vl) +#define __riscv_vlhu_v_u32m2(base, vl) __riscv_th_vlhu_v_u32m2(base, vl) +#define __riscv_vlhu_v_u32m4(base, vl) __riscv_th_vlhu_v_u32m4(base, vl) +#define __riscv_vlhu_v_u32m8(base, vl) __riscv_th_vlhu_v_u32m8(base, vl) +#define __riscv_vlhu_v_u64m1(base, vl) __riscv_th_vlhu_v_u64m1(base, vl) +#define __riscv_vlhu_v_u64m2(base, vl) __riscv_th_vlhu_v_u64m2(base, vl) +#define __riscv_vlhu_v_u64m4(base, vl) __riscv_th_vlhu_v_u64m4(base, vl) +#define __riscv_vlhu_v_u64m8(base, vl) __riscv_th_vlhu_v_u64m8(base, vl) +#define __riscv_vlwu_v_u8m1(base, vl) __riscv_th_vlwu_v_u8m1(base, vl) +#define __riscv_vlwu_v_u8m2(base, vl) __riscv_th_vlwu_v_u8m2(base, vl) +#define __riscv_vlwu_v_u8m4(base, vl) __riscv_th_vlwu_v_u8m4(base, vl) +#define __riscv_vlwu_v_u8m8(base, vl) __riscv_th_vlwu_v_u8m8(base, vl) +#define __riscv_vlwu_v_u16m1(base, vl) __riscv_th_vlwu_v_u16m1(base, vl) +#define __riscv_vlwu_v_u16m2(base, vl) __riscv_th_vlwu_v_u16m2(base, vl) +#define __riscv_vlwu_v_u16m4(base, vl) __riscv_th_vlwu_v_u16m4(base, vl) +#define __riscv_vlwu_v_u16m8(base, vl) __riscv_th_vlwu_v_u16m8(base, vl) +#define __riscv_vlwu_v_u32m1(base, vl) __riscv_th_vlwu_v_u32m1(base, vl) +#define __riscv_vlwu_v_u32m2(base, vl) __riscv_th_vlwu_v_u32m2(base, vl) +#define __riscv_vlwu_v_u32m4(base, vl) __riscv_th_vlwu_v_u32m4(base, vl) +#define __riscv_vlwu_v_u32m8(base, vl) __riscv_th_vlwu_v_u32m8(base, vl) +#define __riscv_vlwu_v_u64m1(base, vl) __riscv_th_vlwu_v_u64m1(base, vl) +#define __riscv_vlwu_v_u64m2(base, vl) __riscv_th_vlwu_v_u64m2(base, vl) +#define __riscv_vlwu_v_u64m4(base, vl) __riscv_th_vlwu_v_u64m4(base, vl) +#define __riscv_vlwu_v_u64m8(base, vl) __riscv_th_vlwu_v_u64m8(base, vl) +#define __riscv_vle8_v_i8m1(base, vl) __riscv_th_vle8_v_i8m1(base, vl) +#define __riscv_vle8_v_i8m2(base, vl) __riscv_th_vle8_v_i8m2(base, vl) +#define __riscv_vle8_v_i8m4(base, vl) __riscv_th_vle8_v_i8m4(base, vl) +#define __riscv_vle8_v_i8m8(base, vl) __riscv_th_vle8_v_i8m8(base, vl) +#define __riscv_vle16_v_i16m1(base, vl) __riscv_th_vle16_v_i16m1(base, vl) +#define __riscv_vle16_v_i16m2(base, vl) __riscv_th_vle16_v_i16m2(base, vl) +#define __riscv_vle16_v_i16m4(base, vl) __riscv_th_vle16_v_i16m4(base, vl) +#define __riscv_vle16_v_i16m8(base, vl) __riscv_th_vle16_v_i16m8(base, vl) +#define __riscv_vle32_v_i32m1(base, vl) __riscv_th_vle32_v_i32m1(base, vl) +#define __riscv_vle32_v_i32m2(base, vl) __riscv_th_vle32_v_i32m2(base, vl) +#define __riscv_vle32_v_i32m4(base, vl) __riscv_th_vle32_v_i32m4(base, vl) +#define __riscv_vle32_v_i32m8(base, vl) __riscv_th_vle32_v_i32m8(base, vl) +#define __riscv_vle64_v_i64m1(base, vl) __riscv_th_vle64_v_i64m1(base, vl) +#define __riscv_vle64_v_i64m2(base, vl) __riscv_th_vle64_v_i64m2(base, vl) +#define __riscv_vle64_v_i64m4(base, vl) __riscv_th_vle64_v_i64m4(base, vl) +#define __riscv_vle64_v_i64m8(base, vl) __riscv_th_vle64_v_i64m8(base, vl) +#define __riscv_vle8_v_u8m1(base, vl) __riscv_th_vle8_v_u8m1(base, vl) +#define __riscv_vle8_v_u8m2(base, vl) __riscv_th_vle8_v_u8m2(base, vl) +#define __riscv_vle8_v_u8m4(base, vl) __riscv_th_vle8_v_u8m4(base, vl) +#define __riscv_vle8_v_u8m8(base, vl) __riscv_th_vle8_v_u8m8(base, vl) +#define __riscv_vle16_v_u16m1(base, vl) __riscv_th_vle16_v_u16m1(base, vl) +#define __riscv_vle16_v_u16m2(base, vl) __riscv_th_vle16_v_u16m2(base, vl) +#define __riscv_vle16_v_u16m4(base, vl) __riscv_th_vle16_v_u16m4(base, vl) +#define __riscv_vle16_v_u16m8(base, vl) __riscv_th_vle16_v_u16m8(base, vl) +#define __riscv_vle32_v_u32m1(base, vl) __riscv_th_vle32_v_u32m1(base, vl) +#define __riscv_vle32_v_u32m2(base, vl) __riscv_th_vle32_v_u32m2(base, vl) +#define __riscv_vle32_v_u32m4(base, vl) __riscv_th_vle32_v_u32m4(base, vl) +#define __riscv_vle32_v_u32m8(base, vl) __riscv_th_vle32_v_u32m8(base, vl) +#define __riscv_vle64_v_u64m1(base, vl) __riscv_th_vle64_v_u64m1(base, vl) +#define __riscv_vle64_v_u64m2(base, vl) __riscv_th_vle64_v_u64m2(base, vl) +#define __riscv_vle64_v_u64m4(base, vl) __riscv_th_vle64_v_u64m4(base, vl) +#define __riscv_vle64_v_u64m8(base, vl) __riscv_th_vle64_v_u64m8(base, vl) +#define __riscv_vle16_v_f16m1(base, vl) __riscv_th_vle16_v_f16m1(base, vl) +#define __riscv_vle16_v_f16m2(base, vl) __riscv_th_vle16_v_f16m2(base, vl) +#define __riscv_vle16_v_f16m4(base, vl) __riscv_th_vle16_v_f16m4(base, vl) +#define __riscv_vle16_v_f16m8(base, vl) __riscv_th_vle16_v_f16m8(base, vl) +#define __riscv_vle32_v_f32m1(base, vl) __riscv_th_vle32_v_f32m1(base, vl) +#define __riscv_vle32_v_f32m2(base, vl) __riscv_th_vle32_v_f32m2(base, vl) +#define __riscv_vle32_v_f32m4(base, vl) __riscv_th_vle32_v_f32m4(base, vl) +#define __riscv_vle32_v_f32m8(base, vl) __riscv_th_vle32_v_f32m8(base, vl) +#define __riscv_vle64_v_f64m1(base, vl) __riscv_th_vle64_v_f64m1(base, vl) +#define __riscv_vle64_v_f64m2(base, vl) __riscv_th_vle64_v_f64m2(base, vl) +#define __riscv_vle64_v_f64m4(base, vl) __riscv_th_vle64_v_f64m4(base, vl) +#define __riscv_vle64_v_f64m8(base, vl) __riscv_th_vle64_v_f64m8(base, vl) + +// Vector Unit-stride stores +#define __riscv_vsb_v_i8m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i8m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i8m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i8m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i8m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i8m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i8m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i8m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i16m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i16m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i16m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i16m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i16m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i16m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i16m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i16m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i32m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i32m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i32m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i32m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i32m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i32m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i32m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i32m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i64m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i64m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i64m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i64m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i64m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i64m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_i64m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_i64m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i8m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i8m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i8m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i8m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i8m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i8m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i8m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i8m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i16m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i16m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i16m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i16m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i16m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i16m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i16m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i16m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i32m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i32m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i32m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i32m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i32m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i32m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i32m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i32m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i64m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i64m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i64m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i64m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i64m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i64m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_i64m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_i64m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i8m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i8m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i8m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i8m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i8m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i8m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i8m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i8m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i16m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i16m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i16m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i16m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i16m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i16m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i16m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i16m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i32m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i32m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i32m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i32m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i32m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i32m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i32m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i32m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i64m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i64m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i64m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i64m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i64m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i64m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_i64m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_i64m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u8m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u8m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u8m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u8m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u8m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u8m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u8m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u8m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u16m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u16m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u16m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u16m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u16m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u16m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u16m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u16m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u32m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u32m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u32m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u32m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u32m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u32m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u32m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u32m8(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u64m1(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u64m1(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u64m2(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u64m2(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u64m4(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u64m4(dst_ptr, vector_value, vl) +#define __riscv_vsb_v_u64m8(dst_ptr, vector_value, vl) __riscv_th_vsb_v_u64m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u8m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u8m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u8m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u8m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u8m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u8m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u8m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u8m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u16m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u16m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u16m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u16m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u16m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u16m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u16m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u16m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u32m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u32m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u32m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u32m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u32m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u32m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u32m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u32m8(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u64m1(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u64m1(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u64m2(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u64m2(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u64m4(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u64m4(dst_ptr, vector_value, vl) +#define __riscv_vsh_v_u64m8(dst_ptr, vector_value, vl) __riscv_th_vsh_v_u64m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u8m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u8m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u8m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u8m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u8m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u8m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u8m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u8m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u16m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u16m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u16m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u16m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u16m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u16m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u16m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u16m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u32m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u32m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u32m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u32m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u32m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u32m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u32m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u32m8(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u64m1(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u64m1(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u64m2(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u64m2(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u64m4(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u64m4(dst_ptr, vector_value, vl) +#define __riscv_vsw_v_u64m8(dst_ptr, vector_value, vl) __riscv_th_vsw_v_u64m8(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_i8m1(dst_ptr, vector_value, vl) __riscv_th_vse8_v_i8m1(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_i8m2(dst_ptr, vector_value, vl) __riscv_th_vse8_v_i8m2(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_i8m4(dst_ptr, vector_value, vl) __riscv_th_vse8_v_i8m4(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_i8m8(dst_ptr, vector_value, vl) __riscv_th_vse8_v_i8m8(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_i16m1(dst_ptr, vector_value, vl) __riscv_th_vse16_v_i16m1(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_i16m2(dst_ptr, vector_value, vl) __riscv_th_vse16_v_i16m2(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_i16m4(dst_ptr, vector_value, vl) __riscv_th_vse16_v_i16m4(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_i16m8(dst_ptr, vector_value, vl) __riscv_th_vse16_v_i16m8(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_i32m1(dst_ptr, vector_value, vl) __riscv_th_vse32_v_i32m1(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_i32m2(dst_ptr, vector_value, vl) __riscv_th_vse32_v_i32m2(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_i32m4(dst_ptr, vector_value, vl) __riscv_th_vse32_v_i32m4(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_i32m8(dst_ptr, vector_value, vl) __riscv_th_vse32_v_i32m8(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_i64m1(dst_ptr, vector_value, vl) __riscv_th_vse64_v_i64m1(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_i64m2(dst_ptr, vector_value, vl) __riscv_th_vse64_v_i64m2(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_i64m4(dst_ptr, vector_value, vl) __riscv_th_vse64_v_i64m4(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_i64m8(dst_ptr, vector_value, vl) __riscv_th_vse64_v_i64m8(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_u8m1(dst_ptr, vector_value, vl) __riscv_th_vse8_v_u8m1(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_u8m2(dst_ptr, vector_value, vl) __riscv_th_vse8_v_u8m2(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_u8m4(dst_ptr, vector_value, vl) __riscv_th_vse8_v_u8m4(dst_ptr, vector_value, vl) +#define __riscv_vse8_v_u8m8(dst_ptr, vector_value, vl) __riscv_th_vse8_v_u8m8(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_u16m1(dst_ptr, vector_value, vl) __riscv_th_vse16_v_u16m1(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_u16m2(dst_ptr, vector_value, vl) __riscv_th_vse16_v_u16m2(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_u16m4(dst_ptr, vector_value, vl) __riscv_th_vse16_v_u16m4(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_u16m8(dst_ptr, vector_value, vl) __riscv_th_vse16_v_u16m8(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_u32m1(dst_ptr, vector_value, vl) __riscv_th_vse32_v_u32m1(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_u32m2(dst_ptr, vector_value, vl) __riscv_th_vse32_v_u32m2(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_u32m4(dst_ptr, vector_value, vl) __riscv_th_vse32_v_u32m4(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_u32m8(dst_ptr, vector_value, vl) __riscv_th_vse32_v_u32m8(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_u64m1(dst_ptr, vector_value, vl) __riscv_th_vse64_v_u64m1(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_u64m2(dst_ptr, vector_value, vl) __riscv_th_vse64_v_u64m2(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_u64m4(dst_ptr, vector_value, vl) __riscv_th_vse64_v_u64m4(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_u64m8(dst_ptr, vector_value, vl) __riscv_th_vse64_v_u64m8(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_f16m1(dst_ptr, vector_value, vl) __riscv_th_vse16_v_f16m1(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_f16m2(dst_ptr, vector_value, vl) __riscv_th_vse16_v_f16m2(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_f16m4(dst_ptr, vector_value, vl) __riscv_th_vse16_v_f16m4(dst_ptr, vector_value, vl) +#define __riscv_vse16_v_f16m8(dst_ptr, vector_value, vl) __riscv_th_vse16_v_f16m8(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_f32m1(dst_ptr, vector_value, vl) __riscv_th_vse32_v_f32m1(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_f32m2(dst_ptr, vector_value, vl) __riscv_th_vse32_v_f32m2(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_f32m4(dst_ptr, vector_value, vl) __riscv_th_vse32_v_f32m4(dst_ptr, vector_value, vl) +#define __riscv_vse32_v_f32m8(dst_ptr, vector_value, vl) __riscv_th_vse32_v_f32m8(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_f64m1(dst_ptr, vector_value, vl) __riscv_th_vse64_v_f64m1(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_f64m2(dst_ptr, vector_value, vl) __riscv_th_vse64_v_f64m2(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_f64m4(dst_ptr, vector_value, vl) __riscv_th_vse64_v_f64m4(dst_ptr, vector_value, vl) +#define __riscv_vse64_v_f64m8(dst_ptr, vector_value, vl) __riscv_th_vse64_v_f64m8(dst_ptr, vector_value, vl) + +}] in +def th_unit_stride_wrapper_macros: RVVHeader; + let SupportOverloading = false, UnMaskedPolicyScheme = HasPassthruOperand in { multiclass RVVVLEBuiltin types> { diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlb.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlb.c new file mode 100644 index 000000000000000..0c245940a483355 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlb.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_th_vlb_v_i8m1(const int8_t *base, size_t vl) { + return __riscv_vlb_v_i8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_th_vlb_v_i8m2(const int8_t *base, size_t vl) { + return __riscv_vlb_v_i8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_th_vlb_v_i8m4(const int8_t *base, size_t vl) { + return __riscv_vlb_v_i8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_th_vlb_v_i8m8(const int8_t *base, size_t vl) { + return __riscv_vlb_v_i8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_th_vlb_v_i16m1(const int16_t *base, size_t vl) { + return __riscv_vlb_v_i16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_th_vlb_v_i16m2(const int16_t *base, size_t vl) { + return __riscv_vlb_v_i16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_th_vlb_v_i16m4(const int16_t *base, size_t vl) { + return __riscv_vlb_v_i16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_th_vlb_v_i16m8(const int16_t *base, size_t vl) { + return __riscv_vlb_v_i16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vlb_v_i32m1(const int32_t *base, size_t vl) { + return __riscv_vlb_v_i32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vlb_v_i32m2(const int32_t *base, size_t vl) { + return __riscv_vlb_v_i32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vlb_v_i32m4(const int32_t *base, size_t vl) { + return __riscv_vlb_v_i32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_th_vlb_v_i32m8(const int32_t *base, size_t vl) { + return __riscv_vlb_v_i32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_th_vlb_v_i64m1(const int64_t *base, size_t vl) { + return __riscv_vlb_v_i64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_th_vlb_v_i64m2(const int64_t *base, size_t vl) { + return __riscv_vlb_v_i64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_th_vlb_v_i64m4(const int64_t *base, size_t vl) { + return __riscv_vlb_v_i64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlb_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlb.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_th_vlb_v_i64m8(const int64_t *base, size_t vl) { + return __riscv_vlb_v_i64m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlbu.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlbu.c new file mode 100644 index 000000000000000..01b8e6c369a6a6c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlbu.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_th_vlbu_v_u8m1(const uint8_t *base, size_t vl) { + return __riscv_vlbu_v_u8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_th_vlbu_v_u8m2(const uint8_t *base, size_t vl) { + return __riscv_vlbu_v_u8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_th_vlbu_v_u8m4(const uint8_t *base, size_t vl) { + return __riscv_vlbu_v_u8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_th_vlbu_v_u8m8(const uint8_t *base, size_t vl) { + return __riscv_vlbu_v_u8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_th_vlbu_v_u16m1(const uint16_t *base, size_t vl) { + return __riscv_vlbu_v_u16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_th_vlbu_v_u16m2(const uint16_t *base, size_t vl) { + return __riscv_vlbu_v_u16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_th_vlbu_v_u16m4(const uint16_t *base, size_t vl) { + return __riscv_vlbu_v_u16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_th_vlbu_v_u16m8(const uint16_t *base, size_t vl) { + return __riscv_vlbu_v_u16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vlbu_v_u32m1(const uint32_t *base, size_t vl) { + return __riscv_vlbu_v_u32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vlbu_v_u32m2(const uint32_t *base, size_t vl) { + return __riscv_vlbu_v_u32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vlbu_v_u32m4(const uint32_t *base, size_t vl) { + return __riscv_vlbu_v_u32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_th_vlbu_v_u32m8(const uint32_t *base, size_t vl) { + return __riscv_vlbu_v_u32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_th_vlbu_v_u64m1(const uint64_t *base, size_t vl) { + return __riscv_vlbu_v_u64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_th_vlbu_v_u64m2(const uint64_t *base, size_t vl) { + return __riscv_vlbu_v_u64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_th_vlbu_v_u64m4(const uint64_t *base, size_t vl) { + return __riscv_vlbu_v_u64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlbu_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlbu.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_th_vlbu_v_u64m8(const uint64_t *base, size_t vl) { + return __riscv_vlbu_v_u64m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle16.c new file mode 100644 index 000000000000000..76eac2e825d02d7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle16.c @@ -0,0 +1,126 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_f16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4f16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_th_vle16_v_f16m1(const _Float16 *base, size_t vl) { + return __riscv_vle16_v_f16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_f16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8f16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_th_vle16_v_f16m2(const _Float16 *base, size_t vl) { + return __riscv_vle16_v_f16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_f16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16f16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_th_vle16_v_f16m4(const _Float16 *base, size_t vl) { + return __riscv_vle16_v_f16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_f16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv32f16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_th_vle16_v_f16m8(const _Float16 *base, size_t vl) { + return __riscv_vle16_v_f16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_th_vle16_v_i16m1(const int16_t *base, size_t vl) { + return __riscv_vle16_v_i16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_th_vle16_v_i16m2(const int16_t *base, size_t vl) { + return __riscv_vle16_v_i16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_th_vle16_v_i16m4(const int16_t *base, size_t vl) { + return __riscv_vle16_v_i16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_th_vle16_v_i16m8(const int16_t *base, size_t vl) { + return __riscv_vle16_v_i16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_th_vle16_v_u16m1(const uint16_t *base, size_t vl) { + return __riscv_vle16_v_u16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_th_vle16_v_u16m2(const uint16_t *base, size_t vl) { + return __riscv_vle16_v_u16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_th_vle16_v_u16m4(const uint16_t *base, size_t vl) { + return __riscv_vle16_v_u16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle16_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_th_vle16_v_u16m8(const uint16_t *base, size_t vl) { + return __riscv_vle16_v_u16m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle32.c new file mode 100644 index 000000000000000..fd7ff33dcbd2277 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle32.c @@ -0,0 +1,126 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_f32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv2f32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_th_vle32_v_f32m1(const float *base, size_t vl) { + return __riscv_vle32_v_f32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_f32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4f32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_th_vle32_v_f32m2(const float *base, size_t vl) { + return __riscv_vle32_v_f32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_f32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8f32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_th_vle32_v_f32m4(const float *base, size_t vl) { + return __riscv_vle32_v_f32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_f32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16f32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_th_vle32_v_f32m8(const float *base, size_t vl) { + return __riscv_vle32_v_f32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vle32_v_i32m1(const int32_t *base, size_t vl) { + return __riscv_vle32_v_i32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vle32_v_i32m2(const int32_t *base, size_t vl) { + return __riscv_vle32_v_i32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vle32_v_i32m4(const int32_t *base, size_t vl) { + return __riscv_vle32_v_i32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_th_vle32_v_i32m8(const int32_t *base, size_t vl) { + return __riscv_vle32_v_i32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vle32_v_u32m1(const uint32_t *base, size_t vl) { + return __riscv_vle32_v_u32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vle32_v_u32m2(const uint32_t *base, size_t vl) { + return __riscv_vle32_v_u32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vle32_v_u32m4(const uint32_t *base, size_t vl) { + return __riscv_vle32_v_u32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle32_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_th_vle32_v_u32m8(const uint32_t *base, size_t vl) { + return __riscv_vle32_v_u32m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle64.c new file mode 100644 index 000000000000000..4964b037a53cc22 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle64.c @@ -0,0 +1,126 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_f64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv1f64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_th_vle64_v_f64m1(const double *base, size_t vl) { + return __riscv_vle64_v_f64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_f64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv2f64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_th_vle64_v_f64m2(const double *base, size_t vl) { + return __riscv_vle64_v_f64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_f64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4f64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_th_vle64_v_f64m4(const double *base, size_t vl) { + return __riscv_vle64_v_f64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_f64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8f64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_th_vle64_v_f64m8(const double *base, size_t vl) { + return __riscv_vle64_v_f64m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_th_vle64_v_i64m1(const int64_t *base, size_t vl) { + return __riscv_vle64_v_i64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_th_vle64_v_i64m2(const int64_t *base, size_t vl) { + return __riscv_vle64_v_i64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_th_vle64_v_i64m4(const int64_t *base, size_t vl) { + return __riscv_vle64_v_i64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_th_vle64_v_i64m8(const int64_t *base, size_t vl) { + return __riscv_vle64_v_i64m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_th_vle64_v_u64m1(const uint64_t *base, size_t vl) { + return __riscv_vle64_v_u64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_th_vle64_v_u64m2(const uint64_t *base, size_t vl) { + return __riscv_vle64_v_u64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_th_vle64_v_u64m4(const uint64_t *base, size_t vl) { + return __riscv_vle64_v_u64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle64_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_th_vle64_v_u64m8(const uint64_t *base, size_t vl) { + return __riscv_vle64_v_u64m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle8.c new file mode 100644 index 000000000000000..7d82425872bfc67 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vle8.c @@ -0,0 +1,86 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_th_vle8_v_i8m1(const int8_t *base, size_t vl) { + return __riscv_vle8_v_i8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_th_vle8_v_i8m2(const int8_t *base, size_t vl) { + return __riscv_vle8_v_i8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_th_vle8_v_i8m4(const int8_t *base, size_t vl) { + return __riscv_vle8_v_i8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_th_vle8_v_i8m8(const int8_t *base, size_t vl) { + return __riscv_vle8_v_i8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_th_vle8_v_u8m1(const uint8_t *base, size_t vl) { + return __riscv_vle8_v_u8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_th_vle8_v_u8m2(const uint8_t *base, size_t vl) { + return __riscv_vle8_v_u8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_th_vle8_v_u8m4(const uint8_t *base, size_t vl) { + return __riscv_vle8_v_u8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vle8_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vle.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_th_vle8_v_u8m8(const uint8_t *base, size_t vl) { + return __riscv_vle8_v_u8m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlh.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlh.c new file mode 100644 index 000000000000000..4f35bf37532f7f1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlh.c @@ -0,0 +1,167 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_th_vlh_v_i8m1(const int8_t *base, size_t vl) { + return __riscv_vlh_v_i8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_th_vlh_v_i8m2(const int8_t *base, size_t vl) { + return __riscv_vlh_v_i8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_th_vlh_v_i8m4(const int8_t *base, size_t vl) { + return __riscv_vlh_v_i8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_th_vlh_v_i8m8(const int8_t *base, size_t vl) { + return __riscv_vlh_v_i8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_th_vlh_v_i16m1(const int16_t *base, size_t vl) { + return __riscv_vlh_v_i16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_th_vlh_v_i16m2(const int16_t *base, size_t vl) { + return __riscv_vlh_v_i16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_th_vlh_v_i16m4(const int16_t *base, size_t vl) { + return __riscv_vlh_v_i16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_th_vlh_v_i16m8(const int16_t *base, size_t vl) { + return __riscv_vlh_v_i16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vlh_v_i32m1(const int32_t *base, size_t vl) { + return __riscv_vlh_v_i32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vlh_v_i32m2(const int32_t *base, size_t vl) { + return __riscv_vlh_v_i32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vlh_v_i32m4(const int32_t *base, size_t vl) { + return __riscv_vlh_v_i32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_th_vlh_v_i32m8(const int32_t *base, size_t vl) { + return __riscv_vlh_v_i32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_th_vlh_v_i64m1(const int64_t *base, size_t vl) { + return __riscv_vlh_v_i64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_th_vlh_v_i64m2(const int64_t *base, size_t vl) { + return __riscv_vlh_v_i64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_th_vlh_v_i64m4(const int64_t *base, size_t vl) { + return __riscv_vlh_v_i64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlh_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlh.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_th_vlh_v_i64m8(const int64_t *base, size_t vl) { + return __riscv_vlh_v_i64m8(base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlhu.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlhu.c new file mode 100644 index 000000000000000..1427896ef00983b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlhu.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_th_vlhu_v_u8m1(const uint8_t *base, size_t vl) { + return __riscv_vlhu_v_u8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_th_vlhu_v_u8m2(const uint8_t *base, size_t vl) { + return __riscv_vlhu_v_u8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_th_vlhu_v_u8m4(const uint8_t *base, size_t vl) { + return __riscv_vlhu_v_u8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_th_vlhu_v_u8m8(const uint8_t *base, size_t vl) { + return __riscv_vlhu_v_u8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_th_vlhu_v_u16m1(const uint16_t *base, size_t vl) { + return __riscv_vlhu_v_u16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_th_vlhu_v_u16m2(const uint16_t *base, size_t vl) { + return __riscv_vlhu_v_u16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_th_vlhu_v_u16m4(const uint16_t *base, size_t vl) { + return __riscv_vlhu_v_u16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_th_vlhu_v_u16m8(const uint16_t *base, size_t vl) { + return __riscv_vlhu_v_u16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vlhu_v_u32m1(const uint32_t *base, size_t vl) { + return __riscv_vlhu_v_u32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vlhu_v_u32m2(const uint32_t *base, size_t vl) { + return __riscv_vlhu_v_u32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vlhu_v_u32m4(const uint32_t *base, size_t vl) { + return __riscv_vlhu_v_u32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_th_vlhu_v_u32m8(const uint32_t *base, size_t vl) { + return __riscv_vlhu_v_u32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_th_vlhu_v_u64m1(const uint64_t *base, size_t vl) { + return __riscv_vlhu_v_u64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_th_vlhu_v_u64m2(const uint64_t *base, size_t vl) { + return __riscv_vlhu_v_u64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_th_vlhu_v_u64m4(const uint64_t *base, size_t vl) { + return __riscv_vlhu_v_u64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlhu_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlhu.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_th_vlhu_v_u64m8(const uint64_t *base, size_t vl) { + return __riscv_vlhu_v_u64m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlw.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlw.c new file mode 100644 index 000000000000000..f26dbb5d41060b3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlw.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_th_vlw_v_i8m1(const int8_t *base, size_t vl) { + return __riscv_vlw_v_i8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_th_vlw_v_i8m2(const int8_t *base, size_t vl) { + return __riscv_vlw_v_i8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_th_vlw_v_i8m4(const int8_t *base, size_t vl) { + return __riscv_vlw_v_i8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_th_vlw_v_i8m8(const int8_t *base, size_t vl) { + return __riscv_vlw_v_i8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_th_vlw_v_i16m1(const int16_t *base, size_t vl) { + return __riscv_vlw_v_i16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_th_vlw_v_i16m2(const int16_t *base, size_t vl) { + return __riscv_vlw_v_i16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_th_vlw_v_i16m4(const int16_t *base, size_t vl) { + return __riscv_vlw_v_i16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_th_vlw_v_i16m8(const int16_t *base, size_t vl) { + return __riscv_vlw_v_i16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_th_vlw_v_i32m1(const int32_t *base, size_t vl) { + return __riscv_vlw_v_i32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_th_vlw_v_i32m2(const int32_t *base, size_t vl) { + return __riscv_vlw_v_i32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_th_vlw_v_i32m4(const int32_t *base, size_t vl) { + return __riscv_vlw_v_i32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_th_vlw_v_i32m8(const int32_t *base, size_t vl) { + return __riscv_vlw_v_i32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_th_vlw_v_i64m1(const int64_t *base, size_t vl) { + return __riscv_vlw_v_i64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_th_vlw_v_i64m2(const int64_t *base, size_t vl) { + return __riscv_vlw_v_i64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_th_vlw_v_i64m4(const int64_t *base, size_t vl) { + return __riscv_vlw_v_i64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlw_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlw.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_th_vlw_v_i64m8(const int64_t *base, size_t vl) { + return __riscv_vlw_v_i64m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlwu.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlwu.c new file mode 100644 index 000000000000000..790cc2d074444d5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vlwu.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv8i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_th_vlwu_v_u8m1(const uint8_t *base, size_t vl) { + return __riscv_vlwu_v_u8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv16i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_th_vlwu_v_u8m2(const uint8_t *base, size_t vl) { + return __riscv_vlwu_v_u8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv32i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_th_vlwu_v_u8m4(const uint8_t *base, size_t vl) { + return __riscv_vlwu_v_u8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv64i8.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_th_vlwu_v_u8m8(const uint8_t *base, size_t vl) { + return __riscv_vlwu_v_u8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv4i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_th_vlwu_v_u16m1(const uint16_t *base, size_t vl) { + return __riscv_vlwu_v_u16m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv8i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_th_vlwu_v_u16m2(const uint16_t *base, size_t vl) { + return __riscv_vlwu_v_u16m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv16i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_th_vlwu_v_u16m4(const uint16_t *base, size_t vl) { + return __riscv_vlwu_v_u16m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv32i16.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_th_vlwu_v_u16m8(const uint16_t *base, size_t vl) { + return __riscv_vlwu_v_u16m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv2i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_th_vlwu_v_u32m1(const uint32_t *base, size_t vl) { + return __riscv_vlwu_v_u32m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv4i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_th_vlwu_v_u32m2(const uint32_t *base, size_t vl) { + return __riscv_vlwu_v_u32m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv8i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_th_vlwu_v_u32m4(const uint32_t *base, size_t vl) { + return __riscv_vlwu_v_u32m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv16i32.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_th_vlwu_v_u32m8(const uint32_t *base, size_t vl) { + return __riscv_vlwu_v_u32m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv1i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_th_vlwu_v_u64m1(const uint64_t *base, size_t vl) { + return __riscv_vlwu_v_u64m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv2i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_th_vlwu_v_u64m2(const uint64_t *base, size_t vl) { + return __riscv_vlwu_v_u64m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv4i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_th_vlwu_v_u64m4(const uint64_t *base, size_t vl) { + return __riscv_vlwu_v_u64m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_th_vlwu_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vlwu.nxv8i64.i64( poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_th_vlwu_v_u64m8(const uint64_t *base, size_t vl) { + return __riscv_vlwu_v_u64m8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsb.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsb.c new file mode 100644 index 000000000000000..10aa7248b8f0dbc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsb.c @@ -0,0 +1,327 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i8m1(int8_t *base, vint8m1_t value, size_t vl) { + return __riscv_vsb_v_i8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i8m2(int8_t *base, vint8m2_t value, size_t vl) { + return __riscv_vsb_v_i8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i8m4(int8_t *base, vint8m4_t value, size_t vl) { + return __riscv_vsb_v_i8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i8m8(int8_t *base, vint8m8_t value, size_t vl) { + return __riscv_vsb_v_i8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i16m1(int16_t *base, vint16m1_t value, size_t vl) { + return __riscv_vsb_v_i16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i16m2(int16_t *base, vint16m2_t value, size_t vl) { + return __riscv_vsb_v_i16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i16m4(int16_t *base, vint16m4_t value, size_t vl) { + return __riscv_vsb_v_i16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i16m8(int16_t *base, vint16m8_t value, size_t vl) { + return __riscv_vsb_v_i16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) { + return __riscv_vsb_v_i32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) { + return __riscv_vsb_v_i32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) { + return __riscv_vsb_v_i32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) { + return __riscv_vsb_v_i32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) { + return __riscv_vsb_v_i64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) { + return __riscv_vsb_v_i64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) { + return __riscv_vsb_v_i64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) { + return __riscv_vsb_v_i64m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u8m1(uint8_t *base, vuint8m1_t value, size_t vl) { + return __riscv_vsb_v_u8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u8m2(uint8_t *base, vuint8m2_t value, size_t vl) { + return __riscv_vsb_v_u8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u8m4(uint8_t *base, vuint8m4_t value, size_t vl) { + return __riscv_vsb_v_u8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u8m8(uint8_t *base, vuint8m8_t value, size_t vl) { + return __riscv_vsb_v_u8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u16m1(uint16_t *base, vuint16m1_t value, size_t vl) { + return __riscv_vsb_v_u16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u16m2(uint16_t *base, vuint16m2_t value, size_t vl) { + return __riscv_vsb_v_u16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u16m4(uint16_t *base, vuint16m4_t value, size_t vl) { + return __riscv_vsb_v_u16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u16m8(uint16_t *base, vuint16m8_t value, size_t vl) { + return __riscv_vsb_v_u16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) { + return __riscv_vsb_v_u32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) { + return __riscv_vsb_v_u32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) { + return __riscv_vsb_v_u32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) { + return __riscv_vsb_v_u32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) { + return __riscv_vsb_v_u64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) { + return __riscv_vsb_v_u64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) { + return __riscv_vsb_v_u64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsb_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsb.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsb_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) { + return __riscv_vsb_v_u64m8(base, value, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse16.c new file mode 100644 index 000000000000000..653d88cb48efd5c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse16.c @@ -0,0 +1,126 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_f16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4f16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_f16m1(_Float16 *base, vfloat16m1_t value, size_t vl) { + return __riscv_vse16_v_f16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_f16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8f16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_f16m2(_Float16 *base, vfloat16m2_t value, size_t vl) { + return __riscv_vse16_v_f16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_f16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16f16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_f16m4(_Float16 *base, vfloat16m4_t value, size_t vl) { + return __riscv_vse16_v_f16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_f16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv32f16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_f16m8(_Float16 *base, vfloat16m8_t value, size_t vl) { + return __riscv_vse16_v_f16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_i16m1(int16_t *base, vint16m1_t value, size_t vl) { + return __riscv_vse16_v_i16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_i16m2(int16_t *base, vint16m2_t value, size_t vl) { + return __riscv_vse16_v_i16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_i16m4(int16_t *base, vint16m4_t value, size_t vl) { + return __riscv_vse16_v_i16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_i16m8(int16_t *base, vint16m8_t value, size_t vl) { + return __riscv_vse16_v_i16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_u16m1(uint16_t *base, vuint16m1_t value, size_t vl) { + return __riscv_vse16_v_u16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_u16m2(uint16_t *base, vuint16m2_t value, size_t vl) { + return __riscv_vse16_v_u16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_u16m4(uint16_t *base, vuint16m4_t value, size_t vl) { + return __riscv_vse16_v_u16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse16_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse16_v_u16m8(uint16_t *base, vuint16m8_t value, size_t vl) { + return __riscv_vse16_v_u16m8(base, value, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse32.c new file mode 100644 index 000000000000000..840117eac0046cc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse32.c @@ -0,0 +1,126 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_f32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv2f32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_f32m1(float *base, vfloat32m1_t value, size_t vl) { + return __riscv_vse32_v_f32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_f32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4f32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_f32m2(float *base, vfloat32m2_t value, size_t vl) { + return __riscv_vse32_v_f32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_f32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8f32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_f32m4(float *base, vfloat32m4_t value, size_t vl) { + return __riscv_vse32_v_f32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_f32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16f32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_f32m8(float *base, vfloat32m8_t value, size_t vl) { + return __riscv_vse32_v_f32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) { + return __riscv_vse32_v_i32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) { + return __riscv_vse32_v_i32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) { + return __riscv_vse32_v_i32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) { + return __riscv_vse32_v_i32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) { + return __riscv_vse32_v_u32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) { + return __riscv_vse32_v_u32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) { + return __riscv_vse32_v_u32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse32_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse32_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) { + return __riscv_vse32_v_u32m8(base, value, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse64.c new file mode 100644 index 000000000000000..14f52a22de00610 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse64.c @@ -0,0 +1,126 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_f64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv1f64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_f64m1(double *base, vfloat64m1_t value, size_t vl) { + return __riscv_vse64_v_f64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_f64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv2f64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_f64m2(double *base, vfloat64m2_t value, size_t vl) { + return __riscv_vse64_v_f64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_f64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4f64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_f64m4(double *base, vfloat64m4_t value, size_t vl) { + return __riscv_vse64_v_f64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_f64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8f64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_f64m8(double *base, vfloat64m8_t value, size_t vl) { + return __riscv_vse64_v_f64m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) { + return __riscv_vse64_v_i64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) { + return __riscv_vse64_v_i64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) { + return __riscv_vse64_v_i64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) { + return __riscv_vse64_v_i64m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) { + return __riscv_vse64_v_u64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) { + return __riscv_vse64_v_u64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) { + return __riscv_vse64_v_u64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse64_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse64_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) { + return __riscv_vse64_v_u64m8(base, value, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse8.c new file mode 100644 index 000000000000000..5d3f62cb19431a8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vse8.c @@ -0,0 +1,86 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_i8m1(int8_t *base, vint8m1_t value, size_t vl) { + return __riscv_vse8_v_i8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_i8m2(int8_t *base, vint8m2_t value, size_t vl) { + return __riscv_vse8_v_i8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_i8m4(int8_t *base, vint8m4_t value, size_t vl) { + return __riscv_vse8_v_i8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_i8m8(int8_t *base, vint8m8_t value, size_t vl) { + return __riscv_vse8_v_i8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_u8m1(uint8_t *base, vuint8m1_t value, size_t vl) { + return __riscv_vse8_v_u8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_u8m2(uint8_t *base, vuint8m2_t value, size_t vl) { + return __riscv_vse8_v_u8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_u8m4(uint8_t *base, vuint8m4_t value, size_t vl) { + return __riscv_vse8_v_u8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vse8_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vse.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vse8_v_u8m8(uint8_t *base, vuint8m8_t value, size_t vl) { + return __riscv_vse8_v_u8m8(base, value, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsh.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsh.c new file mode 100644 index 000000000000000..73d2d68451069a6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsh.c @@ -0,0 +1,326 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i8m1(int8_t *base, vint8m1_t value, size_t vl) { + return __riscv_vsh_v_i8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i8m2(int8_t *base, vint8m2_t value, size_t vl) { + return __riscv_vsh_v_i8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i8m4(int8_t *base, vint8m4_t value, size_t vl) { + return __riscv_vsh_v_i8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i8m8(int8_t *base, vint8m8_t value, size_t vl) { + return __riscv_vsh_v_i8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i16m1(int16_t *base, vint16m1_t value, size_t vl) { + return __riscv_vsh_v_i16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i16m2(int16_t *base, vint16m2_t value, size_t vl) { + return __riscv_vsh_v_i16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i16m4(int16_t *base, vint16m4_t value, size_t vl) { + return __riscv_vsh_v_i16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i16m8(int16_t *base, vint16m8_t value, size_t vl) { + return __riscv_vsh_v_i16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) { + return __riscv_vsh_v_i32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) { + return __riscv_vsh_v_i32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) { + return __riscv_vsh_v_i32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) { + return __riscv_vsh_v_i32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) { + return __riscv_vsh_v_i64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) { + return __riscv_vsh_v_i64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) { + return __riscv_vsh_v_i64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) { + return __riscv_vsh_v_i64m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u8m1(uint8_t *base, vuint8m1_t value, size_t vl) { + return __riscv_vsh_v_u8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u8m2(uint8_t *base, vuint8m2_t value, size_t vl) { + return __riscv_vsh_v_u8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u8m4(uint8_t *base, vuint8m4_t value, size_t vl) { + return __riscv_vsh_v_u8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u8m8(uint8_t *base, vuint8m8_t value, size_t vl) { + return __riscv_vsh_v_u8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u16m1(uint16_t *base, vuint16m1_t value, size_t vl) { + return __riscv_vsh_v_u16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u16m2(uint16_t *base, vuint16m2_t value, size_t vl) { + return __riscv_vsh_v_u16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u16m4(uint16_t *base, vuint16m4_t value, size_t vl) { + return __riscv_vsh_v_u16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u16m8(uint16_t *base, vuint16m8_t value, size_t vl) { + return __riscv_vsh_v_u16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) { + return __riscv_vsh_v_u32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) { + return __riscv_vsh_v_u32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) { + return __riscv_vsh_v_u32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) { + return __riscv_vsh_v_u32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) { + return __riscv_vsh_v_u64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) { + return __riscv_vsh_v_u64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) { + return __riscv_vsh_v_u64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsh_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsh.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsh_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) { + return __riscv_vsh_v_u64m8(base, value, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsw.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsw.c new file mode 100644 index 000000000000000..823fc82a29ded40 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/wrappers/vsw.c @@ -0,0 +1,326 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i8m1(int8_t *base, vint8m1_t value, size_t vl) { + return __riscv_vsw_v_i8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i8m2(int8_t *base, vint8m2_t value, size_t vl) { + return __riscv_vsw_v_i8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i8m4(int8_t *base, vint8m4_t value, size_t vl) { + return __riscv_vsw_v_i8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i8m8(int8_t *base, vint8m8_t value, size_t vl) { + return __riscv_vsw_v_i8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i16m1(int16_t *base, vint16m1_t value, size_t vl) { + return __riscv_vsw_v_i16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i16m2(int16_t *base, vint16m2_t value, size_t vl) { + return __riscv_vsw_v_i16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i16m4(int16_t *base, vint16m4_t value, size_t vl) { + return __riscv_vsw_v_i16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i16m8(int16_t *base, vint16m8_t value, size_t vl) { + return __riscv_vsw_v_i16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) { + return __riscv_vsw_v_i32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) { + return __riscv_vsw_v_i32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) { + return __riscv_vsw_v_i32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) { + return __riscv_vsw_v_i32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) { + return __riscv_vsw_v_i64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) { + return __riscv_vsw_v_i64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) { + return __riscv_vsw_v_i64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_i64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) { + return __riscv_vsw_v_i64m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u8m1(uint8_t *base, vuint8m1_t value, size_t vl) { + return __riscv_vsw_v_u8m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv16i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u8m2(uint8_t *base, vuint8m2_t value, size_t vl) { + return __riscv_vsw_v_u8m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv32i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u8m4(uint8_t *base, vuint8m4_t value, size_t vl) { + return __riscv_vsw_v_u8m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv64i8.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u8m8(uint8_t *base, vuint8m8_t value, size_t vl) { + return __riscv_vsw_v_u8m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u16m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv4i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u16m1(uint16_t *base, vuint16m1_t value, size_t vl) { + return __riscv_vsw_v_u16m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u16m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u16m2(uint16_t *base, vuint16m2_t value, size_t vl) { + return __riscv_vsw_v_u16m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u16m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv16i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u16m4(uint16_t *base, vuint16m4_t value, size_t vl) { + return __riscv_vsw_v_u16m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u16m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv32i16.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u16m8(uint16_t *base, vuint16m8_t value, size_t vl) { + return __riscv_vsw_v_u16m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv2i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) { + return __riscv_vsw_v_u32m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u32m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv4i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) { + return __riscv_vsw_v_u32m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u32m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) { + return __riscv_vsw_v_u32m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u32m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv16i32.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) { + return __riscv_vsw_v_u32m8(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u64m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv1i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) { + return __riscv_vsw_v_u64m1(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u64m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv2i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) { + return __riscv_vsw_v_u64m2(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u64m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv4i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) { + return __riscv_vsw_v_u64m4(base, value, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsw_v_u64m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsw.nxv8i64.i64( [[VALUE]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsw_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) { + return __riscv_vsw_v_u64m8(base, value, vl); +}