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XFree86-fix-07-s3trio64v2gx+netfinity.patch
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XFree86-fix-07-s3trio64v2gx+netfinity.patch
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--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h.fix Mon Jul 2 19:46:04 2001
+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h Mon Jan 21 08:18:14 2002
@@ -251,7 +251,7 @@
#define WaitQueue(v) \
if(!(pS3->PCIRetry)) { \
mem_barrier(); \
- while(inb(GP_STAT) & (0x0100 >> (v))); \
+ while(mmio_INB_GP_STAT() & (0x0100 >> (v))); \
}
#define CMD_REG_WIDTH 0x200 /* select 32bit command register */
--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_accel.c.fix Sun Oct 28 12:33:44 2001
+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_accel.c Mon Jan 21 08:22:08 2002
@@ -46,6 +46,7 @@
static void S3Sync(ScrnInfoPtr pScrn)
{
+ S3Ptr pS3 = S3PTR(pScrn);
WaitIdle();
}
@@ -64,9 +65,7 @@
static void S3SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y,
int w, int h)
{
-#ifdef S3_NEWMMIO
S3Ptr pS3 = S3PTR(pScrn);
-#endif
WaitQueue(5);
SET_CURPT((short)x, (short)y);
@@ -303,9 +302,8 @@
int major, int minor,
int err, int len, int octant)
{
-#ifdef S3_NEWMMIO
S3Ptr pS3 = S3PTR(pScrn);
-#endif
+
unsigned short cmd;
int error, e1, e2;
--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_dga.c.fix Mon Jul 2 19:46:04 2001
+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_dga.c Mon Jan 21 08:18:14 2002
@@ -314,5 +314,6 @@
static void S3_Sync(ScrnInfoPtr pScrn)
{
+ S3Ptr pS3 = S3PTR(pScrn);
WaitIdle();
}
--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_driver.c.fix Thu Dec 27 07:24:19 2001
+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_driver.c Mon Jan 21 08:18:14 2002
@@ -1569,7 +1569,20 @@
outb(0x3c6, 0x00);
- outw(SUBSYS_CNTL, 0x8000 | 0x1000);
+/*
+* XXX: resetting the Trio64V2/GX causes trouble with the SGRAM memory bus
+* (gets out of sync? same as setting CR88_6) which I don't know to fix,
+* so better not reset that chip and cross fingers...
+* This happens at least for some IBM Netfinity boxes (e.g. 7000M10) with 1MB SGRAM.
+*/
+ if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX) {
+ outb(vgaCRIndex, 0x36);
+ tmp = inb(vgaCRReg);
+ if ((tmp & 0x0c) != 0x04) /* no SGRAM */
+ outw(SUBSYS_CNTL, 0x8000 | 0x1000);
+ }
+ else /* do normal reset for S3 chip... */
+ outw(SUBSYS_CNTL, 0x8000 | 0x1000);
outw(SUBSYS_CNTL, 0x4000 | 0x1000);
inw(SUBSYS_STAT);
@@ -1603,6 +1616,12 @@
WaitQueue(5);
SET_SCISSORS(0, 0, pS3->s3ScissR, pS3->s3ScissB);
+ if(pS3->s3Bpp > 2) {
+ if(pS3->S3NewMMIO)
+ SET_MULT_MISC(0x200);
+ else
+ SET_MULT_MISC(0);
+ }
outb(vgaCRIndex, 0x6f);
--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_reg.h.fix Mon Jul 2 19:46:04 2001
+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_reg.h Mon Jan 21 08:18:14 2002
@@ -148,10 +148,23 @@
outw(p, (n) >> 16); \
} else outw(p, n)
+/*
+ * mmio reads from GP_STAT
+ */
+#if !defined(__alpha__)
+#define mmio_INB_GP_STAT() (*(((volatile unsigned char*)pS3->MMIOBase)+GP_STAT) & 0xff)
+#define mmio_INW_GP_STAT() (*(((volatile unsigned short*)pS3->MMIOBase)+GP_STAT/2))
+#else
+#define mmio_INB_GP_STAT() inb(GP_STAT)
+#define mmio_INW_GP_STAT() inw(GP_STAT)
+#endif
#define WaitIdle() do { \
mem_barrier(); \
- while(inw(GP_STAT) & GPBUSY); \
+ if (pS3->S3NewMMIO) \
+ while(mmio_INW_GP_STAT() & GPBUSY); \
+ else \
+ while(inw(GP_STAT) & GPBUSY); \
} while(0)
@@ -184,9 +197,12 @@
#define CMD_REG_WIDTH 0x0000
-#define WaitQueue(n) do { \
+#define WaitQueue(n) do { \
mem_barrier(); \
- while(inb(GP_STAT) & (0x0100 >> (n))); \
+ if (pS3->S3NewMMIO) \
+ while(mmio_INB_GP_STAT() & (0x0100 >> (n))); \
+ else \
+ while(inb(GP_STAT) & (0x0100 >> (n))); \
} while (0)
#define WaitQueue16_32(n16,n32) \