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I suggest changing the default with-isa-spec to support the latest version 20191213, and change the default march to rv64gc instead of rv64imafdc.
Reasons:
This should keep compatibility with programs using csrr/csrw/fence.i, as the definition of G is IMAFDZicsr Zifencei which includes all of the aforementioned instructions.
This change is in line with the specifications of popular RISC-V cores, including the default rocketchip.
The current default for with-isa-spec option introduced with commit 44fedc5e1a8f202248fc0f2b39c84226d8f3d1e6 is v2.2. The commit message says "once we bump to GCC 12 we bump that to 20191213". The gcc submodule has long been bumped to 12.
If the current toolchain has trouble correctly supporting this configuration, can you point me some of the issues so I can try to help iron them out?
The text was updated successfully, but these errors were encountered:
I suggest changing the default
with-isa-spec
to support the latest version20191213
, and change the defaultmarch
torv64gc
instead ofrv64imafdc
.Reasons:
csrr
/csrw
/fence.i
, as the definition ofG
isIMAFDZicsr Zifencei
which includes all of the aforementioned instructions.rocketchip
.with-isa-spec
option introduced with commit44fedc5e1a8f202248fc0f2b39c84226d8f3d1e6
isv2.2
. The commit message says "once we bump to GCC 12 we bump that to 20191213". The gcc submodule has long been bumped to 12.If the current toolchain has trouble correctly supporting this configuration, can you point me some of the issues so I can try to help iron them out?
The text was updated successfully, but these errors were encountered: