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xrun -r sp_default +DUMPWAVE=1 +TESTCASE=/home/icer/work/test/e203_hbirdv2-master/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32um-p-div +SIM_TOOL=xrun 2>&1 | tee rv32um-p-div/rv32um-p-div.log; cd /home/icer/work/test/e203_hbirdv2-master/vsim/run;
TOOL: xrun 20.09-s009: Started on Jan 27, 2024 at 21:16:47 CST
TOOL: xrun(64) 20.09-s009: Started on Jan 27, 2024 at 21:16:47 CST
xrun(64): 20.09-s009: (c) Copyright 1995-2021 Cadence Design Systems, Inc.
xrun: *N,NOSNPR: The default work directory (./xcelium.d/run.lnx8664.20.09.d) is missing. -r sp_default was used and a matching -snapshot sp_default scratch directory was found. xrun will imply the option -snapshot sp_default.
Loading snapshot worklib.sp_default:v .................... Done
SVSEED default: 1
xmsim: *W,RNDXCELON: A newer version of the SystemVerilog constraint solver is being used which has better support for array-solving, new solve-order mechanism, and seed stability enhancements..
xcelium> source /opt/rh/XCELIUM2009/tools/xcelium/files/xmsimrc
xcelium> run
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
TESTCASE= /home/icer/work/test/e203_hbirdv2-master/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32um-p-div
xrun used
xmsim: *W,PRUASZ: Unpacked array at "tb_top.itcm_mem" of 65536 elements exceeds limit of 16384 - not probed
Use 'probe -create -unpacked 65536 tb_top.itcm_mem' or 'setenv SHM_UNPACKED_LIMIT 65536' to adjust limit.
ITCM 0x00: 340510730001aa0d
ITCM 0x01: ff85051300002517
ITCM 0x02: 01f5222301e52023
ITCM 0x03: 040f416334202f73
ITCM 0x04: 4fa507ff02634fa1
ITCM 0x05: 0c634fad05ff0f63
ITCM 0x06: 0bff05634f8505ff
ITCM 0x07: 4f9d0dff00634f95
ITCM 0x16: 2f03f52505130000
ITCM 0x20: 2f8300052f03f065
??????????????????????????????????????????
??????????????????????????????????????????
{i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu}=00001000
muldiv_i_rs1=ffffffec
muldiv_i_rs2=00000006
golden_res=55555552
muldiv_o_wbck_wdat=fffffffd
??????????????????????????????????????????
xmsim: *F,ASRTST (../install/rtl/core/e203_exu_alu_muldiv.v,624): (time 93648 NS) Assertion tb_top.u_e203_soc_top.u_e203_subsys_top.u_e203_subsys_main.u_e203_cpu_top.u_e203_cpu.u_e203_core.u_e203_exu.u_e203_exu_alu.u_e203_exu_alu_muldiv.CHECK_GOLD_AND_ACTUAL_SAME has failed
Memory Usage - Current physical: 97.6M, Current virtual: 458.4M
CPU Usage - 0.6s system + 3.8s user = 4.3s total (100.0% cpu)
Simulation terminated via $fatal(2) at time 93648 NS + 6
../install/rtl/core/e203_exu_alu_muldiv.v:624 $fatal ("\n Error: Oops, This should never happen. \n");
xcelium> exit
TOOL: xrun(64) 20.09-s009: Exiting on Jan 27, 2024 at 21:16:50 CST (total: 00:00:03)
make[1]: Leaving directory `/home/icer/work/test/e203_hbirdv2-master/vsim/run'
The text was updated successfully, but these errors were encountered:
xrun -r sp_default +DUMPWAVE=1 +TESTCASE=/home/icer/work/test/e203_hbirdv2-master/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32um-p-div +SIM_TOOL=xrun 2>&1 | tee rv32um-p-div/rv32um-p-div.log; cd /home/icer/work/test/e203_hbirdv2-master/vsim/run;
TOOL: xrun 20.09-s009: Started on Jan 27, 2024 at 21:16:47 CST
TOOL: xrun(64) 20.09-s009: Started on Jan 27, 2024 at 21:16:47 CST
xrun(64): 20.09-s009: (c) Copyright 1995-2021 Cadence Design Systems, Inc.
xrun: *N,NOSNPR: The default work directory (./xcelium.d/run.lnx8664.20.09.d) is missing. -r sp_default was used and a matching -snapshot sp_default scratch directory was found. xrun will imply the option -snapshot sp_default.
Loading snapshot worklib.sp_default:v .................... Done
SVSEED default: 1
xmsim: *W,RNDXCELON: A newer version of the SystemVerilog constraint solver is being used which has better support for array-solving, new solve-order mechanism, and seed stability enhancements..
xcelium> source /opt/rh/XCELIUM2009/tools/xcelium/files/xmsimrc
xcelium> run
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
TESTCASE= /home/icer/work/test/e203_hbirdv2-master/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32um-p-div
xrun used
xmsim: *W,PRUASZ: Unpacked array at "tb_top.itcm_mem" of 65536 elements exceeds limit of 16384 - not probed
Use 'probe -create -unpacked 65536 tb_top.itcm_mem' or 'setenv SHM_UNPACKED_LIMIT 65536' to adjust limit.
ITCM 0x00: 340510730001aa0d
ITCM 0x01: ff85051300002517
ITCM 0x02: 01f5222301e52023
ITCM 0x03: 040f416334202f73
ITCM 0x04: 4fa507ff02634fa1
ITCM 0x05: 0c634fad05ff0f63
ITCM 0x06: 0bff05634f8505ff
ITCM 0x07: 4f9d0dff00634f95
ITCM 0x16: 2f03f52505130000
ITCM 0x20: 2f8300052f03f065
??????????????????????????????????????????
??????????????????????????????????????????
{i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu}=00001000
muldiv_i_rs1=ffffffec
muldiv_i_rs2=00000006
golden_res=55555552
muldiv_o_wbck_wdat=fffffffd
??????????????????????????????????????????
xmsim: *F,ASRTST (../install/rtl/core/e203_exu_alu_muldiv.v,624): (time 93648 NS) Assertion tb_top.u_e203_soc_top.u_e203_subsys_top.u_e203_subsys_main.u_e203_cpu_top.u_e203_cpu.u_e203_core.u_e203_exu.u_e203_exu_alu.u_e203_exu_alu_muldiv.CHECK_GOLD_AND_ACTUAL_SAME has failed
Memory Usage - Current physical: 97.6M, Current virtual: 458.4M
CPU Usage - 0.6s system + 3.8s user = 4.3s total (100.0% cpu)
Simulation terminated via $fatal(2) at time 93648 NS + 6
../install/rtl/core/e203_exu_alu_muldiv.v:624 $fatal ("\n Error: Oops, This should never happen. \n");
xcelium> exit
TOOL: xrun(64) 20.09-s009: Exiting on Jan 27, 2024 at 21:16:50 CST (total: 00:00:03)
make[1]: Leaving directory `/home/icer/work/test/e203_hbirdv2-master/vsim/run'
The text was updated successfully, but these errors were encountered: