{"payload":{"header_redesign_enabled":false,"results":[{"id":"533485896","archived":false,"color":"#427819","followers":3,"has_funding_file":false,"hl_name":"riscv-non-isa/riscv-cbqri","hl_trunc_description":"This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register…","language":"Makefile","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":533485896,"name":"riscv-cbqri","owner_id":89279762,"owner_login":"riscv-non-isa","updated_at":"2024-07-02T21:07:04.778Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":73,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ariscv-non-isa%252Friscv-cbqri%2B%2Blanguage%253AMakefile","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/riscv-non-isa/riscv-cbqri/star":{"post":"Pgr1keAPSj5L5uiAgJzcPa3xaJOovwcnAlFUgGI8SE2dDbeJfDA3BBNQluX1xL8NhujL174goTCHZ43OM6trzA"},"/riscv-non-isa/riscv-cbqri/unstar":{"post":"eJwWEeY9idVRcdpUu1xz3zbMvkHZYjji_LM6Qmij533-TH1k2Q-IE2y8dlzeh9MpjKD-gzeB8-Zv-W8kfCvpzg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"S-1tyVbeAQK5yjZ0pi2ZOBGgQiH3GMVHq3mW9bV7-o2Mudk_R4uGD36jvUIcoTHy3Z4t4ZL_VhUuFf5XobdWrQ"}}},"title":"Repository search results"}