{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":156304184,"defaultBranch":"master","name":"opensbi","ownerLogin":"riscv-software-src","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2018-11-06T00:50:48.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/89536631?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1722569190.0","currentOid":""},"activityList":{"items":[{"before":"ef4520b1c63fc2770b10d952a800f9734f861b0a","after":"c4940a9517486413cd676fc8032bb55f9d4e2778","ref":"refs/heads/master","pushedAt":"2024-08-27T05:25:34.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"platform: generic: Fix fw_platform_coldboot_harts_init() function\n\nIt is possible that the OpenSBI config DT node is present but\nthe \"cold-boot-harts\" DT property is not present. In this case,\nthe fw_platform_coldboot_harts_init() will do nothing which\nin-turn causes OpenSBI firmware hang at boot time.\n\nTo address the above issue, fallback to the default approach\nwhen the \"cold-boot-harts\" DT property is not present.\n\nFixes: 67ce5a763cfb (\"platform: generic: Add support for specify coldboot harts in DT\")\nSigned-off-by: Anup Patel ","shortMessageHtmlLink":"platform: generic: Fix fw_platform_coldboot_harts_init() function"}},{"before":"b0ad9e0bdd7804fad76dac4228b8a79e3c953310","after":"ef4520b1c63fc2770b10d952a800f9734f861b0a","ref":"refs/heads/master","pushedAt":"2024-08-24T09:21:29.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: Delete redundant `ulong`\n\nIn `csr_read_allowed` and `csr_write_allowed` macros, has already\nconverted second param to `ulong`. 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This is the case when building OpenSBI\nas a QEMU submodule:\n\n$ cat .git\ngitdir: ../../.git/modules/roms/opensbi\n\nAs a result, building OpenSBI tag v1.5.1 in QEMU will result in a binary\nthat will have \"OpenSBI v1.5\" as a banner.\n\nUse \"git rev-parse --git-dir\" instead of checking if '.git' is a dir to\ndetect if the current dir is a git repo.\n\nSigned-off-by: Daniel Henrique Barboza \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"Makefile: fix OPENSBI_VERSION_GIT build with submodules"}},{"before":"8cb7f89d7c6a8506597e7a60078928b86874ed7c","after":"70f3441452ea470fb01be660abdd05495e3b19fd","ref":"refs/heads/master","pushedAt":"2024-08-24T07:48:36.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sse: remove unused sse_inject_out() parameter\n\nThis parameters was a remnant of a previous version, remove it now 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(3)---------------------------+ |(5)----------------------------+\n | OP-TEE OS | | | U-Boot |\n +----------------------------+ | +-----------------------------+\n | |\n | v\n |(6)----------------------------+\n | | Linux |\n | +-----------------------------+\n\nAs OP-TEE OS has device-tree node fixups that need to be passed\nthrough to the next boot stages, e.g. the reserved memory node:\n\n reserved-memory {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n optee_core@f1000000 {\n no-map;\n reg = <0x0 0xf1000000 // OP-TEE OS base address\n 0x0 0x01000000>;\n };\n <...>\n };\n\nInstead of using 0x0 as the default value, allow identical next-arg1\nto be used by non-coldboot domain (i.e., untrusted domain) when the\nproperty is not provided.\n\nAlso, update the description of next-arg1 property in the document.\n\nSigned-off-by: Yu Chien Peter Lin \nReviewed-by: Alvin Chang \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: utils: fdt_domain: Use consistent device-tree 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To avoid using garbage\nvalues, check the result and return early if necessary.\n\nThis issue is not being hit because at the moment\nis_pmp_entry_mapped() is only being called from a single site with a\nvalid hardcoded value.\n\nSigned-off-by: Carlos López \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi: check result of pmp_get() in is_pmp_entry_mapped()"}},{"before":"a2807646a85878cb631cbc2b012cf888fc4427d7","after":"df997c6e55fe5940fd035097e6ecb5612aa95b4b","ref":"refs/heads/master","pushedAt":"2024-08-02T03:14:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"include: Adjust Sscofpmf mhpmevent mask for upper 8 bits\n\nCurrently, OpenSBI reserves the upper 16 bits in mhpmevent for\nthe Sscofpmf extension.\n\nHowever, according to the Sscofpmf extension specification[1],\nit only defines the upper 8 bits in mhpmevent for privilege mode\ninhibit and counter overflow disable. Other bits are defined by\nthe platform for event selection.\n\nSince vendors might define raw event encoding exceeding 48 bits in\nmhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it.\n\nLink: https://github.com/riscvarchive/riscv-count-overflow [1]\nSigned-off-by: Eric Lin \nReviewed-by: Xiang W \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"include: Adjust Sscofpmf mhpmevent mask for upper 8 bits"}},{"before":"bb7267a07f8f93b30355c66538f0752c4766b309","after":"a2807646a85878cb631cbc2b012cf888fc4427d7","ref":"refs/heads/master","pushedAt":"2024-08-01T14:43:57.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"include: Adjust Sscofpmf mhpmevent mask for upper 6 bits\n\nCurrently, OpenSBI reserves the upper 16 bits in mhpmevent for\nthe Sscofpmf extension.\n\nHowever, according to the Sscofpmf extension specification [1],\nit only defines the upper 6 bits in mhpmevent for privilege mode\ninhibit and counter overflow disable. Other bits are defined by\nthe platform for event selection.\n\nSince vendors might define raw event encoding exceeding 48 bits in\nmhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it.\n\nLink: https://github.com/riscv/riscv-isa-manual [1]\nSigned-off-by: Eric Lin \nReviewed-By: Xiang W \nReviewed-By: Anup Patel ","shortMessageHtmlLink":"include: Adjust Sscofpmf mhpmevent mask for upper 6 bits"}},{"before":null,"after":"65a3938fadc537af178c84a349ade31ec6a70846","ref":"refs/heads/release-1.5.x","pushedAt":"2024-07-29T06:06:28.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi_hsm: Save/restore menvcfg only when it exists\n\nAttempting to access the menvcfg CSR raises an illegal instruction\nexception on hardware which implements Sm1p11 or older.\n\nFixes: e9ee9678ba50 (\"lib: sbi: fwft: add support for SBI_FWFT_PTE_AD_HW_UPDATING\")\nSigned-off-by: Samuel Holland \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi_hsm: Save/restore menvcfg only when it exists"}},{"before":"4afb57c9ebe27e29ce3777024bfc186991a8b4fe","after":"bb7267a07f8f93b30355c66538f0752c4766b309","ref":"refs/heads/master","pushedAt":"2024-07-24T06:50:14.000Z","pushType":"push","commitsCount":6,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi: Introduce an early console buffer for caching early prints\n\nThe console device is registered by platform only in early_init()\ncallback so any prints before this point will be lost. Introduce an\nearly console buffer for caching prints before platform early_init().\n\nFor crashes before platform early_init(), users can simply dump the\ncontents of the console_early_buffer[] string using a debugger. The\nrelative address of the console_early_buffer[] string can be found\nusing following two commands:\n\nCONSOLE_EARLY_FIFO_ADDR=`${CROSS_COMPILE}objdump -D \\\nbuild/platform/generic/firmware/fw_dynamic.elf | \\\ngrep \":\" | awk '{print $1}'`\n\n${CROSS_COMPILE}objdump -R build/platform/generic/firmware/fw_dynamic.elf | \\\ngrep $CONSOLE_EARLY_FIFO_ADDR | awk '{print $3}'\n\nSigned-off-by: Anup Patel \nReviewed-By: Himanshu Chauhan ","shortMessageHtmlLink":"lib: sbi: Introduce an early console buffer for caching early prints"}},{"before":"f7a92f6b67bda221e96eb8dfa54e1eb162fa984f","after":"4afb57c9ebe27e29ce3777024bfc186991a8b4fe","ref":"refs/heads/master","pushedAt":"2024-07-24T05:37:34.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi_hsm: Save/restore menvcfg only when it exists\n\nAttempting to access the menvcfg CSR raises an illegal instruction\nexception on hardware which implements Sm1p11 or older.\n\nFixes: e9ee9678ba50 (\"lib: sbi: fwft: add support for SBI_FWFT_PTE_AD_HW_UPDATING\")\nSigned-off-by: Samuel Holland \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi_hsm: Save/restore menvcfg only when it exists"}},{"before":"b7e7e660269106f0c56061c770704a5e5504a98c","after":"f7a92f6b67bda221e96eb8dfa54e1eb162fa984f","ref":"refs/heads/master","pushedAt":"2024-07-23T07:42:10.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: utils/fdt: Add support for parsing riscv,isa-extensions\n\nA new property has been added, with an extensive rationale at [1], that\ncan be used in place of \"riscv,isa\" to indicate what extensions are\nsupported by a given platform that is a list of strings rather than a\nsingle string. There are some differences between the new property,\n\"riscv,isa-extensions\" and the incumbent \"riscv,isa\" - chief among them\nfor the sake of parsing being the list of strings, as opposed to a\nstring. Another advantage is strictly defined meanings for each string\nin a dt-binding, rather than deriving meaning from RVI standards. This\nmay likely to some divergence over time, but, at least for now, there's\nno relevant differences between the two for an M-Mode program.\n\nAdd support for the new property in OpenSBI, prioritising it, before\nfalling back to the, now deprecated, \"riscv,isa\" property if it is not\npresent.\n\nLink: https://lore.kernel.org/all/20230702-eats-scorebook-c951f170d29f@spud/ [1]\nSigned-off-by: Conor Dooley \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: utils/fdt: Add support for parsing riscv,isa-extensions"}},{"before":"0a667542950ac108e609c2bdfed4c0df87363717","after":"b7e7e660269106f0c56061c770704a5e5504a98c","ref":"refs/heads/master","pushedAt":"2024-07-23T04:51:25.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: tests: add math test suite\n\nThis patch introduces a new math test suite to the SBI unit\ntests. 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Running `make clean` should be enough to regenerate\nthe carray-related files.\n\nUpdate the documentation correspondingly.\n\nSigned-off-by: Ivan Orlov \nReviewed-by: Andrew Jones \nSigned-off-by: Ben Dooks \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"docs: writing tests: update cleaning instructions"}},{"before":"455de672dd7c2aa1992df54dfb08dc11abbc1b1a","after":"d8608e615fae150ddb54e9b54d0e1fb5f16a9d9c","ref":"refs/heads/master","pushedAt":"2024-07-04T05:16:21.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi_emulate_csr: Do not log illegal CSR accesses\n\nIllegal CSR accesses from lower privilege modes are delegated to S-mode\nand do not necessarily indicate a bug. Supervisor software may want to\nemulate some CSRs, or may intentionally disable access to certain\nexisting CSRs, and thus will expect traps when those CSRs are accessed.\n\nFor example, Linux disables sstatus.VS by default in order to detect\nwhen userspace first accesses vector register state; this includes the\nCSRs defined by the V extesion. As a result, if the first vector\ninstruction in a process is a CSR access, OpenSBI will log the illegal\ninstruction exception, even though there is no unexpected or erroneous\nbehavior occurring.\n\nSince the illegal instruction exception is delegated to S-mode, S-mode\nsoftware should be responsible for reporting the exception, not OpenSBI.\n\nSigned-off-by: Samuel Holland \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi_emulate_csr: Do not log illegal CSR accesses"}},{"before":"23b7badeee3caa1445784273ba5dc8dbcbba7c34","after":"455de672dd7c2aa1992df54dfb08dc11abbc1b1a","ref":"refs/heads/master","pushedAt":"2024-06-30T09:15:13.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"include: Bump-up version to 1.5\n\nThis patch updates OpenSBI version to 1.5 as part of\nrelease preparation.\n\nSigned-off-by: Anup Patel \nSigned-off-by: Anup Patel ","shortMessageHtmlLink":"include: Bump-up version to 1.5"}},{"before":"caae2f7d455c78c509782e1eb8d47dfdd874b903","after":"23b7badeee3caa1445784273ba5dc8dbcbba7c34","ref":"refs/heads/master","pushedAt":"2024-06-28T03:11:39.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi: check incoming dbtr shmem address\n\nCurrent Debug Trigger SBI extension proposal suggests to activate\nshmem area and obtain its physical address from S-mode software\nin the following way:\n\n: If both `shmem_phys_lo` and `shmem_phys_hi` parameters are not\n: all-ones bitwise then `shmem_phys_lo` specifies the lower XLEN\n: bits and `shmem_phys_hi` specifies the upper XLEN bits of the\n: shared memory physical base address. The `shmem_phys_lo` MUST\n: be `(XLEN / 8)` byte aligned and the size of shared memory is\n: assumed to be `trig_max * (XLEN / 2)` bytes.\n\nFor more details see the current version of the proposal:\n- https://lists.riscv.org/g/tech-debug/message/1302\n\nOn the other hand, on RV32, the M-mode can only access the first 4GB of\nthe physical address space because M-mode does not have MMU to access\nfull 34-bit physical address space. Similarly, on RV64, the M-mode can\nonly access memory addressed by 64 bits.\n\nThis commit checks shmem address in function sbi_dbtr_setup_shmem\nto make sure that shmem_phys_hi part of the valid address is zero.\nBesides, the macro DBTR_SHMEM_MAKE_PHYS is updated to take into\naccount only low XLEN part.\n\nSigned-off-by: Sergey Matyukevich \nReviewed-by: Himanshu Chauhan ","shortMessageHtmlLink":"lib: sbi: check incoming dbtr shmem address"}},{"before":"ecef14d5732f837cbfa4a8cefa8fed7953e7abfb","after":"caae2f7d455c78c509782e1eb8d47dfdd874b903","ref":"refs/heads/master","pushedAt":"2024-06-26T12:54:34.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi: fwft: return SBI_EINVAL rather than SBI_ERR_INVALID_PARAM\n\nError code returned by the ecall handles should use the defines from\nsbi_ecall_interface.h rather than sbi_error.h.\n\nSigned-off-by: Clément Léger \nReviewed-by: Andrew Jones \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi: fwft: return SBI_EINVAL rather than SBI_ERR_INVALID_PARAM"}},{"before":"53844c98d082cbba29a6e568196add6de95e858f","after":"ecef14d5732f837cbfa4a8cefa8fed7953e7abfb","ref":"refs/heads/master","pushedAt":"2024-06-19T12:50:07.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi: implement SBI FWFT extension\n\nThe SBI FWFT extension defines a set of function that can be called\nto control the configuration of some platform features (misaligned\ntrap delegation, etc). This patch implements sbi_fwft_set() and\nsbi_fwft_get() as defined in the specification [1].\n\nLink: https://lists.riscv.org/g/tech-prs/message/924 [1]\nSigned-off-by: Clément Léger \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi: implement SBI FWFT extension"}},{"before":"52dcf351cddf12081acc921c135df265f9d2f243","after":"53844c98d082cbba29a6e568196add6de95e858f","ref":"refs/heads/master","pushedAt":"2024-06-18T15:57:26.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: sbi: Add support for Svade and Svadu extensions\n\nAdd support for Svade and Svadu extensions. When both are present in the\ndevice tree, the M-mode firmware should select the Svade extension\nto comply with the RVA23 profile, which mandates Svade and lists Svadu as\nan optional extension.\n\nSigned-off-by: Yong-Xuan Wang \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: sbi: Add support for Svade and Svadu extensions"}},{"before":"7830e987856eb1319c82664702892b6d50a93e7a","after":"52dcf351cddf12081acc921c135df265f9d2f243","ref":"refs/heads/master","pushedAt":"2024-06-18T11:07:31.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"platform: generic: andes: Add support for RV32 to set up PMA\n\nLike PMP, the behaviors to configure PMA will be different from\nRV64 and RV32. RV64 uses two Andes custom CSRs, pmacfg0 and pmacfg2,\nbut RV32 uses four Andes custom CSRs, pmacfg0 ~ pmacfg3. This patch\nadds support to PMA for RV32.\n\nSigned-off-by: Ben Zong-You Xie \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"platform: generic: andes: Add support for RV32 to set up PMA"}},{"before":"3a94a3258039f225d068cb575844062c3f86bc03","after":"7830e987856eb1319c82664702892b6d50a93e7a","ref":"refs/heads/master","pushedAt":"2024-06-14T03:08:33.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: serial: fix RX path in litex-uart\n\nWhen used to read characters from the terminal (e.g., when the SBI\nconsole is used via ecall from linux with `console=hvc0`), we must\nacknowledge receipt of each character to \"pop\" it off the LiteUART\nhardware queue, and allow the next character to be made available.\n\nFixes: 52af6e4b (\"lib: utils: Add LiteX UART support\")\nSuggested-by: Dolu1990 \nSigned-off-by: Gabriel Somlo \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: serial: fix RX path in litex-uart"}},{"before":"d962db280725b03a0340e05a07e4c85c93f35bc5","after":"3a94a3258039f225d068cb575844062c3f86bc03","ref":"refs/heads/master","pushedAt":"2024-06-13T13:56:46.000Z","pushType":"push","commitsCount":9,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"sbi: sbi_domain_context: Fix trap context for domain context switching\n\nSave/restore sbi_trap_context during domain context switching to\nensure proper trap handling and isolation. This maintains correct\ndomain-specific state, avoiding context corruption.\n\nFixes: abea949721bc (\"lib: sbi: Introduce trap context\")\nSigned-off-by: Yu Chien Peter Lin \nReviewed-by: Alvin Chang \nTested-by: Alvin Chang \nReviewed-by: Yong Li \nTested-by: Yong Li ","shortMessageHtmlLink":"sbi: sbi_domain_context: Fix trap context for domain context switching"}},{"before":"e3a30a2c918aae79d4cc403d474c3d2872a9063c","after":"d962db280725b03a0340e05a07e4c85c93f35bc5","ref":"refs/heads/master","pushedAt":"2024-05-23T12:32:32.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"avpatel","name":"Anup Patel","path":"/avpatel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/444985?s=80&v=4"},"commit":{"message":"lib: utils/gpio: respect flag GPIO_FLAG_ACTIVE_LOW\n\n\"gpio-poweroff\" and \"gpio-restart\" always set gpio to high to\nactive the function, but some chips need a low signal to active.\nFortunately, it can be achieved by setting GPIO_FLAG_ACTIVE_LOW\nfor the gpio. Implement this flag support for the gpio library\nso the gpio reset can function well.\n\nSigned-off-by: Inochi Amaoto \nReviewed-by: Anup Patel ","shortMessageHtmlLink":"lib: utils/gpio: respect flag GPIO_FLAG_ACTIVE_LOW"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEpPVqFQA","startCursor":null,"endCursor":null}},"title":"Activity · riscv-software-src/opensbi"}