From fa3223a347ede2c08679dede45e83958b340cf51 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 16 Jul 2021 15:28:01 +0530 Subject: [PATCH 01/21] adding github actions CI flow for releases --- .github/workflows/main.yml | 98 ++++++++++++++++++++++++++++++++++++++ .github/workflows/test.yml | 32 +++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 .github/workflows/main.yml create mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml new file mode 100644 index 0000000..04843f5 --- /dev/null +++ b/.github/workflows/main.yml @@ -0,0 +1,98 @@ +# This is a basic workflow to help you get started with Actions + +name: CI + +# Controls when the action will run. +on: + # Triggers the workflow on push or pull request events but only for the master branch + push: + branches: [ master ] + + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +# A workflow run is made up of one or more jobs that can run sequentially or in parallel +jobs: + # This workflow contains a single job called "build" + build: + # The type of runner that the job will run on + runs-on: ubuntu-latest + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v2 + + - name: Get version + id: get_version + run: | + echo "::set-output name=version::$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md)" + + - name: Set up Python + uses: actions/setup-python@v2 + with: + python-version: '3.6' + + - name: Install dependencies + run: | + pip install -r riscof/requirements.txt + python -m pip install --upgrade pip + pip install setuptools wheel twine + + - name: Publish package + if: github.ref == 'refs/heads/master' + env: + TWINE_USERNAME: ${{ secrets.PYPIUSERNAME }} + TWINE_PASSWORD: ${{ secrets.PYPIPASSWORD }} + run: | + python setup.py sdist bdist_wheel + twine upload dist/* + + + - name: Extract release notes + id: extract-release-notes + if: github.ref == 'refs/heads/master' + uses: ffurrer2/extract-release-notes@v1 + + - name: Tag + if: github.ref == 'refs/heads/master' + run: | + git tag ${{ steps.get_version.outputs.version }} + git push origin ${{ steps.get_version.outputs.version }} + + - name: Create Release + id: create_release + if: github.ref == 'refs/heads/master' + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # This token is provided by Actions, you do not need to create your own token + with: + release_branch: refs/heads/master + release_name: ${{ steps.get_version.outputs.version }} + tag_name: ${{ steps.get_version.outputs.version }} + body: ${{ steps.extract-release-notes.outputs.release_notes }} + draft: false + prerelease: false + + # - name: Script + # uses: ammaraskar/sphinx-action@master + # with: + # docs-folder: "docs/" + # pre-build-command: " apt-get update -y && apt-get install -y latexmk texlive-latex-recommended texlive-latex-extra texlive-fonts-recommended" + # build-command: " make latexpdf " + + + # - name: Upload Release Asset + # id: upload-release-asset + # if: github.ref == 'refs/heads/master' + # uses: actions/upload-release-asset@v1 + # env: + # GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + # with: + # upload_url: ${{ steps.create_release.outputs.upload_url }} # This pulls from the CREATE RELEASE step above, referencing it's ID to get its outputs object, which include a `upload_url`. See this blog post for more info: https://jasonet.co/posts/new-features-of-github-actions/#passing-data-to-future-steps + # asset_path: ./docs/build/latex/riscv_config.pdf + # asset_name: riscv_config.pdf + # asset_content_type: application/pdf + + + diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 0000000..29c60f4 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,32 @@ +# This is a basic workflow to help you get started with Actions + +name: test + +# Controls when the action will run. +on: + # Triggers the workflow on push or pull request events but only for the master branch + pull_request: + branches: [ master ] + + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +# A workflow run is made up of one or more jobs that can run sequentially or in parallel +jobs: + check-version: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + + - name: version check + run: | + export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); + echo "CHANGELOG VERSION: $CHNGVER" + export INITVER=$(grep -P "__version__ = '.*?'" riscof/__init__.py | awk '{print $3}'|sed "s/'//g"); + echo "INIT VERSION: $INITVER" + if [ "$CHNGVER" = "$INITVER" ]; then + echo "Versions are equal in Changelog and init.py." + else + echo "Versions are not equal in Changelog and init.py." + exit 1 + fi From b106c519f0760fe5179abd8f2cef40ea30fa2e68 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 16 Jul 2021 15:28:53 +0530 Subject: [PATCH 02/21] removing hosted tests and database files These will no longer be required since we will always be using the arch-test-repo as the tests --- riscof/framework/database.yaml | 4823 ----------------- riscof/suite/compliance.cgf | 2221 -------- riscof/suite/env/arch_test.h | 1016 ---- riscof/suite/env/encoding.h | 1493 ----- riscof/suite/rv32i_m/C/cadd-01.S | 3004 ---------- riscof/suite/rv32i_m/C/caddi-01.S | 1949 ------- riscof/suite/rv32i_m/C/caddi16sp-01.S | 414 -- riscof/suite/rv32i_m/C/caddi4spn-01.S | 169 - riscof/suite/rv32i_m/C/cand-01.S | 3004 ---------- riscof/suite/rv32i_m/C/candi-01.S | 1949 ------- riscof/suite/rv32i_m/C/cbeqz-01.S | 494 -- riscof/suite/rv32i_m/C/cbnez-01.S | 494 -- riscof/suite/rv32i_m/C/cebreak-01.S | 70 - riscof/suite/rv32i_m/C/cj-01.S | 159 - riscof/suite/rv32i_m/C/cjal-01.S | 159 - riscof/suite/rv32i_m/C/cjalr-01.S | 229 - riscof/suite/rv32i_m/C/cjr-01.S | 229 - riscof/suite/rv32i_m/C/cli-01.S | 234 - riscof/suite/rv32i_m/C/clui-01.S | 229 - riscof/suite/rv32i_m/C/clw-01.S | 139 - riscof/suite/rv32i_m/C/clwsp-01.S | 229 - riscof/suite/rv32i_m/C/cmv-01.S | 499 -- riscof/suite/rv32i_m/C/cnop-01.S | 139 - riscof/suite/rv32i_m/C/cor-01.S | 3024 ----------- riscof/suite/rv32i_m/C/cslli-01.S | 499 -- riscof/suite/rv32i_m/C/csrai-01.S | 504 -- riscof/suite/rv32i_m/C/csrli-01.S | 494 -- riscof/suite/rv32i_m/C/csub-01.S | 2979 ---------- riscof/suite/rv32i_m/C/csw-01.S | 419 -- riscof/suite/rv32i_m/C/cswsp-01.S | 419 -- riscof/suite/rv32i_m/C/cxor-01.S | 2989 ---------- riscof/suite/rv32i_m/I/add-01.S | 3024 ----------- riscof/suite/rv32i_m/I/addi-01.S | 2884 ---------- riscof/suite/rv32i_m/I/and-01.S | 2999 ---------- riscof/suite/rv32i_m/I/andi-01.S | 2889 ---------- riscof/suite/rv32i_m/I/auipc-01.S | 394 -- riscof/suite/rv32i_m/I/beq-01.S | 2994 ---------- riscof/suite/rv32i_m/I/bge-01.S | 3029 ----------- riscof/suite/rv32i_m/I/bgeu-01.S | 3709 ------------- riscof/suite/rv32i_m/I/blt-01.S | 2979 ---------- riscof/suite/rv32i_m/I/bltu-01.S | 3709 ------------- riscof/suite/rv32i_m/I/bne-01.S | 2999 ---------- riscof/suite/rv32i_m/I/fence-01.S | 59 - riscof/suite/rv32i_m/I/jal-01.S | 234 - riscof/suite/rv32i_m/I/jalr-01.S | 239 - riscof/suite/rv32i_m/I/lb-align-01.S | 239 - riscof/suite/rv32i_m/I/lbu-align-01.S | 234 - riscof/suite/rv32i_m/I/lh-align-01.S | 234 - riscof/suite/rv32i_m/I/lhu-align-01.S | 234 - riscof/suite/rv32i_m/I/lui-01.S | 389 -- riscof/suite/rv32i_m/I/lw-align-01.S | 234 - riscof/suite/rv32i_m/I/or-01.S | 3014 ---------- riscof/suite/rv32i_m/I/ori-01.S | 2879 ---------- riscof/suite/rv32i_m/I/sb-align-01.S | 424 -- riscof/suite/rv32i_m/I/sh-align-01.S | 429 -- riscof/suite/rv32i_m/I/sll-01.S | 519 -- riscof/suite/rv32i_m/I/slli-01.S | 514 -- riscof/suite/rv32i_m/I/slt-01.S | 3004 ---------- riscof/suite/rv32i_m/I/slti-01.S | 2879 ---------- riscof/suite/rv32i_m/I/sltiu-01.S | 3574 ------------ riscof/suite/rv32i_m/I/sltu-01.S | 3689 ------------- riscof/suite/rv32i_m/I/sra-01.S | 524 -- riscof/suite/rv32i_m/I/srai-01.S | 509 -- riscof/suite/rv32i_m/I/srl-01.S | 539 -- riscof/suite/rv32i_m/I/srli-01.S | 524 -- riscof/suite/rv32i_m/I/sub-01.S | 3039 ----------- riscof/suite/rv32i_m/I/sw-align-01.S | 414 -- riscof/suite/rv32i_m/I/xor-01.S | 3019 ----------- riscof/suite/rv32i_m/I/xori-01.S | 2909 ---------- .../suite/rv32i_m/K_unratified/AES32DSI-01.S | 1053 ---- .../suite/rv32i_m/K_unratified/AES32DSI-02.S | 1780 ------ .../suite/rv32i_m/K_unratified/AES32DSMI-01.S | 1053 ---- .../suite/rv32i_m/K_unratified/AES32DSMI-02.S | 1780 ------ .../suite/rv32i_m/K_unratified/AES32ESI-01.S | 1053 ---- .../suite/rv32i_m/K_unratified/AES32ESI-02.S | 1780 ------ .../suite/rv32i_m/K_unratified/AES32ESMI-01.S | 1053 ---- .../suite/rv32i_m/K_unratified/AES32ESMI-02.S | 1780 ------ riscof/suite/rv32i_m/K_unratified/ANDN-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/CLMUL-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/CLMULH-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/ORN-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/PACK-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/PACKH-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/PACKU-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/REV-B-01.S | 1492 ----- riscof/suite/rv32i_m/K_unratified/REV8-01.S | 1492 ----- riscof/suite/rv32i_m/K_unratified/ROL-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/ROR-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/RORI-01.S | 1024 ---- .../rv32i_m/K_unratified/SHA256SIG0-01.S | 1491 ----- .../rv32i_m/K_unratified/SHA256SIG1-01.S | 1491 ----- .../rv32i_m/K_unratified/SHA256SUM0-01.S | 1491 ----- .../rv32i_m/K_unratified/SHA256SUM1-01.S | 1491 ----- .../rv32i_m/K_unratified/SHA512SIG0H-01.S | 1023 ---- .../rv32i_m/K_unratified/SHA512SIG0L-01.S | 1023 ---- .../rv32i_m/K_unratified/SHA512SIG1H-01.S | 1023 ---- .../rv32i_m/K_unratified/SHA512SIG1L-01.S | 1023 ---- .../rv32i_m/K_unratified/SHA512SUM0R-01.S | 1023 ---- .../rv32i_m/K_unratified/SHA512SUM1R-01.S | 1023 ---- riscof/suite/rv32i_m/K_unratified/SM3P0-01.S | 1490 ----- riscof/suite/rv32i_m/K_unratified/SM3P1-01.S | 1490 ----- riscof/suite/rv32i_m/K_unratified/SM4ED-01.S | 1052 ---- riscof/suite/rv32i_m/K_unratified/SM4ED-02.S | 1779 ------ riscof/suite/rv32i_m/K_unratified/SM4KS-01.S | 1052 ---- riscof/suite/rv32i_m/K_unratified/SM4KS-02.S | 1779 ------ riscof/suite/rv32i_m/K_unratified/UNZIP-01.S | 1492 ----- riscof/suite/rv32i_m/K_unratified/XNOR-01.S | 1024 ---- .../suite/rv32i_m/K_unratified/XPERM-B-01.S | 1024 ---- .../suite/rv32i_m/K_unratified/XPERM-N-01.S | 1024 ---- riscof/suite/rv32i_m/K_unratified/ZIP-01.S | 1492 ----- riscof/suite/rv32i_m/M/div-01.S | 3034 ----------- riscof/suite/rv32i_m/M/divu-01.S | 3704 ------------- riscof/suite/rv32i_m/M/mul-01.S | 3009 ---------- riscof/suite/rv32i_m/M/mulh-01.S | 3009 ---------- riscof/suite/rv32i_m/M/mulhsu-01.S | 3319 ------------ riscof/suite/rv32i_m/M/mulhu-01.S | 3699 ------------- riscof/suite/rv32i_m/M/rem-01.S | 3014 ---------- riscof/suite/rv32i_m/M/remu-01.S | 3699 ------------- riscof/suite/rv32i_m/Zifencei/Fencei.S | 99 - riscof/suite/rv32i_m/labels.py | 77 - riscof/suite/rv32i_m/privilege/ebreak.S | 64 - riscof/suite/rv32i_m/privilege/ecall.S | 66 - .../suite/rv32i_m/privilege/misalign-beq-01.S | 76 - .../suite/rv32i_m/privilege/misalign-bge-01.S | 76 - .../rv32i_m/privilege/misalign-bgeu-01.S | 76 - .../suite/rv32i_m/privilege/misalign-blt-01.S | 76 - .../rv32i_m/privilege/misalign-bltu-01.S | 76 - .../suite/rv32i_m/privilege/misalign-bne-01.S | 76 - .../suite/rv32i_m/privilege/misalign-jal-01.S | 76 - .../suite/rv32i_m/privilege/misalign-lh-01.S | 76 - .../suite/rv32i_m/privilege/misalign-lhu-01.S | 76 - .../suite/rv32i_m/privilege/misalign-lw-01.S | 86 - .../suite/rv32i_m/privilege/misalign-sh-01.S | 76 - .../suite/rv32i_m/privilege/misalign-sw-01.S | 86 - .../rv32i_m/privilege/misalign1-jalr-01.S | 80 - .../rv32i_m/privilege/misalign2-jalr-01.S | 82 - riscof/suite/rv64i_m/C/cadd-01.S | 3429 ------------ riscof/suite/rv64i_m/C/caddi-01.S | 2279 -------- riscof/suite/rv64i_m/C/caddi16sp-01.S | 729 --- riscof/suite/rv64i_m/C/caddi4spn-01.S | 164 - riscof/suite/rv64i_m/C/caddiw-01.S | 2269 -------- riscof/suite/rv64i_m/C/caddw-01.S | 3469 ------------ riscof/suite/rv64i_m/C/cand-01.S | 3434 ------------ riscof/suite/rv64i_m/C/candi-01.S | 2269 -------- riscof/suite/rv64i_m/C/cbeqz-01.S | 814 --- riscof/suite/rv64i_m/C/cbnez-01.S | 814 --- riscof/suite/rv64i_m/C/cebreak-01.S | 71 - riscof/suite/rv64i_m/C/cj-01.S | 159 - riscof/suite/rv64i_m/C/cjalr-01.S | 229 - riscof/suite/rv64i_m/C/cjr-01.S | 229 - riscof/suite/rv64i_m/C/cld-01.S | 134 - riscof/suite/rv64i_m/C/cldsp-01.S | 229 - riscof/suite/rv64i_m/C/cli-01.S | 234 - riscof/suite/rv64i_m/C/clui-01.S | 229 - riscof/suite/rv64i_m/C/clw-01.S | 134 - riscof/suite/rv64i_m/C/clwsp-01.S | 229 - riscof/suite/rv64i_m/C/cmv-01.S | 819 --- riscof/suite/rv64i_m/C/cnop-01.S | 139 - riscof/suite/rv64i_m/C/cor-01.S | 3479 ------------ riscof/suite/rv64i_m/C/csd-01.S | 729 --- riscof/suite/rv64i_m/C/csdsp-01.S | 729 --- riscof/suite/rv64i_m/C/cslli-01.S | 809 --- riscof/suite/rv64i_m/C/csrai-01.S | 809 --- riscof/suite/rv64i_m/C/csrli-01.S | 814 --- riscof/suite/rv64i_m/C/csub-01.S | 3434 ------------ riscof/suite/rv64i_m/C/csubw-01.S | 3429 ------------ riscof/suite/rv64i_m/C/csw-01.S | 724 --- riscof/suite/rv64i_m/C/cswsp-01.S | 739 --- riscof/suite/rv64i_m/C/cxor-01.S | 3394 ------------ riscof/suite/rv64i_m/I/add-01.S | 3479 ------------ riscof/suite/rv64i_m/I/addi-01.S | 3179 ----------- riscof/suite/rv64i_m/I/addiw-01.S | 3209 ----------- riscof/suite/rv64i_m/I/addw-01.S | 3474 ------------ riscof/suite/rv64i_m/I/and-01.S | 3469 ------------ riscof/suite/rv64i_m/I/andi-01.S | 3179 ----------- riscof/suite/rv64i_m/I/auipc-01.S | 389 -- riscof/suite/rv64i_m/I/beq-01.S | 3479 ------------ riscof/suite/rv64i_m/I/bge-01.S | 3454 ------------ riscof/suite/rv64i_m/I/bgeu-01.S | 4194 -------------- riscof/suite/rv64i_m/I/blt-01.S | 3454 ------------ riscof/suite/rv64i_m/I/bltu-01.S | 4159 -------------- riscof/suite/rv64i_m/I/bne-01.S | 3474 ------------ riscof/suite/rv64i_m/I/fence-01.S | 63 - riscof/suite/rv64i_m/I/jal-01.S | 234 - riscof/suite/rv64i_m/I/jalr-01.S | 239 - riscof/suite/rv64i_m/I/lb-align-01.S | 234 - riscof/suite/rv64i_m/I/lbu-align-01.S | 239 - riscof/suite/rv64i_m/I/ld-align-01.S | 234 - riscof/suite/rv64i_m/I/lh-align-01.S | 234 - riscof/suite/rv64i_m/I/lhu-align-01.S | 234 - riscof/suite/rv64i_m/I/lui-01.S | 389 -- riscof/suite/rv64i_m/I/lw-align-01.S | 234 - riscof/suite/rv64i_m/I/lwu-align-01.S | 234 - riscof/suite/rv64i_m/I/or-01.S | 3479 ------------ riscof/suite/rv64i_m/I/ori-01.S | 3194 ----------- riscof/suite/rv64i_m/I/sb-align-01.S | 749 --- riscof/suite/rv64i_m/I/sd-align-01.S | 734 --- riscof/suite/rv64i_m/I/sh-align-01.S | 739 --- riscof/suite/rv64i_m/I/sll-01.S | 839 --- riscof/suite/rv64i_m/I/slli-01.S | 829 --- riscof/suite/rv64i_m/I/slliw-01.S | 824 --- riscof/suite/rv64i_m/I/sllw-01.S | 839 --- riscof/suite/rv64i_m/I/slt-01.S | 3464 ------------ riscof/suite/rv64i_m/I/slti-01.S | 3169 ----------- riscof/suite/rv64i_m/I/sltiu-01.S | 3879 ------------- riscof/suite/rv64i_m/I/sltu-01.S | 4189 -------------- riscof/suite/rv64i_m/I/sra-01.S | 844 --- riscof/suite/rv64i_m/I/srai-01.S | 834 --- riscof/suite/rv64i_m/I/sraiw-01.S | 834 --- riscof/suite/rv64i_m/I/sraw-01.S | 844 --- riscof/suite/rv64i_m/I/srl-01.S | 839 --- riscof/suite/rv64i_m/I/srli-01.S | 839 --- riscof/suite/rv64i_m/I/srliw-01.S | 834 --- riscof/suite/rv64i_m/I/srlw-01.S | 844 --- riscof/suite/rv64i_m/I/sub-01.S | 3439 ------------ riscof/suite/rv64i_m/I/subw-01.S | 3474 ------------ riscof/suite/rv64i_m/I/sw-align-01.S | 734 --- riscof/suite/rv64i_m/I/xor-01.S | 3464 ------------ riscof/suite/rv64i_m/I/xori-01.S | 3204 ----------- .../suite/rv64i_m/K_unratified/AES64DS-01.S | 1838 ------- .../suite/rv64i_m/K_unratified/AES64DS-02.S | 1728 ------ .../suite/rv64i_m/K_unratified/AES64DSM-01.S | 1838 ------- .../suite/rv64i_m/K_unratified/AES64DSM-02.S | 1728 ------ .../suite/rv64i_m/K_unratified/AES64ES-01.S | 1838 ------- .../suite/rv64i_m/K_unratified/AES64ES-02.S | 1728 ------ .../suite/rv64i_m/K_unratified/AES64ESM-01.S | 1838 ------- .../suite/rv64i_m/K_unratified/AES64ESM-02.S | 1728 ------ .../suite/rv64i_m/K_unratified/AES64IM-01.S | 2714 ---------- .../suite/rv64i_m/K_unratified/AES64IM-02.S | 2548 --------- .../suite/rv64i_m/K_unratified/AES64KS1I-01.S | 1838 ------- .../suite/rv64i_m/K_unratified/AES64KS1I-02.S | 1728 ------ .../suite/rv64i_m/K_unratified/AES64KS2-01.S | 1838 ------- .../suite/rv64i_m/K_unratified/AES64KS2-02.S | 1728 ------ riscof/suite/rv64i_m/K_unratified/ANDN-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/CLMUL-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/CLMULH-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/ORN-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/PACK-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/PACKH-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/PACKU-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/PACKUW-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/PACKW-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/REV-B-01.S | 2716 ---------- riscof/suite/rv64i_m/K_unratified/REV8-01.S | 2716 ---------- riscof/suite/rv64i_m/K_unratified/REV8-W-01.S | 2716 ---------- riscof/suite/rv64i_m/K_unratified/ROL-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/ROLW-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/ROR-01.S | 1839 ------- riscof/suite/rv64i_m/K_unratified/RORI-01.S | 1838 ------- riscof/suite/rv64i_m/K_unratified/RORIW-01.S | 1838 ------- riscof/suite/rv64i_m/K_unratified/RORW-01.S | 1839 ------- .../rv64i_m/K_unratified/SHA256SIG0-01.S | 2715 ---------- .../rv64i_m/K_unratified/SHA256SIG1-01.S | 2715 ---------- .../rv64i_m/K_unratified/SHA256SUM0-01.S | 2715 ---------- .../rv64i_m/K_unratified/SHA256SUM1-01.S | 2714 ---------- .../rv64i_m/K_unratified/SHA512SIG0-01.S | 2715 ---------- .../rv64i_m/K_unratified/SHA512SIG1-01.S | 2715 ---------- .../rv64i_m/K_unratified/SHA512SUM0-01.S | 2715 ---------- .../rv64i_m/K_unratified/SHA512SUM1-01.S | 2715 ---------- riscof/suite/rv64i_m/K_unratified/SM3P0-01.S | 2714 ---------- riscof/suite/rv64i_m/K_unratified/SM3P1-01.S | 2714 ---------- riscof/suite/rv64i_m/K_unratified/SM4ED-01.S | 1892 ------- riscof/suite/rv64i_m/K_unratified/SM4ED-02.S | 1779 ------ riscof/suite/rv64i_m/K_unratified/SM4KS-01.S | 1892 ------- riscof/suite/rv64i_m/K_unratified/SM4KS-02.S | 1779 ------ riscof/suite/rv64i_m/K_unratified/XNOR-01.S | 1839 ------- .../suite/rv64i_m/K_unratified/XPERM-B-01.S | 1839 ------- .../suite/rv64i_m/K_unratified/XPERM-N-01.S | 1839 ------- riscof/suite/rv64i_m/M/div-01.S | 3479 ------------ riscof/suite/rv64i_m/M/divu-01.S | 4214 -------------- riscof/suite/rv64i_m/M/divuw-01.S | 4199 -------------- riscof/suite/rv64i_m/M/divw-01.S | 3439 ------------ riscof/suite/rv64i_m/M/mul-01.S | 3494 ------------ riscof/suite/rv64i_m/M/mulh-01.S | 3469 ------------ riscof/suite/rv64i_m/M/mulhsu-01.S | 3789 ------------- riscof/suite/rv64i_m/M/mulhu-01.S | 4159 -------------- riscof/suite/rv64i_m/M/mulw-01.S | 3449 ------------ riscof/suite/rv64i_m/M/rem-01.S | 3414 ------------ riscof/suite/rv64i_m/M/remu-01.S | 4199 -------------- riscof/suite/rv64i_m/M/remuw-01.S | 4179 -------------- riscof/suite/rv64i_m/M/remw-01.S | 3464 ------------ riscof/suite/rv64i_m/Zifencei/Fencei.S | 96 - riscof/suite/rv64i_m/privilege/ebreak.S | 65 - riscof/suite/rv64i_m/privilege/ecall.S | 65 - .../suite/rv64i_m/privilege/misalign-beq-01.S | 76 - .../suite/rv64i_m/privilege/misalign-bge-01.S | 76 - .../rv64i_m/privilege/misalign-bgeu-01.S | 76 - .../suite/rv64i_m/privilege/misalign-blt-01.S | 76 - .../rv64i_m/privilege/misalign-bltu-01.S | 76 - .../suite/rv64i_m/privilege/misalign-bne-01.S | 76 - .../suite/rv64i_m/privilege/misalign-jal-01.S | 76 - .../suite/rv64i_m/privilege/misalign-ld-01.S | 106 - .../suite/rv64i_m/privilege/misalign-lh-01.S | 76 - .../suite/rv64i_m/privilege/misalign-lhu-01.S | 76 - .../suite/rv64i_m/privilege/misalign-lw-01.S | 86 - .../suite/rv64i_m/privilege/misalign-lwu-01.S | 86 - .../suite/rv64i_m/privilege/misalign-sd-01.S | 106 - .../suite/rv64i_m/privilege/misalign-sh-01.S | 76 - .../suite/rv64i_m/privilege/misalign-sw-01.S | 86 - .../rv64i_m/privilege/misalign1-jalr-01.S | 80 - .../rv64i_m/privilege/misalign2-jalr-01.S | 82 - riscof/suite/wip/csr_RL_misa.S | 58 - riscof/suite/wip/csr_WARL_misa.S | 70 - riscof/suite/wip/csr_medeleg_ebreak.S | 248 - .../wip/csr_medeleg_illegal_instruction.S | 414 -- ...csr_medeleg_illegal_instruction_modified.S | 352 -- .../csr_medeleg_instruction_access_fault.S | 264 - ...r_medeleg_instruction_address_misaligned.S | 260 - .../wip/csr_medeleg_instruction_page_fault.S | 267 - .../suite/wip/csr_medeleg_load_access_fault.S | 255 - .../wip/csr_medeleg_load_address_misaligned.S | 261 - .../suite/wip/csr_medeleg_load_page_fault.S | 294 - .../wip/csr_medeleg_store_access_fault.S | 254 - .../csr_medeleg_store_address_misaligned.S | 259 - .../suite/wip/csr_medeleg_store_page_fault.S | 294 - riscof/suite/wip/csr_mepc_function_test.S | 280 - riscof/suite/wip/csr_mepc_read_write_test.S | 143 - riscof/suite/wip/csr_misa.S | 43 - riscof/suite/wip/csr_misa_A.S | 72 - riscof/suite/wip/csr_misa_C.S | 64 - riscof/suite/wip/csr_misa_D.S | 205 - riscof/suite/wip/csr_misa_F.S | 205 - riscof/suite/wip/csr_misa_M.S | 64 - riscof/suite/wip/csr_misa_atomic.S | 219 - riscof/suite/wip/csr_misa_cext.S | 182 - riscof/suite/wip/csr_misa_mul.S | 223 - riscof/suite/wip/csr_misa_reserved.S | 203 - riscof/suite/wip/csr_misa_xlen.S | 100 - riscof/suite/wip/csr_mstatus_machine_bit.S | 218 - riscof/suite/wip/csr_mstatus_machine_int.S | 184 - riscof/suite/wip/csr_mstatus_mpp_WARL1.S | 143 - riscof/suite/wip/csr_mstatus_user_bit.S | 159 - riscof/suite/wip/csr_mstatus_user_int.S | 156 - .../suite/wip/csr_mtval_fetch_access_fault.S | 72 - riscof/suite/wip/csr_mtval_fetch_misaligned.S | 80 - riscof/suite/wip/csr_mtval_inst_illegal.S | 78 - riscof/suite/wip/csr_mtval_ld_access_fault.S | 70 - riscof/suite/wip/csr_mtval_ld_misaligned.S | 70 - riscof/suite/wip/csr_mtval_st_access_fault.S | 69 - riscof/suite/wip/csr_mtval_st_misaligned.S | 70 - riscof/suite/wip/csr_mtvec_WARL.S | 98 - riscof/suite/wip/csr_mtvec_asyn_interrupt.S | 113 - riscof/suite/wip/csr_mtvec_syn_interrupt.S | 66 - riscof/suite/wip/machine_WARL_macro.S | 54 - riscof/suite/wip/machine_WLRL_misa.S | 66 - riscof/suite/wip/machine_WPRI_mstatus.S | 73 - riscof/suite/wip/machine_delegation.S | 102 - riscof/suite/wip/machine_undefined_csr.S | 100 - .../I-MISAC-MISALIGN_JMP-01.S | 115 - .../wip/pipelinecleaning/I-MISALIGN_JMP-01.S | 353 -- .../wip/pipelinecleaning/I-MISALIGN_LDST-01.S | 241 - .../suite/wip/pipelinecleaning/csr_misa_M.S | 103 - .../wip/pipelinecleaning/csr_mtvec_WARL.S | 103 - .../wip/pipelinecleaning/csr_mtvec_mode.S | 69 - riscof/suite/wip/reset_misa.S | 40 - riscof/suite/wip/rv32i_m/A/RV32A-AMOADD-W.S | 61 - riscof/suite/wip/rv32i_m/A/RV32A-AMOAND-W.S | 66 - riscof/suite/wip/rv32i_m/A/RV32A-AMOMAX-W.S | 66 - riscof/suite/wip/rv32i_m/A/RV32A-AMOMAXU-W.S | 66 - riscof/suite/wip/rv32i_m/A/RV32A-AMOMIN-W.S | 67 - riscof/suite/wip/rv32i_m/A/RV32A-AMOMINU-W.S | 65 - riscof/suite/wip/rv32i_m/A/RV32A-AMOOR-W.S | 65 - riscof/suite/wip/rv32i_m/A/RV32A-AMOSWAP-W.S | 66 - riscof/suite/wip/rv32i_m/A/RV32A-AMOXOR-W.S | 66 - riscof/suite/wip/rv32i_m/A/RV32A-LRSC.S | 112 - 365 files changed, 477008 deletions(-) delete mode 100644 riscof/framework/database.yaml delete mode 100644 riscof/suite/compliance.cgf delete mode 100644 riscof/suite/env/arch_test.h delete mode 100644 riscof/suite/env/encoding.h delete mode 100644 riscof/suite/rv32i_m/C/cadd-01.S delete mode 100644 riscof/suite/rv32i_m/C/caddi-01.S delete mode 100644 riscof/suite/rv32i_m/C/caddi16sp-01.S delete mode 100644 riscof/suite/rv32i_m/C/caddi4spn-01.S delete mode 100644 riscof/suite/rv32i_m/C/cand-01.S delete mode 100644 riscof/suite/rv32i_m/C/candi-01.S delete mode 100644 riscof/suite/rv32i_m/C/cbeqz-01.S delete mode 100644 riscof/suite/rv32i_m/C/cbnez-01.S delete mode 100644 riscof/suite/rv32i_m/C/cebreak-01.S delete mode 100644 riscof/suite/rv32i_m/C/cj-01.S delete mode 100644 riscof/suite/rv32i_m/C/cjal-01.S delete mode 100644 riscof/suite/rv32i_m/C/cjalr-01.S delete mode 100644 riscof/suite/rv32i_m/C/cjr-01.S delete mode 100644 riscof/suite/rv32i_m/C/cli-01.S delete mode 100644 riscof/suite/rv32i_m/C/clui-01.S delete mode 100644 riscof/suite/rv32i_m/C/clw-01.S delete mode 100644 riscof/suite/rv32i_m/C/clwsp-01.S delete mode 100644 riscof/suite/rv32i_m/C/cmv-01.S delete mode 100644 riscof/suite/rv32i_m/C/cnop-01.S delete mode 100644 riscof/suite/rv32i_m/C/cor-01.S delete mode 100644 riscof/suite/rv32i_m/C/cslli-01.S delete mode 100644 riscof/suite/rv32i_m/C/csrai-01.S delete mode 100644 riscof/suite/rv32i_m/C/csrli-01.S delete mode 100644 riscof/suite/rv32i_m/C/csub-01.S delete mode 100644 riscof/suite/rv32i_m/C/csw-01.S delete mode 100644 riscof/suite/rv32i_m/C/cswsp-01.S delete mode 100644 riscof/suite/rv32i_m/C/cxor-01.S delete mode 100644 riscof/suite/rv32i_m/I/add-01.S delete mode 100644 riscof/suite/rv32i_m/I/addi-01.S delete mode 100644 riscof/suite/rv32i_m/I/and-01.S delete mode 100644 riscof/suite/rv32i_m/I/andi-01.S delete mode 100644 riscof/suite/rv32i_m/I/auipc-01.S delete mode 100644 riscof/suite/rv32i_m/I/beq-01.S delete mode 100644 riscof/suite/rv32i_m/I/bge-01.S delete mode 100644 riscof/suite/rv32i_m/I/bgeu-01.S delete mode 100644 riscof/suite/rv32i_m/I/blt-01.S delete mode 100644 riscof/suite/rv32i_m/I/bltu-01.S delete mode 100644 riscof/suite/rv32i_m/I/bne-01.S delete mode 100644 riscof/suite/rv32i_m/I/fence-01.S delete mode 100644 riscof/suite/rv32i_m/I/jal-01.S delete mode 100644 riscof/suite/rv32i_m/I/jalr-01.S delete mode 100644 riscof/suite/rv32i_m/I/lb-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/lbu-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/lh-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/lhu-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/lui-01.S delete mode 100644 riscof/suite/rv32i_m/I/lw-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/or-01.S delete mode 100644 riscof/suite/rv32i_m/I/ori-01.S delete mode 100644 riscof/suite/rv32i_m/I/sb-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/sh-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/sll-01.S delete mode 100644 riscof/suite/rv32i_m/I/slli-01.S delete mode 100644 riscof/suite/rv32i_m/I/slt-01.S delete mode 100644 riscof/suite/rv32i_m/I/slti-01.S delete mode 100644 riscof/suite/rv32i_m/I/sltiu-01.S delete mode 100644 riscof/suite/rv32i_m/I/sltu-01.S delete mode 100644 riscof/suite/rv32i_m/I/sra-01.S delete mode 100644 riscof/suite/rv32i_m/I/srai-01.S delete mode 100644 riscof/suite/rv32i_m/I/srl-01.S delete mode 100644 riscof/suite/rv32i_m/I/srli-01.S delete mode 100644 riscof/suite/rv32i_m/I/sub-01.S delete mode 100644 riscof/suite/rv32i_m/I/sw-align-01.S delete mode 100644 riscof/suite/rv32i_m/I/xor-01.S delete mode 100644 riscof/suite/rv32i_m/I/xori-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32DSI-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32DSI-02.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32DSMI-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32DSMI-02.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32ESI-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32ESI-02.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32ESMI-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/AES32ESMI-02.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/ANDN-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/CLMUL-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/CLMULH-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/ORN-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/PACK-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/PACKH-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/PACKU-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/REV-B-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/REV8-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/ROL-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/ROR-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/RORI-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA256SIG0-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA256SIG1-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA256SUM0-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA256SUM1-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA512SIG0H-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA512SIG0L-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA512SIG1H-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA512SIG1L-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA512SUM0R-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SHA512SUM1R-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SM3P0-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SM3P1-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SM4ED-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SM4ED-02.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SM4KS-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/SM4KS-02.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/UNZIP-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/XNOR-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/XPERM-B-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/XPERM-N-01.S delete mode 100644 riscof/suite/rv32i_m/K_unratified/ZIP-01.S delete mode 100644 riscof/suite/rv32i_m/M/div-01.S delete mode 100644 riscof/suite/rv32i_m/M/divu-01.S delete mode 100644 riscof/suite/rv32i_m/M/mul-01.S delete mode 100644 riscof/suite/rv32i_m/M/mulh-01.S delete mode 100644 riscof/suite/rv32i_m/M/mulhsu-01.S delete mode 100644 riscof/suite/rv32i_m/M/mulhu-01.S delete mode 100644 riscof/suite/rv32i_m/M/rem-01.S delete mode 100644 riscof/suite/rv32i_m/M/remu-01.S delete mode 100644 riscof/suite/rv32i_m/Zifencei/Fencei.S delete mode 100644 riscof/suite/rv32i_m/labels.py delete mode 100644 riscof/suite/rv32i_m/privilege/ebreak.S delete mode 100644 riscof/suite/rv32i_m/privilege/ecall.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-beq-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-bge-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-bgeu-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-blt-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-bltu-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-bne-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-jal-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-lh-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-lhu-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-lw-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-sh-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign-sw-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign1-jalr-01.S delete mode 100644 riscof/suite/rv32i_m/privilege/misalign2-jalr-01.S delete mode 100644 riscof/suite/rv64i_m/C/cadd-01.S delete mode 100644 riscof/suite/rv64i_m/C/caddi-01.S delete mode 100644 riscof/suite/rv64i_m/C/caddi16sp-01.S delete mode 100644 riscof/suite/rv64i_m/C/caddi4spn-01.S delete mode 100644 riscof/suite/rv64i_m/C/caddiw-01.S delete mode 100644 riscof/suite/rv64i_m/C/caddw-01.S delete mode 100644 riscof/suite/rv64i_m/C/cand-01.S delete mode 100644 riscof/suite/rv64i_m/C/candi-01.S delete mode 100644 riscof/suite/rv64i_m/C/cbeqz-01.S delete mode 100644 riscof/suite/rv64i_m/C/cbnez-01.S delete mode 100644 riscof/suite/rv64i_m/C/cebreak-01.S delete mode 100644 riscof/suite/rv64i_m/C/cj-01.S delete mode 100644 riscof/suite/rv64i_m/C/cjalr-01.S delete mode 100644 riscof/suite/rv64i_m/C/cjr-01.S delete mode 100644 riscof/suite/rv64i_m/C/cld-01.S delete mode 100644 riscof/suite/rv64i_m/C/cldsp-01.S delete mode 100644 riscof/suite/rv64i_m/C/cli-01.S delete mode 100644 riscof/suite/rv64i_m/C/clui-01.S delete mode 100644 riscof/suite/rv64i_m/C/clw-01.S delete mode 100644 riscof/suite/rv64i_m/C/clwsp-01.S delete mode 100644 riscof/suite/rv64i_m/C/cmv-01.S delete mode 100644 riscof/suite/rv64i_m/C/cnop-01.S delete mode 100644 riscof/suite/rv64i_m/C/cor-01.S delete mode 100644 riscof/suite/rv64i_m/C/csd-01.S delete mode 100644 riscof/suite/rv64i_m/C/csdsp-01.S delete mode 100644 riscof/suite/rv64i_m/C/cslli-01.S delete mode 100644 riscof/suite/rv64i_m/C/csrai-01.S delete mode 100644 riscof/suite/rv64i_m/C/csrli-01.S delete mode 100644 riscof/suite/rv64i_m/C/csub-01.S delete mode 100644 riscof/suite/rv64i_m/C/csubw-01.S delete mode 100644 riscof/suite/rv64i_m/C/csw-01.S delete mode 100644 riscof/suite/rv64i_m/C/cswsp-01.S delete mode 100644 riscof/suite/rv64i_m/C/cxor-01.S delete mode 100644 riscof/suite/rv64i_m/I/add-01.S delete mode 100644 riscof/suite/rv64i_m/I/addi-01.S delete mode 100644 riscof/suite/rv64i_m/I/addiw-01.S delete mode 100644 riscof/suite/rv64i_m/I/addw-01.S delete mode 100644 riscof/suite/rv64i_m/I/and-01.S delete mode 100644 riscof/suite/rv64i_m/I/andi-01.S delete mode 100644 riscof/suite/rv64i_m/I/auipc-01.S delete mode 100644 riscof/suite/rv64i_m/I/beq-01.S delete mode 100644 riscof/suite/rv64i_m/I/bge-01.S delete mode 100644 riscof/suite/rv64i_m/I/bgeu-01.S delete mode 100644 riscof/suite/rv64i_m/I/blt-01.S delete mode 100644 riscof/suite/rv64i_m/I/bltu-01.S delete mode 100644 riscof/suite/rv64i_m/I/bne-01.S delete mode 100644 riscof/suite/rv64i_m/I/fence-01.S delete mode 100644 riscof/suite/rv64i_m/I/jal-01.S delete mode 100644 riscof/suite/rv64i_m/I/jalr-01.S delete mode 100644 riscof/suite/rv64i_m/I/lb-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/lbu-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/ld-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/lh-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/lhu-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/lui-01.S delete mode 100644 riscof/suite/rv64i_m/I/lw-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/lwu-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/or-01.S delete mode 100644 riscof/suite/rv64i_m/I/ori-01.S delete mode 100644 riscof/suite/rv64i_m/I/sb-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/sd-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/sh-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/sll-01.S delete mode 100644 riscof/suite/rv64i_m/I/slli-01.S delete mode 100644 riscof/suite/rv64i_m/I/slliw-01.S delete mode 100644 riscof/suite/rv64i_m/I/sllw-01.S delete mode 100644 riscof/suite/rv64i_m/I/slt-01.S delete mode 100644 riscof/suite/rv64i_m/I/slti-01.S delete mode 100644 riscof/suite/rv64i_m/I/sltiu-01.S delete mode 100644 riscof/suite/rv64i_m/I/sltu-01.S delete mode 100644 riscof/suite/rv64i_m/I/sra-01.S delete mode 100644 riscof/suite/rv64i_m/I/srai-01.S delete mode 100644 riscof/suite/rv64i_m/I/sraiw-01.S delete mode 100644 riscof/suite/rv64i_m/I/sraw-01.S delete mode 100644 riscof/suite/rv64i_m/I/srl-01.S delete mode 100644 riscof/suite/rv64i_m/I/srli-01.S delete mode 100644 riscof/suite/rv64i_m/I/srliw-01.S delete mode 100644 riscof/suite/rv64i_m/I/srlw-01.S delete mode 100644 riscof/suite/rv64i_m/I/sub-01.S delete mode 100644 riscof/suite/rv64i_m/I/subw-01.S delete mode 100644 riscof/suite/rv64i_m/I/sw-align-01.S delete mode 100644 riscof/suite/rv64i_m/I/xor-01.S delete mode 100644 riscof/suite/rv64i_m/I/xori-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64DS-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64DS-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64DSM-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64DSM-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64ES-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64ES-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64ESM-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64ESM-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64IM-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64IM-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64KS1I-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64KS1I-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64KS2-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/AES64KS2-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/ANDN-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/CLMUL-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/CLMULH-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/ORN-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/PACK-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/PACKH-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/PACKU-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/PACKUW-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/PACKW-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/REV-B-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/REV8-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/REV8-W-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/ROL-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/ROLW-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/ROR-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/RORI-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/RORIW-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/RORW-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA256SIG0-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA256SIG1-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA256SUM0-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA256SUM1-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA512SIG0-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA512SIG1-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA512SUM0-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SHA512SUM1-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SM3P0-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SM3P1-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SM4ED-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SM4ED-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SM4KS-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/SM4KS-02.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/XNOR-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/XPERM-B-01.S delete mode 100644 riscof/suite/rv64i_m/K_unratified/XPERM-N-01.S delete mode 100644 riscof/suite/rv64i_m/M/div-01.S delete mode 100644 riscof/suite/rv64i_m/M/divu-01.S delete mode 100644 riscof/suite/rv64i_m/M/divuw-01.S delete mode 100644 riscof/suite/rv64i_m/M/divw-01.S delete mode 100644 riscof/suite/rv64i_m/M/mul-01.S delete mode 100644 riscof/suite/rv64i_m/M/mulh-01.S delete mode 100644 riscof/suite/rv64i_m/M/mulhsu-01.S delete mode 100644 riscof/suite/rv64i_m/M/mulhu-01.S delete mode 100644 riscof/suite/rv64i_m/M/mulw-01.S delete mode 100644 riscof/suite/rv64i_m/M/rem-01.S delete mode 100644 riscof/suite/rv64i_m/M/remu-01.S delete mode 100644 riscof/suite/rv64i_m/M/remuw-01.S delete mode 100644 riscof/suite/rv64i_m/M/remw-01.S delete mode 100644 riscof/suite/rv64i_m/Zifencei/Fencei.S delete mode 100644 riscof/suite/rv64i_m/privilege/ebreak.S delete mode 100644 riscof/suite/rv64i_m/privilege/ecall.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-beq-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-bge-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-bgeu-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-blt-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-bltu-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-bne-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-jal-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-ld-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-lh-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-lhu-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-lw-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-lwu-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-sd-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-sh-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign-sw-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign1-jalr-01.S delete mode 100644 riscof/suite/rv64i_m/privilege/misalign2-jalr-01.S delete mode 100644 riscof/suite/wip/csr_RL_misa.S delete mode 100644 riscof/suite/wip/csr_WARL_misa.S delete mode 100644 riscof/suite/wip/csr_medeleg_ebreak.S delete mode 100644 riscof/suite/wip/csr_medeleg_illegal_instruction.S delete mode 100644 riscof/suite/wip/csr_medeleg_illegal_instruction_modified.S delete mode 100644 riscof/suite/wip/csr_medeleg_instruction_access_fault.S delete mode 100644 riscof/suite/wip/csr_medeleg_instruction_address_misaligned.S delete mode 100644 riscof/suite/wip/csr_medeleg_instruction_page_fault.S delete mode 100644 riscof/suite/wip/csr_medeleg_load_access_fault.S delete mode 100644 riscof/suite/wip/csr_medeleg_load_address_misaligned.S delete mode 100644 riscof/suite/wip/csr_medeleg_load_page_fault.S delete mode 100644 riscof/suite/wip/csr_medeleg_store_access_fault.S delete mode 100644 riscof/suite/wip/csr_medeleg_store_address_misaligned.S delete mode 100644 riscof/suite/wip/csr_medeleg_store_page_fault.S delete mode 100644 riscof/suite/wip/csr_mepc_function_test.S delete mode 100644 riscof/suite/wip/csr_mepc_read_write_test.S delete mode 100644 riscof/suite/wip/csr_misa.S delete mode 100644 riscof/suite/wip/csr_misa_A.S delete mode 100644 riscof/suite/wip/csr_misa_C.S delete mode 100644 riscof/suite/wip/csr_misa_D.S delete mode 100644 riscof/suite/wip/csr_misa_F.S delete mode 100644 riscof/suite/wip/csr_misa_M.S delete mode 100644 riscof/suite/wip/csr_misa_atomic.S delete mode 100644 riscof/suite/wip/csr_misa_cext.S delete mode 100644 riscof/suite/wip/csr_misa_mul.S delete mode 100644 riscof/suite/wip/csr_misa_reserved.S delete mode 100644 riscof/suite/wip/csr_misa_xlen.S delete mode 100644 riscof/suite/wip/csr_mstatus_machine_bit.S delete mode 100644 riscof/suite/wip/csr_mstatus_machine_int.S delete mode 100644 riscof/suite/wip/csr_mstatus_mpp_WARL1.S delete mode 100644 riscof/suite/wip/csr_mstatus_user_bit.S delete mode 100644 riscof/suite/wip/csr_mstatus_user_int.S delete mode 100644 riscof/suite/wip/csr_mtval_fetch_access_fault.S delete mode 100644 riscof/suite/wip/csr_mtval_fetch_misaligned.S delete mode 100644 riscof/suite/wip/csr_mtval_inst_illegal.S delete mode 100644 riscof/suite/wip/csr_mtval_ld_access_fault.S delete mode 100644 riscof/suite/wip/csr_mtval_ld_misaligned.S delete mode 100644 riscof/suite/wip/csr_mtval_st_access_fault.S delete mode 100644 riscof/suite/wip/csr_mtval_st_misaligned.S delete mode 100644 riscof/suite/wip/csr_mtvec_WARL.S delete mode 100644 riscof/suite/wip/csr_mtvec_asyn_interrupt.S delete mode 100644 riscof/suite/wip/csr_mtvec_syn_interrupt.S delete mode 100644 riscof/suite/wip/machine_WARL_macro.S delete mode 100644 riscof/suite/wip/machine_WLRL_misa.S delete mode 100644 riscof/suite/wip/machine_WPRI_mstatus.S delete mode 100644 riscof/suite/wip/machine_delegation.S delete mode 100644 riscof/suite/wip/machine_undefined_csr.S delete mode 100644 riscof/suite/wip/pipelinecleaning/I-MISAC-MISALIGN_JMP-01.S delete mode 100644 riscof/suite/wip/pipelinecleaning/I-MISALIGN_JMP-01.S delete mode 100644 riscof/suite/wip/pipelinecleaning/I-MISALIGN_LDST-01.S delete mode 100644 riscof/suite/wip/pipelinecleaning/csr_misa_M.S delete mode 100644 riscof/suite/wip/pipelinecleaning/csr_mtvec_WARL.S delete mode 100644 riscof/suite/wip/pipelinecleaning/csr_mtvec_mode.S delete mode 100644 riscof/suite/wip/reset_misa.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOADD-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOAND-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOMAX-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOMAXU-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOMIN-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOMINU-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOOR-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOSWAP-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-AMOXOR-W.S delete mode 100644 riscof/suite/wip/rv32i_m/A/RV32A-LRSC.S diff --git a/riscof/framework/database.yaml b/riscof/framework/database.yaml deleted file mode 100644 index 4394b6a..0000000 --- a/riscof/framework/database.yaml +++ /dev/null @@ -1,4823 +0,0 @@ -!!omap -- suite/rv32i_m/C/cadd-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cadd -- suite/rv32i_m/C/caddi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddi -- suite/rv32i_m/C/caddi16sp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddi16sp -- suite/rv32i_m/C/caddi4spn-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddi4spn -- suite/rv32i_m/C/cand-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cand -- suite/rv32i_m/C/candi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - candi -- suite/rv32i_m/C/cbeqz-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cbeqz -- suite/rv32i_m/C/cbnez-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cbnez -- suite/rv32i_m/C/cebreak-01.S: - commit_id: 20aced3a7e09ad68a3d57d51840d804c3d51d363 - isa: RV32IC - parts: !!omap - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - cebreak -- suite/rv32i_m/C/cj-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cj -- suite/rv32i_m/C/cjal-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*RV32.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cjal -- suite/rv32i_m/C/cjalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cjalr -- suite/rv32i_m/C/cjr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cjr -- suite/rv32i_m/C/cli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cli -- suite/rv32i_m/C/clui-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clui -- suite/rv32i_m/C/clw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clw -- suite/rv32i_m/C/clwsp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clwsp -- suite/rv32i_m/C/cmv-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cmv -- suite/rv32i_m/C/cnop-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cnop -- suite/rv32i_m/C/cor-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cor -- suite/rv32i_m/C/cslli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cslli -- suite/rv32i_m/C/csrai-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csrai -- suite/rv32i_m/C/csrli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csrli -- suite/rv32i_m/C/csub-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csub -- suite/rv32i_m/C/csw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csw -- suite/rv32i_m/C/cswsp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cswsp -- suite/rv32i_m/C/cxor-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cxor -- suite/rv32i_m/I/add-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - add -- suite/rv32i_m/I/addi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - addi -- suite/rv32i_m/I/and-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - and -- suite/rv32i_m/I/andi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andi -- suite/rv32i_m/I/auipc-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - auipc -- suite/rv32i_m/I/beq-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - beq -- suite/rv32i_m/I/bge-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bge -- suite/rv32i_m/I/bgeu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bgeu -- suite/rv32i_m/I/blt-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - blt -- suite/rv32i_m/I/bltu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bltu -- suite/rv32i_m/I/bne-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bne -- suite/rv32i_m/I/fence-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - fence -- suite/rv32i_m/I/jal-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - jal -- suite/rv32i_m/I/jalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - jalr -- suite/rv32i_m/I/lb-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lb-align -- suite/rv32i_m/I/lbu-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lbu-align -- suite/rv32i_m/I/lh-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lh-align -- suite/rv32i_m/I/lhu-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lhu-align -- suite/rv32i_m/I/lui-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lui -- suite/rv32i_m/I/lw-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lw-align -- suite/rv32i_m/I/or-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - or -- suite/rv32i_m/I/ori-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ori -- suite/rv32i_m/I/sb-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sb-align -- suite/rv32i_m/I/sh-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sh-align -- suite/rv32i_m/I/sll-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sll -- suite/rv32i_m/I/slli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slli -- suite/rv32i_m/I/slt-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slt -- suite/rv32i_m/I/slti-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slti -- suite/rv32i_m/I/sltiu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sltiu -- suite/rv32i_m/I/sltu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sltu -- suite/rv32i_m/I/sra-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sra -- suite/rv32i_m/I/srai-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srai -- suite/rv32i_m/I/srl-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srl -- suite/rv32i_m/I/srli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srli -- suite/rv32i_m/I/sub-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sub -- suite/rv32i_m/I/sw-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sw-align -- suite/rv32i_m/I/xor-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xor -- suite/rv32i_m/I/xori-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xori -- suite/rv32i_m/K_unratified/AES32DSI-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsi -- suite/rv32i_m/K_unratified/AES32DSI-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsi -- suite/rv32i_m/K_unratified/AES32DSMI-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsmi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsmi -- suite/rv32i_m/K_unratified/AES32DSMI-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsmi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32dsmi -- suite/rv32i_m/K_unratified/AES32ESI-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esi -- suite/rv32i_m/K_unratified/AES32ESI-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esi -- suite/rv32i_m/K_unratified/AES32ESMI-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esmi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esmi -- suite/rv32i_m/K_unratified/AES32ESMI-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esmi - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes32esmi -- suite/rv32i_m/K_unratified/ANDN-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andn - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andn - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andn -- suite/rv32i_m/K_unratified/CLMUL-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmul - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmul - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmul -- suite/rv32i_m/K_unratified/CLMULH-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmulh - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmulh - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmulh -- suite/rv32i_m/K_unratified/ORN-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - orn - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - orn - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - orn -- suite/rv32i_m/K_unratified/PACK-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - pack - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - pack - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - pack -- suite/rv32i_m/K_unratified/PACKH-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packh - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packh - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packh -- suite/rv32i_m/K_unratified/PACKU-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packu - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packu -- suite/rv32i_m/K_unratified/REV-B-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev.b - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev.b - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev.b -- suite/rv32i_m/K_unratified/REV8-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8 - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8 - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8 -- suite/rv32i_m/K_unratified/ROL-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rol - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rol - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rol -- suite/rv32i_m/K_unratified/ROR-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ror - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ror - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ror -- suite/rv32i_m/K_unratified/RORI-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rori - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rori - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rori -- suite/rv32i_m/K_unratified/SHA256SIG0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig0 - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig0 -- suite/rv32i_m/K_unratified/SHA256SIG1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig1 - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig1 -- suite/rv32i_m/K_unratified/SHA256SUM0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum0 - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum0 -- suite/rv32i_m/K_unratified/SHA256SUM1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum1 - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum1 -- suite/rv32i_m/K_unratified/SHA512SIG0H-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig0h - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig0h -- suite/rv32i_m/K_unratified/SHA512SIG0L-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig0l - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig0l -- suite/rv32i_m/K_unratified/SHA512SIG1H-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig1h - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig1h -- suite/rv32i_m/K_unratified/SHA512SIG1L-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig1l - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig1l -- suite/rv32i_m/K_unratified/SHA512SUM0R-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum0r - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum0r -- suite/rv32i_m/K_unratified/SHA512SUM1R-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum1r - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum1r -- suite/rv32i_m/K_unratified/SM3P0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm3p0 -- suite/rv32i_m/K_unratified/SM3P1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm3p1 -- suite/rv32i_m/K_unratified/SM4ED-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ed -- suite/rv32i_m/K_unratified/SM4ED-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ed -- suite/rv32i_m/K_unratified/SM4KS-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ks -- suite/rv32i_m/K_unratified/SM4KS-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ks -- suite/rv32i_m/K_unratified/UNZIP-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - unzip - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - unzip - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - unzip -- suite/rv32i_m/K_unratified/XNOR-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xnor - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xnor - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xnor -- suite/rv32i_m/K_unratified/XPERM-B-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.b - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.b - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.b -- suite/rv32i_m/K_unratified/XPERM-N-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.n - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.n - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.n -- suite/rv32i_m/K_unratified/ZIP-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - zip - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - zip - - '2': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - zip -- suite/rv32i_m/M/div-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - div -- suite/rv32i_m/M/divu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - divu -- suite/rv32i_m/M/mul-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mul -- suite/rv32i_m/M/mulh-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulh -- suite/rv32i_m/M/mulhsu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulhsu -- suite/rv32i_m/M/mulhu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulhu -- suite/rv32i_m/M/rem-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rem -- suite/rv32i_m/M/remu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - remu -- suite/rv32i_m/Zifencei/Fencei.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check ISA:=regex(.*Zifencei.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - fencei -- suite/rv32i_m/privilege/ebreak.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - ebreak -- suite/rv32i_m/privilege/ecall.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - ecall -- suite/rv32i_m/privilege/misalign-beq-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-beq - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-beq -- suite/rv32i_m/privilege/misalign-bge-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bge - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bge -- suite/rv32i_m/privilege/misalign-bgeu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bgeu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bgeu -- suite/rv32i_m/privilege/misalign-blt-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-blt - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-blt -- suite/rv32i_m/privilege/misalign-bltu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bltu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bltu -- suite/rv32i_m/privilege/misalign-bne-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bne - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bne -- suite/rv32i_m/privilege/misalign-jal-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-jal - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-jal -- suite/rv32i_m/privilege/misalign-lh-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lh - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lh -- suite/rv32i_m/privilege/misalign-lhu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lhu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lhu -- suite/rv32i_m/privilege/misalign-lw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lw - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lw -- suite/rv32i_m/privilege/misalign-sh-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sh - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sh -- suite/rv32i_m/privilege/misalign-sw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sw - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sw -- suite/rv32i_m/privilege/misalign1-jalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign1-jalr -- suite/rv32i_m/privilege/misalign2-jalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV32I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign2-jalr - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign2-jalr -- suite/rv64i_m/C/cadd-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cadd -- suite/rv64i_m/C/caddi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddi -- suite/rv64i_m/C/caddi16sp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddi16sp -- suite/rv64i_m/C/caddi4spn-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddi4spn -- suite/rv64i_m/C/caddiw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddiw -- suite/rv64i_m/C/caddw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - caddw -- suite/rv64i_m/C/cand-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cand -- suite/rv64i_m/C/candi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - candi -- suite/rv64i_m/C/cbeqz-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cbeqz -- suite/rv64i_m/C/cbnez-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cbnez -- suite/rv64i_m/C/cebreak-01.S: - commit_id: 20aced3a7e09ad68a3d57d51840d804c3d51d363 - isa: RV64IC - parts: !!omap - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - cebreak -- suite/rv64i_m/C/cj-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cj -- suite/rv64i_m/C/cjalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cjalr -- suite/rv64i_m/C/cjr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cjr -- suite/rv64i_m/C/cld-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cld -- suite/rv64i_m/C/cldsp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cldsp -- suite/rv64i_m/C/cli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cli -- suite/rv64i_m/C/clui-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clui -- suite/rv64i_m/C/clw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clw -- suite/rv64i_m/C/clwsp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clwsp -- suite/rv64i_m/C/cmv-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cmv -- suite/rv64i_m/C/cnop-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cnop -- suite/rv64i_m/C/cor-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cor -- suite/rv64i_m/C/csd-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csd -- suite/rv64i_m/C/csdsp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csdsp -- suite/rv64i_m/C/cslli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cslli -- suite/rv64i_m/C/csrai-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csrai -- suite/rv64i_m/C/csrli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csrli -- suite/rv64i_m/C/csub-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csub -- suite/rv64i_m/C/csubw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csubw -- suite/rv64i_m/C/csw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - csw -- suite/rv64i_m/C/cswsp-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cswsp -- suite/rv64i_m/C/cxor-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IC - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - cxor -- suite/rv64i_m/I/add-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - add -- suite/rv64i_m/I/addi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - addi -- suite/rv64i_m/I/addiw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - addiw -- suite/rv64i_m/I/addw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - addw -- suite/rv64i_m/I/and-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - and -- suite/rv64i_m/I/andi-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andi -- suite/rv64i_m/I/auipc-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - auipc -- suite/rv64i_m/I/beq-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - beq -- suite/rv64i_m/I/bge-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bge -- suite/rv64i_m/I/bgeu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bgeu -- suite/rv64i_m/I/blt-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - blt -- suite/rv64i_m/I/bltu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bltu -- suite/rv64i_m/I/bne-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - bne -- suite/rv64i_m/I/fence-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - fence -- suite/rv64i_m/I/jal-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - jal -- suite/rv64i_m/I/jalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - jalr -- suite/rv64i_m/I/lb-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lb-align -- suite/rv64i_m/I/lbu-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lbu-align -- suite/rv64i_m/I/ld-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ld-align -- suite/rv64i_m/I/lh-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lh-align -- suite/rv64i_m/I/lhu-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lhu-align -- suite/rv64i_m/I/lui-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lui -- suite/rv64i_m/I/lw-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lw-align -- suite/rv64i_m/I/lwu-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - lwu-align -- suite/rv64i_m/I/or-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - or -- suite/rv64i_m/I/ori-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ori -- suite/rv64i_m/I/sb-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sb-align -- suite/rv64i_m/I/sd-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sd-align -- suite/rv64i_m/I/sh-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sh-align -- suite/rv64i_m/I/sll-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sll -- suite/rv64i_m/I/slli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slli -- suite/rv64i_m/I/slliw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slliw -- suite/rv64i_m/I/sllw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sllw -- suite/rv64i_m/I/slt-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slt -- suite/rv64i_m/I/slti-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - slti -- suite/rv64i_m/I/sltiu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sltiu -- suite/rv64i_m/I/sltu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sltu -- suite/rv64i_m/I/sra-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sra -- suite/rv64i_m/I/srai-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srai -- suite/rv64i_m/I/sraiw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sraiw -- suite/rv64i_m/I/sraw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sraw -- suite/rv64i_m/I/srl-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srl -- suite/rv64i_m/I/srli-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srli -- suite/rv64i_m/I/srliw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srliw -- suite/rv64i_m/I/srlw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64i - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - srlw -- suite/rv64i_m/I/sub-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sub -- suite/rv64i_m/I/subw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - subw -- suite/rv64i_m/I/sw-align-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sw-align -- suite/rv64i_m/I/xor-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xor -- suite/rv64i_m/I/xori-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xori -- suite/rv64i_m/K_unratified/AES64DS-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ds - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ds -- suite/rv64i_m/K_unratified/AES64DS-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ds - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ds -- suite/rv64i_m/K_unratified/AES64DSM-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64dsm - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64dsm -- suite/rv64i_m/K_unratified/AES64DSM-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64dsm - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64dsm -- suite/rv64i_m/K_unratified/AES64ES-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64es - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64es -- suite/rv64i_m/K_unratified/AES64ES-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64es - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64es -- suite/rv64i_m/K_unratified/AES64ESM-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64esm - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64esm -- suite/rv64i_m/K_unratified/AES64ESM-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64esm - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64esm -- suite/rv64i_m/K_unratified/AES64IM-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64im - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64im -- suite/rv64i_m/K_unratified/AES64IM-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64im - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64im -- suite/rv64i_m/K_unratified/AES64KS1I-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks1i - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks1i -- suite/rv64i_m/K_unratified/AES64KS1I-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks1i - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks1i -- suite/rv64i_m/K_unratified/AES64KS2-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks2 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks2 -- suite/rv64i_m/K_unratified/AES64KS2-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks2 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - aes64ks2 -- suite/rv64i_m/K_unratified/ANDN-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andn - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andn - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - andn -- suite/rv64i_m/K_unratified/CLMUL-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmul - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmul - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmul -- suite/rv64i_m/K_unratified/CLMULH-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmulh - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmulh - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - clmulh -- suite/rv64i_m/K_unratified/ORN-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - orn - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - orn - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - orn -- suite/rv64i_m/K_unratified/PACK-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - pack - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - pack - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - pack -- suite/rv64i_m/K_unratified/PACKH-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packh - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packh - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packh -- suite/rv64i_m/K_unratified/PACKU-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packu - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packu - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packu -- suite/rv64i_m/K_unratified/PACKUW-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packuw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packuw - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packuw -- suite/rv64i_m/K_unratified/PACKW-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packw - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - packw -- suite/rv64i_m/K_unratified/REV-B-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev.b - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev.b - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev.b -- suite/rv64i_m/K_unratified/REV8-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8 - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8 -- suite/rv64i_m/K_unratified/REV8-W-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8.w - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8.w - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rev8.w -- suite/rv64i_m/K_unratified/ROL-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rol - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rol - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rol -- suite/rv64i_m/K_unratified/ROLW-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rolw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rolw - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rolw -- suite/rv64i_m/K_unratified/ROR-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ror - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ror - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - ror -- suite/rv64i_m/K_unratified/RORI-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rori - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rori - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rori -- suite/rv64i_m/K_unratified/RORIW-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - roriw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - roriw - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - roriw -- suite/rv64i_m/K_unratified/RORW-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rorw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rorw - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rorw -- suite/rv64i_m/K_unratified/SHA256SIG0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig0 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig0 -- suite/rv64i_m/K_unratified/SHA256SIG1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig1 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sig1 -- suite/rv64i_m/K_unratified/SHA256SUM0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum0 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum0 -- suite/rv64i_m/K_unratified/SHA256SUM1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum0 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha256sum0 -- suite/rv64i_m/K_unratified/SHA512SIG0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig0 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig0 -- suite/rv64i_m/K_unratified/SHA512SIG1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig1 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sig1 -- suite/rv64i_m/K_unratified/SHA512SUM0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum0 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum0 -- suite/rv64i_m/K_unratified/SHA512SUM1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum1 - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sha512sum1 -- suite/rv64i_m/K_unratified/SM3P0-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm3p0 -- suite/rv64i_m/K_unratified/SM3P1-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm3p1 -- suite/rv64i_m/K_unratified/SM4ED-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ed -- suite/rv64i_m/K_unratified/SM4ED-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ed -- suite/rv64i_m/K_unratified/SM4KS-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ks -- suite/rv64i_m/K_unratified/SM4KS-02.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - sm4ks -- suite/rv64i_m/K_unratified/XNOR-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xnor - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xnor - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xnor -- suite/rv64i_m/K_unratified/XPERM-B-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.b - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.b - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.b -- suite/rv64i_m/K_unratified/XPERM-N-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IK - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*K.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.n - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zkn.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.n - - '2': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zks.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - xperm.n -- suite/rv64i_m/M/div-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - div -- suite/rv64i_m/M/divu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - divu -- suite/rv64i_m/M/divuw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - divuw -- suite/rv64i_m/M/divw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - divw -- suite/rv64i_m/M/mul-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mul -- suite/rv64i_m/M/mulh-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulh -- suite/rv64i_m/M/mulhsu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulhsu -- suite/rv64i_m/M/mulhu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulhu -- suite/rv64i_m/M/mulw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - mulw -- suite/rv64i_m/M/rem-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - rem -- suite/rv64i_m/M/remu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - remu -- suite/rv64i_m/M/remuw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - remuw -- suite/rv64i_m/M/remw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64IM - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*RV64.*I.*M.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - remw -- suite/rv64i_m/Zifencei/Fencei.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check ISA:=regex(.*Zifencei.*) - define: - - def TEST_CASE_1=True - coverage_labels: - - fencei -- suite/rv64i_m/privilege/ebreak.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - ebreak -- suite/rv64i_m/privilege/ecall.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - ecall -- suite/rv64i_m/privilege/misalign-beq-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-beq - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-beq -- suite/rv64i_m/privilege/misalign-bge-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bge - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bge -- suite/rv64i_m/privilege/misalign-bgeu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bgeu - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bgeu -- suite/rv64i_m/privilege/misalign-blt-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-blt - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-blt -- suite/rv64i_m/privilege/misalign-bltu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bltu - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bltu -- suite/rv64i_m/privilege/misalign-bne-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bne - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bne -- suite/rv64i_m/privilege/misalign-jal-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-jal - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-jal -- suite/rv64i_m/privilege/misalign-ld-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-ld - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-ld -- suite/rv64i_m/privilege/misalign-lh-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lh - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lh -- suite/rv64i_m/privilege/misalign-lhu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lhu - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lhu -- suite/rv64i_m/privilege/misalign-lw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lw -- suite/rv64i_m/privilege/misalign-lwu-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lwu - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lwu -- suite/rv64i_m/privilege/misalign-sd-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sd - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sd -- suite/rv64i_m/privilege/misalign-sh-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sh - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sh -- suite/rv64i_m/privilege/misalign-sw-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sw - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sw -- suite/rv64i_m/privilege/misalign1-jalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign1-jalr -- suite/rv64i_m/privilege/misalign2-jalr-01.S: - commit_id: 3dd5d13b561e0745cc69886341117ae81119b2cb - isa: RV64I - parts: !!omap - - '0': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign2-jalr - - '1': - check: - - check ISA:=regex(.*64.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign2-jalr diff --git a/riscof/suite/compliance.cgf b/riscof/suite/compliance.cgf deleted file mode 100644 index 879bcb6..0000000 --- a/riscof/suite/compliance.cgf +++ /dev/null @@ -1,2221 +0,0 @@ -# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore - -datasets: - all_regs: &all_regs - x0: 0 - x1: 0 - x2: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - c_regs: &c_regs - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - - all_regs_mx0: &all_regs_mx0 - x1: 0 - x2: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - cbfmt_immval_sgn: &cbfmt_immval_sgn - 'imm_val == (-2**(6-1))': 0 - 'imm_val == 0': 0 - 'imm_val == (2**(6-1)-1)': 0 - 'imm_val == 1': 0 - - rfmt_op_comb: &rfmt_op_comb - 'rs1 == rs2 != rd': 0 - 'rs1 == rd != rs2': 0 - 'rs2 == rd != rs1': 0 - 'rs1 == rs2 == rd': 0 - 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 - - ifmt_op_comb: &ifmt_op_comb - 'rs1 == rd': 0 - 'rs1 != rd': 0 - - sfmt_op_comb: &sfmt_op_comb - 'rs1 == rs2': 0 - 'rs1 != rs2': 0 - - base_rs1val_sgn: &base_rs1val_sgn - 'rs1_val == (-2**(xlen-1))': 0 - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen-1)-1)': 0 - 'rs1_val == 1': 0 - - base_rs2val_sgn: &base_rs2val_sgn - 'rs2_val == (-2**(xlen-1))': 0 - 'rs2_val == 0': 0 - 'rs2_val == (2**(xlen-1)-1)': 0 - 'rs2_val == 1': 0 - - base_rs1val_unsgn: &base_rs1val_unsgn - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen)-1)': 0 - 'rs1_val == 1': 0 - - base_rs2val_unsgn: &base_rs2val_unsgn - 'rs2_val == 0': 0 - 'rs2_val == (2**(xlen)-1)': 0 - 'rs2_val == 1': 0 - - rfmt_val_comb_sgn: &rfmt_val_comb_sgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val > 0 and rs2_val < 0': 0 - 'rs1_val < 0 and rs2_val < 0': 0 - 'rs1_val < 0 and rs2_val > 0': 0 - 'rs1_val == rs2_val': 0 - 'rs1_val != rs2_val': 0 - - rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0 - - ifmt_val_comb_sgn: &ifmt_val_comb_sgn - 'rs1_val == imm_val': 0 - 'rs1_val != imm_val': 0 - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - - ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn - 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 - 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 - - ifmt_base_immval_sgn: &ifmt_base_immval_sgn - 'imm_val == (-2**(12-1))': 0 - 'imm_val == 0': 0 - 'imm_val == (2**(12-1)-1)': 0 - 'imm_val == 1': 0 - - ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn - 'imm_val == 0': 0 - 'imm_val == (2**(12)-1)': 0 - 'imm_val == 1': 0 - - ifmt_base_shift: &ifmt_base_shift - 'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val < 0 and imm_val == 0': 0 - 'rs1_val > 0 and imm_val == 0': 0 - 'rs1_val < 0 and imm_val == (xlen-1)': 0 - 'rs1_val > 0 and imm_val == (xlen-1)': 0 - 'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0 - - ifmt_base_shift_32w: &ifmt_base_shift_32w - 'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0 - 'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0 - 'rs1_val < 0 and imm_val == 0': 0 - 'rs1_val > 0 and imm_val == 0': 0 - 'rs1_val < 0 and imm_val == 31': 0 - 'rs1_val > 0 and imm_val == 31': 0 - 'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0 - - - rfmt_base_shift: &rfmt_base_shift - 'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val < 0 and rs2_val == 0': 0 - 'rs1_val > 0 and rs2_val == 0': 0 - 'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0 - - bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn - 'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - - bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0 - - rs1val_walking: &rs1val_walking - 'walking_ones("rs1_val", xlen)': 0 - 'walking_zeros("rs1_val", xlen)': 0 - 'alternate("rs1_val",xlen)': 0 - - rs2val_walking: &rs2val_walking - 'walking_ones("rs2_val", xlen)': 0 - 'walking_zeros("rs2_val", xlen)': 0 - 'alternate("rs2_val",xlen)': 0 - - ifmt_immval_walking: &ifmt_immval_walking - 'walking_ones("imm_val", 12)': 0 - 'walking_zeros("imm_val", 12)': 0 - 'alternate("imm_val",12)': 0 - - rs1val_walking_unsgn: &rs1val_walking_unsgn - 'walking_ones("rs1_val", xlen,False)': 0 - 'walking_zeros("rs1_val", xlen,False)': 0 - 'alternate("rs1_val",xlen,False)': 0 - - rs2val_walking_unsgn: &rs2val_walking_unsgn - 'walking_ones("rs2_val", xlen,False)': 0 - 'walking_zeros("rs2_val", xlen,False)': 0 - 'alternate("rs2_val",xlen,False)': 0 - - crfmt_val_comb_sgn: &crfmt_val_comb_sgn - 'rs2_val > 0': 0 - 'rs2_val < 0': 0 - - cbimm_val_walking: &cbimm_val_walking - 'walking_ones("imm_val", 6)': 0 - 'walking_zeros("imm_val", 6)': 0 - 'alternate("imm_val",6)': 0 - - ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn - 'walking_ones("imm_val", 12,False)': 0 - 'walking_zeros("imm_val", 12,False)': 0 - 'alternate("imm_val",12,False)': 0 - -ecall: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - ecall: 0 - -ebreak: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - ebreak: 0 - - -fencei: - config: - - check ISA:=regex(.*I.*Zifencei.*) - opcode: - fence.i: 0 - -misalign-lh: - cond: check ISA:=regex(.*I.*Zicsr.*) - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - opcode: - lh: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-lhu: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - lhu: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-lwu: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: - lwu: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign-sd: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: - sd: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - 'ea_align == 4': 0 - 'ea_align == 5': 0 - 'ea_align == 6': 0 - 'ea_align == 7': 0 - -misalign-ld: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*) - opcode: - ld: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - 'ea_align == 4': 0 - 'ea_align == 5': 0 - 'ea_align == 6': 0 - 'ea_align == 7': 0 - -misalign-lw: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - lw: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign-sh: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - sh: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-sw: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - sw: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign2-jalr: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - jalr: 0 - val_comb: - 'ea_align == 2': 0 - -misalign1-jalr: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - jalr: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-jal: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - jal: 0 - val_comb: - 'ea_align == 2': 0 - -misalign-bge: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - bge: 0 - val_comb: - ' rs1_val>rs2_val and ea_align == 2': 0 - -misalign-bgeu: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - bgeu: 0 - val_comb: - ' rs1_val>rs2_val and ea_align == 2': 0 - -misalign-blt: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - blt: 0 - val_comb: - ' rs1_val 0' : 0 - 'imm_val == 1020': 0 - abstract_comb: - 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 - -clw: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lw: 0 - rs1: - <<: *c_regs - rd: - <<: *c_regs - op_comb: - 'rs1 == rd': 0 - 'rs1 != rd': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 - -cld: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.ld: 0 - rs1: - <<: *c_regs - rd: - <<: *c_regs - op_comb: - 'rs1 == rd': 0 - 'rs1 != rd': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 - -csw: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.sw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 - -csd: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.sd: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 - -cnop: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.nop: 0 - val_comb: - abstract_comb: - <<: *cbimm_val_walking - -caddi: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi: 0 - rd: - <<: *all_regs_mx0 - val_comb: - <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *cbimm_val_walking] - -cjal: - config: - - check ISA:=regex(.*RV32.*I.*C.*) - opcode: - c.jal: 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 - -caddiw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.addiw: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'rs1_val == (-2**(xlen-1))': 0 - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen-1)-1)': 0 - 'rs1_val == 1': 0 - <<: [*cbfmt_immval_sgn, *ifmt_val_comb_sgn] - abstract_comb: - 'walking_ones("rs1_val", xlen)': 0 - 'walking_zeros("rs1_val", xlen)': 0 - 'alternate("rs1_val",xlen)': 0 - <<: [*cbimm_val_walking] - -cli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.li: 0 - rd: - <<: *all_regs - val_comb: - <<: [*cbfmt_immval_sgn] - abstract_comb: - 'walking_ones("imm_val", 6)': 0 - 'walking_zeros("imm_val", 6)': 0 - 'alternate("imm_val", 6)': 0 - -caddi16sp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi16sp: 0 - rd: - x2: 0 - val_comb: - <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] - 'imm_val == -512': 0 - 'imm_val == 496': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 - 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 - 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 - -clui: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lui: 0 - rd: - x0: 0 - x1: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - val_comb: - 'rs1_val > 0 and imm_val > 32': 0 - 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 - 'rs1_val < 0 and imm_val > 32': 0 - 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 - abstract_comb: - 'walking_ones("imm_val", 6, False)': 0 - 'walking_zeros("imm_val", 6, False)': 0 - 'alternate("imm_val", 6, False)': 0 - -csrli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.srli: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -csrai: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.srai: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -candi: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.andi: 0 - rs1: - <<: *c_regs - val_comb: - <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *cbimm_val_walking] - -csub: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.sub: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cxor: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.xor: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cor: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.or: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cand: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.and: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -csubw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.subw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -caddw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.addw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cj: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.j: 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 - -cbeqz: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.beqz: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val == 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - 'rs1_val == 0 and imm_val < 0': 0 - <<: [*base_rs1val_sgn] - abstract_comb: - <<: [*rs1val_walking] - -cbnez: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.bnez: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val == 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - 'rs1_val == 0 and imm_val < 0': 0 - <<: [*base_rs1val_sgn] - abstract_comb: - <<: [*rs1val_walking] - -cslli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.slli: 0 - rd: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -clwsp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lwsp: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - -cldsp: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.ldsp: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 - -cjr: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.jr: 0 - rs1: - <<: *all_regs_mx0 - -cmv: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.mv: 0 - rs2: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - 'rs2 == rd and rs2 != 0': 0 - 'rs2 != rd and rs2 != 0': 0 - val_comb: - <<: [*base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -cadd: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.add: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs_mx0 - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cjalr: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.jalr: 0 - rs1: - <<: *all_regs_mx0 - -cswsp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.swsp: 0 - rs2: - <<: *all_regs - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - -csdsp: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.sdsp: 0 - rs2: - <<: *all_regs - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 -fence: - config: - - check ISA:=regex(.*I.*) - opcode: - fence: 0 - -addi: - config: - - check ISA:=regex(.*I.*) - opcode: - addi: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -slti: - config: - - check ISA:=regex(.*I.*) - opcode: - slti: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -sltiu: - config: - - check ISA:=regex(.*I.*) - opcode: - sltiu: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] - abstract_comb: - <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] - -andi: - config: - - check ISA:=regex(.*I.*) - opcode: - andi: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -ori: - config: - - check ISA:=regex(.*I.*) - opcode: - ori: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -xori: - config: - - check ISA:=regex(.*I.*) - opcode: - xori: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -slli: - config: - - check ISA:=regex(.*I.*) - opcode: - slli: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -srai: - config: - - check ISA:=regex(.*I.*) - opcode: - srai: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -srli: - config: - - check ISA:=regex(.*I.*) - opcode: - srli: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -add: - config: - - check ISA:=regex(.*I.*) - opcode: - add: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sub: - config: - - check ISA:=regex(.*I.*) - opcode: - sub: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -slt: - config: - - check ISA:=regex(.*I.*) - opcode: - slt: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sltu: - config: - - check ISA:=regex(.*I.*) - opcode: - sltu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -and: - config: - - check ISA:=regex(.*I.*) - opcode: - and: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -or: - config: - - check ISA:=regex(.*I.*) - opcode: - or: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -xor: - config: - - check ISA:=regex(.*I.*) - opcode: - xor: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sll: - config: - - check ISA:=regex(.*I.*) - opcode: - sll: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -srl: - config: - - check ISA:=regex(.*I.*) - opcode: - srl: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -sra: - config: - - check ISA:=regex(.*I.*) - opcode: - sra: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -beq: - config: - - check ISA:=regex(.*I.*) - opcode: - beq: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -bge: - config: - - check ISA:=regex(.*I.*) - opcode: - bge: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -bgeu: - config: - - check ISA:=regex(.*I.*) - opcode: - bgeu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_unsgn - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -blt: - config: - - check ISA:=regex(.*I.*) - opcode: - blt: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -bltu: - config: - - check ISA:=regex(.*I.*) - opcode: - bltu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_unsgn - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -bne: - config: - - check ISA:=regex(.*I.*) - opcode: - bne: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -lhu-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lhu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lh-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lh: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lbu-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lbu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lb-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lb: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lw-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lw: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - - -sh-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sh: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - <<: [ *base_rs2val_sgn] - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - abstract_comb: - <<: [*rs2val_walking] - -sb-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sb: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -sw-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sw: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -auipc: - config: - - check ISA:=regex(.*I.*) - opcode: - auipc: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val == 0': 0 - 'imm_val > 0': 0 - 'imm_val == ((2**20)-1)': 0 - -lui: - config: - - check ISA:=regex(.*I.*) - opcode: - lui: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val == 0': 0 - 'imm_val > 0': 0 - 'imm_val == ((2**20)-1)': 0 - -jal: - config: - - check ISA:=regex(.*I.*) - opcode: - jal: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val < 0' : 0 - 'imm_val > 0': 0 - 'imm_val == (-(2**(18)))': 0 - 'imm_val == ((2**(18)))': 0 - -jalr: - config: - - check ISA:=regex(.*I.*) - opcode: - jalr: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - <<: *ifmt_immval_walking - -mul: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mul: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -mulh: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulh: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -mulhu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulhu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -mulhsu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulhsu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -div: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - div: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -divu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - divu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -rem: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - rem: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -remu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - remu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -lwu-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - lwu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -ld-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - ld: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 8) == 0': 0 - 'ea_align == 0 and (imm_val % 8) == 1': 0 - 'ea_align == 0 and (imm_val % 8) == 2': 0 - 'ea_align == 0 and (imm_val % 8) == 3': 0 - 'ea_align == 0 and (imm_val % 8) == 4': 0 - 'ea_align == 0 and (imm_val % 8) == 5': 0 - 'ea_align == 0 and (imm_val % 8) == 6': 0 - 'ea_align == 0 and (imm_val % 8) == 7': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -sd-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sd: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 8) == 0': 0 - 'ea_align == 0 and (imm_val % 8) == 1': 0 - 'ea_align == 0 and (imm_val % 8) == 2': 0 - 'ea_align == 0 and (imm_val % 8) == 3': 0 - 'ea_align == 0 and (imm_val % 8) == 4': 0 - 'ea_align == 0 and (imm_val % 8) == 5': 0 - 'ea_align == 0 and (imm_val % 8) == 6': 0 - 'ea_align == 0 and (imm_val % 8) == 7': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -addiw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - addiw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -slliw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - slliw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -srliw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - srliw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -sraiw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sraiw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -addw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - addw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -subw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - subw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sllw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sllw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 - -srlw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - srlw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 -sraw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sraw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 - -mulw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - mulw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -divw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - divw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -divuw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - divuw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -remw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - remw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -remuw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - remuw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - diff --git a/riscof/suite/env/arch_test.h b/riscof/suite/env/arch_test.h deleted file mode 100644 index b5dab80..0000000 --- a/riscof/suite/env/arch_test.h +++ /dev/null @@ -1,1016 +0,0 @@ -#include "encoding.h" -// TODO the following should come from the YAML. -#ifndef NUM_SPECD_INTCAUSES - #define NUM_SPECD_INTCAUSES 16 -#endif -//#define RVTEST_FIXED_LEN -#ifndef UNROLLSZ - #define UNROLLSZ 5 -#endif -// #ifndef rvtest_gpr_save -// #define rvtest_gpr_save -// #endif - -//----------------------------------------------------------------------- -// RV Arch Test Macros -//----------------------------------------------------------------------- -#ifndef RVMODEL_SET_MSW_INT - #warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_SET_MSW_INT -#endif - -#ifndef RVMODEL_CLEAR_MSW_INT - #warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_CLEAR_MSW_INT -#endif - -#ifndef RVMODEL_CLEAR_MTIMER_INT - #warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_CLEAR_MTIMER_INT -#endif - -#ifndef RVMODEL_CLEAR_MEXT_INT - #warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_CLEAR_MEXT_INT -#endif - -#ifdef RVTEST_FIXED_LEN - #define LI(reg, val)\ - .option push;\ - .option norvc;\ - .align UNROLLSZ;\ - li reg,val;\ - .align UNROLLSZ;\ - .option pop; - - #define LA(reg, val)\ - .option push;\ - .option norvc;\ - .align UNROLLSZ;\ - la reg,val;\ - .align UNROLLSZ;\ - .option pop; - -#else - #define LI(reg,val);\ - .option push;\ - .option norvc;\ - li reg,val;\ - .option pop; - - #define LA(reg,val);\ - .option push;\ - .option norvc;\ - la reg,val;\ - .option pop; -#endif -#if XLEN==64 - #define SREG sd - #define LREG ld - #define REGWIDTH 8 - #define MASK 0xFFFFFFFFFFFFFFFF - -#else - #if XLEN==32 - #define SREG sw - #define LREG lw - #define REGWIDTH 4 - #define MASK 0xFFFFFFFF - - #endif -#endif -#define MMODE_SIG 3 -#define RLENG (REGWIDTH<<3) - -#define RVTEST_ISA(_STR) - -#ifndef DATA_REL_TVAL_MSK - #define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16) -#endif - -#ifndef CODE_REL_TVAL_MSK - #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16) -#endif - - -// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ // - -.macro RVTEST_CODE_BEGIN - .align UNROLLSZ - .section .text.init; - .globl rvtest_init; \ - rvtest_init: -#ifdef rvtest_mtrap_routine - LA(x1, rvtest_trap_prolog ); - jalr ra, x1 - rvtest_prolog_done: -#endif - LI (x1, (0xFEEDBEADFEEDBEAD & MASK)); - LI (x2, (0xFF76DF56FF76DF56 & MASK)); - LI (x3, (0x7FBB6FAB7FBB6FAB & MASK)); - LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK)); - LA (x5, rvtest_code_begin); - LA (x6, rvtest_data_begin); - LI (x7, (0xB7FBB6FAB7FBB6FA & MASK)); - LI (x8, (0x5BFDDB7D5BFDDB7D & MASK)); - LI (x9, (0xADFEEDBEADFEEDBE & MASK)); - LI (x10, (0x56FF76DF56FF76DF & MASK)); - LI (x11, (0xAB7FBB6FAB7FBB6F & MASK)); - LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK)); - LI (x13, (0xEADFEEDBEADFEEDB & MASK)); - LI (x14, (0xF56FF76DF56FF76D & MASK)); - LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)); - LI (x16, (0x7D5BFDDB7D5BFDDB & MASK)); - LI (x17, (0xBEADFEEDBEADFEED & MASK)); - LI (x18, (0xDF56FF76DF56FF76 & MASK)); - LI (x19, (0x6FAB7FBB6FAB7FBB & MASK)); - LI (x20, (0xB7D5BFDDB7D5BFDD & MASK)); - LI (x21, (0xDBEADFEEDBEADFEE & MASK)); - LI (x22, (0x6DF56FF76DF56FF7 & MASK)); - LI (x23, (0xB6FAB7FBB6FAB7FB & MASK)); - LI (x24, (0xDB7D5BFDDB7D5BFD & MASK)); - LI (x25, (0xEDBEADFEEDBEADFE & MASK)); - LI (x26, (0x76DF56FF76DF56FF & MASK)); - LI (x27, (0xBB6FAB7FBB6FAB7F & MASK)); - LI (x28, (0xDDB7D5BFDDB7D5BF & MASK)); - LI (x29, (0xEEDBEADFEEDBEADF & MASK)); - LI (x30, (0xF76DF56FF76DF56F & MASK)); - LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK)); - .globl rvtest_code_begin - rvtest_code_begin: -.endm - -// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------// - -.macro RVTEST_CODE_END - .align 4; - .global rvtest_code_end - rvtest_code_end: -#ifdef rvtest_mtrap_routine - .option push - .option norvc - j exit_cleanup - - rvtest_trap_prolog: - /******************************************************************************/ - /**** Prolog, to be run before any tests ****/ - /**** #include 1 copy of this per mode in rvmodel_boot code? ****/ - /**** ------------------------------------------------------------------- ****/ - /**** if xTVEC isn't completely RW, then we need to change the code at its ****/ - /**** target. The entire trap trampoline and mtrap handler replaces the ****/ - /**** area pointed to by mtvec, after saving its original contents first. ****/ - /**** If it isn't possible to fully write that area, restore and fail. ****/ - /******************************************************************************/ - - //trap_handler_prolog; enter with t1..t6 available - - init_mscratch: - la t1, trapreg_sv - csrrw t1, CSR_MSCRATCH, t1 // swap old mscratch. mscratch not points to trapreg_sv - la t2, mscratch_save - SREG t1, 0(t2) // save old mscratch in mscratch_save region - csrr t1, CSR_MSCRATCH // read the trapreg_sv address - LA( t2, mtrap_sigptr ) // locate the start of the trap signature - SREG t2, 0(t1) // save mtrap_sigptr at first location of trapreg_sv - init_mtvec: - la t1, mtrampoline - la t4, mtvec_save - csrrw t2, CSR_MTVEC, t1 // swap mtvec and trap_trampoline - SREG t2, 0(t4) // save orig mtvec - csrr t3, CSR_MTVEC // now read new_mtval back - beq t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue - - /****************************************************************/ - /**** fixed mtvec, can't move it so move trampoline instead ****/ - /**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end ****/ - /****************************************************************/ - - // t2 = dut's original mtvec setting - // t1 = mtrampoline address - init_tramp: /**** copy trampoline at mtvec tgt ****/ - - csrw CSR_MTVEC, t2 // restore orig mtvec, will now attemp to copy trampoline to it - la t3, tramptbl_sv // addr of save area - addi t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area - - overwrite_tt: // now build new trampoline table with offsets base from curr mtvec - lw t6, 0(t2) // get original mtvec target - sw t6, 0(t3) // save it - lw t5, 0(t1) // get trampoline src - sw t5, 0(t2) // overwrite mtvec target - lw t6, 0(t2) // rd it back to make sure it was written - bne t6, t5, resto_tramp // table isn't fully writable, restore and give up - addi t1, t1, 4 // next src index - addi t2, t2, 4 // next tgt index - addi t3, t3, 4 // next save index - bne t3, t4, overwrite_tt // not done, loop - j rvtest_prolog_done - - resto_tramp: // vector table not writeable, restore - LREG t1, 16(t4) // load mscratch_SAVE at fixed offset from table end - csrw CSR_MSCRATCH, t1 // restore mscratch - LREG t4, 8(t4) // load mtvec_SAVE (used as end of loop marker) - - - resto_loop: // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin - lw t6, 0(t3) // read saved tgt entry - sw t6, 0(t2) // restore original tgt - addi t2, t2, -4 // prev tgt index - addi t3, t3, -4 // prev save index - bne t2, t4, resto_loop // didn't restore to begining yet, loop - - j rvtest_end // failure to replace trampoline - - - #define mhandler \ - csrrw sp, CSR_MSCRATCH, sp; \ - SREG t6, 6*REGWIDTH(sp); \ - jal t6, common_prolog; - - /**********************************************************************/ - /**** This is the entry point for all m-modetraps, vectored or not.****/ - /**** At entry, mscratch will contain a pointer to a scratch area. ****/ - /**** This is an array of branches at 4B intevals that spreads out ****/ - /**** to an array of 32B mhandler macros for specd int causes, and ****/ - /**** to a return for anything above that (which causes a mismatch)****/ - /**********************************************************************/ - mtrampoline: // 64 or 32 entry table - value = 0 - .rept NUM_SPECD_INTCAUSES // located at each possible int vectors - j mtrap_handler + 12*(value) //offset < +/- 1MB - value = value + 1 - .endr - .rept RLENG-NUM_SPECD_INTCAUSES // fill at each impossible entry - mret - .endr - - mtrap_handler: /* after executing, sp points to temp save area, t4 is PC */ - .rept NUM_SPECD_INTCAUSES - mhandler - .endr - - common_prolog: - la t5, common_mhandler - jr t5 - /*********************************************************************/ - /**** common code for all ints & exceptions, will fork to handle ****/ - /**** each separately. The common handler first stores trap mode+ ****/ - /**** vector, and mcause signatures. All traps have 4wd sigs, but ****/ - /**** sw and timer ints only store 3 of the 4. ****/ - /**** sig offset Exception ExtInt SWInt TimerInt ****/ - /**** 0: tval IntID -1 -1 ****/ - /**** 4: mepc mip mip mip ****/ - /**** 8: <---------------------- mcause -------------> ****/ - /**** 12: <--------------------- Vect+mode ----------> ****/ - /*********************************************************************/ - /* in general, CSRs loaded in t2, addresses into t3 */ - - common_mhandler: /* enter with link in t6 */ - SREG t5, 5*REGWIDTH(sp) - SREG t4, 4*REGWIDTH(sp) - SREG t3, 3*REGWIDTH(sp) - SREG t2, 2*REGWIDTH(sp) - SREG t1, 1*REGWIDTH(sp) /* save other temporaries */ - - LREG t1, 0(sp) /* load trap sig pointer (runs backwards from DATA_END) */ - - LA( t3, mtrampoline) - sub t2, t6, t3 /* reloc “link” to 0..63 to show which int vector was taken */ - addi t2, t2, MMODE_SIG /* insert mode# into 1:0 */ - SREG t2, 0*REGWIDTH(t1) /* save 1st sig value, (vect, trapmode) */ - sv_mcause: - csrr t2, CSR_MCAUSE - SREG t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause) */ - - bltz t2, common_mint_handler /* this is a interrupt, not a trap */ - - /********************************************************************/ - /**** This is the exceptions specific code, storing relative mepc****/ - /**** & relative tval signatures. tval is relocated by code or ****/ - /**** data start, or 0 depending on mcause. mepc signature value ****/ - /**** is relocated by code start, and restored adjusted depending****/ - /**** on op alignment so trapped op isn't re-executed. ****/ - /********************************************************************/ - common_mexcpt_handler: - csrr t2, CSR_MEPC - sv_mepc: - LA( t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */ - sub t4, t2, t3 /* convert mepc to rel offset of beginning of test*/ - SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */ - adj_mepc: //adj mepc so there is padding after op, and its 8B aligned - andi t4, t2, 0x2 /* set to 2 if mepc was misaligned */ - sub t2, t2, t4 /* adjust mepc to prev 4B alignment */ - addi t2, t2, 0x8 /* adjust mepc, so it skips past the op, has padding & is 4B aligned */ - csrw CSR_MEPC, t2 /* restore adjusted value, has 1,2, or 3 bytes of padding */ - - - /* calculate relative mtval if it’s an address (by code_begin or data_begin amt) */ - /* note that masks that determine this are implementation specific from YAML */ - - /* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */ - - adj_mtval: - csrr t2, CSR_MCAUSE /* code begin adjustment amount already in t3 */ - - LI(t4, CODE_REL_TVAL_MSK) /* trap#s 12, 3,1,0, -- adjust w/ code_begin */ - sll t4, t4, t2 /* put bit# in MSB */ - bltz t4, sv_mtval /* correct adjustment is code_begin in t3 */ - - LA( t3, mtrap_sigptr) /* adjustment assuming access is to signature region */ - LI(t4, DATA_REL_TVAL_MSK) /* trap#s not 14, 11..8, 2 adjust w/ data_begin */ - sll t4, t4, t2 /* put bit# in MSB */ - bgez t4, no_adj /* correct adjustment is data_begin in t3 */ - sigbound_chk: - csrr t4, CSR_MTVAL /* do a bounds check on mtval */ - bge t3, t4, sv_mtval /* if mtval is greater than the rvmodel_data_begin then use that as anchor */ - LA( t3, rvtest_data_begin) /* else change anchor to rvtest_data_begin */ - blt t3, t4, sv_mtval /* before the signature, use data_begin adj */ - mv t4, t3 /* use sig relative adjust */ - no_adj: - LI(t3, 0) /* else zero adjustment amt */ - - // For Illegal op handling - addi t2, t2, -2 /* check if mcause==2 (illegal op) */ - bnez t2, sv_mtval /* not illegal op, no special treatment */ - csrr t2, CSR_MTVAL - bnez t2, sv_mtval /* mtval isn’t zero, no special treatment */ - illop: - LI(t5, 0x20000) /* get mprv mask */ - csrrs t5, CSR_MSTATUS, t5 /* set mprv while saving the old value */ - csrr t3, CSR_MEPC - lhu t2, 0(t3) /* load 1st 16b of opc w/ old priv, endianess*/ - andi t4, t2, 0x3 - addi t4, t4, -0x3 /* does opcode[1:0]==0b11? (Meaning >16b op) */ - bnez t4, sv_mtval /* entire mtval is in tt2, adj amt will be set to zero */ - lhu t4, 2(t3) - sll t4, t4, 16 - or t3, t2, t4 /* get 2nd hwd, align it & insert it into opcode */ - csrw CSR_MSTATUS, t5 /* restore mstatus */ - -/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/ - - sv_mtval: - csrr t2, CSR_MTVAL - sub t2, t2, t3 /* perform mtval adjust by either code or data position or zero*/ - SREG t2, 3*REGWIDTH(t1) /* save 4th sig value, (rel mtval) into trap signature area */ - - resto_rtn: /* restore and return */ - addi t1, t1,4*REGWIDTH /* adjust trap signature ptr (traps always save 4 words) */ - SREG t1, 0*REGWIDTH(sp) /* save updated trap sig pointer (pts to trap_sigptr */ - - LREG t1, 1*REGWIDTH(sp) - LREG t2, 2*REGWIDTH(sp) - LREG t3, 3*REGWIDTH(sp) - LREG t4, 4*REGWIDTH(sp) - LREG t5, 5*REGWIDTH(sp) - LREG t6, 6*REGWIDTH(sp) /* restore temporaries */ - - csrrw sp, CSR_MSCRATCH, sp /* restore sp from scratch */ - mret - - common_mint_handler: /* t1 has sig ptr, t2 has mcause */ - - LI(t3, 1) - sll t3, t3, t2 /* create mask 1<