diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml new file mode 100644 index 0000000..c2bbf80 --- /dev/null +++ b/.github/workflows/main.yml @@ -0,0 +1,96 @@ +# This is a basic workflow to help you get started with Actions + +name: CI + +# Controls when the action will run. +on: + # Triggers the workflow on push or pull request events but only for the master branch + push: + branches: [ master ] + + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +# A workflow run is made up of one or more jobs that can run sequentially or in parallel +jobs: + # This workflow contains a single job called "build" + build: + # The type of runner that the job will run on + runs-on: ubuntu-latest + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v2 + + - name: Get version + id: get_version + run: | + echo "::set-output name=version::$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md)" + + - name: Set up Python + uses: actions/setup-python@v2 + with: + python-version: '3.6' + + - name: Install dependencies + run: | + pip install -r riscof/requirements.txt + python -m pip install --upgrade pip + pip install setuptools wheel twine + + - name: Publish package + if: github.ref == 'refs/heads/master' + env: + TWINE_USERNAME: ${{ secrets.PYPIUSERNAME }} + TWINE_PASSWORD: ${{ secrets.PYPIPASSWORD }} + run: | + python setup.py sdist bdist_wheel + twine upload dist/* + + - name: Tag + id: create_tag + if: github.ref == 'refs/heads/master' + uses: mathieudutour/github-tag-action@v5.5 + with: + github_token: ${{ secrets.GITHUB_TOKEN }} # This token is provided by Actions, you do not need to create your own token + custom_tag: ${{ steps.get_version.outputs.version }} + create_annotated_tag: True + tag_prefix: '' + + - name: Create Release + id: create_release + if: github.ref == 'refs/heads/master' + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # This token is provided by Actions, you do not need to create your own token + with: + release_branch: refs/heads/master + release_name: ${{ steps.get_version.outputs.version }} + tag_name: ${{ steps.get_version.outputs.version }} + body: ${{ steps.extract-release-notes.outputs.release_notes }} + draft: false + prerelease: false + + # - name: Script + # uses: ammaraskar/sphinx-action@master + # with: + # docs-folder: "docs/" + # pre-build-command: " apt-get update -y && apt-get install -y latexmk texlive-latex-recommended texlive-latex-extra texlive-fonts-recommended" + # build-command: " make latexpdf " + + + # - name: Upload Release Asset + # id: upload-release-asset + # if: github.ref == 'refs/heads/master' + # uses: actions/upload-release-asset@v1 + # env: + # GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + # with: + # upload_url: ${{ steps.create_release.outputs.upload_url }} # This pulls from the CREATE RELEASE step above, referencing it's ID to get its outputs object, which include a `upload_url`. See this blog post for more info: https://jasonet.co/posts/new-features-of-github-actions/#passing-data-to-future-steps + # asset_path: ./docs/build/latex/riscv_config.pdf + # asset_name: riscv_config.pdf + # asset_content_type: application/pdf + + + diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 0000000..29c60f4 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,32 @@ +# This is a basic workflow to help you get started with Actions + +name: test + +# Controls when the action will run. +on: + # Triggers the workflow on push or pull request events but only for the master branch + pull_request: + branches: [ master ] + + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +# A workflow run is made up of one or more jobs that can run sequentially or in parallel +jobs: + check-version: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + + - name: version check + run: | + export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); + echo "CHANGELOG VERSION: $CHNGVER" + export INITVER=$(grep -P "__version__ = '.*?'" riscof/__init__.py | awk '{print $3}'|sed "s/'//g"); + echo "INIT VERSION: $INITVER" + if [ "$CHNGVER" = "$INITVER" ]; then + echo "Versions are equal in Changelog and init.py." + else + echo "Versions are not equal in Changelog and init.py." + exit 1 + fi diff --git a/.gitignore b/.gitignore index 19e2699..f99e905 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,8 @@ common/__pycache__/ framework/__pycache__/ +riscv-arch-test/ + dbgen/__pycache__/ *work/ diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml deleted file mode 100644 index 80b38f5..0000000 --- a/.gitlab-ci.yml +++ /dev/null @@ -1,71 +0,0 @@ -stages: - - pre-merge-check - - deploy - - post-deploy-check - -pre-merge-check: - stage: pre-merge-check - script: - - export PATH="/home/gitlab-runner/.pyenv/bin:$PATH" - - eval "$(pyenv init -)" - - eval "$(pyenv virtualenv-init -)" - - pyenv shell 3.6.10 - - ./version_check.sh - - pip3 install --upgrade pip - - pip3 install -r riscof/requirements.txt -U - #- source /tools/setup.sh - #- git clone https://gitlab.com/incoresemi/riscof-plugins.git - #- python3 -m riscof.main --help - # - python3 -m riscof.main setup --refname=riscvOVPsim --dutname=spike_simple - # - sed -i 's/riscof/riscof\/riscof-plugins/g' config.ini - # - cat config.ini - # - python3 -m riscof.main run --config=config.ini --no-browser - - python3 setup.py sdist - only: - refs: - - merge_requests - tags: - - incore-group - -deploy: - stage: deploy - script: - - export PATH="/home/gitlab-runner/.pyenv/bin:$PATH" - - eval "$(pyenv init -)" - - eval "$(pyenv virtualenv-init -)" - - pyenv shell 3.6.10 - - pip3 install --upgrade pip - - pip install -U twine semver python-gitlab - - python setup.py sdist - - python -m twine upload --username "__token__" --password $pypitoken dist/* - - python /scratch/version-extract.py - only: - refs: - - master - tags: - - incore-group - except: - - schedules - -post-deploy-check: - stage: post-deploy-check - script: - - export PATH="/home/gitlab-runner/.pyenv/bin:$PATH" - - eval "$(pyenv init -)" - - eval "$(pyenv virtualenv-init -)" - - pyenv shell 3.6.10 - - pip3 install --upgrade pip - - pip3 install -U riscof - - source /tools/setup.sh - - git clone https://gitlab.com/incoresemi/riscof-plugins.git - - riscof --help - #- riscof setup --refname=riscvOVPsim --dutname=spike_simple - #- sed -i 's/riscof/riscof\/riscof-plugins/g' config.ini - #- cat config.ini - #- riscof run --config=config.ini --no-browser - only: - refs: - - master - tags: - - incore-group - diff --git a/CHANGELOG.md b/CHANGELOG.md index b6a3248..fa19779 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,7 +1,27 @@ -# Changelog +# CHANGELOG This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [1.21.0] - 2021-07-21 +- Changed CI script from gitlab to github actions +- Removing hosted cgf files +- Removing hosted riscv-test-suite +- Removing hosted database.yaml +- Updated report to capture the version of the riscv-arch-test suite used during run +- Added new cli - 'arch-test' to automatically clone, update and maintain the riscv-arch-test repo +- Using annotated tags for CI releases +- `suite` and `env` are now required cli args +- updated docs + - added new sections on commands and inputs. + - Revised the installation and riscv-arch-test sections. + - Fixed testlist and dbgen usage and formats + - Cleaned up examples. + - Removed testformat spec. + - Removed section on adding new tests. + - Adding new doc on available PLUGINS for RISCOF. + - Fixed links for new repo transition + + ## [1.20.3] - 2021-06-30 - Updated docs with guide on running riscv-arch-tests with RISCOF diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index 1206f8c..ea99f49 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -16,12 +16,12 @@ Types of Contributions Report Bugs ~~~~~~~~~~~ -Report bugs at https://gitlab.com/incoresemi/riscof/issues. +Report bugs at https://github.com/riscv/riscof/issues. Submit Feedback ~~~~~~~~~~~~~~~ -The best way to send feedback is to file an issue at https://gitlab.com/incoresemi/riscof/issues. +The best way to send feedback is to file an issue at https://github.com/riscv/riscof/issues. If you are proposing a feature: @@ -38,7 +38,7 @@ Ready to contribute? Here's how to set up `riscof` for local development. 1. Fork the `riscof` repo on GitLab. 2. Clone your fork locally:: - $ git clone https://gitlab.com/incoresemi/riscof.git + $ git clone https://github.com/riscv/riscof.git 3. Create an issue and WIP merge request that creates a working branch for you:: @@ -54,6 +54,25 @@ Ready to contribute? Here's how to set up `riscof` for local development. 5. Submit a merge request through the GitLab website. +Versioning +---------- + +When issuing pull requests, an entry in the CHANGELOG.md is mandatory. The arch-test-repo adheres to +the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must +be followed while assigning a new version number : + +- Patch-updates: all doc updates (like typos, more clarification,etc) and updates to unratified extensions. +- Minor-updates: Fixing bugs in current features, adding new features which do not break current features or working. +- Major-updates: Changes to the framework flow (backward compatible or incompatible). + +Note: You can have either a patch or minor or major update. +Note: In case of a conflict, the maintainers will decide the final version to be assigned. + +To update the version of the python package for deployment you can use the following:: + +$ bumpversion --no-tag --config-file setup.cfg patch # possible: major / minor / patch + + Merge Request Guidelines ---------------------------- @@ -61,7 +80,7 @@ Before you submit a merge request, check that it meets these guidelines: 1. The merge request should include tests (if any). 2. If the merge request adds functionality, the docs should be updated. -3. The merge request should work for Python 3.6, 3.7 and 3.8, and for PyPy. +3. The merge request should work for Python 3.6, 3.7 and 3.8, and for PyPi. and make sure that the tests (if any) pass for all supported Python versions. Deploying diff --git a/PLUGINS.rst b/PLUGINS.rst new file mode 100644 index 0000000..6c25c71 --- /dev/null +++ b/PLUGINS.rst @@ -0,0 +1,11 @@ +.. _prebuilt_plugins: + +List of Reference RISCOF Plugins +================================ + +This section provides a list of pre-built riscof-plugins which users can refer +to, to build plugins for their own DUT + +- Spike: https://github.com/riscv/riscv-isa-sim/riscof-plugins/README.md +- SAIL_cSim: https://github.com/rems-project/sail-riscv/riscof-plugins/README.md +- InCore Plugins: https://gitlab.com/incoresemi/riscof-plugins (This is a collection of riscof based plugins for various targets hosted purely for reference.) diff --git a/docs/source/_templates/versions.html b/docs/source/_templates/versions.html index 36541fe..361ce6b 100644 --- a/docs/source/_templates/versions.html +++ b/docs/source/_templates/versions.html @@ -15,10 +15,10 @@
{{ _('Quick Links') }}
- Project Home + Project Home
- Releases + Releases
diff --git a/docs/source/arch-tests.rst b/docs/source/arch-tests.rst index a7fb585..8089ad5 100644 --- a/docs/source/arch-tests.rst +++ b/docs/source/arch-tests.rst @@ -13,6 +13,8 @@ to the :ref:`install_riscof` section for the same. Setup all the DUT and Ref Plugins +--------------------------------- + 1. You will first need to install the SAIL C-emulator on your system. You can refer to the :ref:`plugin_models` section for steps on installing the SAIL C-emulator. 2. You will then need to download/clone the ``sail_cSim`` riscof plugin. You can do this with the @@ -21,49 +23,57 @@ Setup all the DUT and Ref Plugins .. code-block:: console $ cd ~/ - $ git clone https://gitlab.com/incoresemi/riscof-plugins.git + $ git clone https://github.com/rems-project/sail-riscv.git + + You will need the path of the `riscof-plugins` directory from the above repo for the next + steps. 3. You will also need to create a riscof-plugin for you own DUT. If you haven't already done so, please refer to the :ref:`plugins` section for details on building one. Create a config.ini file +------------------------ + 1. You will need to create a `config.ini` file with the following contents. .. code-block:: ini [RISCOF] ReferencePlugin=sail_cSim - ReferencePluginPath=/path/to/riscof-plugins/sail_cSim - DUTPlugin= - DUTPluginPath=/path/to/your/dut-plugin-directory + ReferencePluginPath=/path/to/sail-riscv/riscof-plugins/sail_cSim + DUTPlugin= + DUTPluginPath=/path/to/your/dut-directory ## Example configuration for spike plugin. - [dut-plugin-name] - pluginpath=/path/to/your/dut-plugin-directory - ispec=/path/to/your/dut-plugin-directory/dut_isa.yaml - pspec=/path/to/your/dut-plugin-directory/dut_platform.yaml + [dut-name] + pluginpath=/path/to/your/dut-directory + ispec=/path/to/your/dut-directory/dut_isa.yaml + pspec=/path/to/your/dut-directory/dut_platform.yaml [sail_cSim] - pluginpath=/path/to/riscof-plugins/sail_cSim + pluginpath=/path/to/sail-riscv/riscof-plugins/sail_cSim .. tip:: For details on the various configuration options supported by the *sail_cSim* plugin refer `here `_. -.. _csim_docs: https://gitlab.com/incoresemi/riscof-plugins/-/blob/master/sail_cSim/README.md +.. _csim_docs: https://github.com/rems-project/sail-riscv/riscof-plugins/README.md Cloning the riscv-arch-test repo +-------------------------------- + 1. You will also need to download/clone the riscv-arch-test repository: .. code-block:: console - $ cd ~/ - $ git clone https://github.com/riscv/riscv-arch-test.git + $ riscof --verbose info arch-tests --clone Running Tests with RISCOF +------------------------- + 1. Run the tests using the following: .. code-block:: console - $ riscof --verbose run --config ~/config.ini --suite ~/riscv-arch-test/riscv-test-suite/rv32i_m --env ~/riscv-arch-test/riscv-test-suite/env + $ riscof --verbose info run --config ~/config.ini --suite ./riscv-arch-test/riscv-test-suite/rv32i_m --env ./riscv-arch-test/riscv-test-suite/env The above step will first create a database of the all tests from the ``rv32i_m`` directory (recursively). This database can be found in the `riscof_work/database.yaml` file that is diff --git a/docs/source/code-doc.rst b/docs/source/code-doc.rst index b62dfb3..154aca2 100644 --- a/docs/source/code-doc.rst +++ b/docs/source/code-doc.rst @@ -27,6 +27,8 @@ Utils :special-members: :private-members: +.. _abstract_class: + Abstract Base Classes ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/source/commands.rst b/docs/source/commands.rst new file mode 100644 index 0000000..c681d1e --- /dev/null +++ b/docs/source/commands.rst @@ -0,0 +1,177 @@ +.. _commands: + + +############### +RISCOF Commands +############### + +This section provides an overview and working of the various sub commands available in RISCOF. +The current list of subcommands includes: + +- arch-tests +- coverage +- gendb +- setup +- validateyaml +- testlist +- run + +arch-tests +---------- +This command is used to clone and update the tests from the official `riscv-arch-test `_ repository. + +This command requires one of the following flags to be specified from the cli. + +- show-version: Display the current version of the official suite present at the specified directory path. +- clone: Clone the suite from github. +- update: Update the suite to reflect latest changes from github. + +Optional arguments from the cli: + +- get-version: The specific version of the tests to be fetched. Can be used with both the clone and + update flags. The latest release is fetched if skipped. +- dir: The path to the directory where the suite is to be cloned to. Defaults to + ``./riscv-arch-test`` if skipped. + +coverage +-------- + +This command is used to collect the ISA coverage metrics of a given test-suite and generate a coverage +report in html. + +This command will require the following inputs from the cli: + +- suite: The test suite path on which coverage needs to be run +- env: The path to the environment directory containing the suite-specific header files. +- cgf: list of covergroup-format files specifying the coverpoints that need to be covered by the + the suite + +Optional arguments from the cli: + +- config: path to the ``config.ini`` file. Defaults to ``./config.ini`` if skipped. +- work-dir: path to the working directory where all artifacts need to be dumped. Defaults to + ``./riscof_work`` +- no-browser: when used, RISCOF skips automatically opening the html report in the default web + browser. + +The coverage command simply passes the cgf files to the reference plugin's runTests function. The +Reference plugin is responsible to generating a yaml based coverage report for each test using ``riscv-isac``. +The yaml file should be named ``coverage.rpt``. The ``riscv-isac`` run will also generate a data-propagation +report which should be named as ``ref.md``. + +Once the coverage files for each test has been generated, RISCOF will parse through the working +directories and merge all the ``coverage.rpt`` files to create a single yaml coverage report: +``suite_coverage.rpt``. RISCOF then also converts this to an HTML based reports and open it on the +default web-browser. + +For a example on using this feature please refer to the :ref:`coverage` section. + +gendb +----- + +This command is used to generate a database yaml file for all tests available in the test-suite. The +commands requires the following inputs from the cli: + +- suite: The test suite path for which database needs to be generated. +- work-dir: path to the working directory where all artifacts need to be dumped. Defaults to + ``./riscof_work`` + +This utility parses the ``suite`` directory and collects all the .S files. For each .S file, the +utility will parse the test and collect informations from various macros such as RVTEST_ISA, +RVTEST_CASE, etc. For each test the utility will create a new entry in a dictionary which captures +the different parts of the tests, the enabling conditions of each part, the coverage contributions +of each part, any compile macros required for each part and muc more. + +The generated database yaml will follow the syntax described in section :ref:`database`. + +The output of this utility is a ``database.yaml`` located in the ``work_dir`` directory. This file is +used by RISCOF to select and filter tests based on input DUT configuration. + +.. note:: The tests that are parsed by the gendb utility must follow the `TestFormat Spec + `_ set forth + by the riscv-arch-test SIG. + +setup +----- + +The setup command is used to generate a series of Template files that are required by RISCOF. +These files are meant to provide ease to users integrating their DUT to RISCOF for the first time +and should be modified by the users. + +The setup utility takes in the following optional inputs from the cli: + +- dutname: name of the dut for running the tests on. The utility will use this name to create a + template plugin directory with all the relevant files. These files will have to be modified by + the user. Defaults to "spike" when skipped. +- refname: name of the reference plugin to be used in RISCOF. The utility will use this name to + create a reference plugin directory with all the relevant files. + + +The setup utility will also create a sample config.ini file using the above inputs. + +validateyaml +------------ + +This command simply performs a validation of the isa spec and the platform pspec yamls of the DUT +as mentioned in the ``config.ini`` using riscv-config. The outputs are checked version of the yamls in +the directory pointed by ``work_dir`` + +testlist +-------- + +This command is used to filter tests from the database.yaml based on the configuration of DUT +present in the isa and platform yamls as mentioned in the ``config.ini``. This command will require +the following inputs from the cli: + +- suite: The test suite from which the test need to filtered. + +This command takes the following optional inputs from cli + +- config: path to the ``config.ini`` file. Defaults to ``./config.ini`` if skipped. +- work-dir: path to the working directory where all artifacts need to be dumped. Defaults to + ``./riscof_work`` + +The utility first creates a ``database.yaml`` for the input suite. For each test in the database yaml, +this utility will check if the conditions of any parts of a test are enabled based on the isa and +platform yaml specs of the DUT. If any part is enabled, then the corresponding test is entered into +the teslist along with the respective coverage labels and compile macros. + +The utility will dump the test list in the ``testlist.yaml`` file in the ``work_dir`` directory. This +yaml will follow the same syntax as defined in the :ref:`testlist` section. + +run +--- + +This is probably the primary command of RISCOF which is going to be widely used. This command is +currently responsible for first validating the inputs yamls, +creating a database of the tests in the ``suite`` directory, generate a +filtered test-list, run the tests on the DUT and then the Reference Plugins, and finally compare the +generated signatures and present an html report of the findings. + +The following inputs are required on the cli by this command: + +- suite: The test suite path on which coverage needs to be run +- env: The path to the environment directory containing the suite-specific header files. + +Optional arguments from the cli: + +- config: path to the ``config.ini`` file. Defaults to ``./config.ini`` if skipped. +- work-dir: path to the working directory where all artifacts need to be dumped. Defaults to + ``./riscof_work`` +- no-browser: when used, RISCOF skips automatically opening the html report in the default web + browser. + +All artifacts of this command are generated in the ``work_dir`` directory. Typicall artifacts will +include: + +==================== ============================================================= +Artifact Description +==================== ============================================================= +database.yaml This is the database of all the tests in the suite directory +Makefile.DUT* This is the Makefile generated by the DUT Plugin. +Makefile.Reference* This is the Makefile generated by the Reference Plugin. +report.html The final report generated at the end of the run after signature comparison +yaml files verified and checked yaml versions of the input isa and platform yamls +test_list.yaml This list of filtered tests from the database.yaml +src directory this will include a directory for each test in the test_list.yaml. Each test-directory will include the test, compiled-binaries, signatures from both the DUT and the Reference Plugin. +==================== ============================================================= diff --git a/docs/source/conf.py b/docs/source/conf.py index d4390f0..d48bc0b 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -91,7 +91,7 @@ def setup(app): # -- Options for HTML output ------------------------------------------------- -gitlab_url = 'https://gitlab.com/incoresemi/riscof' +github_url = 'https://github.com/riscv/riscof' html_show_sourcelink = True # The theme to use for HTML and HTML Help pages. See the documentation for # a list of builtin themes. diff --git a/docs/source/coverage.rst b/docs/source/coverage.rst index 6f859d4..0a447f1 100644 --- a/docs/source/coverage.rst +++ b/docs/source/coverage.rst @@ -1,8 +1,8 @@ -.. _coverage: - .. highlight:: shell +.. _coverage: + ############## Coverage Stats @@ -11,7 +11,7 @@ Coverage Stats This section will discuss how to generate a coverage statistics report of a given suite using `RISCV_ISAC `_. -If you have followed the `installation ` steps of this guide then ``riscv_isac`` should +If you have followed the :ref:`quickstart` steps of this guide then ``riscv_isac`` should already be installed on your system. If not then please follow the installation guide provided `here `_ to install ``riscv_isac`` @@ -29,13 +29,13 @@ used to check for coverage. A sample ``config.ini`` is shown below:: [RISCOF] ReferencePlugin=cSail ReferencePluginPath=/home/neel/temp/riscof-plugins/sail_cSim - DUTPlugin=spike_simple - DUTPluginPath=/home/neel/temp/riscof-plugins/spike_simple + DUTPlugin=spike + DUTPluginPath=/home/neel/temp/riscof-plugins/spike - [spike_simple] - pluginpath=/home/neel/temp/riscof-plugins/spike_simple - ispec=/home/neel/temp/riscof-plugins/spike_simple/spike_simple_isa.yaml - pspec=/home/neel/temp/riscof-plugins/spike_simple/spike_simple_platform.yaml + [spike] + pluginpath=/home/neel/temp/riscof-plugins/spike + ispec=/home/neel/temp/riscof-plugins/spike/spike_isa.yaml + pspec=/home/neel/temp/riscof-plugins/spike/spike_platform.yaml [cSail] pluginpath=/home/neel/temp/riscof-plugins/sail_cSim @@ -44,7 +44,7 @@ To run coverage .. code-block:: shell-session - $ riscof coverage + $ riscof --verbose debug coverage --suite /path/to/suite --env /path/to/suite The log of the above command is shown below: @@ -53,19 +53,19 @@ The log of the above command is shown below: INFO | [--root--]: Reading configuration from: /home/neel/temp/config.ini INFO | [--root--]: Preparing Models INFO | [--riscv_config.checker--]: Input-ISA file - INFO | [--riscv_config.checker--]: Loading input file: /home/neel/temp/riscof-plugins/spike_simple/spike_simple_isa.yaml + INFO | [--riscv_config.checker--]: Loading input file: /home/neel/temp/riscof-plugins/spike/spike_isa.yaml INFO | [--riscv_config.checker--]: Load Schema /home/neel/.pyenv/versions/3.7.0/envs/venv/lib/python3.7/site-packages/riscv_config/schemas/schema_isa.yaml INFO | [--riscv_config.checker--]: Processing Hart: hart0 INFO | [--riscv_config.checker--]: Initiating Validation INFO | [--riscv_config.checker--]: No errors for Hart: 0 :) INFO | [--riscv_config.checker--]: Initiating post processing and reset value checks. - INFO | [--riscv_config.checker--]: Dumping out Normalized Checked YAML: /home/neel/temp/riscof_work/spike_simple_isa_checked.yaml + INFO | [--riscv_config.checker--]: Dumping out Normalized Checked YAML: /home/neel/temp/riscof_work/spike_isa_checked.yaml INFO | [--riscv_config.checker--]: Input-Platform file - INFO | [--riscv_config.checker--]: Loading input file: /home/neel/temp/riscof-plugins/spike_simple/spike_simple_platform.yaml + INFO | [--riscv_config.checker--]: Loading input file: /home/neel/temp/riscof-plugins/spike/spike_platform.yaml INFO | [--riscv_config.checker--]: Load Schema /home/neel/.pyenv/versions/3.7.0/envs/venv/lib/python3.7/site-packages/riscv_config/schemas/schema_platform.yaml INFO | [--riscv_config.checker--]: Initiating Validation INFO | [--riscv_config.checker--]: No Syntax errors in Input Platform Yaml. :) - INFO | [--riscv_config.checker--]: Dumping out Normalized Checked YAML: /home/neel/temp/riscof_work/spike_simple_platform_checked.yaml + INFO | [--riscv_config.checker--]: Dumping out Normalized Checked YAML: /home/neel/temp/riscof_work/spike_platform_checked.yaml INFO | [--root--]: Will collect Coverage using RISCV-ISAC INFO | [--root--]: CGF file being used : /scratch/git-repo/incoresemi/riscof/riscof/suite/compliance.cgf INFO | [--riscof.framework.test--]: Selecting Tests. diff --git a/docs/source/database.rst b/docs/source/database.rst index f86b977..e3e8998 100644 --- a/docs/source/database.rst +++ b/docs/source/database.rst @@ -4,18 +4,11 @@ Database Generator ################## -RISCOF internally maintains a database of all the assembly tests available in the suite. This -database is maintained as a YAML file and serves the purpose of selecting relevant tests for a given -DUT model. +RISCOF includes an internal utility which is used to generate a database of all the assembly tests +available in a ``suite`` directory. This database is maintained as a YAML file and serves the +purpose of selecting relevant tests for a given DUT model. -The database can be generated for a given suite/folder using the ``dbgen`` (a.k.a database -generator) utility available for developers in the RISCOF git repository. - - -.. warning:: This utility is meant for developers contributing to the assembly suite and is not - intended to be used as a stand-alone utility. - -The ``dbgen`` utility recursively walks the specified directory/suite/modified to find all .S files +The ``dbgen`` utility recursively walks the specified ``suite`` to find all .S files in them and constructs a dictionary of sorts, for the framework. The tests in the directory are identified by their relative path from the repository home. Each test in the database is defined as follows: @@ -54,12 +47,7 @@ Usage .. code-block:: bash - cd riscof - python -m riscof.main gendb - -Output: - - Currently the database is stored in 'framework/database.yaml'. + riscof --verbose debug gendb --env /path/to/env/ --suite /path/to/suite/ Reasons of Failure ^^^^^^^^^^^^^^^^^^ @@ -76,6 +64,6 @@ Notes 1. The database is always alphabetically ordered 2. The database checks for macro sanity - i.e. certain macros exists and in the correct order. -3. Each time a new test is added the database utility has to be run manually and the database.yaml +3. Each time a new test is added to the ``suite`` directory, the database utility has to be run manually and the database.yaml has to be up-streamed manually to the repository. diff --git a/docs/source/index.rst b/docs/source/index.rst index 304ac06..0cccef8 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -10,13 +10,12 @@ Welcome to RISCOF intro overview installation + commands + inputs plugins arch-tests testlist database - newtest coverage - testformat - RISCV-Config [External] code-doc changelog diff --git a/docs/source/inputs.rst b/docs/source/inputs.rst new file mode 100644 index 0000000..c8355f8 --- /dev/null +++ b/docs/source/inputs.rst @@ -0,0 +1,143 @@ +.. _inputs: + +########################### +Understanding RISCOF Inputs +########################### + +There are three major inputs that are required by most of the subcommand of riscof listed in the +:ref:`commands` section: + +1. The ``config.ini`` file +2. The ``DUT plugin directory`` +3. The ``Reference plugin directory`` + +This section will discuss each of the above requirements in detail + +.. _config_syntax: + +Config.ini Syntax +================= + +The ``config.ini`` file follows the `ini `_ syntax and is +used to specify the name of the dut and reference plugins, path of the model plugins, plugin +specific parameters and paths to the DUT's riscv-config based isa and platform yamls. + + +A generic format of the ``config.ini`` file required by riscof is presented below. A similar +template file can be generated using the ``--setup`` command of RISCOF. + +.. code-block:: ini + + [RISCOF] + ReferencePlugin= + ReferencePluginPath + DUTPlugin= + DUTPluginPath= + + [dut-name] + pluginpath= + ispec= + pspec= + jobs= #OPTIONAL + PATH= #OPTIONAL + + [ref-name] + pluginpath= + jobs= #OPTIONAL + PATH= #OPTIONAL + + +The config file also allows you to define specific nodes/fields +which can be used by the respective model plugins. For e.g., in the above template the +`pluginpath` variable under the `[dut-name]` header is available to the DUT python plugin file +via RISCOF. The plugin may use this pluginpath to detect the ``env`` files, scripts and other +collaterals that may be required during execution. + +Similarly one can define more variables and prefixes here which can directly be +used in the respective plugins. This allows one to build parameterized and configurable plugins, the +values of which are defined in the the ``config.ini`` file. + +For example, in the case of sail we can define a ``PATH`` variable which can point to where the C +emulator binaries are located. This allows the plugin to directly probe the variable and use this +as part of the execution commands. + +The idea here is to have a single place of change which is easy rather than hard-coding the same +within the plugins. + +File path specification +----------------------- + +Different values are allowed for the entries in ``config.ini`` to specify a path. +They are checked in the following order, with the first found valid entry being used: + +1. Absolute path: Usage of user home (``~``) is allowed. +2. Relative to current working directory: The path within the location where RISCOF command was + executed. +3. Relative to ``config.ini`` location: A path starting from the point where ``config.ini`` is stored. + +.. _plugin_directory: + +Model Plugin Directories +======================== + +Majority of the RISCOF commands also require access to the DUT and Reference Model plugins for +successful execution. + +A typical DUT plugin directory has the following structure:: + + ├──dut-name/ # DUT plugin templates + ├── env + │   ├── link.ld # DUT linker script + │   └── model_test.h # DUT specific header file + ├── riscof_dut-name.py # DUT python plugin + ├── dut-name_isa.yaml # DUT ISA yaml based on riscv-config + └── dut-name_platform.yaml # DUT Platform yaml based on riscv-config + +A typical Reference directory has the following structure:: + + ├──ref-name/ # Reference plugin templates + ├── env + │   ├── link.ld # Reference linker script + │   └── model_test.h # Reference specific header file + ├── riscof_ref-name.py # Reference python plugin + + +env directory +------------- + +The ``env`` directory in each must contain: + + - ``model_test.h`` header file which provides the model specific macros as described in the + `TestFormat Spec + `_. + - ``link.ld`` linker script which can be used by the plugin during test-compilation. + +The ``env`` folder can also contain other necessary plugin specific files for pre/post processing of +logs, signatures, elfs, etc. + +YAML specs +---------- + +The yaml specs in the DUT plugin directory are the most important inputs to the RISCOF framework. +All decisions of filtering tests depend on the these YAML files. The files must follow the +syntax/format specified by `riscv-config `_. These YAMLs are +validated in RISCOF using riscv-config. + +The YAMLs are only required for the DUT plugin, since the reference plugin should use the same YAMLS +for its configuration and execution. + +.. note:: It is not necessary to have the YAML files in the plugin directory, but is recommended as + a good practice. The files can exist anywhere in your system, as long as the respective paths in + the ``config.ini`` file correctly point to it. + +Python Plugin +------------- + +The python files prefixed with ``riscof_`` are the most important component of the model plugins. +These python files define how the particular model compiles a test, runs it on the DUT and extracts the +signature. + +To provide a standardized interface for all models, the python plugins must define all actions of +the model under specific functions defined by the :ref:`abstract_class` +specified by RISCOF. A more detailed explanation on how to build this file for you model can be +found in the :ref:`plugin_def` section. diff --git a/docs/source/installation.rst b/docs/source/installation.rst index d186262..97ba989 100644 --- a/docs/source/installation.rst +++ b/docs/source/installation.rst @@ -125,7 +125,7 @@ Install RISCOF .. code-block:: console - $ pip3 install git+https://gitlab.com/incoresemi/riscof.git + $ pip3 install git+https://github.com/riscv/riscof.git This is the preferred method to install RISCOF, as it will always install the most recent stable release. @@ -158,13 +158,13 @@ Install RISCOF .. tab:: for Dev - The sources for RISCOF can be downloaded from the `GitLab repo`_. + The sources for RISCOF can be downloaded from the `Github repo`_. You can clone the repository: .. code-block:: console - $ git clone https://gitlab.com/incoresemi/riscof.git + $ git clone https://github.com/riscv/riscof.git Once you have a copy of the source, you can install it with: @@ -174,7 +174,7 @@ Install RISCOF $ cd riscof $ pip3 install --editable . - .. _Gitlab repo: https://gitlab.com/incoresemi/riscof + .. _Github repo: https://github.com/riscv/riscof Test RISCOF =========== @@ -183,91 +183,115 @@ Once you have installed RISCOF you can execute ``riscof --help`` to print the he .. code-block:: bash - usage: riscof [-h] [--version] [--verbose] - {coverage,gendb,setup,validateyaml,run,testlist} ... - - RISCOF is a framework used to run the Architectural Tests on a DUT and check - compatibility with the RISC-V ISA - - optional arguments: - --verbose [Default=info] - --version, -v Print version of RISCOF being used - -h, --help show this help message and exit - - Action: - The action to be performed by riscof. - - {coverage,gendb,setup,validateyaml,run,testlist} - List of actions supported by riscof. - coverage Generate Coverage Report for the given YAML spec. - gendb Generate Database for the standard suite. - setup Initiate setup for riscof. - validateyaml Validate the Input YAMLs using riscv-config. - run Run the tests on DUT and reference and compare - signatures. - testlist Generate the test list for the given DUT and suite. - Action 'coverage' - - usage: riscof coverage [-h] [--config PATH] [--cgf PATH] [--suite PATH] - [--work-dir PATH] [--no-browser] - - optional arguments: - --cgf PATH The Path to the cgf file(s). Multiple allowed - --config PATH The Path to the config file. [Default=./config.ini] - --no-browser Do not open the browser for showing the test report. - --suite PATH The Path to the custom suite directory. - --work-dir PATH The Path to the work-dir. - -h, --help show this help message and exit - - Action 'gendb' - - usage: riscof gendb [-h] [--suite PATH] [--work-dir PATH] - - optional arguments: - --suite PATH The Path to the custom suite directory. - --work-dir PATH The Path to the work-dir. - -h, --help show this help message and exit - - Action 'setup' - - usage: riscof setup [-h] [--dutname NAME] [--refname NAME] [--work-dir PATH] - - optional arguments: - --dutname NAME Name of DUT plugin. [Default=spike] - --refname NAME Name of Reference plugin. [Default=sail_cSim] - --work-dir PATH The Path to the work-dir. - -h, --help show this help message and exit - - Action 'validateyaml' - - usage: riscof validateyaml [-h] [--config PATH] [--work-dir PATH] - - optional arguments: - --config PATH The Path to the config file. [Default=./config.ini] - --work-dir PATH The Path to the work-dir. - -h, --help show this help message and exit - - Action 'run' - - usage: riscof run [-h] [--config PATH] [--suite PATH] [--no-browser] - [--work-dir PATH] - - optional arguments: - --config PATH The Path to the config file. [Default=./config.ini] - --no-browser Do not open the browser for showing the test report. - --suite PATH The Path to the custom suite directory. - --work-dir PATH The Path to the work-dir. - -h, --help show this help message and exit - - Action 'testlist' - - usage: riscof testlist [-h] [--work-dir PATH] [--config PATH] [--suite PATH] - - optional arguments: - --config PATH The Path to the config file. [Default=./config.ini] - --suite PATH The Path to the custom suite directory. - --work-dir PATH The Path to the work-dir. - -h, --help show this help message and exit + usage: riscof [-h] [--version] [--verbose] + {arch-tests,coverage,gendb,setup,validateyaml,run,testlist} ... + + RISCOF is a framework used to run the Architectural Tests on a DUT and check + compatibility with the RISC-V ISA + + optional arguments: + --verbose [Default=info] + --version, -v Print version of RISCOF being used + -h, --help show this help message and exit + + Action: + The action to be performed by riscof. + + {arch-tests,coverage,gendb,setup,validateyaml,run,testlist} + List of actions supported by riscof. + arch-tests Setup and maintenance for Architectural Test Suite. + coverage Generate Coverage Report for the given YAML spec. + gendb Generate Database for the standard suite. + setup Initiate setup for riscof. + validateyaml Validate the Input YAMLs using riscv-config. + run Run the tests on DUT and reference and compare + signatures. + testlist Generate the test list for the given DUT and suite. + Action 'arch-tests' + + usage: riscof arch-tests [-h] [--dir PATH] [--get-version] [--clone] + [--update] [--show-version] + + optional arguments: + --clone Clone and setup the architectural tests from the remote + repository. + --dir PATH The Path to the directory to initialise/containing the + tests.[Default = ./riscv-arch-test] + --get-version Version of the repository to get. To be used with the + update/clone argument. [Default = latest] + --show-version Print the version of the architectural tests being used. + --update Update the architectural tests to the latest release. + -h, --help show this help message and exit + + Action 'coverage' + + usage: riscof coverage [-h] [--config PATH] --cgf PATH --suite PATH --env PATH + [--work-dir PATH] [--no-browser] + + optional arguments: + --cgf PATH The Path to the cgf file(s). Multiple allowed + --config PATH The Path to the config file. [Default=./config.ini] + --env PATH The Path to the custom env directory. + --no-browser Do not open the browser for showing the test report. + --suite PATH The Path to the custom suite directory. + --work-dir PATH The Path to the work-dir. + -h, --help show this help message and exit + + Action 'gendb' + + usage: riscof gendb [-h] --suite PATH --env PATH [--work-dir PATH] + + optional arguments: + --env PATH The Path to the custom env directory. + --suite PATH The Path to the custom suite directory. + --work-dir PATH The Path to the work-dir. + -h, --help show this help message and exit + + Action 'setup' + + usage: riscof setup [-h] [--dutname NAME] [--refname NAME] [--work-dir PATH] + + optional arguments: + --dutname NAME Name of DUT plugin. [Default=spike] + --refname NAME Name of Reference plugin. [Default=sail_cSim] + --work-dir PATH The Path to the work-dir. + -h, --help show this help message and exit + + Action 'validateyaml' + + usage: riscof validateyaml [-h] [--config PATH] [--work-dir PATH] + + optional arguments: + --config PATH The Path to the config file. [Default=./config.ini] + --work-dir PATH The Path to the work-dir. + -h, --help show this help message and exit + + Action 'run' + + usage: riscof run [-h] [--config PATH] --suite PATH --env PATH [--no-browser] + [--work-dir PATH] + + optional arguments: + --config PATH The Path to the config file. [Default=./config.ini] + --env PATH The Path to the custom env directory. + --no-browser Do not open the browser for showing the test report. + --suite PATH The Path to the custom suite directory. + --work-dir PATH The Path to the work-dir. + -h, --help show this help message and exit + + Action 'testlist' + + usage: riscof testlist [-h] [--work-dir PATH] [--config PATH] --suite PATH + --env PATH + + optional arguments: + --config PATH The Path to the config file. [Default=./config.ini] + --env PATH The Path to the custom env directory. + --suite PATH The Path to the custom suite directory. + --work-dir PATH The Path to the work-dir. + -h, --help show this help message and exit + + Install RISCV-GNU Toolchain =========================== @@ -399,16 +423,40 @@ These are often used as reference models in RISCOF. Create Neccesary Env Files ========================== -RISCOF requires python plugins for each model (DUT and Reference) to be submitted. These plugins -provide a quick and standard way of building the model, compiling the tests and executing the tests -on the models. Along with the python plugins of each model, one would also have to provide the -`YAML` configuration files of the DUT as per the norms of ``riscv-config``. Some models might also -require special macros to be executed as prelude or post-testing. These macros can be provided to -RISCOF as a header file: ``model_test.h``. +In order to run tests via RISCOF you will need to provide the following items : + + - **config.ini**: This file is a basic configuration file following the `ini` syntax. This file + will capture information like: name of the dut/reference plugins, path to the plugins, path to + the riscv-config based yamls, etc. For more information on the contents and syntax please refer + to the :ref:`config_syntax` section + - **dut-plugin directory**: RISCOF requires that the DUT model for testing is presented in the + form of a python plugin. The python plugin is nothing more than a python file which includes + certain standard and defined functions to carry out the activities of test-compilation, + execution and signature extraction. This python file name needs to be prefixed with ``riscof_`` + and must be present in the dut-plugin directory. One can refer to the :ref:`plugin_def` section + for more details on how to write this python file. + + The directory will also need to contain the `riscv-config` based isa and platform yamls which provide + a definition of the DUT. These yamls will be used to filter tests that need to be run on the + DUT. + + Finally, an env directory will also need to be present in the dut-plugin directory, which + contains the environment files like the ``model_test.h`` that is required to compile and run the tests + on the DUT. Refer to the `TestFormat spec + `_ for definition of macros that can be used in the + ``model_test.h`` file. The env directory may also include other files like the linker script, + post-processing scripts that the user may want. + + - **reference-plugin directory**: Similar to the DUT plugin, RISCOF also expects a reference model + plugin. The structure of the directory and files is the same as that of the DUT. However, the + isa and platform yamls are not required since RISCOF will always pick the yamls from the DUT + plugin for all purposes. + +.. For sample templates of pre-built plugins please refer to : `riscof-plugins `_. -For sample templates of pre-built plugins please refer to : `riscof-plugins `_. +For sample templates of pre-built plugins please refer to :ref:`prebuilt_plugins`. -To make things even simpler, RISCOF generates standard pre-built templates for DUTs and Reference +To make things simpler, RISCOF generates standard pre-built templates for DUTs and Reference Models for the user via the ``setup`` command as shown below:: $ riscof setup --dutname=spike @@ -418,22 +466,19 @@ The above command will generate the following files and directories in the curre ├──config.ini # configuration file for riscof ├──spike/ # DUT plugin templates ├── env - │   ├── link.ld - │   └── model_test.h - ├── riscof_spike.py - ├── spike_isa.yaml - └── spike_platform.yaml + │   ├── link.ld # DUT linker script + │   └── model_test.h # DUT specific header file + ├── riscof_spike.py # DUT python plugin + ├── spike_isa.yaml # DUT ISA yaml based on riscv-config + └── spike_platform.yaml # DUT Platform yaml based on riscv-config ├──sail_cSim/ # reference plugin templates ├── env - │   ├── link.ld - │   └── model_test.h + │   ├── link.ld # Reference linker script + │   └── model_test.h # Reference model specific header file ├── __init__.py - └── riscof_sail_cSim.py + └── riscof_sail_cSim.py # Reference model python plugin. - - -The ``config.ini`` file is used to capture specific paths of the plugins of reference and DUT model, -along with the paths to isa and platform input YAMLs. The ``config.ini`` will look something like this by default:: +The generate template ``config.ini`` will look something like this by default:: [RISCOF] @@ -456,9 +501,11 @@ above config:: PATH= - The folder ``spike`` contains various templates of files that would be required for testing of any generic DUT. Components of this folder will need to be modified by the user as per the DUT spec. +By default the ``model_test.h`` files and the ``link.ld`` file will work out of the box for +``spike`` and ``sail`` models. + Since our DUT model in this guide is spike, you will only have to change the execute command at line 100 of spike/riscof_spike.py to the following: @@ -466,7 +513,6 @@ spike/riscof_spike.py to the following: execute += self.dut_exe + ' --log-commits --log dump --isa={0} +signature={1} +signature-granularity=4 {2};'.format(self.isa, sig_file, elf) - .. note:: Custom DUTs can go through the various ``#TODO`` comments to figure out what changes need to be made in the respective python file. @@ -486,7 +532,7 @@ We are now ready to run the architectural tests on the DUT via RISCOF. .. tip:: For details on the various configuration options supported by the *sail_cSim* plugin refer `here `_. -.. _csim_docs: https://gitlab.com/incoresemi/riscof-plugins/-/blob/master/sail_cSim/README.md +.. _csim_docs: https://github.com/rems-project/sail-riscv/riscof-plugin/README.md Running RISCOF ============== @@ -518,7 +564,7 @@ This should print the following: [INFO] : No Syntax errors in Input Platform Yaml. :) [INFO] : Dumping out Normalized Checked YAML: /scratch/git-repo/incoresemi/riscof/riscof_work/sample_platform_checked.yaml -The next step is generate the list of tests that need to be run on the models. +The next step is to generate the list of tests that need to be run on the models. .. code-block:: bash diff --git a/docs/source/intro.rst b/docs/source/intro.rst index dbf9769..17b3d5f 100644 --- a/docs/source/intro.rst +++ b/docs/source/intro.rst @@ -18,7 +18,7 @@ comply with that profile. These tests also help ensure that the implementer has both understood and implemented the specification correctly. -The RISC-V Architectural Test suite is a minimal filter. Passing the tests and having the results +The `RISC-V Architectural Test Suite `_ is a minimal filter. Passing the tests and having the results approved by RISC-V International is a prerequisite to licensing the RISC-V trademarks in connection with the design. Passing the RISC-V Architectural Tests does not mean that the design complies with the RISC-V Architecture. These are only a basic set of tests checking important aspects of the specification @@ -41,14 +41,14 @@ Users ----- RISCOF, as a utility is targeted towards verification and design engineers who wish to check if -their RISC-V implementation (simulation models, HDL models, etc.) is compliant to the RISC-V +their RISC-V implementation (simulation models, HDL models, etc.) meets the RISC-V ISA specification. This document will refer to this category of audience as users of RISCOF in the remaining sections of this document. Contributors ------------ -Engineers who would like to enhance the features of the framework or contribute tests to the -architectural test suite, will be referred to as contributors/developers in the remaining sections of this +Engineers who would like to enhance the features of the framework will be referred to as +contributors/developers in the remaining sections of this document. This framework enables engineers to author scalable and parameterized tests which can evolve along with the evolution of the specification itself. diff --git a/docs/source/newtest.rst b/docs/source/newtest.rst deleted file mode 100644 index 45b5878..0000000 --- a/docs/source/newtest.rst +++ /dev/null @@ -1,36 +0,0 @@ -.. _newtest: - -################ -Adding New Tests -################ - -This section pertains to developers who wish to add new tests to the architectural test suite. -Please follow the below steps for such contributions: - -1. All tests should strictly follow the test-spec format available here: - :ref:`Test Spec Format` - -2. The test should then be placed in the appropriate folder within the ``riscof/riscof/suite`` - directory. Guidelines on directory structure are also available in the same - Test Spec Format mentioned above. - -3. After adding the test in the suite directory, you will have to generate the - database YAML using the following command: - - .. code-block:: bash - - riscof gendb - - The above command will generate a new file: ``framework/database.yaml`` - For more information on the dbgen utility please refer: :ref:`database` - -4. Please update the CHANGELOG.md file with your changes. -5. You can now create a merge request on the RISCOF repository which should - contain the following: - - - updated CHANGELOG.md file - - updated database.yaml file - - new assembly file in the suite-directory - -The maintainer is now responsible for reviewing the changes and update the -version number in ``riscof/__init__.py`` for proper pypi deployment. diff --git a/docs/source/overview.rst b/docs/source/overview.rst index 0f91b97..a71cf9b 100644 --- a/docs/source/overview.rst +++ b/docs/source/overview.rst @@ -107,8 +107,8 @@ suites. At the end of execution, RISCOF generates an HTML report which provides details of the implementation and tests that were passed/failed by the implementation. -Execution flow for Contributors -=============================== +Execution flow for Test Developers +================================== This subsection describes at an abstract level a typical flow that will have to be used by test authors to contribute their tests to RISCOF's architectural test suite. @@ -117,10 +117,8 @@ A test by a contributor must always adhere to the :ref:`Test Format Spec `_ or can be handwritten. -Once a suite or directory of tests is available, the contributor can force RISCOF to use only those -tests in the database by using the ``--suite`` argument. This allows the user to validate that the -tests can be compiled and executed on the implementation and the reference model without having to -run all the remaining, already checked-in, tests. +Once a suite or directory of tests is available, the user can validate that the +tests can be compiled and executed on the implementation and the reference model. To provide coverage and quality analysis of the tests being contributed, the contributor can run RISCOF in coverage mode. Under this mode, RISCOF runs the selected set of tests only on the @@ -129,6 +127,8 @@ which provides a coverage report on the entire suite. Note, one must also provid (Cover Group Format File) which contains all the necessary cover-points the tests are meant to cover. Details of the CGF and its format is available here: `CGF `_ . -Once the tests are ready and have passed the quality checks, the contributor make a -pull-request/merge-request on the RISCOF repository with the tests placed in the write order. +.. note:: Generating a coverage report for each test requires support from the reference plugin + itself. RISCOF only performs the function of merging the individual coverage reports. +Once the tests are ready, the contributor can make a pull request on the +`RISCV-ARCH-TEST `_ repository. diff --git a/docs/source/plugins.rst b/docs/source/plugins.rst index c0aadd9..47f06f6 100644 --- a/docs/source/plugins.rst +++ b/docs/source/plugins.rst @@ -2,36 +2,72 @@ .. _plugins: -######################## -Create your Model Plugin -######################## +########################## +Building your Model Plugin +########################## -RISCOF requires python plugins for each model (DUT and Reference) to be submitted. These plugins -provide a quick and standard way of building any model, compiling any/all the tests and -executing the tests on the models. -Why Python Plugins ? -==================== +As mentioned in the :ref:`inputs` section, the DUT and Reference plugin directories (and their +items) are the most crucial components required by the RISCOF framework for successful execution. +This section will walk you through in detail on how to build the various items of the DUT plugin +directories. + +A typical DUT plugin directory has the following structure:: + + ├──dut-name/ # DUT plugin templates + ├── env + │   ├── link.ld # DUT linker script + │   └── model_test.h # DUT specific header file + ├── riscof_dut-name.py # DUT python plugin + ├── dut-name_isa.yaml # DUT ISA yaml based on riscv-config + └── dut-name_platform.yaml # DUT Platform yaml based on riscv-config + +The ``env`` directory in must contain: + + - ``model_test.h`` header file which provides the model specific macros as described in the + `TestFormat Spec + `_. + - ``link.ld`` linker script which can be used by the plugin during test-compilation. + +The ``env`` folder can also contain other necessary plugin specific files for pre/post processing of +logs, signatures, elfs, etc. -Since the entire RISCOF framework is in python it did not make sense to have the -user-DUT in a separate environment. It would then cause issues in transferring data across -these environments/domains. +The yaml specs in the DUT plugin directory are the most important inputs to the RISCOF framework. +All decisions of filtering tests depend on the these YAML files. The files must follow the +syntax/format specified by `riscv-config `_. These YAMLs are +validated in RISCOF using riscv-config. -While many prefer the conventional *Makefile/autoconf* approach, transferring the *test-list* in YAML -to be used by another Makefile-environment seemed like a bad and an unscalable idea. +The python plugin files capture the behavior of model for compiling tests, executing them on the DUT +and finally extracting the signature for each test. The following sections provide a detailed +explanation on how to build the python files for your model. -Expecting initial hesitation, we have tried to ensure that the python plugins can be made extremely -simple (as crude as writing out bash instructions using shellCommand libraries). -Considering there would be a few backlashes in these choices, we have given enough pit-stops in the -flow: ``validation, test-list, coverage, etc`` so one can stop at any point in the flow and move -to their custom domain. +Why Python Based Plugins ? +========================== +- Since the entire RISCOF framework is in python it did not make sense to have the + user-DUT in a separate environment. It would then cause issues in transferring data across + these environments/domains. + +- While many prefer the conventional *Makefile/autoconf* approach, transferring the *test-list* in YAML + to be used by another Makefile-environment seemed like a bad and an unscalable idea. + +- Expecting initial hesitation, we have tried to ensure that the python plugins can be made extremely + simple (as crude as writing out bash instructions using shellCommand libraries). + +- Considering there would be a few backlashes in these choices, we have given enough pit-stops in the + flow: ``validation, test-list, coverage, etc`` so one can stop at any point in the flow and move + to their custom domain. + +- Having a python plugin **does not change your test-bench** in anyway. The plugins only act as a common + interface between your environment and RISCOF. All you need to do is call the respective sim + commands from within the python plugin. + If you do feel the flow can be further improved or changed please do drop in an issue on the official repository. -Generate Templates -================== +Start with Templates +==================== A sample template of the plugin and all other required collateral can be generated through RISCOF using the following command:: @@ -44,7 +80,7 @@ This above command should generate a spike folder with the following contents: .. code-block:: bash - env # contains sample header file and linker file + env # contains sample header file and linker file riscof_spike.py # sample spike plugin for RISCOF spike_isa.yaml # sample ISA YAML configuration file spike_platform.yaml # sample PLATFORM YAML configuration file @@ -76,50 +112,28 @@ The following changes need to be made: paragraphs. The plugin file in the ``spike`` folder: riscof_spike.py is the one that needs to be -changed and updated for each model. As can be seen from this python file, it creates a Metaclass for the plugins -supported by the abstract base class. This class basically offers the users three basic -functions: ``initialize`` , ``build`` and ``runTests``. For each model RISCOF calls these functions in the following order: +changed and updated for each model as described in the next section. -.. code-block:: bash - - initialize --> build --> runTests Please note the user is free to add more custom functions in this file which are called within the three base functions (as mentioned above). -Config.ini Syntax -================= - -The ``config.ini`` file generated using the above ``--setup`` command is used by RISCOF to locate the DUT and Reference -plugins (along with their necessary collaterals). The config file also allows you to define specific nodes/fields -which can be used by the respective model plugins. For e.g., in the default ``config.ini`` template the -`pluginpath` variable under the `[spike]` header is available to the riscof_spike.py -plugin via RISCOF. Similarly one can define more variables and prefixes here which can directly be -used in the plugins. - -For example, in the case of sail we can define a `PATH` variable which can point to where the C -emulator binaries are located. This allows the plugin to directly probe which variable and use this -as part of the execution commands. - -The idea here is to have a single place of change which is easy rather than hard-coding the same -within the plugins. +.. _plugin_def: -File path specification ------------------------ +Plugin Function Definitions +=========================== -Different values are allowed for the entries in ``config.ini`` to specify a path. -They are checked in the following order, with the first found valid entry being used: - -1. Absolute path: Usage of user home (``~``) is allowed. -2. Relative to current working directory: The path within the location where RISCOF was started. -3. Relative to ``config.ini`` location: A path staring from the point where ``config.ini`` is stored. +As can be seen from the template python file, it creates a Metaclass for the plugins +supported by the :ref:`abstract_class`. This class basically offers the users three basic +functions: ``initialize`` , ``build`` and ``runTests``. +For each model RISCOF calls these functions in the following order: +.. code-block:: bash -Function Definitions -==================== + initialize --> build --> runTests We now define the various arguments and expected functionality of each of the above -mentioned functions. Please note, this is not strict guide and the users can choose to perform +mentioned functions. Please note, this is not a strict guide and the users can choose to perform different actions in different functions as opposed to what is outlined in this guide as long as they comply with the order of the functions being called and the signatures are generated in their respective directories at the end of the `runTest` function. @@ -332,6 +346,9 @@ the ``make.makeCommand``. More details of this utility are available at: :ref:`u make.add_target(execute) make.execute_all(self.work_dir) +.. include:: ../../PLUGINS.rst + + Other Utilities available ========================= diff --git a/docs/source/testlist.rst b/docs/source/testlist.rst index 6e7680d..c01ff5f 100644 --- a/docs/source/testlist.rst +++ b/docs/source/testlist.rst @@ -21,6 +21,7 @@ syntax: work_dir: macros: [ ] isa: + coverage_labels: [ ] test_path: The test-list is meant to be used by the DUT/Golden model plugins to generate execution @@ -30,20 +31,36 @@ A sample test_list.yaml would look like the following: .. code-block:: yaml - suite/rv32i_m/C/C-ADD.S: - work_dir: /scratch/git-repo/incoresemi/riscof-plugins/riscof_work/rv32i_m/C/C-ADD.S - macros: [TEST_CASE_1=True, XLEN=32] - isa: RV32IC - test_path: /home/neel/.pyenv/versions/3.7.0/envs/venv/lib/python3.7/site-packages/riscof/suite/rv32i_m/C/C-ADD.S - suite/rv32i_m/C/C-ADDI.S: - work_dir: /scratch/git-repo/incoresemi/riscof-plugins/riscof_work/rv32i_m/C/C-ADDI.S - macros: [TEST_CASE_1=True, XLEN=32] - isa: RV32IC - test_path: /home/neel/.pyenv/versions/3.7.0/envs/venv/lib/python3.7/site-packages/riscof/suite/rv32i_m/C/C-ADDI.S - suite/rv32i_m/C/C-ADDI16SP.S: - work_dir: /scratch/git-repo/incoresemi/riscof-plugins/riscof_work/rv32i_m/C/C-ADDI16SP.S - macros: [TEST_CASE_1=True, XLEN=32] - isa: RV32IC + /scratch/git-repo/github/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S: + work_dir: /scratch/git-repo/incoresemi/temp/riscof_work/src/div-01.S + macros: + - TEST_CASE_1=True + - XLEN=64 + isa: RV64IM + coverage_labels: + - div + test_path: /scratch/git-repo/github/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S + + /scratch/git-repo/github/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S: + work_dir: /scratch/git-repo/incoresemi/temp/riscof_work/src/divu-01.S + macros: + - TEST_CASE_1=True + - XLEN=64 + isa: RV64IM + coverage_labels: + - divu + test_path: /scratch/git-repo/github/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S + + /scratch/git-repo/github/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S: + work_dir: /scratch/git-repo/incoresemi/temp/riscof_work/src/divuw-01.S + macros: + - TEST_CASE_1=True + - XLEN=64 + isa: RV64IM + coverage_labels: + - divuw + test_path: /scratch/git-repo/github/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S + ... ... ... diff --git a/riscof/Templates/coverage.html b/riscof/Templates/coverage.html index 9eb19a0..130240e 100644 --- a/riscof/Templates/coverage.html +++ b/riscof/Templates/coverage.html @@ -258,10 +258,10 @@

Environment

- + - - + + diff --git a/riscof/Templates/report.html b/riscof/Templates/report.html index 9572242..32710e8 100644 --- a/riscof/Templates/report.html +++ b/riscof/Templates/report.html @@ -270,7 +270,10 @@

Environment

Riscof Version{{ version }}
{{ riscof_version }}
Reference{{ reference }}
Riscv-arch-test Version/Commit Id{{ rvarch_version }}
ISA {{ isa }}
- + + + + diff --git a/riscof/__init__.py b/riscof/__init__.py index 10f2d9f..48d477c 100644 --- a/riscof/__init__.py +++ b/riscof/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'info@incoresemi.com' -__version__ = '1.20.3' +__version__ = '1.21.0' diff --git a/riscof/arch_test.py b/riscof/arch_test.py new file mode 100644 index 0000000..83f97f8 --- /dev/null +++ b/riscof/arch_test.py @@ -0,0 +1,60 @@ +# See LICENSE.incore for details + +import logging +import git +from git import InvalidGitRepositoryError +import riscof.constants as constants +logger = logging.getLogger(__name__) + +def get_version(path): + ver_dict = { + 'commit': '-', + 'version': '-' + } + success = False + try: + repo = git.Repo(path,search_parent_directories=True) + except InvalidGitRepositoryError: + logger.debug("Suite path is not a git repository.") + else: + commit = repo.head.commit + tags = repo.tags + remote = repo.remote() + url = remote.url + if (tags) and (url==constants.https_url or url == ssh_url): + ver_dict['commit'] = str(commit) + for tag in tags: + if tag.commit == commit: + ver_dict['version'] = str(tag) + success = True + else: + logger.debug("Repository is not the official RISCV Architectural Test suite or the \ +branch is not the master branch.") + return ver_dict,success + +def update(path,branch='master'): + version,is_repo = get_version(path) + if is_repo: + logger.debug("Current version of the repository: " + version['version']) + logger.debug("Current commit hash of the repository: " + version['commit']) + repo = git.Repo(path) + repo.git.pull('origin','master') + latest_tag = (repo.tags)[-1] + checkout_target = latest_tag if branch=='latest' else branch + repo.git.checkout(checkout_target) + version,_ = get_version(path) + logger.info("Updated version of the repository: " + version['version']) + logger.info("Updated commit hash of the repository: " + version['commit']) + else: + logger.info("Directory does not contain the riscv-arch-test repo.") + +def clone(path,branch="master"): + logger.info("Clonning repository at "+str(path)) + repo = git.Repo.clone_from(constants.https_url, path) + latest_tag = (repo.tags)[-1] + checkout_target = latest_tag if branch=='latest' else branch + repo.git.checkout(checkout_target) + version, _ = get_version(path) + logger.info("Clonned version {0} of the repository with commit hash {1} ".format( + str(version['version']),version['commit'])) + diff --git a/riscof/constants.py b/riscof/constants.py index dc283e3..a38d51e 100644 --- a/riscof/constants.py +++ b/riscof/constants.py @@ -3,15 +3,18 @@ root = os.path.abspath(os.path.dirname(__file__)) suite = os.path.join(root,"suite/") -cgf_dir = os.path.join(root,"coverage/") - -cgf_file = [] -cgf_file.append(os.path.join(root,"coverage/dataset.cgf")) -for path in os.listdir(cgf_dir): - if path != 'dataset.cgf': - full_path = os.path.join(cgf_dir, path) - if os.path.isfile(full_path): - cgf_file.append(full_path) +#cgf_dir = os.path.join(root,"coverage/") +# +#cgf_file = [] +#cgf_file.append(os.path.join(root,"coverage/dataset.cgf")) +#for path in os.listdir(cgf_dir): +# if path != 'dataset.cgf': +# full_path = os.path.join(cgf_dir, path) +# if os.path.isfile(full_path): +# cgf_file.append(full_path) + +https_url = 'https://github.com/riscv/riscv-arch-test.git' +ssh_url = 'git@github.com:riscv/riscv-arch-test.git' framework_db = os.path.join(root, "framework/database.yaml") cwd = os.getcwd() diff --git a/riscof/coverage/dataset.cgf b/riscof/coverage/dataset.cgf deleted file mode 100644 index d786910..0000000 --- a/riscof/coverage/dataset.cgf +++ /dev/null @@ -1,323 +0,0 @@ -# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore - -datasets: - rv32e_regs_mx0: &rv32e_regs_mx0 - x1: 0 - x2: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - rv32e_regs: &rv32e_regs - x0: 0 - x1: 0 - x2: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - - all_regs: &all_regs - x0: 0 - x1: 0 - x2: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - c_regs: &c_regs - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - - all_regs_mx2: &all_regs_mx2 - x1: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - all_regs_mx0: &all_regs_mx0 - x1: 0 - x2: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - cbfmt_immval_sgn: &cbfmt_immval_sgn - 'imm_val == (-2**(6-1))': 0 - 'imm_val == 0': 0 - 'imm_val == (2**(6-1)-1)': 0 - 'imm_val == 1': 0 - - rfmt_op_comb: &rfmt_op_comb - 'rs1 == rs2 != rd': 0 - 'rs1 == rd != rs2': 0 - 'rs2 == rd != rs1': 0 - 'rs1 == rs2 == rd': 0 - 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 - - ifmt_op_comb: &ifmt_op_comb - 'rs1 == rd': 0 - 'rs1 != rd': 0 - - sfmt_op_comb: &sfmt_op_comb - 'rs1 == rs2': 0 - 'rs1 != rs2': 0 - - base_rs1val_sgn: &base_rs1val_sgn - 'rs1_val == (-2**(xlen-1))': 0 - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen-1)-1)': 0 - 'rs1_val == 1': 0 - - base_rs2val_sgn: &base_rs2val_sgn - 'rs2_val == (-2**(xlen-1))': 0 - 'rs2_val == 0': 0 - 'rs2_val == (2**(xlen-1)-1)': 0 - 'rs2_val == 1': 0 - - base_rs1val_unsgn: &base_rs1val_unsgn - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen)-1)': 0 - 'rs1_val == 1': 0 - - base_rs2val_unsgn: &base_rs2val_unsgn - 'rs2_val == 0': 0 - 'rs2_val == (2**(xlen)-1)': 0 - 'rs2_val == 1': 0 - - rfmt_val_comb_sgn: &rfmt_val_comb_sgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val > 0 and rs2_val < 0': 0 - 'rs1_val < 0 and rs2_val < 0': 0 - 'rs1_val < 0 and rs2_val > 0': 0 - 'rs1_val == rs2_val': 0 - 'rs1_val != rs2_val': 0 - - rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0 - - ifmt_val_comb_sgn: &ifmt_val_comb_sgn - 'rs1_val == imm_val': 0 - 'rs1_val != imm_val': 0 - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - - ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn - 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 - 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 - - ifmt_base_immval_sgn: &ifmt_base_immval_sgn - 'imm_val == (-2**(12-1))': 0 - 'imm_val == 0': 0 - 'imm_val == (2**(12-1)-1)': 0 - 'imm_val == 1': 0 - - ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn - 'imm_val == 0': 0 - 'imm_val == (2**(12)-1)': 0 - 'imm_val == 1': 0 - - ifmt_base_shift: &ifmt_base_shift - 'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val < 0 and imm_val == 0': 0 - 'rs1_val > 0 and imm_val == 0': 0 - 'rs1_val < 0 and imm_val == (xlen-1)': 0 - 'rs1_val > 0 and imm_val == (xlen-1)': 0 - 'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0 - - ifmt_base_shift_32w: &ifmt_base_shift_32w - 'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0 - 'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0 - 'rs1_val < 0 and imm_val == 0': 0 - 'rs1_val > 0 and imm_val == 0': 0 - 'rs1_val < 0 and imm_val == 31': 0 - 'rs1_val > 0 and imm_val == 31': 0 - 'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0 - - - rfmt_base_shift: &rfmt_base_shift - 'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val < 0 and rs2_val == 0': 0 - 'rs1_val > 0 and rs2_val == 0': 0 - 'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0 - - bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn - 'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - - bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0 - - rs1val_walking: &rs1val_walking - 'walking_ones("rs1_val", xlen)': 0 - 'walking_zeros("rs1_val", xlen)': 0 - 'alternate("rs1_val",xlen)': 0 - - rs2val_walking: &rs2val_walking - 'walking_ones("rs2_val", xlen)': 0 - 'walking_zeros("rs2_val", xlen)': 0 - 'alternate("rs2_val",xlen)': 0 - - ifmt_immval_walking: &ifmt_immval_walking - 'walking_ones("imm_val", 12)': 0 - 'walking_zeros("imm_val", 12)': 0 - 'alternate("imm_val",12)': 0 - - rs1val_walking_unsgn: &rs1val_walking_unsgn - 'walking_ones("rs1_val", xlen,False)': 0 - 'walking_zeros("rs1_val", xlen,False)': 0 - 'alternate("rs1_val",xlen,False)': 0 - - rs2val_walking_unsgn: &rs2val_walking_unsgn - 'walking_ones("rs2_val", xlen,False)': 0 - 'walking_zeros("rs2_val", xlen,False)': 0 - 'alternate("rs2_val",xlen,False)': 0 - - crfmt_val_comb_sgn: &crfmt_val_comb_sgn - 'rs2_val > 0': 0 - 'rs2_val < 0': 0 - - cbimm_val_walking: &cbimm_val_walking - 'walking_ones("imm_val", 6)': 0 - 'walking_zeros("imm_val", 6)': 0 - 'alternate("imm_val",6)': 0 - - ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn - 'walking_ones("imm_val", 12,False)': 0 - 'walking_zeros("imm_val", 12,False)': 0 - 'alternate("imm_val",12,False)': 0 - diff --git a/riscof/coverage/rvi.cgf b/riscof/coverage/rvi.cgf deleted file mode 100644 index 899bea4..0000000 --- a/riscof/coverage/rvi.cgf +++ /dev/null @@ -1,1003 +0,0 @@ -# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore - -fence: - config: - - check ISA:=regex(.*I.*) - opcode: - fence: 0 - -addi: - config: - - check ISA:=regex(.*I.*) - opcode: - addi: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 - <<: [*rs1val_walking, *ifmt_immval_walking] - -slti: - config: - - check ISA:=regex(.*I.*) - opcode: - slti: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 - <<: [*rs1val_walking, *ifmt_immval_walking] - -sltiu: - config: - - check ISA:=regex(.*I.*) - opcode: - sltiu: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)],signed=False)': 0 - <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] - -andi: - config: - - check ISA:=regex(.*I.*) - opcode: - andi: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 - <<: [*rs1val_walking, *ifmt_immval_walking] - -ori: - config: - - check ISA:=regex(.*I.*) - opcode: - ori: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 - <<: [*rs1val_walking, *ifmt_immval_walking] - -xori: - config: - - check ISA:=regex(.*I.*) - opcode: - xori: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 - <<: [*rs1val_walking, *ifmt_immval_walking] - -slli: - config: - - check ISA:=regex(.*I.*) - opcode: - slli: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -srai: - config: - - check ISA:=regex(.*I.*) - opcode: - srai: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -srli: - config: - - check ISA:=regex(.*I.*) - opcode: - srli: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -add: - config: - - check ISA:=regex(.*I.*) - opcode: - add: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -sub: - config: - - check ISA:=regex(.*I.*) - opcode: - sub: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -slt: - config: - - check ISA:=regex(.*I.*) - opcode: - slt: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -sltu: - config: - - check ISA:=regex(.*I.*) - opcode: - sltu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - 'sp_dataset(xlen,signed=False)': 0 - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -and: - config: - - check ISA:=regex(.*I.*) - opcode: - and: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -or: - config: - - check ISA:=regex(.*I.*) - opcode: - or: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -xor: - config: - - check ISA:=regex(.*I.*) - opcode: - xor: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -sll: - config: - - check ISA:=regex(.*I.*) - opcode: - sll: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -srl: - config: - - check ISA:=regex(.*I.*) - opcode: - srl: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -sra: - config: - - check ISA:=regex(.*I.*) - opcode: - sra: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -beq: - config: - - check ISA:=regex(.*I.*) - opcode: - beq: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - 'sp_dataset(xlen)': 0 - -bge: - config: - - check ISA:=regex(.*I.*) - opcode: - bge: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - 'sp_dataset(xlen)': 0 - -bgeu: - config: - - check ISA:=regex(.*I.*) - opcode: - bgeu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_unsgn - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - 'sp_dataset(xlen,signed=False)': 0 - -blt: - config: - - check ISA:=regex(.*I.*) - opcode: - blt: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - 'sp_dataset(xlen)': 0 - -bltu: - config: - - check ISA:=regex(.*I.*) - opcode: - bltu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_unsgn - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - 'sp_dataset(xlen,signed=False)': 0 - -bne: - config: - - check ISA:=regex(.*I.*) - opcode: - bne: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - 'sp_dataset(xlen)': 0 - -lhu-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lhu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lh-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lh: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lbu-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lbu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lb-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lb: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lw-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lw: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - - -sh-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sh: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - <<: [ *base_rs2val_sgn] - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - abstract_comb: - <<: [*rs2val_walking] - -sb-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sb: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -sw-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sw: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -auipc: - config: - - check ISA:=regex(.*I.*) - opcode: - auipc: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val == 0': 0 - 'imm_val > 0': 0 - 'imm_val == ((2**20)-1)': 0 - abstract_comb: - 'sp_dataset(20,["imm_val"],signed=False)': 0 - 'walking_ones("imm_val", 20, False)': 0 - 'walking_zeros("imm_val", 20, False)': 0 - 'alternate("imm_val", 20, False)': 0 - -lui: - config: - - check ISA:=regex(.*I.*) - opcode: - lui: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val == 0': 0 - 'imm_val > 0': 0 - 'imm_val == ((2**20)-1)': 0 - abstract_comb: - 'sp_dataset(20,["imm_val"],signed=False)': 0 - 'walking_ones("imm_val", 20, False)': 0 - 'walking_zeros("imm_val", 20, False)': 0 - 'alternate("imm_val", 20, False)': 0 - -jal: - config: - - check ISA:=regex(.*I.*) - opcode: - jal: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val < 0' : 0 - 'imm_val > 0': 0 - 'imm_val == (-(2**(18)))': 0 - 'imm_val == ((2**(18)))': 0 - -jalr: - config: - - check ISA:=regex(.*I.*) - opcode: - jalr: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - <<: *ifmt_immval_walking - -lwu-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - lwu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -ld-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - ld: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 8) == 0': 0 - 'ea_align == 0 and (imm_val % 8) == 1': 0 - 'ea_align == 0 and (imm_val % 8) == 2': 0 - 'ea_align == 0 and (imm_val % 8) == 3': 0 - 'ea_align == 0 and (imm_val % 8) == 4': 0 - 'ea_align == 0 and (imm_val % 8) == 5': 0 - 'ea_align == 0 and (imm_val % 8) == 6': 0 - 'ea_align == 0 and (imm_val % 8) == 7': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -sd-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sd: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 8) == 0': 0 - 'ea_align == 0 and (imm_val % 8) == 1': 0 - 'ea_align == 0 and (imm_val % 8) == 2': 0 - 'ea_align == 0 and (imm_val % 8) == 3': 0 - 'ea_align == 0 and (imm_val % 8) == 4': 0 - 'ea_align == 0 and (imm_val % 8) == 5': 0 - 'ea_align == 0 and (imm_val % 8) == 6': 0 - 'ea_align == 0 and (imm_val % 8) == 7': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -addiw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - addiw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 - <<: [*rs1val_walking, *ifmt_immval_walking] - -slliw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - slliw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -srliw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - srliw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -sraiw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sraiw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -addw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - addw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -subw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - subw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -sllw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sllw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 - -srlw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - srlw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 -sraw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sraw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 diff --git a/riscof/coverage/rvi_c.cgf b/riscof/coverage/rvi_c.cgf deleted file mode 100644 index cd5f5b7..0000000 --- a/riscof/coverage/rvi_c.cgf +++ /dev/null @@ -1,586 +0,0 @@ -# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore - -cebreak: - config: - - check ISA:=regex(.*I.*Zicsr.*C.*) - opcode: - c.ebreak: 0 - -caddi4spn: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi4spn: 0 - rd: - <<: *c_regs - val_comb: - 'imm_val > 0' : 0 - 'imm_val == 1020': 0 - abstract_comb: - 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 - -clw: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lw: 0 - rs1: - <<: *c_regs - rd: - <<: *c_regs - op_comb: - 'rs1 == rd': 0 - 'rs1 != rd': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 - -cld: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.ld: 0 - rs1: - <<: *c_regs - rd: - <<: *c_regs - op_comb: - 'rs1 == rd': 0 - 'rs1 != rd': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 - -csw: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.sw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 - -csd: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.sd: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 - -cnop: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.nop: 0 - val_comb: - abstract_comb: - <<: *cbimm_val_walking - -caddi: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi: 0 - rd: - <<: *all_regs_mx0 - val_comb: - <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 - <<: [*rs1val_walking, *cbimm_val_walking] - -cjal: - config: - - check ISA:=regex(.*RV32.*I.*C.*) - opcode: - c.jal: 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 - - -caddiw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.addiw: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'rs1_val == (-2**(xlen-1))': 0 - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen-1)-1)': 0 - 'rs1_val == 1': 0 - <<: [*cbfmt_immval_sgn, *ifmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 - 'walking_ones("rs1_val", xlen)': 0 - 'walking_zeros("rs1_val", xlen)': 0 - 'alternate("rs1_val",xlen)': 0 - <<: [*cbimm_val_walking] - -cli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.li: 0 - rd: - <<: *all_regs - val_comb: - <<: [*cbfmt_immval_sgn] - abstract_comb: - 'walking_ones("imm_val", 6)': 0 - 'walking_zeros("imm_val", 6)': 0 - 'alternate("imm_val", 6)': 0 - -caddi16sp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi16sp: 0 - rd: - x2: 0 - val_comb: - <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] - 'imm_val == -512': 0 - 'imm_val == 496': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 - 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 - 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 - -clui: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lui: 0 - rd: - x0: 0 - x1: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - val_comb: - 'rs1_val > 0 and imm_val > 32': 0 - 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 - 'rs1_val < 0 and imm_val > 32': 0 - 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 - abstract_comb: - 'walking_ones("imm_val", 6, False)': 0 - 'walking_zeros("imm_val", 6, False)': 0 - 'alternate("imm_val", 6, False)': 0 - -csrli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.srli: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -csrai: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.srai: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -candi: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.andi: 0 - rs1: - <<: *c_regs - val_comb: - <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 - <<: [*rs1val_walking, *cbimm_val_walking] - -csub: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.sub: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -cxor: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.xor: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -cor: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.or: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -cand: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.and: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -csubw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.subw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -caddw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.addw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -cj: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.j: 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 - -cbeqz: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.beqz: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val == 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - 'rs1_val == 0 and imm_val < 0': 0 - <<: [*base_rs1val_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - -cbnez: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.bnez: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val == 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - 'rs1_val == 0 and imm_val < 0': 0 - <<: [*base_rs1val_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - -cslli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.slli: 0 - rd: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - 'sp_dataset(xlen,["rs1_val"])': 0 - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -clwsp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lwsp: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - -cldsp: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.ldsp: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 - -cjr: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.jr: 0 - rs1: - <<: *all_regs_mx0 - -cmv: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.mv: 0 - rs2: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - 'rs2 == rd and rs2 != 0': 0 - 'rs2 != rd and rs2 != 0': 0 - val_comb: - <<: [*base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen,["rs2_val"])': 0 - <<: [*rs2val_walking] - -cadd: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.add: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs_mx0 - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking,*rs2val_walking] - -cjalr: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.jalr: 0 - rs1: - <<: *all_regs_mx0 - -cswsp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.swsp: 0 - rs2: - <<: *all_regs_mx2 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - -csdsp: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.sdsp: 0 - rs2: - <<: *all_regs_mx2 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/riscof/coverage/rvi_fencei.cgf b/riscof/coverage/rvi_fencei.cgf deleted file mode 100644 index 9a32e49..0000000 --- a/riscof/coverage/rvi_fencei.cgf +++ /dev/null @@ -1,8 +0,0 @@ - -fencei: - config: - - check ISA:=regex(.*I.*Zifencei.*) - opcode: - fence.i: 0 - - diff --git a/riscof/coverage/rvi_m.cgf b/riscof/coverage/rvi_m.cgf deleted file mode 100644 index 88dd077..0000000 --- a/riscof/coverage/rvi_m.cgf +++ /dev/null @@ -1,250 +0,0 @@ -# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore - -mul: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mul: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -mulh: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulh: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -mulhu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulhu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - 'sp_dataset(xlen,signed=False)': 0 - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -mulhsu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulhsu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_unsgn, *rfmt_val_comb_unsgn] - 'rs1_val < 0 and rs2_val > 0': 0 - abstract_comb: - 'sp_dataset(xlen,[("rs1_val",xlen),("rs2_val",xlen,False)])': 0 - <<: [*rs1val_walking, *rs2val_walking_unsgn] - -div: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - div: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -divu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - divu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - 'sp_dataset(xlen,signed=False)': 0 - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -rem: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - rem: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -remu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - remu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - 'sp_dataset(xlen,signed=False)': 0 - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -mulw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - mulw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -divw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - divw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -divuw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - divuw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - 'sp_dataset(xlen,signed=False)': 0 - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -remw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - remw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - 'sp_dataset(xlen)': 0 - <<: [*rs1val_walking, *rs2val_walking] - -remuw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - remuw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - 'sp_dataset(xlen,signed=False)': 0 - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - diff --git a/riscof/coverage/rvi_priv.cgf b/riscof/coverage/rvi_priv.cgf deleted file mode 100644 index c36521e..0000000 --- a/riscof/coverage/rvi_priv.cgf +++ /dev/null @@ -1,201 +0,0 @@ -ecall: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - ecall: 0 - -ebreak: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - ebreak: 0 - -misalign-lh: - cond: check ISA:=regex(.*I.*Zicsr.*) - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - opcode: - lh: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-lhu: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - lhu: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-lwu: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: - lwu: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign-sd: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: - sd: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - 'ea_align == 4': 0 - 'ea_align == 5': 0 - 'ea_align == 6': 0 - 'ea_align == 7': 0 - -misalign-ld: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*) - opcode: - ld: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - 'ea_align == 4': 0 - 'ea_align == 5': 0 - 'ea_align == 6': 0 - 'ea_align == 7': 0 - -misalign-lw: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - lw: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign-sh: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - sh: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-sw: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - sw: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign2-jalr: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - jalr: 0 - val_comb: - 'imm_val%2 == 1 and ea_align == 2': 0 - 'imm_val%2 == 0 and ea_align == 2': 0 - -misalign1-jalr: - config: - - check ISA:=regex(.*I.*) - opcode: - jalr: 0 - val_comb: - 'imm_val%2 == 1 and ea_align == 1': 0 - 'imm_val%2 == 0 and ea_align == 1': 0 - -misalign-jal: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - jal: 0 - val_comb: - 'ea_align == 2': 0 - -misalign-bge: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - bge: 0 - val_comb: - ' rs1_val>rs2_val and ea_align == 2': 0 - -misalign-bgeu: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - bgeu: 0 - val_comb: - ' rs1_val>rs2_val and ea_align == 2': 0 - -misalign-blt: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - blt: 0 - val_comb: - ' rs1_val 0 and rs2_val > 0': 0 - 'rs1_val > 0 and rs2_val < 0': 0 - 'rs1_val < 0 and rs2_val < 0': 0 - 'rs1_val < 0 and rs2_val > 0': 0 - 'rs1_val == rs2_val': 0 - 'rs1_val != rs2_val': 0 - - rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0 - - ifmt_val_comb_sgn: &ifmt_val_comb_sgn - 'rs1_val == imm_val': 0 - 'rs1_val != imm_val': 0 - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - - ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn - 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 - 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 - - ifmt_base_immval_sgn: &ifmt_base_immval_sgn - 'imm_val == (-2**(12-1))': 0 - 'imm_val == 0': 0 - 'imm_val == (2**(12-1)-1)': 0 - 'imm_val == 1': 0 - - ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn - 'imm_val == 0': 0 - 'imm_val == (2**(12)-1)': 0 - 'imm_val == 1': 0 - - ifmt_base_shift: &ifmt_base_shift - 'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val < 0 and imm_val == 0': 0 - 'rs1_val > 0 and imm_val == 0': 0 - 'rs1_val < 0 and imm_val == (xlen-1)': 0 - 'rs1_val > 0 and imm_val == (xlen-1)': 0 - 'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0 - - ifmt_base_shift_32w: &ifmt_base_shift_32w - 'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0 - 'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0 - 'rs1_val < 0 and imm_val == 0': 0 - 'rs1_val > 0 and imm_val == 0': 0 - 'rs1_val < 0 and imm_val == 31': 0 - 'rs1_val > 0 and imm_val == 31': 0 - 'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0 - 'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0 - - - rfmt_base_shift: &rfmt_base_shift - 'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val < 0 and rs2_val == 0': 0 - 'rs1_val > 0 and rs2_val == 0': 0 - 'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0 - 'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0 - - bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn - 'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 - 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - - bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn - 'rs1_val > 0 and rs2_val > 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0 - 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0 - - rs1val_walking: &rs1val_walking - 'walking_ones("rs1_val", xlen)': 0 - 'walking_zeros("rs1_val", xlen)': 0 - 'alternate("rs1_val",xlen)': 0 - - rs2val_walking: &rs2val_walking - 'walking_ones("rs2_val", xlen)': 0 - 'walking_zeros("rs2_val", xlen)': 0 - 'alternate("rs2_val",xlen)': 0 - - ifmt_immval_walking: &ifmt_immval_walking - 'walking_ones("imm_val", 12)': 0 - 'walking_zeros("imm_val", 12)': 0 - 'alternate("imm_val",12)': 0 - - rs1val_walking_unsgn: &rs1val_walking_unsgn - 'walking_ones("rs1_val", xlen,False)': 0 - 'walking_zeros("rs1_val", xlen,False)': 0 - 'alternate("rs1_val",xlen,False)': 0 - - rs2val_walking_unsgn: &rs2val_walking_unsgn - 'walking_ones("rs2_val", xlen,False)': 0 - 'walking_zeros("rs2_val", xlen,False)': 0 - 'alternate("rs2_val",xlen,False)': 0 - - crfmt_val_comb_sgn: &crfmt_val_comb_sgn - 'rs2_val > 0': 0 - 'rs2_val < 0': 0 - - cbimm_val_walking: &cbimm_val_walking - 'walking_ones("imm_val", 6)': 0 - 'walking_zeros("imm_val", 6)': 0 - 'alternate("imm_val",6)': 0 - - ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn - 'walking_ones("imm_val", 12,False)': 0 - 'walking_zeros("imm_val", 12,False)': 0 - 'alternate("imm_val",12,False)': 0 - -ecall: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - ecall: 0 - -ebreak: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - ebreak: 0 - - -fencei: - config: - - check ISA:=regex(.*I.*Zifencei.*) - opcode: - fence.i: 0 - -misalign-lh: - cond: check ISA:=regex(.*I.*Zicsr.*) - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - opcode: - lh: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-lhu: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - lhu: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-lwu: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: - lwu: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign-sd: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*Zicsr.*) - opcode: - sd: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - 'ea_align == 4': 0 - 'ea_align == 5': 0 - 'ea_align == 6': 0 - 'ea_align == 7': 0 - -misalign-ld: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*64.*I.*) - opcode: - ld: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - 'ea_align == 4': 0 - 'ea_align == 5': 0 - 'ea_align == 6': 0 - 'ea_align == 7': 0 - -misalign-lw: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - lw: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign-sh: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - sh: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-sw: - config: - - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True - - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*Zicsr.*) - opcode: - sw: 0 - val_comb: - 'ea_align == 1': 0 - 'ea_align == 2': 0 - 'ea_align == 3': 0 - -misalign2-jalr: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - jalr: 0 - val_comb: - 'ea_align == 2': 0 - -misalign1-jalr: - config: - - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True - opcode: - jalr: 0 - val_comb: - 'ea_align == 1': 0 - -misalign-jal: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - jal: 0 - val_comb: - 'ea_align == 2': 0 - -misalign-bge: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - bge: 0 - val_comb: - ' rs1_val>rs2_val and ea_align == 2': 0 - -misalign-bgeu: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - bgeu: 0 - val_comb: - ' rs1_val>rs2_val and ea_align == 2': 0 - -misalign-blt: - config: - - check ISA:=regex(.*I.*C.*) - - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True - cond: check ISA:=regex(.*I.*) - opcode: - blt: 0 - val_comb: - ' rs1_val 0' : 0 - 'imm_val == 1020': 0 - abstract_comb: - 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 - -clw: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lw: 0 - rs1: - <<: *c_regs - rd: - <<: *c_regs - op_comb: - 'rs1 == rd': 0 - 'rs1 != rd': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 - -cld: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.ld: 0 - rs1: - <<: *c_regs - rd: - <<: *c_regs - op_comb: - 'rs1 == rd': 0 - 'rs1 != rd': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 - -csw: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.sw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 - -csd: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.sd: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 - -cnop: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.nop: 0 - val_comb: - abstract_comb: - <<: *cbimm_val_walking - -caddi: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi: 0 - rd: - <<: *all_regs_mx0 - val_comb: - <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *cbimm_val_walking] - -cjal: - config: - - check ISA:=regex(.*RV32.*I.*C.*) - opcode: - c.jal: 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 - -caddiw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.addiw: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'rs1_val == (-2**(xlen-1))': 0 - 'rs1_val == 0': 0 - 'rs1_val == (2**(xlen-1)-1)': 0 - 'rs1_val == 1': 0 - <<: [*cbfmt_immval_sgn, *ifmt_val_comb_sgn] - abstract_comb: - 'walking_ones("rs1_val", xlen)': 0 - 'walking_zeros("rs1_val", xlen)': 0 - 'alternate("rs1_val",xlen)': 0 - <<: [*cbimm_val_walking] - -cli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.li: 0 - rd: - <<: *all_regs - val_comb: - <<: [*cbfmt_immval_sgn] - abstract_comb: - 'walking_ones("imm_val", 6)': 0 - 'walking_zeros("imm_val", 6)': 0 - 'alternate("imm_val", 6)': 0 - -caddi16sp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.addi16sp: 0 - rd: - x2: 0 - val_comb: - <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] - 'imm_val == -512': 0 - 'imm_val == 496': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 - 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 - 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 - -clui: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lui: 0 - rd: - x0: 0 - x1: 0 - x3: 0 - x4: 0 - x5: 0 - x6: 0 - x7: 0 - x8: 0 - x9: 0 - x10: 0 - x11: 0 - x12: 0 - x13: 0 - x14: 0 - x15: 0 - x16: 0 - x17: 0 - x18: 0 - x19: 0 - x20: 0 - x21: 0 - x22: 0 - x23: 0 - x24: 0 - x25: 0 - x26: 0 - x27: 0 - x28: 0 - x29: 0 - x30: 0 - x31: 0 - - val_comb: - 'rs1_val > 0 and imm_val > 32': 0 - 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 - 'rs1_val < 0 and imm_val > 32': 0 - 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 - abstract_comb: - 'walking_ones("imm_val", 6, False)': 0 - 'walking_zeros("imm_val", 6, False)': 0 - 'alternate("imm_val", 6, False)': 0 - -csrli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.srli: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -csrai: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.srai: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -candi: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.andi: 0 - rs1: - <<: *c_regs - val_comb: - <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *cbimm_val_walking] - -csub: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.sub: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cxor: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.xor: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cor: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.or: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cand: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.and: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -csubw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.subw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -caddw: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.addw: 0 - rs1: - <<: *c_regs - rs2: - <<: *c_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cj: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.j: 0 - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 - 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 - -cbeqz: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.beqz: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val == 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - 'rs1_val == 0 and imm_val < 0': 0 - <<: [*base_rs1val_sgn] - abstract_comb: - <<: [*rs1val_walking] - -cbnez: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.bnez: 0 - rs1: - <<: *c_regs - val_comb: - 'rs1_val > 0 and imm_val > 0': 0 - 'rs1_val < 0 and imm_val > 0': 0 - 'rs1_val == 0 and imm_val > 0': 0 - 'rs1_val > 0 and imm_val < 0': 0 - 'rs1_val < 0 and imm_val < 0': 0 - 'rs1_val == 0 and imm_val < 0': 0 - <<: [*base_rs1val_sgn] - abstract_comb: - <<: [*rs1val_walking] - -cslli: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.slli: 0 - rd: - <<: *c_regs - val_comb: - 'rs1_val < 0 and imm_val < xlen': 0 - 'rs1_val > 0 and imm_val < xlen': 0 - 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 - 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -clwsp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.lwsp: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - -cldsp: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.ldsp: 0 - rd: - <<: *all_regs_mx0 - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 - -cjr: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.jr: 0 - rs1: - <<: *all_regs_mx0 - -cmv: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.mv: 0 - rs2: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - 'rs2 == rd and rs2 != 0': 0 - 'rs2 != rd and rs2 != 0': 0 - val_comb: - <<: [*base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -cadd: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.add: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs_mx0 - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] - abstract_comb: - <<: [*rs1val_walking,*rs2val_walking] - -cjalr: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.jalr: 0 - rs1: - <<: *all_regs_mx0 - -cswsp: - config: - - check ISA:=regex(.*I.*C.*) - opcode: - c.swsp: 0 - rs2: - <<: *all_regs - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 - -csdsp: - config: - - check ISA:=regex(.*RV64.*I.*C.*) - opcode: - c.sdsp: 0 - rs2: - <<: *all_regs - val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 -fence: - config: - - check ISA:=regex(.*I.*) - opcode: - fence: 0 - -addi: - config: - - check ISA:=regex(.*I.*) - opcode: - addi: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -slti: - config: - - check ISA:=regex(.*I.*) - opcode: - slti: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -sltiu: - config: - - check ISA:=regex(.*I.*) - opcode: - sltiu: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] - abstract_comb: - <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] - -andi: - config: - - check ISA:=regex(.*I.*) - opcode: - andi: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -ori: - config: - - check ISA:=regex(.*I.*) - opcode: - ori: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -xori: - config: - - check ISA:=regex(.*I.*) - opcode: - xori: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -slli: - config: - - check ISA:=regex(.*I.*) - opcode: - slli: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -srai: - config: - - check ISA:=regex(.*I.*) - opcode: - srai: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -srli: - config: - - check ISA:=regex(.*I.*) - opcode: - srli: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 - 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 - -add: - config: - - check ISA:=regex(.*I.*) - opcode: - add: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sub: - config: - - check ISA:=regex(.*I.*) - opcode: - sub: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -slt: - config: - - check ISA:=regex(.*I.*) - opcode: - slt: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sltu: - config: - - check ISA:=regex(.*I.*) - opcode: - sltu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -and: - config: - - check ISA:=regex(.*I.*) - opcode: - and: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -or: - config: - - check ISA:=regex(.*I.*) - opcode: - or: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -xor: - config: - - check ISA:=regex(.*I.*) - opcode: - xor: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sll: - config: - - check ISA:=regex(.*I.*) - opcode: - sll: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -srl: - config: - - check ISA:=regex(.*I.*) - opcode: - srl: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -sra: - config: - - check ISA:=regex(.*I.*) - opcode: - sra: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 - 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 - 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 - -beq: - config: - - check ISA:=regex(.*I.*) - opcode: - beq: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -bge: - config: - - check ISA:=regex(.*I.*) - opcode: - bge: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -bgeu: - config: - - check ISA:=regex(.*I.*) - opcode: - bgeu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_unsgn - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -blt: - config: - - check ISA:=regex(.*I.*) - opcode: - blt: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -bltu: - config: - - check ISA:=regex(.*I.*) - opcode: - bltu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_unsgn - abstract_comb: - <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] - -bne: - config: - - check ISA:=regex(.*I.*) - opcode: - bne: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - op_comb: - <<: *sfmt_op_comb - val_comb: - <<: *bfmt_base_branch_val_align_sgn - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -lhu-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lhu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lh-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lh: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lbu-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lbu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lb-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lb: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -lw-align: - config: - - check ISA:=regex(.*I.*) - opcode: - lw: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - - -sh-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sh: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - <<: [ *base_rs2val_sgn] - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - abstract_comb: - <<: [*rs2val_walking] - -sb-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sb: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'ea_align == 2 and (imm_val % 4) == 0': 0 - 'ea_align == 2 and (imm_val % 4) == 1': 0 - 'ea_align == 2 and (imm_val % 4) == 2': 0 - 'ea_align == 2 and (imm_val % 4) == 3': 0 - 'ea_align == 1 and (imm_val % 4) == 0': 0 - 'ea_align == 1 and (imm_val % 4) == 1': 0 - 'ea_align == 1 and (imm_val % 4) == 2': 0 - 'ea_align == 1 and (imm_val % 4) == 3': 0 - 'ea_align == 3 and (imm_val % 4) == 0': 0 - 'ea_align == 3 and (imm_val % 4) == 1': 0 - 'ea_align == 3 and (imm_val % 4) == 2': 0 - 'ea_align == 3 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -sw-align: - config: - - check ISA:=regex(.*I.*) - opcode: - sw: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -auipc: - config: - - check ISA:=regex(.*I.*) - opcode: - auipc: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val == 0': 0 - 'imm_val > 0': 0 - 'imm_val == ((2**20)-1)': 0 - -lui: - config: - - check ISA:=regex(.*I.*) - opcode: - lui: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val == 0': 0 - 'imm_val > 0': 0 - 'imm_val == ((2**20)-1)': 0 - -jal: - config: - - check ISA:=regex(.*I.*) - opcode: - jal: 0 - rd: - <<: *all_regs - val_comb: - 'imm_val < 0' : 0 - 'imm_val > 0': 0 - 'imm_val == (-(2**(18)))': 0 - 'imm_val == ((2**(18)))': 0 - -jalr: - config: - - check ISA:=regex(.*I.*) - opcode: - jalr: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'imm_val > 0': 0 - 'imm_val < 0': 0 - abstract_comb: - <<: *ifmt_immval_walking - -mul: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mul: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -mulh: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulh: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -mulhu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulhu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -mulhsu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - mulhsu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -div: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - div: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -divu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - divu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -rem: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - rem: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -remu: - config: - - check ISA:=regex(.*I.*M.*) - opcode: - remu: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -lwu-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - lwu: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 4) == 0': 0 - 'ea_align == 0 and (imm_val % 4) == 1': 0 - 'ea_align == 0 and (imm_val % 4) == 2': 0 - 'ea_align == 0 and (imm_val % 4) == 3': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -ld-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - ld: 0 - rs1: - <<: *all_regs_mx0 - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - 'ea_align == 0 and (imm_val % 8) == 0': 0 - 'ea_align == 0 and (imm_val % 8) == 1': 0 - 'ea_align == 0 and (imm_val % 8) == 2': 0 - 'ea_align == 0 and (imm_val % 8) == 3': 0 - 'ea_align == 0 and (imm_val % 8) == 4': 0 - 'ea_align == 0 and (imm_val % 8) == 5': 0 - 'ea_align == 0 and (imm_val % 8) == 6': 0 - 'ea_align == 0 and (imm_val % 8) == 7': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - -sd-align: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sd: 0 - rs1: - <<: *all_regs_mx0 - rs2: - <<: *all_regs - op_comb: - 'rs1 != rs2': 0 - val_comb: - 'ea_align == 0 and (imm_val % 8) == 0': 0 - 'ea_align == 0 and (imm_val % 8) == 1': 0 - 'ea_align == 0 and (imm_val % 8) == 2': 0 - 'ea_align == 0 and (imm_val % 8) == 3': 0 - 'ea_align == 0 and (imm_val % 8) == 4': 0 - 'ea_align == 0 and (imm_val % 8) == 5': 0 - 'ea_align == 0 and (imm_val % 8) == 6': 0 - 'ea_align == 0 and (imm_val % 8) == 7': 0 - 'imm_val > 0': 0 - 'imm_val < 0': 0 - 'imm_val == 0': 0 - <<: [ *base_rs2val_sgn] - abstract_comb: - <<: [*rs2val_walking] - -addiw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - addiw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] - abstract_comb: - <<: [*rs1val_walking, *ifmt_immval_walking] - -slliw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - slliw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -srliw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - srliw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -sraiw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sraiw: 0 - rs1: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *ifmt_op_comb - val_comb: - <<: *ifmt_base_shift_32w - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("imm_val", 5, False)': 0 - 'walking_zeros("imm_val", 5, False)': 0 - 'alternate("imm_val", 5, False)': 0 - -addw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - addw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -subw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - subw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -sllw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sllw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 - -srlw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - srlw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 -sraw: - config: - - check ISA:=regex(.*RV64.*I.*) - opcode: - sraw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: *rfmt_base_shift - abstract_comb: - <<: [*rs1val_walking] - 'walking_ones("rs2_val", 5, False)': 0 - 'walking_zeros("rs2_val", 5, False)': 0 - 'alternate("rs2_val", 5, False)': 0 - -mulw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - mulw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -divw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - divw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -divuw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - divuw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -remw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - remw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - -remuw: - config: - - check ISA:=regex(.*RV64.*I.*M.*) - opcode: - remuw: 0 - rs1: - <<: *all_regs - rs2: - <<: *all_regs - rd: - <<: *all_regs - op_comb: - <<: *rfmt_op_comb - val_comb: - <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] - abstract_comb: - <<: [*rs1val_walking, *rs2val_walking] - diff --git a/riscof/suite/env/arch_test.h b/riscof/suite/env/arch_test.h deleted file mode 100644 index b5dab80..0000000 --- a/riscof/suite/env/arch_test.h +++ /dev/null @@ -1,1016 +0,0 @@ -#include "encoding.h" -// TODO the following should come from the YAML. -#ifndef NUM_SPECD_INTCAUSES - #define NUM_SPECD_INTCAUSES 16 -#endif -//#define RVTEST_FIXED_LEN -#ifndef UNROLLSZ - #define UNROLLSZ 5 -#endif -// #ifndef rvtest_gpr_save -// #define rvtest_gpr_save -// #endif - -//----------------------------------------------------------------------- -// RV Arch Test Macros -//----------------------------------------------------------------------- -#ifndef RVMODEL_SET_MSW_INT - #warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_SET_MSW_INT -#endif - -#ifndef RVMODEL_CLEAR_MSW_INT - #warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_CLEAR_MSW_INT -#endif - -#ifndef RVMODEL_CLEAR_MTIMER_INT - #warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_CLEAR_MTIMER_INT -#endif - -#ifndef RVMODEL_CLEAR_MEXT_INT - #warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro" - #define RVMODEL_CLEAR_MEXT_INT -#endif - -#ifdef RVTEST_FIXED_LEN - #define LI(reg, val)\ - .option push;\ - .option norvc;\ - .align UNROLLSZ;\ - li reg,val;\ - .align UNROLLSZ;\ - .option pop; - - #define LA(reg, val)\ - .option push;\ - .option norvc;\ - .align UNROLLSZ;\ - la reg,val;\ - .align UNROLLSZ;\ - .option pop; - -#else - #define LI(reg,val);\ - .option push;\ - .option norvc;\ - li reg,val;\ - .option pop; - - #define LA(reg,val);\ - .option push;\ - .option norvc;\ - la reg,val;\ - .option pop; -#endif -#if XLEN==64 - #define SREG sd - #define LREG ld - #define REGWIDTH 8 - #define MASK 0xFFFFFFFFFFFFFFFF - -#else - #if XLEN==32 - #define SREG sw - #define LREG lw - #define REGWIDTH 4 - #define MASK 0xFFFFFFFF - - #endif -#endif -#define MMODE_SIG 3 -#define RLENG (REGWIDTH<<3) - -#define RVTEST_ISA(_STR) - -#ifndef DATA_REL_TVAL_MSK - #define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16) -#endif - -#ifndef CODE_REL_TVAL_MSK - #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16) -#endif - - -// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ // - -.macro RVTEST_CODE_BEGIN - .align UNROLLSZ - .section .text.init; - .globl rvtest_init; \ - rvtest_init: -#ifdef rvtest_mtrap_routine - LA(x1, rvtest_trap_prolog ); - jalr ra, x1 - rvtest_prolog_done: -#endif - LI (x1, (0xFEEDBEADFEEDBEAD & MASK)); - LI (x2, (0xFF76DF56FF76DF56 & MASK)); - LI (x3, (0x7FBB6FAB7FBB6FAB & MASK)); - LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK)); - LA (x5, rvtest_code_begin); - LA (x6, rvtest_data_begin); - LI (x7, (0xB7FBB6FAB7FBB6FA & MASK)); - LI (x8, (0x5BFDDB7D5BFDDB7D & MASK)); - LI (x9, (0xADFEEDBEADFEEDBE & MASK)); - LI (x10, (0x56FF76DF56FF76DF & MASK)); - LI (x11, (0xAB7FBB6FAB7FBB6F & MASK)); - LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK)); - LI (x13, (0xEADFEEDBEADFEEDB & MASK)); - LI (x14, (0xF56FF76DF56FF76D & MASK)); - LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)); - LI (x16, (0x7D5BFDDB7D5BFDDB & MASK)); - LI (x17, (0xBEADFEEDBEADFEED & MASK)); - LI (x18, (0xDF56FF76DF56FF76 & MASK)); - LI (x19, (0x6FAB7FBB6FAB7FBB & MASK)); - LI (x20, (0xB7D5BFDDB7D5BFDD & MASK)); - LI (x21, (0xDBEADFEEDBEADFEE & MASK)); - LI (x22, (0x6DF56FF76DF56FF7 & MASK)); - LI (x23, (0xB6FAB7FBB6FAB7FB & MASK)); - LI (x24, (0xDB7D5BFDDB7D5BFD & MASK)); - LI (x25, (0xEDBEADFEEDBEADFE & MASK)); - LI (x26, (0x76DF56FF76DF56FF & MASK)); - LI (x27, (0xBB6FAB7FBB6FAB7F & MASK)); - LI (x28, (0xDDB7D5BFDDB7D5BF & MASK)); - LI (x29, (0xEEDBEADFEEDBEADF & MASK)); - LI (x30, (0xF76DF56FF76DF56F & MASK)); - LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK)); - .globl rvtest_code_begin - rvtest_code_begin: -.endm - -// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------// - -.macro RVTEST_CODE_END - .align 4; - .global rvtest_code_end - rvtest_code_end: -#ifdef rvtest_mtrap_routine - .option push - .option norvc - j exit_cleanup - - rvtest_trap_prolog: - /******************************************************************************/ - /**** Prolog, to be run before any tests ****/ - /**** #include 1 copy of this per mode in rvmodel_boot code? ****/ - /**** ------------------------------------------------------------------- ****/ - /**** if xTVEC isn't completely RW, then we need to change the code at its ****/ - /**** target. The entire trap trampoline and mtrap handler replaces the ****/ - /**** area pointed to by mtvec, after saving its original contents first. ****/ - /**** If it isn't possible to fully write that area, restore and fail. ****/ - /******************************************************************************/ - - //trap_handler_prolog; enter with t1..t6 available - - init_mscratch: - la t1, trapreg_sv - csrrw t1, CSR_MSCRATCH, t1 // swap old mscratch. mscratch not points to trapreg_sv - la t2, mscratch_save - SREG t1, 0(t2) // save old mscratch in mscratch_save region - csrr t1, CSR_MSCRATCH // read the trapreg_sv address - LA( t2, mtrap_sigptr ) // locate the start of the trap signature - SREG t2, 0(t1) // save mtrap_sigptr at first location of trapreg_sv - init_mtvec: - la t1, mtrampoline - la t4, mtvec_save - csrrw t2, CSR_MTVEC, t1 // swap mtvec and trap_trampoline - SREG t2, 0(t4) // save orig mtvec - csrr t3, CSR_MTVEC // now read new_mtval back - beq t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue - - /****************************************************************/ - /**** fixed mtvec, can't move it so move trampoline instead ****/ - /**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end ****/ - /****************************************************************/ - - // t2 = dut's original mtvec setting - // t1 = mtrampoline address - init_tramp: /**** copy trampoline at mtvec tgt ****/ - - csrw CSR_MTVEC, t2 // restore orig mtvec, will now attemp to copy trampoline to it - la t3, tramptbl_sv // addr of save area - addi t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area - - overwrite_tt: // now build new trampoline table with offsets base from curr mtvec - lw t6, 0(t2) // get original mtvec target - sw t6, 0(t3) // save it - lw t5, 0(t1) // get trampoline src - sw t5, 0(t2) // overwrite mtvec target - lw t6, 0(t2) // rd it back to make sure it was written - bne t6, t5, resto_tramp // table isn't fully writable, restore and give up - addi t1, t1, 4 // next src index - addi t2, t2, 4 // next tgt index - addi t3, t3, 4 // next save index - bne t3, t4, overwrite_tt // not done, loop - j rvtest_prolog_done - - resto_tramp: // vector table not writeable, restore - LREG t1, 16(t4) // load mscratch_SAVE at fixed offset from table end - csrw CSR_MSCRATCH, t1 // restore mscratch - LREG t4, 8(t4) // load mtvec_SAVE (used as end of loop marker) - - - resto_loop: // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin - lw t6, 0(t3) // read saved tgt entry - sw t6, 0(t2) // restore original tgt - addi t2, t2, -4 // prev tgt index - addi t3, t3, -4 // prev save index - bne t2, t4, resto_loop // didn't restore to begining yet, loop - - j rvtest_end // failure to replace trampoline - - - #define mhandler \ - csrrw sp, CSR_MSCRATCH, sp; \ - SREG t6, 6*REGWIDTH(sp); \ - jal t6, common_prolog; - - /**********************************************************************/ - /**** This is the entry point for all m-modetraps, vectored or not.****/ - /**** At entry, mscratch will contain a pointer to a scratch area. ****/ - /**** This is an array of branches at 4B intevals that spreads out ****/ - /**** to an array of 32B mhandler macros for specd int causes, and ****/ - /**** to a return for anything above that (which causes a mismatch)****/ - /**********************************************************************/ - mtrampoline: // 64 or 32 entry table - value = 0 - .rept NUM_SPECD_INTCAUSES // located at each possible int vectors - j mtrap_handler + 12*(value) //offset < +/- 1MB - value = value + 1 - .endr - .rept RLENG-NUM_SPECD_INTCAUSES // fill at each impossible entry - mret - .endr - - mtrap_handler: /* after executing, sp points to temp save area, t4 is PC */ - .rept NUM_SPECD_INTCAUSES - mhandler - .endr - - common_prolog: - la t5, common_mhandler - jr t5 - /*********************************************************************/ - /**** common code for all ints & exceptions, will fork to handle ****/ - /**** each separately. The common handler first stores trap mode+ ****/ - /**** vector, and mcause signatures. All traps have 4wd sigs, but ****/ - /**** sw and timer ints only store 3 of the 4. ****/ - /**** sig offset Exception ExtInt SWInt TimerInt ****/ - /**** 0: tval IntID -1 -1 ****/ - /**** 4: mepc mip mip mip ****/ - /**** 8: <---------------------- mcause -------------> ****/ - /**** 12: <--------------------- Vect+mode ----------> ****/ - /*********************************************************************/ - /* in general, CSRs loaded in t2, addresses into t3 */ - - common_mhandler: /* enter with link in t6 */ - SREG t5, 5*REGWIDTH(sp) - SREG t4, 4*REGWIDTH(sp) - SREG t3, 3*REGWIDTH(sp) - SREG t2, 2*REGWIDTH(sp) - SREG t1, 1*REGWIDTH(sp) /* save other temporaries */ - - LREG t1, 0(sp) /* load trap sig pointer (runs backwards from DATA_END) */ - - LA( t3, mtrampoline) - sub t2, t6, t3 /* reloc “link” to 0..63 to show which int vector was taken */ - addi t2, t2, MMODE_SIG /* insert mode# into 1:0 */ - SREG t2, 0*REGWIDTH(t1) /* save 1st sig value, (vect, trapmode) */ - sv_mcause: - csrr t2, CSR_MCAUSE - SREG t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause) */ - - bltz t2, common_mint_handler /* this is a interrupt, not a trap */ - - /********************************************************************/ - /**** This is the exceptions specific code, storing relative mepc****/ - /**** & relative tval signatures. tval is relocated by code or ****/ - /**** data start, or 0 depending on mcause. mepc signature value ****/ - /**** is relocated by code start, and restored adjusted depending****/ - /**** on op alignment so trapped op isn't re-executed. ****/ - /********************************************************************/ - common_mexcpt_handler: - csrr t2, CSR_MEPC - sv_mepc: - LA( t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */ - sub t4, t2, t3 /* convert mepc to rel offset of beginning of test*/ - SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */ - adj_mepc: //adj mepc so there is padding after op, and its 8B aligned - andi t4, t2, 0x2 /* set to 2 if mepc was misaligned */ - sub t2, t2, t4 /* adjust mepc to prev 4B alignment */ - addi t2, t2, 0x8 /* adjust mepc, so it skips past the op, has padding & is 4B aligned */ - csrw CSR_MEPC, t2 /* restore adjusted value, has 1,2, or 3 bytes of padding */ - - - /* calculate relative mtval if it’s an address (by code_begin or data_begin amt) */ - /* note that masks that determine this are implementation specific from YAML */ - - /* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */ - - adj_mtval: - csrr t2, CSR_MCAUSE /* code begin adjustment amount already in t3 */ - - LI(t4, CODE_REL_TVAL_MSK) /* trap#s 12, 3,1,0, -- adjust w/ code_begin */ - sll t4, t4, t2 /* put bit# in MSB */ - bltz t4, sv_mtval /* correct adjustment is code_begin in t3 */ - - LA( t3, mtrap_sigptr) /* adjustment assuming access is to signature region */ - LI(t4, DATA_REL_TVAL_MSK) /* trap#s not 14, 11..8, 2 adjust w/ data_begin */ - sll t4, t4, t2 /* put bit# in MSB */ - bgez t4, no_adj /* correct adjustment is data_begin in t3 */ - sigbound_chk: - csrr t4, CSR_MTVAL /* do a bounds check on mtval */ - bge t3, t4, sv_mtval /* if mtval is greater than the rvmodel_data_begin then use that as anchor */ - LA( t3, rvtest_data_begin) /* else change anchor to rvtest_data_begin */ - blt t3, t4, sv_mtval /* before the signature, use data_begin adj */ - mv t4, t3 /* use sig relative adjust */ - no_adj: - LI(t3, 0) /* else zero adjustment amt */ - - // For Illegal op handling - addi t2, t2, -2 /* check if mcause==2 (illegal op) */ - bnez t2, sv_mtval /* not illegal op, no special treatment */ - csrr t2, CSR_MTVAL - bnez t2, sv_mtval /* mtval isn’t zero, no special treatment */ - illop: - LI(t5, 0x20000) /* get mprv mask */ - csrrs t5, CSR_MSTATUS, t5 /* set mprv while saving the old value */ - csrr t3, CSR_MEPC - lhu t2, 0(t3) /* load 1st 16b of opc w/ old priv, endianess*/ - andi t4, t2, 0x3 - addi t4, t4, -0x3 /* does opcode[1:0]==0b11? (Meaning >16b op) */ - bnez t4, sv_mtval /* entire mtval is in tt2, adj amt will be set to zero */ - lhu t4, 2(t3) - sll t4, t4, 16 - or t3, t2, t4 /* get 2nd hwd, align it & insert it into opcode */ - csrw CSR_MSTATUS, t5 /* restore mstatus */ - -/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/ - - sv_mtval: - csrr t2, CSR_MTVAL - sub t2, t2, t3 /* perform mtval adjust by either code or data position or zero*/ - SREG t2, 3*REGWIDTH(t1) /* save 4th sig value, (rel mtval) into trap signature area */ - - resto_rtn: /* restore and return */ - addi t1, t1,4*REGWIDTH /* adjust trap signature ptr (traps always save 4 words) */ - SREG t1, 0*REGWIDTH(sp) /* save updated trap sig pointer (pts to trap_sigptr */ - - LREG t1, 1*REGWIDTH(sp) - LREG t2, 2*REGWIDTH(sp) - LREG t3, 3*REGWIDTH(sp) - LREG t4, 4*REGWIDTH(sp) - LREG t5, 5*REGWIDTH(sp) - LREG t6, 6*REGWIDTH(sp) /* restore temporaries */ - - csrrw sp, CSR_MSCRATCH, sp /* restore sp from scratch */ - mret - - common_mint_handler: /* t1 has sig ptr, t2 has mcause */ - - LI(t3, 1) - sll t3, t3, t2 /* create mask 1<
Riscof Version{{ version }}
{{ riscof_version }}
Riscv-arch-test Version/Commit Id{{ rvarch_version }}
DUT {{ dut }}