diff --git a/chapter8.adoc b/chapter8.adoc
index 2a604bd..46b3def 100644
--- a/chapter8.adoc
+++ b/chapter8.adoc
@@ -104,8 +104,9 @@ The `metrcen` is an enable control for external trace for the `M-mode` driven by
 an external trace module and is expected to be established by the RoT (following
 RISC-V security model recommendations SR_GEN_007 and 012). When privilege is
 `M-mode`, the `metrcen` gates the `halted` signal (from the hart) into the hart
-trace encoder. Per the specification <<R24>>, this side-band `halted` signal
-being asserted, prevents the hart from generating any trace output.
+trace encoder. Per the Efficient trace specification cite:[Etrc], this side-band
+`halted` signal being asserted, stops subsequent tracing from the hart. On this
+signal being deasserted, the encode can start tracing again.
 
 [NOTE]
 ====
@@ -113,6 +114,8 @@ Implementation of the `halted` side-band signal is required to support external
 tracing with supervisor domains
 ====
 
+`Smsdetrc` specifies the following behavior for tracing with supervisor domains:
+
 When `metrcen` is 0:
 `halted` is asserted on:
 
diff --git a/example.bib b/example.bib
index 0844807..44856f9 100644
--- a/example.bib
+++ b/example.bib
@@ -23,3 +23,8 @@ @electronic{ExtDbg
   title = {RISC-V Debug Specification},
   url = {https://github.com/riscv/riscv-debug-spec}
 }
+
+@electronic{ETrc,
+  title = {RISC-V Efficient Trace for RISC-V, v2.0.2, March 5, 2024},
+  url = {https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf}
+}