vcfg-format.adoc

Formats for Vector Configuration Instructions under OP-V major opcode

{reg: [
  {bits: 7,  name: 0x57, attr: 'vsetvli'},
  {bits: 5,  name: 'rd', type: 4},
  {bits: 3,  name: 7},
  {bits: 5,  name: 'rs1', type: 4},
  {bits: 11, name: 'zimm[10:0]', type: 5},
  {bits: 1,  name: '0'},
]}

{reg: [
  {bits: 7,  name: 0x57, attr: 'vsetivli'},
  {bits: 5,  name: 'rd', type: 4},
  {bits: 3,  name: 7},
  {bits: 5,  name: 'uimm[4:0]', type: 5},
  {bits: 10, name: 'zimm[9:0]', type: 5},
  {bits: 1, name: '1'},
  {bits: 1,  name: '1'},
]}

{reg: [
  {bits: 7,  name: 0x57, attr: 'vsetvl'},
  {bits: 5,  name: 'rd', type: 4},
  {bits: 3,  name: 7},
  {bits: 5,  name: 'rs1', type: 4},
  {bits: 5,  name: 'rs2', type: 4},
  {bits: 6,  name: 0x1000},
  {bits: 1,  name: 1},
]}