TimberWolfSC runs forever without showing any errors or progress

[xphoniex]

I'm trying to run this design through Qflow process and I'm stuck at Placement stage (Graywolf v0.1.4), I've tried on separate days spending 6 and 9 hours respectively and it's just not terminating, yet when I check top, the TimberWolfSC seems to be using a full core.

$ ./qflow_exec.sh
Qrouter detail maze router version 1.4.83.T
Reading LEF data from file /usr/local/share/qflow/tech/osu018/osu018_stdcells.lef.
LEF Read, Line 191: NOTE:  Old format VIARULE ignored.
LEF Read, Line 192: NOTE:  Old format VIARULE ignored.
LEF Read, Line 196: NOTE:  Old format VIARULE ignored.
LEF Read, Line 197: NOTE:  Old format VIARULE ignored.
LEF Read, Line 207: NOTE:  Old format VIARULE ignored.
LEF Read, Line 208: NOTE:  Old format VIARULE ignored.
LEF Read, Line 212: NOTE:  Old format VIARULE ignored.
LEF Read, Line 213: NOTE:  Old format VIARULE ignored.
LEF Read, Line 223: NOTE:  Old format VIARULE ignored.
LEF Read, Line 224: NOTE:  Old format VIARULE ignored.
LEF Read, Line 228: NOTE:  Old format VIARULE ignored.
LEF Read, Line 229: NOTE:  Old format VIARULE ignored.
LEF Read, Line 239: NOTE:  Old format VIARULE ignored.
LEF Read, Line 240: NOTE:  Old format VIARULE ignored.
LEF Read, Line 244: NOTE:  Old format VIARULE ignored.
LEF Read, Line 245: NOTE:  Old format VIARULE ignored.
LEF Read, Line 255: NOTE:  Old format VIARULE ignored.
LEF Read, Line 256: NOTE:  Old format VIARULE ignored.
LEF Read, Line 260: NOTE:  Old format VIARULE ignored.
LEF Read, Line 261: NOTE:  Old format VIARULE ignored.
LEF file:  Defines site core (ignored)
LEF read: Processed 2941 lines.
LEF Read: encountered 0 errors and 20 warnings total.
Vertical route layer at non-minimum pitch 1.6.  Using smaller pitch 0.8, will route on 1-of-2 tracks for layer metal6.
Running vlog2Cel to generate input files for graywolf
vlog2Cel  -l  /usr/local/share/qflow/tech/osu018/osu018_stdcells.lef -u 100 -o /qflow-piccolo/layout/mkCPU.cel /qflow-piccolo/synthesis/mkCPU.rtlnopwr.v
No mkCPU.cel1 file found for project. . . no partial blockages to apply to layout.
No mkCPU.cel2 file found for project. . . continuing without pin placement hints
Running GrayWolf placement
graywolf  mkCPU

Is there any way to debug this? I'm not getting any logs or any errors. Is the placement stage supposed to take this long?

The synthesis has 300K cells which I understand is a large number and if I try to change the density, it gets stuck and doesn't even show the graphical interface. And it prints the width to be:

Number of cells = 388742, total width = 133089600

which mean the width is 1.86 meters even when lambda is 14nm! Is this correct?

[jalcim]

same problem on debian 9 with same log content : for this code test

module gate_buf (e1, s);

   input e1;

   output s;

   buf buf0(s, e1);

endmodule

[xphoniex]

@jalcim try a more complex test code, or copy/paste your code a few times.