From 39788e07bae91e9974ba6879a63e4e8b97503f5b Mon Sep 17 00:00:00 2001 From: Scott McMurray Date: Sat, 3 Jun 2023 00:41:50 -0700 Subject: [PATCH 1/3] Promote unchecked_add/sub/mul/shl/shr to mir::BinOp --- .../src/codegen_i128.rs | 9 +- compiler/rustc_codegen_cranelift/src/num.rs | 16 ++- compiler/rustc_codegen_ssa/src/common.rs | 4 +- compiler/rustc_codegen_ssa/src/mir/rvalue.rs | 33 +++++- .../src/interpret/operator.rs | 66 +++++++---- .../rustc_const_eval/src/interpret/step.rs | 8 +- .../src/transform/promote_consts.rs | 7 +- .../src/transform/validate.rs | 20 +++- compiler/rustc_middle/src/mir/syntax.rs | 13 ++ compiler/rustc_middle/src/mir/tcx.rs | 18 ++- .../src/lower_intrinsics.rs | 12 +- compiler/rustc_smir/src/rustc_smir/mod.rs | 5 + .../rustc_smir/src/stable_mir/mir/body.rs | 5 + compiler/rustc_ty_utils/src/consts.rs | 5 +- ...hl_unsigned_bigger.Inline.panic-abort.diff | 8 +- ...l_unsigned_bigger.Inline.panic-unwind.diff | 8 +- ...ed_bigger.PreCodegen.after.panic-abort.mir | 5 +- ...d_bigger.PreCodegen.after.panic-unwind.mir | 5 +- ...l_unsigned_smaller.Inline.panic-abort.diff | 8 +- ..._unsigned_smaller.Inline.panic-unwind.diff | 8 +- ...d_smaller.PreCodegen.after.panic-abort.mir | 5 +- ..._smaller.PreCodegen.after.panic-unwind.mir | 5 +- ..._shr_signed_bigger.Inline.panic-abort.diff | 8 +- ...shr_signed_bigger.Inline.panic-unwind.diff | 8 +- ...ed_bigger.PreCodegen.after.panic-abort.mir | 5 +- ...d_bigger.PreCodegen.after.panic-unwind.mir | 5 +- ...shr_signed_smaller.Inline.panic-abort.diff | 8 +- ...hr_signed_smaller.Inline.panic-unwind.diff | 8 +- ...d_smaller.PreCodegen.after.panic-abort.mir | 5 +- ..._smaller.PreCodegen.after.panic-unwind.mir | 5 +- tests/mir-opt/lower_intrinsics.rs | 5 + ...unchecked.LowerIntrinsics.panic-abort.diff | 112 +++++++++++++++++- ...nchecked.LowerIntrinsics.panic-unwind.diff | 112 +++++++++++++++++- ...ecked_ops.checked_shl.PreCodegen.after.mir | 35 +++--- ...mut_range.PreCodegen.after.panic-abort.mir | 63 +++++----- ...ut_range.PreCodegen.after.panic-unwind.mir | 63 +++++----- 36 files changed, 502 insertions(+), 213 deletions(-) diff --git a/compiler/rustc_codegen_cranelift/src/codegen_i128.rs b/compiler/rustc_codegen_cranelift/src/codegen_i128.rs index f751d8c179db5..13568b198db1b 100644 --- a/compiler/rustc_codegen_cranelift/src/codegen_i128.rs +++ b/compiler/rustc_codegen_cranelift/src/codegen_i128.rs @@ -22,8 +22,8 @@ pub(crate) fn maybe_codegen<'tcx>( match bin_op { BinOp::BitAnd | BinOp::BitOr | BinOp::BitXor => None, - BinOp::Add | BinOp::Sub => None, - BinOp::Mul => { + BinOp::Add | BinOp::AddUnchecked | BinOp::Sub | BinOp::SubUnchecked => None, + BinOp::Mul | BinOp::MulUnchecked => { let args = [lhs.load_scalar(fx), rhs.load_scalar(fx)]; let ret_val = fx.lib_call( "__multi3", @@ -69,7 +69,7 @@ pub(crate) fn maybe_codegen<'tcx>( } } BinOp::Lt | BinOp::Le | BinOp::Eq | BinOp::Ge | BinOp::Gt | BinOp::Ne => None, - BinOp::Shl | BinOp::Shr => None, + BinOp::Shl | BinOp::ShlUnchecked | BinOp::Shr | BinOp::ShrUnchecked => None, } } @@ -131,9 +131,10 @@ pub(crate) fn maybe_codegen_checked<'tcx>( fx.lib_call(name, param_types, vec![], &args); Some(out_place.to_cvalue(fx)) } + BinOp::AddUnchecked | BinOp::SubUnchecked | BinOp::MulUnchecked => unreachable!(), BinOp::Offset => unreachable!("offset should only be used on pointers, not 128bit ints"), BinOp::Div | BinOp::Rem => unreachable!(), BinOp::Lt | BinOp::Le | BinOp::Eq | BinOp::Ge | BinOp::Gt | BinOp::Ne => unreachable!(), - BinOp::Shl | BinOp::Shr => unreachable!(), + BinOp::Shl | BinOp::ShlUnchecked | BinOp::Shr | BinOp::ShrUnchecked => unreachable!(), } } diff --git a/compiler/rustc_codegen_cranelift/src/num.rs b/compiler/rustc_codegen_cranelift/src/num.rs index ba53e01c7a212..ac1a6cce096f4 100644 --- a/compiler/rustc_codegen_cranelift/src/num.rs +++ b/compiler/rustc_codegen_cranelift/src/num.rs @@ -128,10 +128,11 @@ pub(crate) fn codegen_int_binop<'tcx>( let rhs = in_rhs.load_scalar(fx); let b = fx.bcx.ins(); + // FIXME trap on overflow for the Unchecked versions let val = match bin_op { - BinOp::Add => b.iadd(lhs, rhs), - BinOp::Sub => b.isub(lhs, rhs), - BinOp::Mul => b.imul(lhs, rhs), + BinOp::Add | BinOp::AddUnchecked => b.iadd(lhs, rhs), + BinOp::Sub | BinOp::SubUnchecked => b.isub(lhs, rhs), + BinOp::Mul | BinOp::MulUnchecked => b.imul(lhs, rhs), BinOp::Div => { if signed { b.sdiv(lhs, rhs) @@ -149,16 +150,19 @@ pub(crate) fn codegen_int_binop<'tcx>( BinOp::BitXor => b.bxor(lhs, rhs), BinOp::BitAnd => b.band(lhs, rhs), BinOp::BitOr => b.bor(lhs, rhs), - BinOp::Shl => b.ishl(lhs, rhs), - BinOp::Shr => { + BinOp::Shl | BinOp::ShlUnchecked => b.ishl(lhs, rhs), + BinOp::Shr | BinOp::ShrUnchecked => { if signed { b.sshr(lhs, rhs) } else { b.ushr(lhs, rhs) } } + BinOp::Offset => unreachable!("Offset is not an integer operation"), // Compare binops handles by `codegen_binop`. - _ => unreachable!("{:?}({:?}, {:?})", bin_op, in_lhs.layout().ty, in_rhs.layout().ty), + BinOp::Eq | BinOp::Ne | BinOp::Lt | BinOp::Le | BinOp::Gt | BinOp::Ge => { + unreachable!("{:?}({:?}, {:?})", bin_op, in_lhs.layout().ty, in_rhs.layout().ty); + } }; CValue::by_val(val, in_lhs.layout()) diff --git a/compiler/rustc_codegen_ssa/src/common.rs b/compiler/rustc_codegen_ssa/src/common.rs index e1abb73a504a3..5a68075991f16 100644 --- a/compiler/rustc_codegen_ssa/src/common.rs +++ b/compiler/rustc_codegen_ssa/src/common.rs @@ -132,7 +132,7 @@ pub fn build_langcall<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( // all shifts). For 32- and 64-bit types, this matches the semantics // of Java. (See related discussion on #1877 and #10183.) -pub fn build_unchecked_lshift<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( +pub fn build_masked_lshift<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( bx: &mut Bx, lhs: Bx::Value, rhs: Bx::Value, @@ -143,7 +143,7 @@ pub fn build_unchecked_lshift<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( bx.shl(lhs, rhs) } -pub fn build_unchecked_rshift<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( +pub fn build_masked_rshift<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( bx: &mut Bx, lhs_t: Ty<'tcx>, lhs: Bx::Value, diff --git a/compiler/rustc_codegen_ssa/src/mir/rvalue.rs b/compiler/rustc_codegen_ssa/src/mir/rvalue.rs index 5241a5aee008e..2d3d0ec68b81c 100644 --- a/compiler/rustc_codegen_ssa/src/mir/rvalue.rs +++ b/compiler/rustc_codegen_ssa/src/mir/rvalue.rs @@ -798,6 +798,13 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { bx.add(lhs, rhs) } } + mir::BinOp::AddUnchecked => { + if is_signed { + bx.unchecked_sadd(lhs, rhs) + } else { + bx.unchecked_uadd(lhs, rhs) + } + } mir::BinOp::Sub => { if is_float { bx.fsub(lhs, rhs) @@ -805,6 +812,13 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { bx.sub(lhs, rhs) } } + mir::BinOp::SubUnchecked => { + if is_signed { + bx.unchecked_ssub(lhs, rhs) + } else { + bx.unchecked_usub(lhs, rhs) + } + } mir::BinOp::Mul => { if is_float { bx.fmul(lhs, rhs) @@ -812,6 +826,13 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { bx.mul(lhs, rhs) } } + mir::BinOp::MulUnchecked => { + if is_signed { + bx.unchecked_smul(lhs, rhs) + } else { + bx.unchecked_umul(lhs, rhs) + } + } mir::BinOp::Div => { if is_float { bx.fdiv(lhs, rhs) @@ -848,8 +869,16 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { bx.inbounds_gep(llty, lhs, &[rhs]) } } - mir::BinOp::Shl => common::build_unchecked_lshift(bx, lhs, rhs), - mir::BinOp::Shr => common::build_unchecked_rshift(bx, input_ty, lhs, rhs), + mir::BinOp::Shl => common::build_masked_lshift(bx, lhs, rhs), + mir::BinOp::ShlUnchecked => { + let rhs = base::cast_shift_expr_rhs(bx, lhs, rhs); + bx.shl(lhs, rhs) + } + mir::BinOp::Shr => common::build_masked_rshift(bx, input_ty, lhs, rhs), + mir::BinOp::ShrUnchecked => { + let rhs = base::cast_shift_expr_rhs(bx, lhs, rhs); + if is_signed { bx.ashr(lhs, rhs) } else { bx.lshr(lhs, rhs) } + } mir::BinOp::Ne | mir::BinOp::Lt | mir::BinOp::Gt diff --git a/compiler/rustc_const_eval/src/interpret/operator.rs b/compiler/rustc_const_eval/src/interpret/operator.rs index 7186148daf0ba..7bca7efdf5a83 100644 --- a/compiler/rustc_const_eval/src/interpret/operator.rs +++ b/compiler/rustc_const_eval/src/interpret/operator.rs @@ -3,10 +3,13 @@ use rustc_middle::mir; use rustc_middle::mir::interpret::{InterpResult, Scalar}; use rustc_middle::ty::layout::{LayoutOf, TyAndLayout}; use rustc_middle::ty::{self, FloatTy, Ty}; +use rustc_span::symbol::sym; use rustc_target::abi::Abi; use super::{ImmTy, Immediate, InterpCx, Machine, PlaceTy}; +use crate::fluent_generated as fluent; + impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { /// Applies the binary operation `op` to the two operands and writes a tuple of the result /// and a boolean signifying the potential overflow to the destination. @@ -139,8 +142,17 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { ) -> InterpResult<'tcx, (Scalar, bool, Ty<'tcx>)> { use rustc_middle::mir::BinOp::*; + let throw_ub_on_overflow = match bin_op { + AddUnchecked => Some(sym::unchecked_add), + SubUnchecked => Some(sym::unchecked_sub), + MulUnchecked => Some(sym::unchecked_mul), + ShlUnchecked => Some(sym::unchecked_shl), + ShrUnchecked => Some(sym::unchecked_shr), + _ => None, + }; + // Shift ops can have an RHS with a different numeric type. - if bin_op == Shl || bin_op == Shr { + if matches!(bin_op, Shl | ShlUnchecked | Shr | ShrUnchecked) { let size = u128::from(left_layout.size.bits()); // Even if `r` is signed, we treat it as if it was unsigned (i.e., we use its // zero-extended form). This matches the codegen backend: @@ -155,6 +167,7 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { // integers are maximally 128bits wide, so negative shifts *always* overflow and we have // consistent results for the same value represented at different bit widths. assert!(size <= 128); + let original_r = r; let overflow = r >= size; // The shift offset is implicitly masked to the type size, to make sure this operation // is always defined. This is the one MIR operator that does *not* directly map to a @@ -166,19 +179,28 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { let result = if left_layout.abi.is_signed() { let l = self.sign_extend(l, left_layout) as i128; let result = match bin_op { - Shl => l.checked_shl(r).unwrap(), - Shr => l.checked_shr(r).unwrap(), + Shl | ShlUnchecked => l.checked_shl(r).unwrap(), + Shr | ShrUnchecked => l.checked_shr(r).unwrap(), _ => bug!(), }; result as u128 } else { match bin_op { - Shl => l.checked_shl(r).unwrap(), - Shr => l.checked_shr(r).unwrap(), + Shl | ShlUnchecked => l.checked_shl(r).unwrap(), + Shr | ShrUnchecked => l.checked_shr(r).unwrap(), _ => bug!(), } }; let truncated = self.truncate(result, left_layout); + + if overflow && let Some(intrinsic_name) = throw_ub_on_overflow { + throw_ub_custom!( + fluent::const_eval_overflow_shift, + val = original_r, + name = intrinsic_name + ); + } + return Ok((Scalar::from_uint(truncated, left_layout.size), overflow, left_layout.ty)); } @@ -216,9 +238,9 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { Rem if r == 0 => throw_ub!(RemainderByZero), Div => Some(i128::overflowing_div), Rem => Some(i128::overflowing_rem), - Add => Some(i128::overflowing_add), - Sub => Some(i128::overflowing_sub), - Mul => Some(i128::overflowing_mul), + Add | AddUnchecked => Some(i128::overflowing_add), + Sub | SubUnchecked => Some(i128::overflowing_sub), + Mul | MulUnchecked => Some(i128::overflowing_mul), _ => None, }; if let Some(op) = op { @@ -242,11 +264,11 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { // If that truncation loses any information, we have an overflow. let result = result as u128; let truncated = self.truncate(result, left_layout); - return Ok(( - Scalar::from_uint(truncated, size), - oflo || self.sign_extend(truncated, left_layout) != result, - left_layout.ty, - )); + let overflow = oflo || self.sign_extend(truncated, left_layout) != result; + if overflow && let Some(intrinsic_name) = throw_ub_on_overflow { + throw_ub_custom!(fluent::const_eval_overflow, name = intrinsic_name); + } + return Ok((Scalar::from_uint(truncated, size), overflow, left_layout.ty)); } } @@ -263,12 +285,12 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { BitAnd => (Scalar::from_uint(l & r, size), left_layout.ty), BitXor => (Scalar::from_uint(l ^ r, size), left_layout.ty), - Add | Sub | Mul | Rem | Div => { + Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Rem | Div => { assert!(!left_layout.abi.is_signed()); let op: fn(u128, u128) -> (u128, bool) = match bin_op { - Add => u128::overflowing_add, - Sub => u128::overflowing_sub, - Mul => u128::overflowing_mul, + Add | AddUnchecked => u128::overflowing_add, + Sub | SubUnchecked => u128::overflowing_sub, + Mul | MulUnchecked => u128::overflowing_mul, Div if r == 0 => throw_ub!(DivisionByZero), Rem if r == 0 => throw_ub!(RemainderByZero), Div => u128::overflowing_div, @@ -279,11 +301,11 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { // Truncate to target type. // If that truncation loses any information, we have an overflow. let truncated = self.truncate(result, left_layout); - return Ok(( - Scalar::from_uint(truncated, size), - oflo || truncated != result, - left_layout.ty, - )); + let overflow = oflo || truncated != result; + if overflow && let Some(intrinsic_name) = throw_ub_on_overflow { + throw_ub_custom!(fluent::const_eval_overflow, name = intrinsic_name); + } + return Ok((Scalar::from_uint(truncated, size), overflow, left_layout.ty)); } _ => span_bug!( diff --git a/compiler/rustc_const_eval/src/interpret/step.rs b/compiler/rustc_const_eval/src/interpret/step.rs index 1e60a1e72ea07..050ed291b4fc7 100644 --- a/compiler/rustc_const_eval/src/interpret/step.rs +++ b/compiler/rustc_const_eval/src/interpret/step.rs @@ -16,7 +16,8 @@ use super::{ImmTy, InterpCx, Machine}; fn binop_left_homogeneous(op: mir::BinOp) -> bool { use rustc_middle::mir::BinOp::*; match op { - Add | Sub | Mul | Div | Rem | BitXor | BitAnd | BitOr | Offset | Shl | Shr => true, + Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor + | BitAnd | BitOr | Offset | Shl | ShlUnchecked | Shr | ShrUnchecked => true, Eq | Ne | Lt | Le | Gt | Ge => false, } } @@ -26,8 +27,9 @@ fn binop_left_homogeneous(op: mir::BinOp) -> bool { fn binop_right_homogeneous(op: mir::BinOp) -> bool { use rustc_middle::mir::BinOp::*; match op { - Add | Sub | Mul | Div | Rem | BitXor | BitAnd | BitOr | Eq | Ne | Lt | Le | Gt | Ge => true, - Offset | Shl | Shr => false, + Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor + | BitAnd | BitOr | Eq | Ne | Lt | Le | Gt | Ge => true, + Offset | Shl | ShlUnchecked | Shr | ShrUnchecked => false, } } diff --git a/compiler/rustc_const_eval/src/transform/promote_consts.rs b/compiler/rustc_const_eval/src/transform/promote_consts.rs index 44b143c77f36e..3802df5d3fc98 100644 --- a/compiler/rustc_const_eval/src/transform/promote_consts.rs +++ b/compiler/rustc_const_eval/src/transform/promote_consts.rs @@ -569,13 +569,18 @@ impl<'tcx> Validator<'_, 'tcx> { | BinOp::Gt | BinOp::Offset | BinOp::Add + | BinOp::AddUnchecked | BinOp::Sub + | BinOp::SubUnchecked | BinOp::Mul + | BinOp::MulUnchecked | BinOp::BitXor | BinOp::BitAnd | BinOp::BitOr | BinOp::Shl - | BinOp::Shr => {} + | BinOp::ShlUnchecked + | BinOp::Shr + | BinOp::ShrUnchecked => {} } self.validate_operand(lhs)?; diff --git a/compiler/rustc_const_eval/src/transform/validate.rs b/compiler/rustc_const_eval/src/transform/validate.rs index 3c350e25ba6ec..d421c7a2755ea 100644 --- a/compiler/rustc_const_eval/src/transform/validate.rs +++ b/compiler/rustc_const_eval/src/transform/validate.rs @@ -556,7 +556,7 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { ); } } - Shl | Shr => { + Shl | ShlUnchecked | Shr | ShrUnchecked => { for x in [a, b] { check_kinds!( x, @@ -601,6 +601,24 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { ); } } + AddUnchecked | SubUnchecked | MulUnchecked => { + for x in [a, b] { + check_kinds!( + x, + "Cannot perform unchecked arithmetic on type {:?}", + ty::Uint(..) | ty::Int(..) + ) + } + if a != b { + self.fail( + location, + format!( + "Cannot perform unchecked arithmetic on unequal types {:?} and {:?}", + a, b + ), + ); + } + } } } Rvalue::CheckedBinaryOp(op, vals) => { diff --git a/compiler/rustc_middle/src/mir/syntax.rs b/compiler/rustc_middle/src/mir/syntax.rs index 1a65f74f4fe22..ddc9fdc9a4239 100644 --- a/compiler/rustc_middle/src/mir/syntax.rs +++ b/compiler/rustc_middle/src/mir/syntax.rs @@ -1267,10 +1267,16 @@ pub enum UnOp { pub enum BinOp { /// The `+` operator (addition) Add, + /// Like `Add`, but with UB on overflow. (Integers only.) + AddUnchecked, /// The `-` operator (subtraction) Sub, + /// Like `Sub`, but with UB on overflow. (Integers only.) + SubUnchecked, /// The `*` operator (multiplication) Mul, + /// Like `Mul`, but with UB on overflow. (Integers only.) + MulUnchecked, /// The `/` operator (division) /// /// For integer types, division by zero is UB, as is `MIN / -1` for signed. @@ -1296,10 +1302,17 @@ pub enum BinOp { /// /// The offset is truncated to the size of the first operand before shifting. Shl, + /// Like `Shl`, but is UB if the RHS >= LHS::BITS + ShlUnchecked, /// The `>>` operator (shift right) /// /// The offset is truncated to the size of the first operand before shifting. + /// + /// This is an arithmetic shift if the LHS is signed + /// and a logical shift if the LHS is unsigned. Shr, + /// Like `Shl`, but is UB if the RHS >= LHS::BITS + ShrUnchecked, /// The `==` operator (equality) Eq, /// The `<` operator (less than) diff --git a/compiler/rustc_middle/src/mir/tcx.rs b/compiler/rustc_middle/src/mir/tcx.rs index 5ca8241344832..4a16abdd4e38f 100644 --- a/compiler/rustc_middle/src/mir/tcx.rs +++ b/compiler/rustc_middle/src/mir/tcx.rs @@ -235,8 +235,11 @@ impl<'tcx> BinOp { // FIXME: handle SIMD correctly match self { &BinOp::Add + | &BinOp::AddUnchecked | &BinOp::Sub + | &BinOp::SubUnchecked | &BinOp::Mul + | &BinOp::MulUnchecked | &BinOp::Div | &BinOp::Rem | &BinOp::BitXor @@ -246,7 +249,11 @@ impl<'tcx> BinOp { assert_eq!(lhs_ty, rhs_ty); lhs_ty } - &BinOp::Shl | &BinOp::Shr | &BinOp::Offset => { + &BinOp::Shl + | &BinOp::ShlUnchecked + | &BinOp::Shr + | &BinOp::ShrUnchecked + | &BinOp::Offset => { lhs_ty // lhs_ty can be != rhs_ty } &BinOp::Eq | &BinOp::Lt | &BinOp::Le | &BinOp::Ne | &BinOp::Ge | &BinOp::Gt => { @@ -293,7 +300,14 @@ impl BinOp { BinOp::Gt => hir::BinOpKind::Gt, BinOp::Le => hir::BinOpKind::Le, BinOp::Ge => hir::BinOpKind::Ge, - BinOp::Offset => unreachable!(), + BinOp::AddUnchecked + | BinOp::SubUnchecked + | BinOp::MulUnchecked + | BinOp::ShlUnchecked + | BinOp::ShrUnchecked + | BinOp::Offset => { + unreachable!() + } } } } diff --git a/compiler/rustc_mir_transform/src/lower_intrinsics.rs b/compiler/rustc_mir_transform/src/lower_intrinsics.rs index 3a7d58f712568..ce98e9b0c8432 100644 --- a/compiler/rustc_mir_transform/src/lower_intrinsics.rs +++ b/compiler/rustc_mir_transform/src/lower_intrinsics.rs @@ -85,8 +85,13 @@ impl<'tcx> MirPass<'tcx> for LowerIntrinsics { sym::wrapping_add | sym::wrapping_sub | sym::wrapping_mul + | sym::unchecked_add + | sym::unchecked_sub + | sym::unchecked_mul | sym::unchecked_div - | sym::unchecked_rem => { + | sym::unchecked_rem + | sym::unchecked_shl + | sym::unchecked_shr => { let target = target.unwrap(); let lhs; let rhs; @@ -99,8 +104,13 @@ impl<'tcx> MirPass<'tcx> for LowerIntrinsics { sym::wrapping_add => BinOp::Add, sym::wrapping_sub => BinOp::Sub, sym::wrapping_mul => BinOp::Mul, + sym::unchecked_add => BinOp::AddUnchecked, + sym::unchecked_sub => BinOp::SubUnchecked, + sym::unchecked_mul => BinOp::MulUnchecked, sym::unchecked_div => BinOp::Div, sym::unchecked_rem => BinOp::Rem, + sym::unchecked_shl => BinOp::ShlUnchecked, + sym::unchecked_shr => BinOp::ShrUnchecked, _ => bug!("unexpected intrinsic"), }; block.statements.push(Statement { diff --git a/compiler/rustc_smir/src/rustc_smir/mod.rs b/compiler/rustc_smir/src/rustc_smir/mod.rs index 6bd030b13d1ce..fd108eda5e88d 100644 --- a/compiler/rustc_smir/src/rustc_smir/mod.rs +++ b/compiler/rustc_smir/src/rustc_smir/mod.rs @@ -250,15 +250,20 @@ impl Stable for mir::BinOp { use mir::BinOp; match self { BinOp::Add => stable_mir::mir::BinOp::Add, + BinOp::AddUnchecked => stable_mir::mir::BinOp::AddUnchecked, BinOp::Sub => stable_mir::mir::BinOp::Sub, + BinOp::SubUnchecked => stable_mir::mir::BinOp::SubUnchecked, BinOp::Mul => stable_mir::mir::BinOp::Mul, + BinOp::MulUnchecked => stable_mir::mir::BinOp::MulUnchecked, BinOp::Div => stable_mir::mir::BinOp::Div, BinOp::Rem => stable_mir::mir::BinOp::Rem, BinOp::BitXor => stable_mir::mir::BinOp::BitXor, BinOp::BitAnd => stable_mir::mir::BinOp::BitAnd, BinOp::BitOr => stable_mir::mir::BinOp::BitOr, BinOp::Shl => stable_mir::mir::BinOp::Shl, + BinOp::ShlUnchecked => stable_mir::mir::BinOp::ShlUnchecked, BinOp::Shr => stable_mir::mir::BinOp::Shr, + BinOp::ShrUnchecked => stable_mir::mir::BinOp::ShrUnchecked, BinOp::Eq => stable_mir::mir::BinOp::Eq, BinOp::Lt => stable_mir::mir::BinOp::Lt, BinOp::Le => stable_mir::mir::BinOp::Le, diff --git a/compiler/rustc_smir/src/stable_mir/mir/body.rs b/compiler/rustc_smir/src/stable_mir/mir/body.rs index 9df7b4945b70a..468e915d1a073 100644 --- a/compiler/rustc_smir/src/stable_mir/mir/body.rs +++ b/compiler/rustc_smir/src/stable_mir/mir/body.rs @@ -88,15 +88,20 @@ pub enum AssertMessage { #[derive(Clone, Debug)] pub enum BinOp { Add, + AddUnchecked, Sub, + SubUnchecked, Mul, + MulUnchecked, Div, Rem, BitXor, BitAnd, BitOr, Shl, + ShlUnchecked, Shr, + ShrUnchecked, Eq, Lt, Le, diff --git a/compiler/rustc_ty_utils/src/consts.rs b/compiler/rustc_ty_utils/src/consts.rs index ce77df0df5dcf..387adda8f579f 100644 --- a/compiler/rustc_ty_utils/src/consts.rs +++ b/compiler/rustc_ty_utils/src/consts.rs @@ -78,8 +78,9 @@ pub(crate) fn destructure_const<'tcx>( fn check_binop(op: mir::BinOp) -> bool { use mir::BinOp::*; match op { - Add | Sub | Mul | Div | Rem | BitXor | BitAnd | BitOr | Shl | Shr | Eq | Lt | Le | Ne - | Ge | Gt => true, + Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor + | BitAnd | BitOr | Shl | ShlUnchecked | Shr | ShrUnchecked | Eq | Lt | Le | Ne | Ge + | Gt => true, Offset => false, } } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-abort.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-abort.diff index 1ed65b310ac00..1ab1d01e5faca 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-abort.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-abort.diff @@ -21,12 +21,12 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shl(move _3, move _4) -> [return: bb1, unwind unreachable]; +- } +- +- bb1: { + StorageLive(_5); + _5 = _4 as u64 (IntToInt); -+ _0 = unchecked_shl::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShlUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-unwind.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-unwind.diff index 7a27675638b01..577fc8bee66fa 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-unwind.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-unwind.diff @@ -21,12 +21,12 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shl(move _3, move _4) -> bb1; +- } +- +- bb1: { + StorageLive(_5); + _5 = _4 as u64 (IntToInt); -+ _0 = unchecked_shl::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShlUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-abort.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-abort.mir index eee56b9560d06..65b832497f9d5 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-abort.mir @@ -15,10 +15,7 @@ fn unchecked_shl_unsigned_bigger(_1: u64, _2: u32) -> u64 { bb0: { StorageLive(_3); _3 = _2 as u64 (IntToInt); - _0 = unchecked_shl::(_1, move _3) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShlUnchecked(_1, move _3); StorageDead(_3); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-unwind.mir index eee56b9560d06..65b832497f9d5 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-unwind.mir @@ -15,10 +15,7 @@ fn unchecked_shl_unsigned_bigger(_1: u64, _2: u32) -> u64 { bb0: { StorageLive(_3); _3 = _2 as u64 (IntToInt); - _0 = unchecked_shl::(_1, move _3) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShlUnchecked(_1, move _3); StorageDead(_3); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-abort.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-abort.diff index 6c809f0b533e7..90b32247c95ea 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-abort.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-abort.diff @@ -23,6 +23,9 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shl(move _3, move _4) -> [return: bb1, unwind unreachable]; +- } +- +- bb1: { + StorageLive(_5); + StorageLive(_6); + StorageLive(_7); @@ -32,10 +35,7 @@ + assume(move _6); + StorageDead(_6); + _5 = _4 as u16 (IntToInt); -+ _0 = unchecked_shl::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShlUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-unwind.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-unwind.diff index 0753c1b05df44..ba159c063b3b0 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-unwind.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-unwind.diff @@ -23,6 +23,9 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shl(move _3, move _4) -> bb1; +- } +- +- bb1: { + StorageLive(_5); + StorageLive(_6); + StorageLive(_7); @@ -32,10 +35,7 @@ + assume(move _6); + StorageDead(_6); + _5 = _4 as u16 (IntToInt); -+ _0 = unchecked_shl::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShlUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-abort.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-abort.mir index 7bf10b365a6cf..3f388a69d7ebe 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-abort.mir @@ -24,10 +24,7 @@ fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 { assume(move _4); StorageDead(_4); _5 = _2 as u16 (IntToInt); - _0 = unchecked_shl::(_1, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShlUnchecked(_1, move _5); StorageDead(_5); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-unwind.mir index 7bf10b365a6cf..3f388a69d7ebe 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-unwind.mir @@ -24,10 +24,7 @@ fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 { assume(move _4); StorageDead(_4); _5 = _2 as u16 (IntToInt); - _0 = unchecked_shl::(_1, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShlUnchecked(_1, move _5); StorageDead(_5); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-abort.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-abort.diff index 04ddb4e80ff56..1e83fec4f3d00 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-abort.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-abort.diff @@ -21,12 +21,12 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shr(move _3, move _4) -> [return: bb1, unwind unreachable]; +- } +- +- bb1: { + StorageLive(_5); + _5 = _4 as i64 (IntToInt); -+ _0 = unchecked_shr::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShrUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-unwind.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-unwind.diff index 762aa1564b507..d7ff104b92e9a 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-unwind.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-unwind.diff @@ -21,12 +21,12 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shr(move _3, move _4) -> bb1; +- } +- +- bb1: { + StorageLive(_5); + _5 = _4 as i64 (IntToInt); -+ _0 = unchecked_shr::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShrUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-abort.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-abort.mir index 858760d065c94..7524ec4970e4b 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-abort.mir @@ -15,10 +15,7 @@ fn unchecked_shr_signed_bigger(_1: i64, _2: u32) -> i64 { bb0: { StorageLive(_3); _3 = _2 as i64 (IntToInt); - _0 = unchecked_shr::(_1, move _3) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShrUnchecked(_1, move _3); StorageDead(_3); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-unwind.mir index 858760d065c94..7524ec4970e4b 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.panic-unwind.mir @@ -15,10 +15,7 @@ fn unchecked_shr_signed_bigger(_1: i64, _2: u32) -> i64 { bb0: { StorageLive(_3); _3 = _2 as i64 (IntToInt); - _0 = unchecked_shr::(_1, move _3) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShrUnchecked(_1, move _3); StorageDead(_3); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-abort.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-abort.diff index 5739336cb4f3c..fa7e5d16e39f2 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-abort.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-abort.diff @@ -23,6 +23,9 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shr(move _3, move _4) -> [return: bb1, unwind unreachable]; +- } +- +- bb1: { + StorageLive(_5); + StorageLive(_6); + StorageLive(_7); @@ -32,10 +35,7 @@ + assume(move _6); + StorageDead(_6); + _5 = _4 as i16 (IntToInt); -+ _0 = unchecked_shr::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShrUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-unwind.diff b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-unwind.diff index e04912e1d1cff..3d398e00fc890 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-unwind.diff +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.panic-unwind.diff @@ -23,6 +23,9 @@ StorageLive(_4); _4 = _2; - _0 = core::num::::unchecked_shr(move _3, move _4) -> bb1; +- } +- +- bb1: { + StorageLive(_5); + StorageLive(_6); + StorageLive(_7); @@ -32,10 +35,7 @@ + assume(move _6); + StorageDead(_6); + _5 = _4 as i16 (IntToInt); -+ _0 = unchecked_shr::(_3, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { ++ _0 = ShrUnchecked(_3, move _5); + StorageDead(_5); StorageDead(_4); StorageDead(_3); diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-abort.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-abort.mir index 08b044f4f9e62..64ea25349ac00 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-abort.mir @@ -24,10 +24,7 @@ fn unchecked_shr_signed_smaller(_1: i16, _2: u32) -> i16 { assume(move _4); StorageDead(_4); _5 = _2 as i16 (IntToInt); - _0 = unchecked_shr::(_1, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShrUnchecked(_1, move _5); StorageDead(_5); return; } diff --git a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-unwind.mir index 08b044f4f9e62..64ea25349ac00 100644 --- a/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.panic-unwind.mir @@ -24,10 +24,7 @@ fn unchecked_shr_signed_smaller(_1: i16, _2: u32) -> i16 { assume(move _4); StorageDead(_4); _5 = _2 as i16 (IntToInt); - _0 = unchecked_shr::(_1, move _5) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _0 = ShrUnchecked(_1, move _5); StorageDead(_5); return; } diff --git a/tests/mir-opt/lower_intrinsics.rs b/tests/mir-opt/lower_intrinsics.rs index 876b4497034e3..0758e9b775b9d 100644 --- a/tests/mir-opt/lower_intrinsics.rs +++ b/tests/mir-opt/lower_intrinsics.rs @@ -13,8 +13,13 @@ pub fn wrapping(a: i32, b: i32) { // EMIT_MIR lower_intrinsics.unchecked.LowerIntrinsics.diff pub unsafe fn unchecked(a: i32, b: i32) { + let _a = core::intrinsics::unchecked_add(a, b); + let _b = core::intrinsics::unchecked_sub(a, b); + let _c = core::intrinsics::unchecked_mul(a, b); let _x = core::intrinsics::unchecked_div(a, b); let _y = core::intrinsics::unchecked_rem(a, b); + let _i = core::intrinsics::unchecked_shl(a, b); + let _j = core::intrinsics::unchecked_shr(a, b); } // EMIT_MIR lower_intrinsics.size_of.LowerIntrinsics.diff diff --git a/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-abort.diff b/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-abort.diff index c532d74ced053..dd92b8d6d2ca9 100644 --- a/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-abort.diff +++ b/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-abort.diff @@ -10,11 +10,41 @@ let mut _5: i32; let mut _7: i32; let mut _8: i32; + let mut _10: i32; + let mut _11: i32; + let mut _13: i32; + let mut _14: i32; + let mut _16: i32; + let mut _17: i32; + let mut _19: i32; + let mut _20: i32; + let mut _22: i32; + let mut _23: i32; scope 1 { - debug _x => _3; + debug _a => _3; let _6: i32; scope 2 { - debug _y => _6; + debug _b => _6; + let _9: i32; + scope 3 { + debug _c => _9; + let _12: i32; + scope 4 { + debug _x => _12; + let _15: i32; + scope 5 { + debug _y => _15; + let _18: i32; + scope 6 { + debug _i => _18; + let _21: i32; + scope 7 { + debug _j => _21; + } + } + } + } + } } } @@ -24,8 +54,8 @@ _4 = _1; StorageLive(_5); _5 = _2; -- _3 = unchecked_div::(move _4, move _5) -> [return: bb1, unwind unreachable]; -+ _3 = Div(move _4, move _5); +- _3 = unchecked_add::(move _4, move _5) -> [return: bb1, unwind unreachable]; ++ _3 = AddUnchecked(move _4, move _5); + goto -> bb1; } @@ -37,15 +67,85 @@ _7 = _1; StorageLive(_8); _8 = _2; -- _6 = unchecked_rem::(move _7, move _8) -> [return: bb2, unwind unreachable]; -+ _6 = Rem(move _7, move _8); +- _6 = unchecked_sub::(move _7, move _8) -> [return: bb2, unwind unreachable]; ++ _6 = SubUnchecked(move _7, move _8); + goto -> bb2; } bb2: { StorageDead(_8); StorageDead(_7); + StorageLive(_9); + StorageLive(_10); + _10 = _1; + StorageLive(_11); + _11 = _2; +- _9 = unchecked_mul::(move _10, move _11) -> [return: bb3, unwind unreachable]; ++ _9 = MulUnchecked(move _10, move _11); ++ goto -> bb3; + } + + bb3: { + StorageDead(_11); + StorageDead(_10); + StorageLive(_12); + StorageLive(_13); + _13 = _1; + StorageLive(_14); + _14 = _2; +- _12 = unchecked_div::(move _13, move _14) -> [return: bb4, unwind unreachable]; ++ _12 = Div(move _13, move _14); ++ goto -> bb4; + } + + bb4: { + StorageDead(_14); + StorageDead(_13); + StorageLive(_15); + StorageLive(_16); + _16 = _1; + StorageLive(_17); + _17 = _2; +- _15 = unchecked_rem::(move _16, move _17) -> [return: bb5, unwind unreachable]; ++ _15 = Rem(move _16, move _17); ++ goto -> bb5; + } + + bb5: { + StorageDead(_17); + StorageDead(_16); + StorageLive(_18); + StorageLive(_19); + _19 = _1; + StorageLive(_20); + _20 = _2; +- _18 = unchecked_shl::(move _19, move _20) -> [return: bb6, unwind unreachable]; ++ _18 = ShlUnchecked(move _19, move _20); ++ goto -> bb6; + } + + bb6: { + StorageDead(_20); + StorageDead(_19); + StorageLive(_21); + StorageLive(_22); + _22 = _1; + StorageLive(_23); + _23 = _2; +- _21 = unchecked_shr::(move _22, move _23) -> [return: bb7, unwind unreachable]; ++ _21 = ShrUnchecked(move _22, move _23); ++ goto -> bb7; + } + + bb7: { + StorageDead(_23); + StorageDead(_22); _0 = const (); + StorageDead(_21); + StorageDead(_18); + StorageDead(_15); + StorageDead(_12); + StorageDead(_9); StorageDead(_6); StorageDead(_3); return; diff --git a/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-unwind.diff b/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-unwind.diff index c532d74ced053..dd92b8d6d2ca9 100644 --- a/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-unwind.diff +++ b/tests/mir-opt/lower_intrinsics.unchecked.LowerIntrinsics.panic-unwind.diff @@ -10,11 +10,41 @@ let mut _5: i32; let mut _7: i32; let mut _8: i32; + let mut _10: i32; + let mut _11: i32; + let mut _13: i32; + let mut _14: i32; + let mut _16: i32; + let mut _17: i32; + let mut _19: i32; + let mut _20: i32; + let mut _22: i32; + let mut _23: i32; scope 1 { - debug _x => _3; + debug _a => _3; let _6: i32; scope 2 { - debug _y => _6; + debug _b => _6; + let _9: i32; + scope 3 { + debug _c => _9; + let _12: i32; + scope 4 { + debug _x => _12; + let _15: i32; + scope 5 { + debug _y => _15; + let _18: i32; + scope 6 { + debug _i => _18; + let _21: i32; + scope 7 { + debug _j => _21; + } + } + } + } + } } } @@ -24,8 +54,8 @@ _4 = _1; StorageLive(_5); _5 = _2; -- _3 = unchecked_div::(move _4, move _5) -> [return: bb1, unwind unreachable]; -+ _3 = Div(move _4, move _5); +- _3 = unchecked_add::(move _4, move _5) -> [return: bb1, unwind unreachable]; ++ _3 = AddUnchecked(move _4, move _5); + goto -> bb1; } @@ -37,15 +67,85 @@ _7 = _1; StorageLive(_8); _8 = _2; -- _6 = unchecked_rem::(move _7, move _8) -> [return: bb2, unwind unreachable]; -+ _6 = Rem(move _7, move _8); +- _6 = unchecked_sub::(move _7, move _8) -> [return: bb2, unwind unreachable]; ++ _6 = SubUnchecked(move _7, move _8); + goto -> bb2; } bb2: { StorageDead(_8); StorageDead(_7); + StorageLive(_9); + StorageLive(_10); + _10 = _1; + StorageLive(_11); + _11 = _2; +- _9 = unchecked_mul::(move _10, move _11) -> [return: bb3, unwind unreachable]; ++ _9 = MulUnchecked(move _10, move _11); ++ goto -> bb3; + } + + bb3: { + StorageDead(_11); + StorageDead(_10); + StorageLive(_12); + StorageLive(_13); + _13 = _1; + StorageLive(_14); + _14 = _2; +- _12 = unchecked_div::(move _13, move _14) -> [return: bb4, unwind unreachable]; ++ _12 = Div(move _13, move _14); ++ goto -> bb4; + } + + bb4: { + StorageDead(_14); + StorageDead(_13); + StorageLive(_15); + StorageLive(_16); + _16 = _1; + StorageLive(_17); + _17 = _2; +- _15 = unchecked_rem::(move _16, move _17) -> [return: bb5, unwind unreachable]; ++ _15 = Rem(move _16, move _17); ++ goto -> bb5; + } + + bb5: { + StorageDead(_17); + StorageDead(_16); + StorageLive(_18); + StorageLive(_19); + _19 = _1; + StorageLive(_20); + _20 = _2; +- _18 = unchecked_shl::(move _19, move _20) -> [return: bb6, unwind unreachable]; ++ _18 = ShlUnchecked(move _19, move _20); ++ goto -> bb6; + } + + bb6: { + StorageDead(_20); + StorageDead(_19); + StorageLive(_21); + StorageLive(_22); + _22 = _1; + StorageLive(_23); + _23 = _2; +- _21 = unchecked_shr::(move _22, move _23) -> [return: bb7, unwind unreachable]; ++ _21 = ShrUnchecked(move _22, move _23); ++ goto -> bb7; + } + + bb7: { + StorageDead(_23); + StorageDead(_22); _0 = const (); + StorageDead(_21); + StorageDead(_18); + StorageDead(_15); + StorageDead(_12); + StorageDead(_9); StorageDead(_6); StorageDead(_3); return; diff --git a/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir index 1a7d5433e3597..800308c2e0bdd 100644 --- a/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir @@ -7,10 +7,9 @@ fn checked_shl(_1: u32, _2: u32) -> Option { scope 1 (inlined core::num::::checked_shl) { debug self => _1; debug rhs => _2; - let mut _7: u32; - let mut _8: bool; + let mut _7: bool; scope 2 { - debug a => _7; + debug a => _5; debug b => _6; } scope 3 (inlined core::num::::overflowing_shl) { @@ -36,44 +35,38 @@ fn checked_shl(_1: u32, _2: u32) -> Option { } bb0: { - StorageLive(_6); - StorageLive(_7); StorageLive(_5); + StorageLive(_6); StorageLive(_4); StorageLive(_3); _3 = const 31_u32; _4 = BitAnd(_2, move _3); StorageDead(_3); - _5 = unchecked_shl::(_1, _4) -> [return: bb1, unwind unreachable]; + _5 = ShlUnchecked(_1, _4); + StorageDead(_4); + _6 = Ge(_2, const _); + StorageLive(_7); + _7 = unlikely(_6) -> [return: bb1, unwind unreachable]; } bb1: { - StorageDead(_4); - _6 = Ge(_2, const _); - _7 = move _5; - StorageDead(_5); - StorageLive(_8); - _8 = unlikely(_6) -> [return: bb2, unwind unreachable]; + switchInt(move _7) -> [0: bb2, otherwise: bb3]; } bb2: { - switchInt(move _8) -> [0: bb3, otherwise: bb4]; + _0 = Option::::Some(_5); + goto -> bb4; } bb3: { - _0 = Option::::Some(_7); - goto -> bb5; - } - - bb4: { _0 = Option::::None; - goto -> bb5; + goto -> bb4; } - bb5: { - StorageDead(_8); + bb4: { StorageDead(_7); StorageDead(_6); + StorageDead(_5); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir index 79282d88905b2..9d914e95344e1 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir @@ -10,18 +10,17 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> debug self => _1; debug index => std::ops::Range{ .0 => _3, .1 => _4, }; let mut _5: *mut [u32]; - let mut _14: *mut [u32]; + let mut _13: *mut [u32]; scope 2 { scope 3 (inlined as SliceIndex<[u32]>>::get_unchecked_mut) { debug self => std::ops::Range{ .0 => _3, .1 => _4, }; debug slice => _5; let mut _7: *mut u32; let mut _8: *mut u32; - let mut _9: usize; + let _15: usize; let _16: usize; - let _17: usize; scope 4 { - debug this => std::ops::Range{ .0 => _16, .1 => _17, }; + debug this => std::ops::Range{ .0 => _15, .1 => _16, }; scope 5 { let _6: usize; scope 6 { @@ -37,30 +36,30 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> } scope 14 (inlined slice_from_raw_parts_mut::) { debug data => _8; - debug len => _9; - let mut _10: *mut (); + debug len => _6; + let mut _9: *mut (); scope 15 (inlined ptr::mut_ptr::::cast::<()>) { debug self => _8; } scope 16 (inlined std::ptr::from_raw_parts_mut::<[u32]>) { - debug data_address => _10; - debug metadata => _9; - let mut _11: *const (); - let mut _12: std::ptr::metadata::PtrComponents<[u32]>; - let mut _13: std::ptr::metadata::PtrRepr<[u32]>; + debug data_address => _9; + debug metadata => _6; + let mut _10: *const (); + let mut _11: std::ptr::metadata::PtrComponents<[u32]>; + let mut _12: std::ptr::metadata::PtrRepr<[u32]>; scope 17 { } } } } scope 7 (inlined as SliceIndex<[T]>>::get_unchecked_mut::runtime::) { - debug this => std::ops::Range{ .0 => _16, .1 => _17, }; + debug this => std::ops::Range{ .0 => _15, .1 => _16, }; debug slice => _5; scope 8 (inlined ptr::mut_ptr::::len) { debug self => _5; - let mut _15: *const [u32]; + let mut _14: *const [u32]; scope 9 (inlined std::ptr::metadata::<[u32]>) { - debug ptr => _15; + debug ptr => _14; scope 10 { } } @@ -75,46 +74,40 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> bb0: { _3 = move (_2.0: usize); _4 = move (_2.1: usize); - StorageLive(_14); + StorageLive(_13); StorageLive(_5); _5 = &raw mut (*_1); + StorageLive(_6); + StorageLive(_14); StorageLive(_15); StorageLive(_16); - StorageLive(_17); - StorageLive(_6); - _6 = unchecked_sub::(_4, _3) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _6 = SubUnchecked(_4, _3); StorageLive(_8); StorageLive(_7); _7 = _5 as *mut u32 (PtrToPtr); _8 = Offset(_7, _3); StorageDead(_7); StorageLive(_9); - _9 = _6; - StorageLive(_10); - _10 = _8 as *mut () (PtrToPtr); - StorageLive(_13); + _9 = _8 as *mut () (PtrToPtr); StorageLive(_12); StorageLive(_11); - _11 = _10 as *const () (Pointer(MutToConstPointer)); - _12 = ptr::metadata::PtrComponents::<[u32]> { data_address: move _11, metadata: _9 }; + StorageLive(_10); + _10 = _9 as *const () (Pointer(MutToConstPointer)); + _11 = ptr::metadata::PtrComponents::<[u32]> { data_address: move _10, metadata: _6 }; + StorageDead(_10); + _12 = ptr::metadata::PtrRepr::<[u32]> { const_ptr: move _11 }; StorageDead(_11); - _13 = ptr::metadata::PtrRepr::<[u32]> { const_ptr: move _12 }; + _13 = (_12.1: *mut [u32]); StorageDead(_12); - _14 = (_13.1: *mut [u32]); - StorageDead(_13); - StorageDead(_10); StorageDead(_9); StorageDead(_8); - StorageDead(_6); - StorageDead(_17); StorageDead(_16); StorageDead(_15); - StorageDead(_5); - _0 = &mut (*_14); StorageDead(_14); + StorageDead(_6); + StorageDead(_5); + _0 = &mut (*_13); + StorageDead(_13); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir index 79282d88905b2..9d914e95344e1 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir @@ -10,18 +10,17 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> debug self => _1; debug index => std::ops::Range{ .0 => _3, .1 => _4, }; let mut _5: *mut [u32]; - let mut _14: *mut [u32]; + let mut _13: *mut [u32]; scope 2 { scope 3 (inlined as SliceIndex<[u32]>>::get_unchecked_mut) { debug self => std::ops::Range{ .0 => _3, .1 => _4, }; debug slice => _5; let mut _7: *mut u32; let mut _8: *mut u32; - let mut _9: usize; + let _15: usize; let _16: usize; - let _17: usize; scope 4 { - debug this => std::ops::Range{ .0 => _16, .1 => _17, }; + debug this => std::ops::Range{ .0 => _15, .1 => _16, }; scope 5 { let _6: usize; scope 6 { @@ -37,30 +36,30 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> } scope 14 (inlined slice_from_raw_parts_mut::) { debug data => _8; - debug len => _9; - let mut _10: *mut (); + debug len => _6; + let mut _9: *mut (); scope 15 (inlined ptr::mut_ptr::::cast::<()>) { debug self => _8; } scope 16 (inlined std::ptr::from_raw_parts_mut::<[u32]>) { - debug data_address => _10; - debug metadata => _9; - let mut _11: *const (); - let mut _12: std::ptr::metadata::PtrComponents<[u32]>; - let mut _13: std::ptr::metadata::PtrRepr<[u32]>; + debug data_address => _9; + debug metadata => _6; + let mut _10: *const (); + let mut _11: std::ptr::metadata::PtrComponents<[u32]>; + let mut _12: std::ptr::metadata::PtrRepr<[u32]>; scope 17 { } } } } scope 7 (inlined as SliceIndex<[T]>>::get_unchecked_mut::runtime::) { - debug this => std::ops::Range{ .0 => _16, .1 => _17, }; + debug this => std::ops::Range{ .0 => _15, .1 => _16, }; debug slice => _5; scope 8 (inlined ptr::mut_ptr::::len) { debug self => _5; - let mut _15: *const [u32]; + let mut _14: *const [u32]; scope 9 (inlined std::ptr::metadata::<[u32]>) { - debug ptr => _15; + debug ptr => _14; scope 10 { } } @@ -75,46 +74,40 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> bb0: { _3 = move (_2.0: usize); _4 = move (_2.1: usize); - StorageLive(_14); + StorageLive(_13); StorageLive(_5); _5 = &raw mut (*_1); + StorageLive(_6); + StorageLive(_14); StorageLive(_15); StorageLive(_16); - StorageLive(_17); - StorageLive(_6); - _6 = unchecked_sub::(_4, _3) -> [return: bb1, unwind unreachable]; - } - - bb1: { + _6 = SubUnchecked(_4, _3); StorageLive(_8); StorageLive(_7); _7 = _5 as *mut u32 (PtrToPtr); _8 = Offset(_7, _3); StorageDead(_7); StorageLive(_9); - _9 = _6; - StorageLive(_10); - _10 = _8 as *mut () (PtrToPtr); - StorageLive(_13); + _9 = _8 as *mut () (PtrToPtr); StorageLive(_12); StorageLive(_11); - _11 = _10 as *const () (Pointer(MutToConstPointer)); - _12 = ptr::metadata::PtrComponents::<[u32]> { data_address: move _11, metadata: _9 }; + StorageLive(_10); + _10 = _9 as *const () (Pointer(MutToConstPointer)); + _11 = ptr::metadata::PtrComponents::<[u32]> { data_address: move _10, metadata: _6 }; + StorageDead(_10); + _12 = ptr::metadata::PtrRepr::<[u32]> { const_ptr: move _11 }; StorageDead(_11); - _13 = ptr::metadata::PtrRepr::<[u32]> { const_ptr: move _12 }; + _13 = (_12.1: *mut [u32]); StorageDead(_12); - _14 = (_13.1: *mut [u32]); - StorageDead(_13); - StorageDead(_10); StorageDead(_9); StorageDead(_8); - StorageDead(_6); - StorageDead(_17); StorageDead(_16); StorageDead(_15); - StorageDead(_5); - _0 = &mut (*_14); StorageDead(_14); + StorageDead(_6); + StorageDead(_5); + _0 = &mut (*_13); + StorageDead(_13); return; } } From 3fd8501823a36b057cc539551655b8adbc4acf76 Mon Sep 17 00:00:00 2001 From: Scott McMurray Date: Sat, 3 Jun 2023 02:38:22 -0700 Subject: [PATCH 2/3] Remove unchecked_add/sub/mul/shl/shr from CTFE/cg_ssa/cg_clif --- .../src/intrinsics/mod.rs | 20 ++------ .../rustc_codegen_ssa/src/mir/intrinsic.rs | 49 +++---------------- .../src/interpret/intrinsics.rs | 31 ------------ 3 files changed, 9 insertions(+), 91 deletions(-) diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs index 1e83c30bd677a..5862f18299e90 100644 --- a/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs +++ b/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs @@ -472,25 +472,11 @@ fn codegen_regular_intrinsic_call<'tcx>( ret.write_cvalue(fx, CValue::by_val(align, usize_layout)); } - sym::unchecked_add - | sym::unchecked_sub - | sym::unchecked_mul - | sym::exact_div - | sym::unchecked_shl - | sym::unchecked_shr => { + sym::exact_div => { intrinsic_args!(fx, args => (x, y); intrinsic); - // FIXME trap on overflow - let bin_op = match intrinsic { - sym::unchecked_add => BinOp::Add, - sym::unchecked_sub => BinOp::Sub, - sym::unchecked_mul => BinOp::Mul, - sym::exact_div => BinOp::Div, - sym::unchecked_shl => BinOp::Shl, - sym::unchecked_shr => BinOp::Shr, - _ => unreachable!(), - }; - let res = crate::num::codegen_int_binop(fx, bin_op, x, y); + // FIXME trap on inexact + let res = crate::num::codegen_int_binop(fx, BinOp::Div, x, y); ret.write_cvalue(fx, res); } sym::saturating_add | sym::saturating_sub => { diff --git a/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs b/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs index 9ac2424e76be0..8a65dd593b8c1 100644 --- a/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs +++ b/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs @@ -211,52 +211,15 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { args[1].val.unaligned_volatile_store(bx, dst); return; } - | sym::unchecked_shl - | sym::unchecked_shr - | sym::unchecked_add - | sym::unchecked_sub - | sym::unchecked_mul - | sym::exact_div => { + sym::exact_div => { let ty = arg_tys[0]; match int_type_width_signed(ty, bx.tcx()) { - Some((_width, signed)) => match name { - sym::exact_div => { - if signed { - bx.exactsdiv(args[0].immediate(), args[1].immediate()) - } else { - bx.exactudiv(args[0].immediate(), args[1].immediate()) - } - } - sym::unchecked_shl => bx.shl(args[0].immediate(), args[1].immediate()), - sym::unchecked_shr => { - if signed { - bx.ashr(args[0].immediate(), args[1].immediate()) - } else { - bx.lshr(args[0].immediate(), args[1].immediate()) - } - } - sym::unchecked_add => { - if signed { - bx.unchecked_sadd(args[0].immediate(), args[1].immediate()) - } else { - bx.unchecked_uadd(args[0].immediate(), args[1].immediate()) - } - } - sym::unchecked_sub => { - if signed { - bx.unchecked_ssub(args[0].immediate(), args[1].immediate()) - } else { - bx.unchecked_usub(args[0].immediate(), args[1].immediate()) - } - } - sym::unchecked_mul => { - if signed { - bx.unchecked_smul(args[0].immediate(), args[1].immediate()) - } else { - bx.unchecked_umul(args[0].immediate(), args[1].immediate()) - } + Some((_width, signed)) => { + if signed { + bx.exactsdiv(args[0].immediate(), args[1].immediate()) + } else { + bx.exactudiv(args[0].immediate(), args[1].immediate()) } - _ => bug!(), }, None => { bx.tcx().sess.emit_err(InvalidMonomorphization::BasicIntegerType { span, name, ty }); diff --git a/compiler/rustc_const_eval/src/interpret/intrinsics.rs b/compiler/rustc_const_eval/src/interpret/intrinsics.rs index 7192bbc00d556..8f4cf23770e3d 100644 --- a/compiler/rustc_const_eval/src/interpret/intrinsics.rs +++ b/compiler/rustc_const_eval/src/interpret/intrinsics.rs @@ -234,37 +234,6 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { let r = self.read_immediate(&args[1])?; self.exact_div(&l, &r, dest)?; } - sym::unchecked_shl - | sym::unchecked_shr - | sym::unchecked_add - | sym::unchecked_sub - | sym::unchecked_mul => { - let l = self.read_immediate(&args[0])?; - let r = self.read_immediate(&args[1])?; - let bin_op = match intrinsic_name { - sym::unchecked_shl => BinOp::Shl, - sym::unchecked_shr => BinOp::Shr, - sym::unchecked_add => BinOp::Add, - sym::unchecked_sub => BinOp::Sub, - sym::unchecked_mul => BinOp::Mul, - _ => bug!(), - }; - let (val, overflowed, _ty) = self.overflowing_binary_op(bin_op, &l, &r)?; - if overflowed { - let layout = self.layout_of(substs.type_at(0))?; - let r_val = r.to_scalar().to_bits(layout.size)?; - if let sym::unchecked_shl | sym::unchecked_shr = intrinsic_name { - throw_ub_custom!( - fluent::const_eval_overflow_shift, - val = r_val, - name = intrinsic_name - ); - } else { - throw_ub_custom!(fluent::const_eval_overflow, name = intrinsic_name); - } - } - self.write_scalar(val, dest)?; - } sym::rotate_left | sym::rotate_right => { // rotate_left: (X << (S % BW)) | (X >> ((BW - S) % BW)) // rotate_right: (X << ((BW - S) % BW)) | (X >> (S % BW)) From c780e55995dd29ac3e6577af8e8e1daa28998a63 Mon Sep 17 00:00:00 2001 From: Scott McMurray Date: Sun, 4 Jun 2023 11:09:20 -0700 Subject: [PATCH 3/3] Dedup some type checks in the MIR validator --- .../rustc_const_eval/src/interpret/step.rs | 30 +------- .../src/transform/validate.rs | 77 +++++++------------ compiler/rustc_const_eval/src/util/mod.rs | 26 +++++++ 3 files changed, 57 insertions(+), 76 deletions(-) diff --git a/compiler/rustc_const_eval/src/interpret/step.rs b/compiler/rustc_const_eval/src/interpret/step.rs index 050ed291b4fc7..619da8abb7d22 100644 --- a/compiler/rustc_const_eval/src/interpret/step.rs +++ b/compiler/rustc_const_eval/src/interpret/step.rs @@ -9,29 +9,7 @@ use rustc_middle::mir::interpret::{InterpResult, Scalar}; use rustc_middle::ty::layout::LayoutOf; use super::{ImmTy, InterpCx, Machine}; - -/// Classify whether an operator is "left-homogeneous", i.e., the LHS has the -/// same type as the result. -#[inline] -fn binop_left_homogeneous(op: mir::BinOp) -> bool { - use rustc_middle::mir::BinOp::*; - match op { - Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor - | BitAnd | BitOr | Offset | Shl | ShlUnchecked | Shr | ShrUnchecked => true, - Eq | Ne | Lt | Le | Gt | Ge => false, - } -} -/// Classify whether an operator is "right-homogeneous", i.e., the RHS has the -/// same type as the LHS. -#[inline] -fn binop_right_homogeneous(op: mir::BinOp) -> bool { - use rustc_middle::mir::BinOp::*; - match op { - Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor - | BitAnd | BitOr | Eq | Ne | Lt | Le | Gt | Ge => true, - Offset | Shl | ShlUnchecked | Shr | ShrUnchecked => false, - } -} +use crate::util; impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { /// Returns `true` as long as there are more things to do. @@ -181,9 +159,9 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { } BinaryOp(bin_op, box (ref left, ref right)) => { - let layout = binop_left_homogeneous(bin_op).then_some(dest.layout); + let layout = util::binop_left_homogeneous(bin_op).then_some(dest.layout); let left = self.read_immediate(&self.eval_operand(left, layout)?)?; - let layout = binop_right_homogeneous(bin_op).then_some(left.layout); + let layout = util::binop_right_homogeneous(bin_op).then_some(left.layout); let right = self.read_immediate(&self.eval_operand(right, layout)?)?; self.binop_ignore_overflow(bin_op, &left, &right, &dest)?; } @@ -191,7 +169,7 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> { CheckedBinaryOp(bin_op, box (ref left, ref right)) => { // Due to the extra boolean in the result, we can never reuse the `dest.layout`. let left = self.read_immediate(&self.eval_operand(left, None)?)?; - let layout = binop_right_homogeneous(bin_op).then_some(left.layout); + let layout = util::binop_right_homogeneous(bin_op).then_some(left.layout); let right = self.read_immediate(&self.eval_operand(right, layout)?)?; self.binop_with_overflow(bin_op, &left, &right, &dest)?; } diff --git a/compiler/rustc_const_eval/src/transform/validate.rs b/compiler/rustc_const_eval/src/transform/validate.rs index d421c7a2755ea..f197541da5bea 100644 --- a/compiler/rustc_const_eval/src/transform/validate.rs +++ b/compiler/rustc_const_eval/src/transform/validate.rs @@ -498,8 +498,8 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { fn visit_rvalue(&mut self, rvalue: &Rvalue<'tcx>, location: Location) { macro_rules! check_kinds { - ($t:expr, $text:literal, $($patterns:tt)*) => { - if !matches!(($t).kind(), $($patterns)*) { + ($t:expr, $text:literal, $typat:pat) => { + if !matches!(($t).kind(), $typat) { self.fail(location, format!($text, $t)); } }; @@ -527,6 +527,25 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { use BinOp::*; let a = vals.0.ty(&self.body.local_decls, self.tcx); let b = vals.1.ty(&self.body.local_decls, self.tcx); + if crate::util::binop_right_homogeneous(*op) { + if let Eq | Lt | Le | Ne | Ge | Gt = op { + // The function pointer types can have lifetimes + if !self.mir_assign_valid_types(a, b) { + self.fail( + location, + format!("Cannot {op:?} compare incompatible types {a:?} and {b:?}"), + ); + } + } else if a != b { + self.fail( + location, + format!( + "Cannot perform binary op {op:?} on unequal types {a:?} and {b:?}" + ), + ); + } + } + match op { Offset => { check_kinds!(a, "Cannot offset non-pointer type {:?}", ty::RawPtr(..)); @@ -538,7 +557,7 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { for x in [a, b] { check_kinds!( x, - "Cannot compare type {:?}", + "Cannot {op:?} compare type {:?}", ty::Bool | ty::Char | ty::Int(..) @@ -548,19 +567,13 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { | ty::FnPtr(..) ) } - // The function pointer types can have lifetimes - if !self.mir_assign_valid_types(a, b) { - self.fail( - location, - format!("Cannot compare unequal types {:?} and {:?}", a, b), - ); - } } - Shl | ShlUnchecked | Shr | ShrUnchecked => { + AddUnchecked | SubUnchecked | MulUnchecked | Shl | ShlUnchecked | Shr + | ShrUnchecked => { for x in [a, b] { check_kinds!( x, - "Cannot shift non-integer type {:?}", + "Cannot {op:?} non-integer type {:?}", ty::Uint(..) | ty::Int(..) ) } @@ -569,55 +582,19 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { for x in [a, b] { check_kinds!( x, - "Cannot perform bitwise op on type {:?}", + "Cannot perform bitwise op {op:?} on type {:?}", ty::Uint(..) | ty::Int(..) | ty::Bool ) } - if a != b { - self.fail( - location, - format!( - "Cannot perform bitwise op on unequal types {:?} and {:?}", - a, b - ), - ); - } } Add | Sub | Mul | Div | Rem => { for x in [a, b] { check_kinds!( x, - "Cannot perform arithmetic on type {:?}", + "Cannot perform arithmetic {op:?} on type {:?}", ty::Uint(..) | ty::Int(..) | ty::Float(..) ) } - if a != b { - self.fail( - location, - format!( - "Cannot perform arithmetic on unequal types {:?} and {:?}", - a, b - ), - ); - } - } - AddUnchecked | SubUnchecked | MulUnchecked => { - for x in [a, b] { - check_kinds!( - x, - "Cannot perform unchecked arithmetic on type {:?}", - ty::Uint(..) | ty::Int(..) - ) - } - if a != b { - self.fail( - location, - format!( - "Cannot perform unchecked arithmetic on unequal types {:?} and {:?}", - a, b - ), - ); - } } } } diff --git a/compiler/rustc_const_eval/src/util/mod.rs b/compiler/rustc_const_eval/src/util/mod.rs index 7641f560714d4..289e342259547 100644 --- a/compiler/rustc_const_eval/src/util/mod.rs +++ b/compiler/rustc_const_eval/src/util/mod.rs @@ -1,3 +1,5 @@ +use rustc_middle::mir; + mod alignment; mod check_validity_requirement; mod compare_types; @@ -7,3 +9,27 @@ pub use self::alignment::is_disaligned; pub use self::check_validity_requirement::check_validity_requirement; pub use self::compare_types::{is_equal_up_to_subtyping, is_subtype}; pub use self::type_name::type_name; + +/// Classify whether an operator is "left-homogeneous", i.e., the LHS has the +/// same type as the result. +#[inline] +pub(crate) fn binop_left_homogeneous(op: mir::BinOp) -> bool { + use rustc_middle::mir::BinOp::*; + match op { + Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor + | BitAnd | BitOr | Offset | Shl | ShlUnchecked | Shr | ShrUnchecked => true, + Eq | Ne | Lt | Le | Gt | Ge => false, + } +} + +/// Classify whether an operator is "right-homogeneous", i.e., the RHS has the +/// same type as the LHS. +#[inline] +pub(crate) fn binop_right_homogeneous(op: mir::BinOp) -> bool { + use rustc_middle::mir::BinOp::*; + match op { + Add | AddUnchecked | Sub | SubUnchecked | Mul | MulUnchecked | Div | Rem | BitXor + | BitAnd | BitOr | Eq | Ne | Lt | Le | Gt | Ge => true, + Offset | Shl | ShlUnchecked | Shr | ShrUnchecked => false, + } +}