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LLVM 12 regression (GlobalISel): AArch64 backend generates incorrect code for ashr <i8 x 16> #84028

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Amanieu opened this issue Apr 9, 2021 · 0 comments · Fixed by #84051
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LLVM 12 regression (GlobalISel): AArch64 backend generates incorrect code for ashr <i8 x 16> #84028

Amanieu opened this issue Apr 9, 2021 · 0 comments · Fixed by #84051
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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-simd Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. I-unsound Issue: A soundness hole (worst kind of bug), see: https://en.wikipedia.org/wiki/Soundness O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state

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@Amanieu
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Amanieu commented Apr 9, 2021

This is causing test failures in stdarch (rust-lang/stdarch#1111).

Upstream LLVM bug: https://bugs.llvm.org/show_bug.cgi?id=49904
@jonas-schievink jonas-schievink added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-simd Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. I-unsound Issue: A soundness hole (worst kind of bug), see: https://en.wikipedia.org/wiki/Soundness O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state labels Apr 9, 2021
@rustbot rustbot added the I-prioritize Issue: Indicates that prioritization has been requested for this issue. label Apr 9, 2021
@Amanieu Amanieu mentioned this issue Apr 10, 2021
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@bors bors closed this as completed in 18c524f Apr 10, 2021
@apiraino apiraino removed the I-prioritize Issue: Indicates that prioritization has been requested for this issue. label Jan 6, 2023
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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-simd Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. I-unsound Issue: A soundness hole (worst kind of bug), see: https://en.wikipedia.org/wiki/Soundness O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state
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Update LLVM submodule Amanieu/rust
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@Amanieu @jonas-schievink @apiraino @rustbot