From dd8dc65149c0f641efadb4a6808d99882b33522e Mon Sep 17 00:00:00 2001 From: "rongfu.leng" Date: Thu, 6 Jun 2024 20:53:40 +0800 Subject: [PATCH] Enable f16 in assembly on aarch64 platforms that support it Signed-off-by: rongfu.leng --- compiler/rustc_target/src/asm/aarch64.rs | 4 ++-- library/backtrace | 2 +- src/doc/book | 2 +- src/doc/edition-guide | 2 +- src/doc/reference | 2 +- src/doc/rust-by-example | 2 +- src/tools/cargo | 2 +- tests/ui/asm/aarch64/type-check-3.stderr | 2 +- tests/ui/asm/aarch64/type-f16.rs | 21 +++++++++++++++++++++ 9 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 tests/ui/asm/aarch64/type-f16.rs diff --git a/compiler/rustc_target/src/asm/aarch64.rs b/compiler/rustc_target/src/asm/aarch64.rs index 1a3218da1af04..c1061c7a2ce64 100644 --- a/compiler/rustc_target/src/asm/aarch64.rs +++ b/compiler/rustc_target/src/asm/aarch64.rs @@ -59,9 +59,9 @@ impl AArch64InlineAsmRegClass { match self { Self::reg => types! { _: I8, I16, I32, I64, F32, F64; }, Self::vreg | Self::vreg_low16 => types! { - neon: I8, I16, I32, I64, F32, F64, + neon: I8, I16, I32, I64, F16, F32, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2), VecF64(1), - VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2); + VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF16(4),VecF16(8),VecF32(4), VecF64(2); }, Self::preg => &[], } diff --git a/library/backtrace b/library/backtrace index 72265bea21089..5e05efa87905f 160000 --- a/library/backtrace +++ b/library/backtrace @@ -1 +1 @@ -Subproject commit 72265bea210891ae47bbe6d4f17b493ef0606619 +Subproject commit 5e05efa87905fb5b351a2bc5644d60c57d6d9327 diff --git a/src/doc/book b/src/doc/book index 45c1a6d69edfd..5228bfac8267a 160000 --- a/src/doc/book +++ b/src/doc/book @@ -1 +1 @@ -Subproject commit 45c1a6d69edfd1fc91fb7504cb73958dbd09441e +Subproject commit 5228bfac8267ad24659a81b92ec5417976b5edbc diff --git a/src/doc/edition-guide b/src/doc/edition-guide index cb58c430b4e80..bbaabbe088e21 160000 --- a/src/doc/edition-guide +++ b/src/doc/edition-guide @@ -1 +1 @@ -Subproject commit cb58c430b4e8054c2cb81d2d4434092c482a93d8 +Subproject commit bbaabbe088e21a81a0d9ae6757705020d5d7b416 diff --git a/src/doc/reference b/src/doc/reference index 0b805c6580401..6019b76f5b289 160000 --- a/src/doc/reference +++ b/src/doc/reference @@ -1 +1 @@ -Subproject commit 0b805c65804019b0ac8f2fe3117afad82a6069b8 +Subproject commit 6019b76f5b28938565b251bbba0bf5cc5c43d863 diff --git a/src/doc/rust-by-example b/src/doc/rust-by-example index b1d97bd6113ab..4840dca06cadf 160000 --- a/src/doc/rust-by-example +++ b/src/doc/rust-by-example @@ -1 +1 @@ -Subproject commit b1d97bd6113aba732b2091ce093c76f2d05bb8a0 +Subproject commit 4840dca06cadf48b305d3ce0aeafde7f80933f80 diff --git a/src/tools/cargo b/src/tools/cargo index 4ed7bee47f7dd..34a6a87d8a233 160000 --- a/src/tools/cargo +++ b/src/tools/cargo @@ -1 +1 @@ -Subproject commit 4ed7bee47f7dd4416b36fada1909e9a62c546246 +Subproject commit 34a6a87d8a2330d8c9d578f927489689328a652d diff --git a/tests/ui/asm/aarch64/type-check-3.stderr b/tests/ui/asm/aarch64/type-check-3.stderr index 9e37bb4c203f5..60a60b65cb93d 100644 --- a/tests/ui/asm/aarch64/type-check-3.stderr +++ b/tests/ui/asm/aarch64/type-check-3.stderr @@ -111,7 +111,7 @@ error: type `Simd256bit` cannot be used with this register class LL | asm!("{}", in(vreg) f64x4); | ^^^^^ | - = note: register class `vreg` supports these types: i8, i16, i32, i64, f32, f64, i8x8, i16x4, i32x2, i64x1, f32x2, f64x1, i8x16, i16x8, i32x4, i64x2, f32x4, f64x2 + = note: register class `vreg` supports these types: i8, i16, i32, i64, f16, f32, f64, i8x8, i16x4, i32x2, i64x1, f32x2, f64x1, i8x16, i16x8, i32x4, i64x2, f16x4, f16x8, f32x4, f64x2 error: incompatible types for asm inout argument --> $DIR/type-check-3.rs:88:33 diff --git a/tests/ui/asm/aarch64/type-f16.rs b/tests/ui/asm/aarch64/type-f16.rs new file mode 100644 index 0000000000000..763ea4684da37 --- /dev/null +++ b/tests/ui/asm/aarch64/type-f16.rs @@ -0,0 +1,21 @@ +//@ only-aarch64 +//@ run-pass + +#![feature(f16, f128)] +use std::arch::asm; +#[inline(never)] +pub fn f32_to_f16_asm(a: f32) -> f16 { + let ret: f16; + unsafe { + asm!( + "fcvt {ret:h}, {a:s}", + a = in(vreg) a, + ret = lateout(vreg) ret, + options(nomem, nostack), + ); + } + ret +} +fn main() { + assert_eq!(f32_to_f16_asm(1.0 as f32), 1.0); +}