From 275071e6b5091dbc2ece87381a0262654515603d Mon Sep 17 00:00:00 2001 From: gnzlbg Date: Thu, 4 Jan 2018 12:19:11 +0100 Subject: [PATCH] fmt and clippy --- coresimd/src/x86/i586/bswap.rs | 4 +++ coresimd/src/x86/i686/sse4a.rs | 4 +-- coresimd/src/x86/i686/ssse3.rs | 6 ++++- coresimd/src/x86/macros.rs | 10 ++++---- coresimd/src/x86/x86_64/sse41.rs | 2 ++ stdsimd-test/src/lib.rs | 38 ++++++++++++++++------------ stdsimd-verify/tests/x86-intel.rs | 41 +++++++++++++++---------------- 7 files changed, 60 insertions(+), 45 deletions(-) diff --git a/coresimd/src/x86/i586/bswap.rs b/coresimd/src/x86/i586/bswap.rs index 15cd0b1c47..8bac167569 100644 --- a/coresimd/src/x86/i586/bswap.rs +++ b/coresimd/src/x86/i586/bswap.rs @@ -1,3 +1,7 @@ +//! Byte swap intrinsics. + +#![cfg_attr(feature = "cargo-clippy", allow(stutter))] + #[cfg(test)] use stdsimd_test::assert_instr; diff --git a/coresimd/src/x86/i686/sse4a.rs b/coresimd/src/x86/i686/sse4a.rs index 9c47617ff6..884097e871 100644 --- a/coresimd/src/x86/i686/sse4a.rs +++ b/coresimd/src/x86/i686/sse4a.rs @@ -1,4 +1,4 @@ -//! `i686`'s Streaming SIMD Extensions 4a (SSE4a) +//! `i686`'s Streaming SIMD Extensions 4a (`SSE4a`) use core::mem; use v128::*; @@ -52,7 +52,7 @@ pub unsafe fn _mm_extract_si64(x: i64x2, y: i64x2) -> i64x2 { #[target_feature = "+sse4a"] #[cfg_attr(test, assert_instr(insertq))] pub unsafe fn _mm_insert_si64(x: i64x2, y: i64x2) -> i64x2 { - insertq(x, mem::transmute(y)) + insertq(x, y) } /// Non-temporal store of `a.0` into `p`. diff --git a/coresimd/src/x86/i686/ssse3.rs b/coresimd/src/x86/i686/ssse3.rs index bf31cbb647..965973598e 100644 --- a/coresimd/src/x86/i686/ssse3.rs +++ b/coresimd/src/x86/i686/ssse3.rs @@ -256,7 +256,11 @@ mod tests { unsafe fn _mm_alignr_pi8() { let a = u32x2::new(0x89ABCDEF_u32, 0x01234567_u32); let b = u32x2::new(0xBBAA9988_u32, 0xFFDDEECC_u32); - let r = ssse3::_mm_alignr_pi8(u8x8::from(a).into(), u8x8::from(b).into(), 4); + let r = ssse3::_mm_alignr_pi8( + u8x8::from(a).into(), + u8x8::from(b).into(), + 4, + ); assert_eq!(r, ::std::mem::transmute(0x89abcdefffddeecc_u64)); } diff --git a/coresimd/src/x86/macros.rs b/coresimd/src/x86/macros.rs index 79109fd67c..ea72c062e8 100644 --- a/coresimd/src/x86/macros.rs +++ b/coresimd/src/x86/macros.rs @@ -3,7 +3,7 @@ macro_rules! constify_imm8 { ($imm8:expr, $expand:ident) => { #[allow(overflowing_literals)] - match $imm8 & 0b1111_1111 { + match ($imm8) & 0b1111_1111 { 0 => $expand!(0), 1 => $expand!(1), 2 => $expand!(2), @@ -267,7 +267,7 @@ macro_rules! constify_imm8 { macro_rules! constify_imm6 { ($imm8:expr, $expand:ident) => { #[allow(overflowing_literals)] - match $imm8 & 0b1_1111 { + match ($imm8) & 0b1_1111 { 0 => $expand!(0), 1 => $expand!(1), 2 => $expand!(2), @@ -307,7 +307,7 @@ macro_rules! constify_imm6 { macro_rules! constify_imm4 { ($imm8:expr, $expand:ident) => { #[allow(overflowing_literals)] - match $imm8 & 0b1111 { + match ($imm8) & 0b1111 { 0 => $expand!(0), 1 => $expand!(1), 2 => $expand!(2), @@ -331,7 +331,7 @@ macro_rules! constify_imm4 { macro_rules! constify_imm3 { ($imm8:expr, $expand:ident) => { #[allow(overflowing_literals)] - match $imm8 & 0b111 { + match ($imm8) & 0b111 { 0 => $expand!(0), 1 => $expand!(1), 2 => $expand!(2), @@ -347,7 +347,7 @@ macro_rules! constify_imm3 { macro_rules! constify_imm2 { ($imm8:expr, $expand:ident) => { #[allow(overflowing_literals)] - match $imm8 & 0b11 { + match ($imm8) & 0b11 { 0 => $expand!(0), 1 => $expand!(1), 2 => $expand!(2), diff --git a/coresimd/src/x86/x86_64/sse41.rs b/coresimd/src/x86/x86_64/sse41.rs index b2417a8e59..20fa606d5f 100644 --- a/coresimd/src/x86/x86_64/sse41.rs +++ b/coresimd/src/x86/x86_64/sse41.rs @@ -1,3 +1,5 @@ +//! `i686`'s Streaming SIMD Extensions 4.1 (SSE4.1) + use v128::*; #[cfg(test)] diff --git a/stdsimd-test/src/lib.rs b/stdsimd-test/src/lib.rs index d41bec2564..1ec3d96920 100644 --- a/stdsimd-test/src/lib.rs +++ b/stdsimd-test/src/lib.rs @@ -304,19 +304,20 @@ pub fn assert(fnptr: usize, fnname: &str, expected: &str) { None => continue, }; if !part.contains("call") { - continue + continue; } // On 32-bit x86 position independent code will call itself and be // immediately followed by a `pop` to learn about the current address. // Let's not take that into account when considering whether a function // failed inlining something. - let followed_by_pop = function.instrs.get(i + 1) + let followed_by_pop = function + .instrs + .get(i + 1) .and_then(|i| i.parts.get(0)) - .map(|s| s.contains("pop")) - .unwrap_or(false); + .map_or(false, |s| s.contains("pop")); if followed_by_pop && cfg!(target_arch = "x86") { - continue + continue; } inlining_failed = true; @@ -324,14 +325,14 @@ pub fn assert(fnptr: usize, fnname: &str, expected: &str) { } let instruction_limit = match expected { - // cpuid returns a pretty big aggregate structure so excempt it from the - // slightly more restrictive 20 instructions below + // cpuid returns a pretty big aggregate structure so excempt it from + // the slightly more restrictive 20 instructions below "cpuid" => 30, - // Apparently on Windows LLVM generates a bunch of saves/restores of xmm - // registers around these intstructions which blows the 20 limit - // below. As it seems dictates by Windows's abi (I guess?) we probably - // can't do much about it... + // Apparently on Windows LLVM generates a bunch of saves/restores of + // xmm registers around these intstructions which blows the 20 + // limit below. As it seems dictates by Windows's abi (I + // guess?) we probably can't do much about it... "vzeroall" | "vzeroupper" if cfg!(windows) => 30, _ => 20, @@ -363,12 +364,17 @@ pub fn assert(fnptr: usize, fnname: &str, expected: &str) { expected ); } else if !probably_only_one_instruction { - panic!("instruction found, but the disassembly contains too many \ - instructions: #instructions = {} >= {} (limit)", - function.instrs.len(), instruction_limit); + panic!( + "instruction found, but the disassembly contains too many \ + instructions: #instructions = {} >= {} (limit)", + function.instrs.len(), + instruction_limit + ); } else if inlining_failed { - panic!("instruction found, but the disassembly contains `call` \ - instructions, which hint that inlining failed"); + panic!( + "instruction found, but the disassembly contains `call` \ + instructions, which hint that inlining failed" + ); } } diff --git a/stdsimd-verify/tests/x86-intel.rs b/stdsimd-verify/tests/x86-intel.rs index ce425bdd6a..87c1a1fc87 100644 --- a/stdsimd-verify/tests/x86-intel.rs +++ b/stdsimd-verify/tests/x86-intel.rs @@ -1,5 +1,7 @@ #![feature(proc_macro)] #![allow(bad_style)] +#![cfg_attr(feature = "cargo-clippy", + allow(shadow_reuse, cast_lossless, match_same_arms))] #[macro_use] extern crate serde_derive; @@ -111,7 +113,7 @@ fn verify_all_signatures() { let data: Data = serde_xml_rs::deserialize(xml).expect("failed to deserialize xml"); let mut map = HashMap::new(); - for intrinsic in data.intrinsics.iter() { + for intrinsic in &data.intrinsics { // This intrinsic has multiple definitions in the XML, so just ignore // it. if intrinsic.name == "_mm_prefetch" { @@ -148,8 +150,8 @@ fn verify_all_signatures() { // Verify that all `#[target_feature]` annotations are correct, // ensuring that we've actually enabled the right instruction // set for this intrinsic. - assert!(intel.cpuid.len() > 0, "missing cpuid for {}", rust.name); - for cpuid in intel.cpuid.iter() { + assert!(!intel.cpuid.is_empty(), "missing cpuid for {}", rust.name); + for cpuid in &intel.cpuid { // this is needed by _xsave and probably some related intrinsics, // but let's just skip it for now. if *cpuid == "XSS" { @@ -181,7 +183,7 @@ fn verify_all_signatures() { // TODO: we should test this, but it generates too many failures right // now if false { - if rust.instrs.len() == 0 { + if rust.instrs.is_empty() { assert_eq!( intel.instruction.len(), 0, @@ -192,8 +194,8 @@ fn verify_all_signatures() { // If intel doesn't list any instructions and we do then don't // bother trying to look for instructions in intel, we've just got // some extra assertions on our end. - } else if intel.instruction.len() > 0 { - for instr in rust.instrs.iter() { + } else if !intel.instruction.is_empty() { + for instr in rust.instrs { assert!( intel .instruction @@ -208,25 +210,22 @@ fn verify_all_signatures() { } // Make sure we've got the right return type. - match rust.ret { - Some(t) => equate(t, &intel.rettype, &rust.name), - None => { - assert!( - intel.rettype == "" || intel.rettype == "void", - "{} returns `{}` with intel, void in rust", - rust.name, - intel.rettype - ); - } + if let Some(t) = rust.ret { + equate(t, &intel.rettype, rust.name); + } else { + assert!( + intel.rettype == "" || intel.rettype == "void", + "{} returns `{}` with intel, void in rust", + rust.name, + intel.rettype + ); } // If there's no arguments on Rust's side intel may list one "void" // argument, so handle that here. - if rust.arguments.len() == 0 { - if intel.parameters.len() == 1 { - assert_eq!(intel.parameters[0].type_, "void"); - continue; - } + if rust.arguments.is_empty() && intel.parameters.len() == 1 { + assert_eq!(intel.parameters[0].type_, "void"); + continue; } // Otherwise we want all parameters to be exactly the same