diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv.td b/clang/include/clang/Basic/riscv_vector_xtheadv.td index f69692bc5821f..09b0fe6366d38 100644 --- a/clang/include/clang/Basic/riscv_vector_xtheadv.td +++ b/clang/include/clang/Basic/riscv_vector_xtheadv.td @@ -99,7 +99,7 @@ void __riscv_vwrite_csr(enum RVV_CSR __csr, unsigned long __value) { } } }] in -def xvread_xvwrite_csr: RVVHeader; +def th_vread_th_vwrite_csr: RVVHeader; // vsetvl/vsetvlmax are a macro because they require constant integers in SEW // and LMUL. @@ -108,55 +108,55 @@ let HeaderCode = /* These two builtins comes from the 1.0 implementation, */ /* for compatibility, we forward these calls to the corresponding 0.7 builtins. */ -#define __builtin_rvv_vsetvli(avl, sew, lmul) __builtin_rvv_xvsetvl((size_t)(avl), sew, lmul) -#define __builtin_rvv_vsetvlimax(sew, lmul) __builtin_rvv_xvsetvlmax(sew, lmul) +#define __builtin_rvv_vsetvli(avl, sew, lmul) __builtin_rvv_th_vsetvl((size_t)(avl), sew, lmul) +#define __builtin_rvv_vsetvlimax(sew, lmul) __builtin_rvv_th_vsetvlmax(sew, lmul) -#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 0) -#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 1) -#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 2) -#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 3) +#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 0) +#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 1) +#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 2) +#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 3) -#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 0) -#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 1) -#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 2) -#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 3) +#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 0) +#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 1) +#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 2) +#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 3) -#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 0) -#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 1) -#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 2) -#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 3) +#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 0) +#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 1) +#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 2) +#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 3) #if __riscv_v_elen >= 64 -#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 0) -#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 1) -#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 2) -#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 3) +#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 0) +#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 1) +#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 2) +#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 3) #endif -#define __riscv_vsetvlmax_e8m1() __builtin_rvv_xvsetvlmax(0, 0) -#define __riscv_vsetvlmax_e8m2() __builtin_rvv_xvsetvlmax(0, 1) -#define __riscv_vsetvlmax_e8m4() __builtin_rvv_xvsetvlmax(0, 2) -#define __riscv_vsetvlmax_e8m8() __builtin_rvv_xvsetvlmax(0, 3) +#define __riscv_vsetvlmax_e8m1() __builtin_rvv_th_vsetvlmax(0, 0) +#define __riscv_vsetvlmax_e8m2() __builtin_rvv_th_vsetvlmax(0, 1) +#define __riscv_vsetvlmax_e8m4() __builtin_rvv_th_vsetvlmax(0, 2) +#define __riscv_vsetvlmax_e8m8() __builtin_rvv_th_vsetvlmax(0, 3) -#define __riscv_vsetvlmax_e16m1() __builtin_rvv_xvsetvlmax(1, 0) -#define __riscv_vsetvlmax_e16m2() __builtin_rvv_xvsetvlmax(1, 1) -#define __riscv_vsetvlmax_e16m4() __builtin_rvv_xvsetvlmax(1, 2) -#define __riscv_vsetvlmax_e16m8() __builtin_rvv_xvsetvlmax(1, 3) +#define __riscv_vsetvlmax_e16m1() __builtin_rvv_th_vsetvlmax(1, 0) +#define __riscv_vsetvlmax_e16m2() __builtin_rvv_th_vsetvlmax(1, 1) +#define __riscv_vsetvlmax_e16m4() __builtin_rvv_th_vsetvlmax(1, 2) +#define __riscv_vsetvlmax_e16m8() __builtin_rvv_th_vsetvlmax(1, 3) -#define __riscv_vsetvlmax_e32m1() __builtin_rvv_xvsetvlmax(2, 0) -#define __riscv_vsetvlmax_e32m2() __builtin_rvv_xvsetvlmax(2, 1) -#define __riscv_vsetvlmax_e32m4() __builtin_rvv_xvsetvlmax(2, 2) -#define __riscv_vsetvlmax_e32m8() __builtin_rvv_xvsetvlmax(2, 3) +#define __riscv_vsetvlmax_e32m1() __builtin_rvv_th_vsetvlmax(2, 0) +#define __riscv_vsetvlmax_e32m2() __builtin_rvv_th_vsetvlmax(2, 1) +#define __riscv_vsetvlmax_e32m4() __builtin_rvv_th_vsetvlmax(2, 2) +#define __riscv_vsetvlmax_e32m8() __builtin_rvv_th_vsetvlmax(2, 3) #if __riscv_v_elen >= 64 -#define __riscv_vsetvlmax_e64m1() __builtin_rvv_xvsetvlmax(3, 0) -#define __riscv_vsetvlmax_e64m2() __builtin_rvv_xvsetvlmax(3, 1) -#define __riscv_vsetvlmax_e64m4() __builtin_rvv_xvsetvlmax(3, 2) -#define __riscv_vsetvlmax_e64m8() __builtin_rvv_xvsetvlmax(3, 3) +#define __riscv_vsetvlmax_e64m1() __builtin_rvv_th_vsetvlmax(3, 0) +#define __riscv_vsetvlmax_e64m2() __builtin_rvv_th_vsetvlmax(3, 1) +#define __riscv_vsetvlmax_e64m4() __builtin_rvv_th_vsetvlmax(3, 2) +#define __riscv_vsetvlmax_e64m8() __builtin_rvv_th_vsetvlmax(3, 3) #endif }] in -def xvsetvl_macro: RVVHeader; +def th_vsetvl_macro: RVVHeader; let HasBuiltinAlias = false, HasVL = false, @@ -165,8 +165,8 @@ let HasBuiltinAlias = false, Log2LMUL = [0], ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type { - def xvsetvl : RVVBuiltin<"", "zzKzKz", "i">; - def xvsetvlmax : RVVBuiltin<"", "zKzKz", "i">; + def th_vsetvl : RVVBuiltin<"", "zzKzKz", "i">; + def th_vsetvlmax : RVVBuiltin<"", "zKzKz", "i">; } //===----------------------------------------------------------------------===// @@ -174,5 +174,5 @@ let HasBuiltinAlias = false, //===----------------------------------------------------------------------===// let UnMaskedPolicyScheme = HasPassthruOperand in { - defm xvadd : RVVIntBinBuiltinSet; + defm th_vadd : RVVIntBinBuiltinSet; } diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 8398eeef2cbd7..02810930aabf7 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -200,12 +200,9 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 11))); } - if (ISAInfo->hasExtension("xtheadv")) { - // TODO: should we define __riscv_vector here? - Builder.defineMacro("__riscv_vector"); - Builder.defineMacro("__riscv_vector_xtheadv"); - // TODO: which intrinsic version? reuse the v0.11 for now. - Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 11))); + if (ISAInfo->hasExtension("xtheadvector")) { + // https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/298/files + Builder.defineMacro("__riscv_th_v_intrinsic", Twine(getVersionValue(0, 11))); } auto VScale = getVScaleRange(Opts); diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index 2f7a5b4c3ed26..d378ef1033c14 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -385,12 +385,12 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST LLVM_TARGETS_TO_BUILD) ) endif() if(RISCV IN_LIST LLVM_TARGETS_TO_BUILD) - # Generate riscv_vector.h and riscv_vector_xtheadv.h + # Generate riscv_vector.h and riscv_th_vector.h clang_generate_header(-gen-riscv-vector-header riscv_vector.td riscv_vector.h) - clang_generate_header(-gen-riscv-xtheadv-header riscv_vector_xtheadv.td riscv_vector_xtheadv.h) + clang_generate_header(-gen-riscv-xtheadv-header riscv_vector_xtheadv.td riscv_th_vector.h) list(APPEND riscv_generated_files "${CMAKE_CURRENT_BINARY_DIR}/riscv_vector.h" - "${CMAKE_CURRENT_BINARY_DIR}/riscv_vector_xtheadv.h" + "${CMAKE_CURRENT_BINARY_DIR}/riscv_th_vector.h" ) endif() diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp index 6c6b7d8bb7ce8..a8a4cb797d6f7 100644 --- a/clang/lib/Parse/ParsePragma.cpp +++ b/clang/lib/Parse/ParsePragma.cpp @@ -4027,7 +4027,7 @@ void PragmaMaxTokensTotalHandler::HandlePragma(Preprocessor &PP, // Handle '#pragma clang riscv intrinsic vector'. // '#pragma clang riscv intrinsic sifive_vector' -// '#pragma clang riscv intrinsic xtheadv_vector'. +// '#pragma clang riscv intrinsic thead_vector'. void PragmaRISCVHandler::HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer, Token &FirstToken) { @@ -4044,10 +4044,10 @@ void PragmaRISCVHandler::HandlePragma(Preprocessor &PP, PP.Lex(Tok); II = Tok.getIdentifierInfo(); if (!II || !(II->isStr("vector") || II->isStr("sifive_vector") || - II->isStr("xtheadv_vector"))) { + II->isStr("thead_vector"))) { PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument) << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true - << "'vector', 'sifive_vector' or 'xtheadv_vector'"; + << "'vector', 'sifive_vector' or 'thead_vector'"; return; } @@ -4062,6 +4062,6 @@ void PragmaRISCVHandler::HandlePragma(Preprocessor &PP, Actions.DeclareRISCVVBuiltins = true; else if (II->isStr("sifive_vector")) Actions.DeclareRISCVSiFiveVectorBuiltins = true; - else if (II->isStr("xtheadv_vector")) + else if (II->isStr("thead_vector")) Actions.DeclareRISCVXTHeadVBuiltins = true; } diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 90ef18b622c57..47ced9d90ff7d 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4608,10 +4608,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vsetvlimax: return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || CheckRISCVLMUL(TheCall, 1, true); - case RISCVVector::BI__builtin_rvv_xvsetvl: + case RISCVVector::BI__builtin_rvv_th_vsetvl: return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3) || CheckRISCVLMUL(TheCall, 2, false); - case RISCVVector::BI__builtin_rvv_xvsetvlmax: + case RISCVVector::BI__builtin_rvv_th_vsetvlmax: return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || CheckRISCVLMUL(TheCall, 1, false); case RISCVVector::BI__builtin_rvv_vget_v: { @@ -5419,20 +5419,20 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) || Ty->isRVVType(/* ElementCount */ 1)) && (!TI.hasFeature("zve64x") && - !TI.hasFeature("xtheadv"))) + !TI.hasFeature("xtheadvector"))) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x"; if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) && - (!TI.hasFeature("zvfh") && !TI.hasFeature("xtheadv"))) + (!TI.hasFeature("zvfh") && !TI.hasFeature("xtheadvector"))) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfh"; if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) && - (!TI.hasFeature("zve32f") && !TI.hasFeature("xtheadv"))) + (!TI.hasFeature("zve32f") && !TI.hasFeature("xtheadvector"))) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f"; if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ true) && - (!TI.hasFeature("zve64d") && !TI.hasFeature("xtheadv"))) + (!TI.hasFeature("zve64d") && !TI.hasFeature("xtheadvector"))) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d"; // Given that caller already checked isRVVType() before calling this function, // if we don't have at least zve32x supported, then we need to emit error. - if (!TI.hasFeature("zve32x") && !TI.hasFeature("xtheadv")) + if (!TI.hasFeature("zve32x") && !TI.hasFeature("xtheadvector")) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32x"; } diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-error.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-error.c index 089aae9b784eb..4a822f3da066a 100644 --- a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-error.c +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-error.c @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadv -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64V %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64V %s // RUN: not %clang_cc1 -triple riscv64 -emit-llvm-only %s 2>&1 | FileCheck %s --check-prefix=CHECK-RV64-ERR // CHECK-RV64V-LABEL: @test( // CHECK-RV64V-NEXT: entry: -// CHECK-RV64V-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xvsetvl.i64(i64 1, i64 0, i64 0) +// CHECK-RV64V-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.th.vsetvl.i64(i64 1, i64 0, i64 0) // CHECK-RV64V-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK-RV64V-NEXT: ret i32 [[CONV]] // -// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions to be enabled: 'Xtheadv' +// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions to be enabled: 'Xtheadvector' -#include +#include int test() { return __builtin_rvv_vsetvli(1, 0, 0); // e8m1 diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-errors.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-errors.c index ead13497bc871..eb8f8a15b4a81 100644 --- a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-errors.c +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-errors.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +xtheadv -fsyntax-only -verify +// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +xtheadvector -fsyntax-only -verify #include diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp index b041567642eb3..ed932e2a8ee12 100644 --- a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadv \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ // RUN: -O0 -emit-llvm %s -o - | FileCheck %s #include -// This test case tests the typedef generated under riscv_vector_xtheadv.h +// This test case tests the typedef generated under riscv_th_vector.h // CHECK-LABEL: define dso_local void @_Z3foov // CHECK-SAME: () #[[ATTR0:[0-9]+]] { diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 9199c3d64f5ae..5b74ee1627d42 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -416,9 +416,9 @@ // RUN: FileCheck -check-prefix=RV32-V-GOODVERS %s // RV32-V-GOODVERS: "-target-feature" "+v" -// RUN: %clang --target=riscv32-unknown-elf -march=rv32i_xtheadv -### %s -c 2>&1 | \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32i_xtheadvector -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-V0P7-GOODVERS %s -// RV32-V0P7-GOODVERS: "-target-feature" "+xtheadv" +// RV32-V0P7-GOODVERS: "-target-feature" "+xtheadvector" // RUN: %clang --target=riscv32-unknown-elf -march=rv32iv1p0_zvl32b0p1 -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-ZVL-BADVERS %s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 3c62b9f740e37..f6b33c8813f4e 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -223,12 +223,13 @@ // CHECK-V-EXT: __riscv_vector 1 // RUN: %clang -target riscv32-unknown-linux-gnu \ -// RUN: -march=rv32i_xtheadv -x c -E -dM %s \ +// RUN: -march=rv32i_xtheadvector -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-V0P7-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu \ -// RUN: -march=rv64i_xtheadv -x c -E -dM %s \ +// RUN: -march=rv64i_xtheadvector -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-V0P7-EXT %s -// CHECK-V0P7-EXT: __riscv_xtheadv 7000{{$}} +// CHECK-V0P7-EXT: __riscv_th_v_intrinsic 11000{{$}} +// CHECK-V0P7-EXT: __riscv_xtheadvector 7000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu \ // RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \ diff --git a/clang/test/Sema/riscv-bad-intrinsic-pragma.c b/clang/test/Sema/riscv-bad-intrinsic-pragma.c index 76adc15eb884f..d4b2273b6a0bf 100644 --- a/clang/test/Sema/riscv-bad-intrinsic-pragma.c +++ b/clang/test/Sema/riscv-bad-intrinsic-pragma.c @@ -2,7 +2,7 @@ // RUN: 2>&1 | FileCheck %s #pragma clang riscv intrinsic vvvv -// CHECK: warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector', 'sifive_vector' or 'xtheadv_vector' [-Wignored-pragmas] +// CHECK: warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector', 'sifive_vector' or 'thead_vector' [-Wignored-pragmas] #pragma clang riscv what + 3241 // CHECK: warning: unexpected argument 'what' to '#pragma riscv'; expected 'intrinsic' [-Wignored-pragmas] diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 9af9c8250ded2..98717c40442dd 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -100,7 +100,7 @@ class RVVEmitter { public: RVVEmitter(RecordKeeper &R) : Records(R) {} - /// Emit riscv_vector.h or riscv_vector_xtheadv.h + /// Emit riscv_vector.h or riscv_th_vector.h void createHeader(raw_ostream &o, clang::RVVHeaderType Type); /// Emit all the __builtin prototypes and code needed by Sema. @@ -328,11 +328,12 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) { " */\n\n"; if (Type == clang::RVVHeaderType::RVV) { - // `__riscv_vector_xtheadv` is defined in `RISCVTargetInfo::getTargetDefines` - // If in `riscv_vector.h` we found that the xtheadv extension is required and enabled, - // we forward the include directive to the real header containing intrinsics for xtheadv. - OS << "#ifdef __riscv_vector_xtheadv\n"; - OS << "#include \n"; + // `__riscv_th_v_intrinsic` is defined in `RISCVTargetInfo::getTargetDefines` + // If in `riscv_vector.h` we found that the xtheadvector extension is required and enabled, + // we forward the include directive to the desired one. + // https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/298/files + OS << "#if defined (__riscv_xtheadvector) && defined (__riscv_th_v_intrinsic)\n"; + OS << "#include \n"; OS << "#else\n\n"; // Otherwise, we include the real header containing intrinsics for RVV 1.0 } @@ -348,10 +349,10 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) { OS << "#ifndef __riscv_vector\n"; break; case clang::RVVHeaderType::XTHEADV_VECTOR: - OS << "#ifndef __riscv_vector_xtheadv\n"; + OS << "#ifndef __riscv_xtheadvector\n"; break; } - OS << "#error \"Vector intrinsics require the vector extension.\"\n"; + OS << "#error \"Vector intrinsics require either Vector extension or XTheadVector extension.\"\n"; OS << "#endif\n\n"; OS << "#ifdef __cplusplus\n"; @@ -363,7 +364,7 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) { OS << "#pragma clang riscv intrinsic vector\n\n"; break; case clang::RVVHeaderType::XTHEADV_VECTOR: - OS << "#pragma clang riscv intrinsic xtheadv_vector\n\n"; + OS << "#pragma clang riscv intrinsic thead_vector\n\n"; break; } @@ -438,7 +439,7 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) { OS << "#endif // __RISCV_VECTOR_H\n"; if (Type == clang::RVVHeaderType::RVV) { - OS << "#endif // __riscv_vector_xtheadv\n\n"; + OS << "#endif // __riscv_xtheadvector\n\n"; } } @@ -452,7 +453,7 @@ void RVVEmitter::createBuiltins(raw_ostream &OS, clang::RVVHeaderType Type) { OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n"; OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, " "ATTRS, \"" - << (Type == clang::RVVHeaderType::RVV ? "zve32x" : "xtheadv") << "\")\n"; + << (Type == clang::RVVHeaderType::RVV ? "zve32x" : "xtheadvector") << "\")\n"; OS << "#endif\n"; for (auto &Def : Defs) { auto P = diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index 92e5257257bc6..f74a6fbdc6229 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -27,7 +27,7 @@ namespace clang { // Decide whether to emit header code // `#pragma clang riscv intrinsic vector` for RVV 1.0 (the `RVV`), // or -// `#pragma clang riscv intrinsic xtheadv_vector` for RVV 0.7.1 (the +// `#pragma clang riscv intrinsic thead_vector` for RVV 0.7.1 (the // `XTHEADV_VECTOR`). enum RVVHeaderType : uint8_t { RVV, XTHEADV_VECTOR }; diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td index 2afacf7eaf0bf..f0ab47071edf8 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td @@ -17,23 +17,23 @@ let TargetPrefix = "riscv" in { // 6. Configuration-Setting and Utility - def int_riscv_xvsetvl : Intrinsic<[llvm_anyint_ty], - [/* AVL */ LLVMMatchType<0>, - /* SEW */ LLVMMatchType<0>, - /* LMUL */ LLVMMatchType<0> - ], - [IntrNoMem, - ImmArg>, - ImmArg> - ]>; - def int_riscv_xvsetvlmax : Intrinsic<[llvm_anyint_ty], - [/* SEW */ LLVMMatchType<0>, - /* LMUL */ LLVMMatchType<0> - ], - [IntrNoMem, - ImmArg>, - ImmArg> - ]>; + def int_riscv_th_vsetvl : Intrinsic<[llvm_anyint_ty], + [/* AVL */ LLVMMatchType<0>, + /* SEW */ LLVMMatchType<0>, + /* LMUL */ LLVMMatchType<0> + ], + [IntrNoMem, + ImmArg>, + ImmArg> + ]>; + def int_riscv_th_vsetvlmax : Intrinsic<[llvm_anyint_ty], + [/* SEW */ LLVMMatchType<0>, + /* LMUL */ LLVMMatchType<0> + ], + [IntrNoMem, + ImmArg>, + ImmArg> + ]>; } // TargetPrefix = "riscv" let TargetPrefix = "riscv" in { @@ -84,29 +84,29 @@ let TargetPrefix = "riscv" in { // We define vlx (e.g. vlb), vlxu (e.g. vlbu) and vle // seperately here because otherwise we cannot distinguish // which intrinsic the user actually calls when lowering pseudos. - def int_riscv_xvlb : XVUSLoad; - def int_riscv_xvlh : XVUSLoad; - def int_riscv_xvlw : XVUSLoad; - def int_riscv_xvle : XVUSLoad; - def int_riscv_xvlbu : XVUSLoad; - def int_riscv_xvlhu : XVUSLoad; - def int_riscv_xvlwu : XVUSLoad; - def int_riscv_xvlb_mask : XVUSLoadMasked; - def int_riscv_xvlh_mask : XVUSLoadMasked; - def int_riscv_xvlw_mask : XVUSLoadMasked; - def int_riscv_xvle_mask : XVUSLoadMasked; - def int_riscv_xvlbu_mask : XVUSLoadMasked; - def int_riscv_xvlhu_mask : XVUSLoadMasked; - def int_riscv_xvlwu_mask : XVUSLoadMasked; + def int_riscv_th_vlb : XVUSLoad; + def int_riscv_th_vlh : XVUSLoad; + def int_riscv_th_vlw : XVUSLoad; + def int_riscv_th_vle : XVUSLoad; + def int_riscv_th_vlbu : XVUSLoad; + def int_riscv_th_vlhu : XVUSLoad; + def int_riscv_th_vlwu : XVUSLoad; + def int_riscv_th_vlb_mask : XVUSLoadMasked; + def int_riscv_th_vlh_mask : XVUSLoadMasked; + def int_riscv_th_vlw_mask : XVUSLoadMasked; + def int_riscv_th_vle_mask : XVUSLoadMasked; + def int_riscv_th_vlbu_mask : XVUSLoadMasked; + def int_riscv_th_vlhu_mask : XVUSLoadMasked; + def int_riscv_th_vlwu_mask : XVUSLoadMasked; - def int_riscv_xvsb : XVUSStore; - def int_riscv_xvsh : XVUSStore; - def int_riscv_xvsw : XVUSStore; - def int_riscv_xvse : XVUSStore; - def int_riscv_xvsb_mask : XVUSStoreMasked; - def int_riscv_xvsh_mask : XVUSStoreMasked; - def int_riscv_xvsw_mask : XVUSStoreMasked; - def int_riscv_xvse_mask : XVUSStoreMasked; + def int_riscv_th_vsb : XVUSStore; + def int_riscv_th_vsh : XVUSStore; + def int_riscv_th_vsw : XVUSStore; + def int_riscv_th_vse : XVUSStore; + def int_riscv_th_vsb_mask : XVUSStoreMasked; + def int_riscv_th_vsh_mask : XVUSStoreMasked; + def int_riscv_th_vsw_mask : XVUSStoreMasked; + def int_riscv_th_vse_mask : XVUSStoreMasked; // 7.5 Vector Strided Instructions // For strided load with passthru operand @@ -149,29 +149,29 @@ let TargetPrefix = "riscv" in { let VLOperand = 4; } - def int_riscv_xvlsb : XVSLoad; - def int_riscv_xvlsh : XVSLoad; - def int_riscv_xvlsw : XVSLoad; - def int_riscv_xvlse : XVSLoad; - def int_riscv_xvlsbu : XVSLoad; - def int_riscv_xvlshu : XVSLoad; - def int_riscv_xvlswu : XVSLoad; - def int_riscv_xvlsb_mask : XVSLoadMasked; - def int_riscv_xvlsh_mask : XVSLoadMasked; - def int_riscv_xvlsw_mask : XVSLoadMasked; - def int_riscv_xvlse_mask : XVSLoadMasked; - def int_riscv_xvlsbu_mask : XVSLoadMasked; - def int_riscv_xvlshu_mask : XVSLoadMasked; - def int_riscv_xvlswu_mask : XVSLoadMasked; + def int_riscv_th_vlsb : XVSLoad; + def int_riscv_th_vlsh : XVSLoad; + def int_riscv_th_vlsw : XVSLoad; + def int_riscv_th_vlse : XVSLoad; + def int_riscv_th_vlsbu : XVSLoad; + def int_riscv_th_vlshu : XVSLoad; + def int_riscv_th_vlswu : XVSLoad; + def int_riscv_th_vlsb_mask : XVSLoadMasked; + def int_riscv_th_vlsh_mask : XVSLoadMasked; + def int_riscv_th_vlsw_mask : XVSLoadMasked; + def int_riscv_th_vlse_mask : XVSLoadMasked; + def int_riscv_th_vlsbu_mask : XVSLoadMasked; + def int_riscv_th_vlshu_mask : XVSLoadMasked; + def int_riscv_th_vlswu_mask : XVSLoadMasked; - def int_riscv_xvssb : XVSStore; - def int_riscv_xvssh : XVSStore; - def int_riscv_xvssw : XVSStore; - def int_riscv_xvsse : XVSStore; - def int_riscv_xvssb_mask : XVSStoreMasked; - def int_riscv_xvssh_mask : XVSStoreMasked; - def int_riscv_xvssw_mask : XVSStoreMasked; - def int_riscv_xvsse_mask : XVSStoreMasked; + def int_riscv_th_vssb : XVSStore; + def int_riscv_th_vssh : XVSStore; + def int_riscv_th_vssw : XVSStore; + def int_riscv_th_vsse : XVSStore; + def int_riscv_th_vssb_mask : XVSStoreMasked; + def int_riscv_th_vssh_mask : XVSStoreMasked; + def int_riscv_th_vssw_mask : XVSStoreMasked; + def int_riscv_th_vsse_mask : XVSStoreMasked; // 7.6. Vector Indexed Instructions // For indexed load with passthru operand @@ -213,29 +213,29 @@ let TargetPrefix = "riscv" in { let VLOperand = 4; } - def int_riscv_xvlxb : XVILoad; - def int_riscv_xvlxh : XVILoad; - def int_riscv_xvlxw : XVILoad; - def int_riscv_xvlxe : XVILoad; - def int_riscv_xvlxbu : XVILoad; - def int_riscv_xvlxhu : XVILoad; - def int_riscv_xvlxwu : XVILoad; - def int_riscv_xvlxb_mask : XVILoadMasked; - def int_riscv_xvlxh_mask : XVILoadMasked; - def int_riscv_xvlxw_mask : XVILoadMasked; - def int_riscv_xvlxe_mask : XVILoadMasked; - def int_riscv_xvlxbu_mask : XVILoadMasked; - def int_riscv_xvlxhu_mask : XVILoadMasked; - def int_riscv_xvlxwu_mask : XVILoadMasked; + def int_riscv_th_vlxb : XVILoad; + def int_riscv_th_vlxh : XVILoad; + def int_riscv_th_vlxw : XVILoad; + def int_riscv_th_vlxe : XVILoad; + def int_riscv_th_vlxbu : XVILoad; + def int_riscv_th_vlxhu : XVILoad; + def int_riscv_th_vlxwu : XVILoad; + def int_riscv_th_vlxb_mask : XVILoadMasked; + def int_riscv_th_vlxh_mask : XVILoadMasked; + def int_riscv_th_vlxw_mask : XVILoadMasked; + def int_riscv_th_vlxe_mask : XVILoadMasked; + def int_riscv_th_vlxbu_mask : XVILoadMasked; + def int_riscv_th_vlxhu_mask : XVILoadMasked; + def int_riscv_th_vlxwu_mask : XVILoadMasked; - def int_riscv_xvsxb : XVIStore; - def int_riscv_xvsxh : XVIStore; - def int_riscv_xvsxw : XVIStore; - def int_riscv_xvsxe : XVIStore; - def int_riscv_xvsxb_mask : XVIStoreMasked; - def int_riscv_xvsxh_mask : XVIStoreMasked; - def int_riscv_xvsxw_mask : XVIStoreMasked; - def int_riscv_xvsxe_mask : XVIStoreMasked; + def int_riscv_th_vsxb : XVIStore; + def int_riscv_th_vsxh : XVIStore; + def int_riscv_th_vsxw : XVIStore; + def int_riscv_th_vsxe : XVIStore; + def int_riscv_th_vsxb_mask : XVIStoreMasked; + def int_riscv_th_vsxh_mask : XVIStoreMasked; + def int_riscv_th_vsxw_mask : XVIStoreMasked; + def int_riscv_th_vsxe_mask : XVIStoreMasked; // 7.7 Unit-Stride Fault-only-first Loads // For unit stride fault-only-first load without mask @@ -292,31 +292,31 @@ let TargetPrefix = "riscv" in { def "int_riscv_" # NAME # "_mask" : XVAMOMask; } - defm xvamoswap : XIntrinsicVAMO; - defm xvamoadd : XIntrinsicVAMO; - defm xvamoxor : XIntrinsicVAMO; - defm xvamoand : XIntrinsicVAMO; - defm xvamoor : XIntrinsicVAMO; - defm xvamomin : XIntrinsicVAMO; - defm xvamomax : XIntrinsicVAMO; - defm xvamominu : XIntrinsicVAMO; - defm xvamomaxu : XIntrinsicVAMO; + defm th_vamoswap : XIntrinsicVAMO; + defm th_vamoadd : XIntrinsicVAMO; + defm th_vamoxor : XIntrinsicVAMO; + defm th_vamoand : XIntrinsicVAMO; + defm th_vamoor : XIntrinsicVAMO; + defm th_vamomin : XIntrinsicVAMO; + defm th_vamomax : XIntrinsicVAMO; + defm th_vamominu : XIntrinsicVAMO; + defm th_vamomaxu : XIntrinsicVAMO; } // TargetPrefix = "riscv" let TargetPrefix = "riscv" in { // 12. Vector Integer Arithmetic Instructions - defm xvadd : RISCVBinaryAAX; + defm th_vadd : RISCVBinaryAAX; } // TargetPrefix = "riscv" let TargetPrefix = "riscv" in { // 12.14. Vector Integer Merge and Move Instructions // Output: (vector) // Input: (passthru, vector_in, vl) - def int_riscv_xvmv_v_v : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, - LLVMMatchType<0>, - llvm_anyint_ty], - [IntrNoMem]>, RISCVVIntrinsic { + def int_riscv_th_vmv_v_v : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, + LLVMMatchType<0>, + llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic { let VLOperand = 2; } } // TargetPrefix = "riscv" diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index b0c70d1c2b606..f2ba38994428e 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -80,11 +80,11 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"xtheadmemidx", RISCVExtensionVersion{1, 0}}, {"xtheadmempair", RISCVExtensionVersion{1, 0}}, {"xtheadsync", RISCVExtensionVersion{1, 0}}, - // T-Head vector extension (namely Vector extension 0.7.1) series. - {"xtheadv", RISCVExtensionVersion{0, 7}}, // T-Head vector extension series: Zvamo {"xtheadvamo", RISCVExtensionVersion{0, 7}}, {"xtheadvdot", RISCVExtensionVersion{1, 0}}, + // T-Head vector extension (namely Vector extension 0.7.1) series. + {"xtheadvector", RISCVExtensionVersion{0, 7}}, // T-Head vector extension series: Zvediv {"xtheadvediv", RISCVExtensionVersion{0, 7}}, // T-Head vector extension series: Zvlsseg @@ -965,10 +965,10 @@ Error RISCVISAInfo::checkDependency() { errc::invalid_argument, "'xtheadvamo' requires 'a' extension to also be specified"); - if (Exts.count("xtheadv") && HasVector) + if (Exts.count("xtheadvector") && HasVector) return createStringError( errc::invalid_argument, - "'xtheadv' extension is incompatible with 'v' or 'zve*' extension"); + "'xtheadvector' extension is incompatible with 'v' or 'zve*' extension"); // Additional dependency checks. // TODO: The 'q' extension requires rv64. diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 5114de311af41..8749831a6ed41 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1328,10 +1328,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool MatchingInlineAsm) { MCInst Inst; FeatureBitset MissingFeatures; - bool IsRVV0p71 = getSTI().hasFeature(RISCV::FeatureVendorXTHeadV); auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, - MatchingInlineAsm, IsRVV0p71 ? 1 : 0); + MatchingInlineAsm); switch (Result) { default: break; @@ -3343,7 +3342,7 @@ void RISCVAsmParser::emitXVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, .addOperand(Inst.getOperand(1)) .addOperand(Inst.getOperand(2)) .addReg(RISCV::NoRegister)); - emitToStreamer(Out, MCInstBuilder(RISCV::XVMNAND_MM) + emitToStreamer(Out, MCInstBuilder(RISCV::TH_VMNAND_MM) .addOperand(Inst.getOperand(0)) .addOperand(Inst.getOperand(0)) .addOperand(Inst.getOperand(0))); @@ -3359,7 +3358,7 @@ void RISCVAsmParser::emitXVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, .addOperand(Inst.getOperand(1)) .addOperand(Inst.getOperand(2)) .addOperand(Inst.getOperand(3))); - emitToStreamer(Out, MCInstBuilder(RISCV::XVMXOR_MM) + emitToStreamer(Out, MCInstBuilder(RISCV::TH_VMXOR_MM) .addOperand(Inst.getOperand(0)) .addOperand(Inst.getOperand(0)) .addReg(RISCV::V0)); @@ -3375,7 +3374,7 @@ void RISCVAsmParser::emitXVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, .addOperand(Inst.getOperand(2)) .addOperand(Inst.getOperand(3)) .addReg(RISCV::NoRegister)); - emitToStreamer(Out, MCInstBuilder(RISCV::XVMANDN_MM) + emitToStreamer(Out, MCInstBuilder(RISCV::TH_VMANDN_MM) .addOperand(Inst.getOperand(0)) .addOperand(Inst.getOperand(0)) .addOperand(Inst.getOperand(1))); @@ -3444,8 +3443,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, if (Opcode == RISCV::PseudoVMSGEU_VX_M_T || Opcode == RISCV::PseudoVMSGE_VX_M_T || - Opcode == RISCV::PseudoXVMSGEU_VX_M_T || - Opcode == RISCV::PseudoXVMSGE_VX_M_T) { + Opcode == RISCV::PseudoTH_VMSGEU_VX_M_T || + Opcode == RISCV::PseudoTH_VMSGE_VX_M_T) { unsigned DestReg = Inst.getOperand(0).getReg(); unsigned TempReg = Inst.getOperand(1).getReg(); if (DestReg == TempReg) { @@ -3711,27 +3710,27 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, emitVMSGE_VI(Inst, RISCV::VMSLEU_VI, RISCV::VMSNE_VV, IDLoc, Out, false); return false; // for XTHeadV Extension - case RISCV::PseudoXVMSGEU_VX: - case RISCV::PseudoXVMSGEU_VX_M: - case RISCV::PseudoXVMSGEU_VX_M_T: - emitXVMSGE(Inst, RISCV::XVMSLTU_VX, IDLoc, Out); + case RISCV::PseudoTH_VMSGEU_VX: + case RISCV::PseudoTH_VMSGEU_VX_M: + case RISCV::PseudoTH_VMSGEU_VX_M_T: + emitXVMSGE(Inst, RISCV::TH_VMSLTU_VX, IDLoc, Out); return false; - case RISCV::PseudoXVMSGE_VX: - case RISCV::PseudoXVMSGE_VX_M: - case RISCV::PseudoXVMSGE_VX_M_T: - emitXVMSGE(Inst, RISCV::XVMSLT_VX, IDLoc, Out); + case RISCV::PseudoTH_VMSGE_VX: + case RISCV::PseudoTH_VMSGE_VX_M: + case RISCV::PseudoTH_VMSGE_VX_M_T: + emitXVMSGE(Inst, RISCV::TH_VMSLT_VX, IDLoc, Out); return false; - case RISCV::PseudoXVMSGE_VI: - emitVMSGE_VI(Inst, RISCV::XVMSGT_VI, RISCV::XVMSGT_VI, IDLoc, Out, true); + case RISCV::PseudoTH_VMSGE_VI: + emitVMSGE_VI(Inst, RISCV::TH_VMSGT_VI, RISCV::TH_VMSGT_VI, IDLoc, Out, true); return false; - case RISCV::PseudoXVMSLT_VI: - emitVMSGE_VI(Inst, RISCV::XVMSLE_VI, RISCV::XVMSLE_VI, IDLoc, Out, true); + case RISCV::PseudoTH_VMSLT_VI: + emitVMSGE_VI(Inst, RISCV::TH_VMSLE_VI, RISCV::TH_VMSLE_VI, IDLoc, Out, true); return false; - case RISCV::PseudoXVMSGEU_VI: - emitVMSGE_VI(Inst, RISCV::XVMSGTU_VI, RISCV::XVMSEQ_VV, IDLoc, Out, false); + case RISCV::PseudoTH_VMSGEU_VI: + emitVMSGE_VI(Inst, RISCV::TH_VMSGTU_VI, RISCV::TH_VMSEQ_VV, IDLoc, Out, false); return false; - case RISCV::PseudoXVMSLTU_VI: - emitVMSGE_VI(Inst, RISCV::XVMSLEU_VI, RISCV::XVMSNE_VV, IDLoc, Out, false); + case RISCV::PseudoTH_VMSLTU_VI: + emitVMSGE_VI(Inst, RISCV::TH_VMSLEU_VI, RISCV::TH_VMSNE_VV, IDLoc, Out, false); return false; } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 67d3ca44249fb..8665cab3fa27c 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -557,7 +557,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableTHeadV32, "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadV, DecoderTableRVV0p7132, - "XTHeadV custom opcode table"); + "XTHeadVector custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index d495f9d72ec15..be93d5933d332 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -61,16 +61,9 @@ def RISCVAsmWriter : AsmWriter { int PassSubtarget = 1; } -def RVV0p71AsmParserVariant : AsmParserVariant { - int Variant = 1; - string Name = "RVV0p71"; -} - def RISCV : Target { let InstructionSet = RISCVInstrInfo; let AssemblyParsers = [RISCVAsmParser]; - let AssemblyParserVariants = [DefaultAsmParserVariant, - RVV0p71AsmParserVariant]; let AssemblyWriters = [RISCVAsmWriter]; let AllowRegisterRenaming = 1; } diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index 287941f7ab9a3..90bdb55e6e2d6 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -125,8 +125,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB, case RISCV::PseudoVSETVLIX0: case RISCV::PseudoVSETIVLI: return expandVSetVL(MBB, MBBI); - case RISCV::PseudoXVSETVLI: - case RISCV::PseudoXVSETVLIX0: + case RISCV::PseudoTH_VSETVLI: + case RISCV::PseudoTH_VSETVLIX0: return expandXVSetVL(MBB, MBBI); case RISCV::PseudoVMCLR_M_B1: case RISCV::PseudoVMCLR_M_B2: @@ -259,10 +259,10 @@ bool RISCVExpandPseudo::expandXVSetVL(MachineBasicBlock &MBB, DebugLoc DL = MBBI->getDebugLoc(); - assert((MBBI->getOpcode() == RISCV::PseudoXVSETVLI || - MBBI->getOpcode() == RISCV::PseudoXVSETVLIX0) && + assert((MBBI->getOpcode() == RISCV::PseudoTH_VSETVLI || + MBBI->getOpcode() == RISCV::PseudoTH_VSETVLIX0) && "Unexpected pseudo instruction"); - unsigned Opcode = RISCV::XVSETVLI; + unsigned Opcode = RISCV::TH_VSETVLI; const MCInstrDesc &Desc = TII->get(Opcode); assert(Desc.getNumOperands() == 3 && "Unexpected instruction format"); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f82f8e82e62c7..f003c7455792e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -897,11 +897,11 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", //===----------------------------------------------------------------------===// def FeatureVendorXTHeadV - : SubtargetFeature<"xtheadv", "HasVendorXTHeadV", "true", - "'xtheadv' (T-Head Base Vector Instructions)">; + : SubtargetFeature<"xtheadvector", "HasVendorXTHeadV", "true", + "'xtheadvector' (T-Head Base Vector Instructions)">; def HasVendorXTHeadV : Predicate<"Subtarget->hasVendorXTHeadV()">, AssemblerPredicate<(all_of FeatureVendorXTHeadV), - "'xtheadv' (T-Head Base Vector Instructions)">; + "'xtheadvector' (T-Head Base Vector Instructions)">; def FeatureVendorXTHeadVlsseg : SubtargetFeature<"xtheadvlsseg", "HasVendorXTHeadVlsseg", "true", @@ -931,31 +931,31 @@ def HasStdVOrXTHeadV : Predicate<"Subtarget->hasStdVOrXTHeadV()">, (any_of FeatureStdExtZve32x, FeatureVendorXTHeadV), "'V' (Vector Extension for Application Processors), 'Zve32x', " "'Zve64x' (Vector Extensions for Embedded Processors) or" - "'XTHeadV' (Vector Extension for T-Head)">; + "'XTHeadVector' (Vector Extension for T-Head)">; def HasStdVOrXTHeadVI64 : Predicate<"Subtarget->hasStdVOrXTHeadVI64()">, AssemblerPredicate< (any_of FeatureStdExtZve64x, FeatureVendorXTHeadV), "'V' (Vector Extension for Application Processors), 'Zve64x' " "(Vector Extensions for Embedded Processors) or" - "'XTHeadV' (Vector Extension for T-Head)">; + "'XTHeadVector' (Vector Extension for T-Head)">; def HasStdVOrXTHeadVF16 : Predicate<"Subtarget->hasStdVOrXTHeadVF16()">, AssemblerPredicate< (any_of FeatureStdExtZvfh, FeatureVendorXTHeadV), "'V' (Vector Extension for Application Processors), 'Zvfh' " "(Vector Extensions for Embedded Processors) or" - "'XTHeadV' (Vector Extension for T-Head)">; + "'XTHeadVector' (Vector Extension for T-Head)">; def HasStdVOrXTHeadVF32 : Predicate<"Subtarget->hasStdVOrXTHeadVF32()">, AssemblerPredicate< (any_of FeatureStdExtZve32f, FeatureVendorXTHeadV), "'V' (Vector Extension for Application Processors), 'Zve32f' " "(Vector Extensions for Embedded Processors) or" - "'XTHeadV' (Vector Extension for T-Head)">; + "'XTHeadVector' (Vector Extension for T-Head)">; def HasStdVOrXTHeadVF64 : Predicate<"Subtarget->hasStdVOrXTHeadVF64()">, AssemblerPredicate< (any_of FeatureStdExtZve64d, FeatureVendorXTHeadV), "'V' (Vector Extension for Application Processors), 'Zve64d' " "(Vector Extensions for Embedded Processors) or" - "'XTHeadV' (Vector Extension for T-Head)">; + "'XTHeadVector' (Vector Extension for T-Head)">; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index b620f976b2020..2868fb58ad762 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -354,44 +354,44 @@ void RISCVDAGToDAGISel::selectXVL( bool IsMasked, bool IsStrided, bool IsIndexed, bool IsFF, bool IsE) { auto Tag2Log2MEM = [] (unsigned no) { switch (no) { - case Intrinsic::riscv_xvlb: - case Intrinsic::riscv_xvlbu: - case Intrinsic::riscv_xvlb_mask: - case Intrinsic::riscv_xvlbu_mask: - case Intrinsic::riscv_xvlsb: - case Intrinsic::riscv_xvlsbu: - case Intrinsic::riscv_xvlsb_mask: - case Intrinsic::riscv_xvlsbu_mask: - case Intrinsic::riscv_xvlxb: - case Intrinsic::riscv_xvlxbu: - case Intrinsic::riscv_xvlxb_mask: - case Intrinsic::riscv_xvlxbu_mask: + case Intrinsic::riscv_th_vlb: + case Intrinsic::riscv_th_vlbu: + case Intrinsic::riscv_th_vlb_mask: + case Intrinsic::riscv_th_vlbu_mask: + case Intrinsic::riscv_th_vlsb: + case Intrinsic::riscv_th_vlsbu: + case Intrinsic::riscv_th_vlsb_mask: + case Intrinsic::riscv_th_vlsbu_mask: + case Intrinsic::riscv_th_vlxb: + case Intrinsic::riscv_th_vlxbu: + case Intrinsic::riscv_th_vlxb_mask: + case Intrinsic::riscv_th_vlxbu_mask: return 3; - case Intrinsic::riscv_xvlh: - case Intrinsic::riscv_xvlhu: - case Intrinsic::riscv_xvlh_mask: - case Intrinsic::riscv_xvlhu_mask: - case Intrinsic::riscv_xvlsh: - case Intrinsic::riscv_xvlshu: - case Intrinsic::riscv_xvlsh_mask: - case Intrinsic::riscv_xvlshu_mask: - case Intrinsic::riscv_xvlxh: - case Intrinsic::riscv_xvlxhu: - case Intrinsic::riscv_xvlxh_mask: - case Intrinsic::riscv_xvlxhu_mask: + case Intrinsic::riscv_th_vlh: + case Intrinsic::riscv_th_vlhu: + case Intrinsic::riscv_th_vlh_mask: + case Intrinsic::riscv_th_vlhu_mask: + case Intrinsic::riscv_th_vlsh: + case Intrinsic::riscv_th_vlshu: + case Intrinsic::riscv_th_vlsh_mask: + case Intrinsic::riscv_th_vlshu_mask: + case Intrinsic::riscv_th_vlxh: + case Intrinsic::riscv_th_vlxhu: + case Intrinsic::riscv_th_vlxh_mask: + case Intrinsic::riscv_th_vlxhu_mask: return 4; - case Intrinsic::riscv_xvlw: - case Intrinsic::riscv_xvlwu: - case Intrinsic::riscv_xvlw_mask: - case Intrinsic::riscv_xvlwu_mask: - case Intrinsic::riscv_xvlsw: - case Intrinsic::riscv_xvlswu: - case Intrinsic::riscv_xvlsw_mask: - case Intrinsic::riscv_xvlswu_mask: - case Intrinsic::riscv_xvlxw: - case Intrinsic::riscv_xvlxwu: - case Intrinsic::riscv_xvlxw_mask: - case Intrinsic::riscv_xvlxwu_mask: + case Intrinsic::riscv_th_vlw: + case Intrinsic::riscv_th_vlwu: + case Intrinsic::riscv_th_vlw_mask: + case Intrinsic::riscv_th_vlwu_mask: + case Intrinsic::riscv_th_vlsw: + case Intrinsic::riscv_th_vlswu: + case Intrinsic::riscv_th_vlsw_mask: + case Intrinsic::riscv_th_vlswu_mask: + case Intrinsic::riscv_th_vlxw: + case Intrinsic::riscv_th_vlxwu: + case Intrinsic::riscv_th_vlxw_mask: + case Intrinsic::riscv_th_vlxwu_mask: return 5; } llvm_unreachable("Impossible intrinsic tag"); @@ -440,26 +440,26 @@ void RISCVDAGToDAGISel::selectXVS( bool IsStrided, bool IsIndexed, bool IsE) { auto Tag2Log2MEM = [] (unsigned no) { switch (no) { - case Intrinsic::riscv_xvsb: - case Intrinsic::riscv_xvsb_mask: - case Intrinsic::riscv_xvssb: - case Intrinsic::riscv_xvssb_mask: - case Intrinsic::riscv_xvsxb: - case Intrinsic::riscv_xvsxb_mask: + case Intrinsic::riscv_th_vsb: + case Intrinsic::riscv_th_vsb_mask: + case Intrinsic::riscv_th_vssb: + case Intrinsic::riscv_th_vssb_mask: + case Intrinsic::riscv_th_vsxb: + case Intrinsic::riscv_th_vsxb_mask: return 3; - case Intrinsic::riscv_xvsh: - case Intrinsic::riscv_xvsh_mask: - case Intrinsic::riscv_xvssh: - case Intrinsic::riscv_xvssh_mask: - case Intrinsic::riscv_xvsxh: - case Intrinsic::riscv_xvsxh_mask: + case Intrinsic::riscv_th_vsh: + case Intrinsic::riscv_th_vsh_mask: + case Intrinsic::riscv_th_vssh: + case Intrinsic::riscv_th_vssh_mask: + case Intrinsic::riscv_th_vsxh: + case Intrinsic::riscv_th_vsxh_mask: return 4; - case Intrinsic::riscv_xvsw: - case Intrinsic::riscv_xvsw_mask: - case Intrinsic::riscv_xvssw: - case Intrinsic::riscv_xvssw_mask: - case Intrinsic::riscv_xvsxw: - case Intrinsic::riscv_xvsxw_mask: + case Intrinsic::riscv_th_vsw: + case Intrinsic::riscv_th_vsw_mask: + case Intrinsic::riscv_th_vssw: + case Intrinsic::riscv_th_vssw_mask: + case Intrinsic::riscv_th_vsxw: + case Intrinsic::riscv_th_vsxw_mask: return 5; } llvm_unreachable("Impossible intrinsic tag"); @@ -771,13 +771,13 @@ void RISCVDAGToDAGISel::selectXVSETVLI(SDNode *Node) { unsigned IntNo = Node->getConstantOperandVal(0); - assert((IntNo == Intrinsic::riscv_xvsetvlmax || - IntNo == Intrinsic::riscv_xvsetvl) && + assert((IntNo == Intrinsic::riscv_th_vsetvlmax || + IntNo == Intrinsic::riscv_th_vsetvl) && "Unexpected vsetvl intrinsic"); // declare i64 @llvm.riscv.xvsetvl (i64 %avl, i64 %sew, i64 %lmul); // declare i64 @llvm.riscv.xvsetvlmax( i64 %sew, i64 %lmul); - bool IsMax = IntNo == Intrinsic::riscv_xvsetvlmax; + bool IsMax = IntNo == Intrinsic::riscv_th_vsetvlmax; unsigned SEWPosition = IsMax ? 1 : 2; unsigned ExpectedOperands = SEWPosition + 2; assert(Node->getNumOperands() == ExpectedOperands && @@ -810,10 +810,10 @@ void RISCVDAGToDAGISel::selectXVSETVLI(SDNode *Node) { unsigned Opcode; if (IsMax) { // spec: if rs1 = x0, then use maximum vector length - Opcode = RISCV::PseudoXVSETVLIX0; + Opcode = RISCV::PseudoTH_VSETVLIX0; AVLOp = CurDAG->getRegister(RISCV::X0, XLenVT); } else { - Opcode = RISCV::PseudoXVSETVLI; + Opcode = RISCV::PseudoTH_VSETVLI; AVLOp = Node->getOperand(1); } @@ -1796,8 +1796,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { case Intrinsic::riscv_vsetvli: case Intrinsic::riscv_vsetvlimax: return selectVSETVLI(Node); - case Intrinsic::riscv_xvsetvl: - case Intrinsic::riscv_xvsetvlmax: + case Intrinsic::riscv_th_vsetvl: + case Intrinsic::riscv_th_vsetvlmax: return selectXVSETVLI(Node); } break; @@ -1947,20 +1947,20 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, Load); return; } - case Intrinsic::riscv_xvlxb: - case Intrinsic::riscv_xvlxh: - case Intrinsic::riscv_xvlxw: - case Intrinsic::riscv_xvlxe: { + case Intrinsic::riscv_th_vlxb: + case Intrinsic::riscv_th_vlxh: + case Intrinsic::riscv_th_vlxw: + case Intrinsic::riscv_th_vlxe: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/false, /*IsMasked*/false, /*IsStrided*/false, /*IsIndexed*/true, /*IsFF*/false, - IntNo == Intrinsic::riscv_xvlxe); + IntNo == Intrinsic::riscv_th_vlxe); return; } - case Intrinsic::riscv_xvlxbu: - case Intrinsic::riscv_xvlxhu: - case Intrinsic::riscv_xvlxwu: { + case Intrinsic::riscv_th_vlxbu: + case Intrinsic::riscv_th_vlxhu: + case Intrinsic::riscv_th_vlxwu: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/true, @@ -1968,20 +1968,20 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { /*IsIndexed*/true, /*IsFF*/false, /*IsE*/false); return; } - case Intrinsic::riscv_xvlxb_mask: - case Intrinsic::riscv_xvlxh_mask: - case Intrinsic::riscv_xvlxw_mask: - case Intrinsic::riscv_xvlxe_mask: { + case Intrinsic::riscv_th_vlxb_mask: + case Intrinsic::riscv_th_vlxh_mask: + case Intrinsic::riscv_th_vlxw_mask: + case Intrinsic::riscv_th_vlxe_mask: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/false, /*IsMasked*/true, /*IsStrided*/false, /*IsIndexed*/true, /*IsFF*/false, - IntNo == Intrinsic::riscv_xvlxe_mask); + IntNo == Intrinsic::riscv_th_vlxe_mask); return; } - case Intrinsic::riscv_xvlxbu_mask: - case Intrinsic::riscv_xvlxhu_mask: - case Intrinsic::riscv_xvlxwu_mask: { + case Intrinsic::riscv_th_vlxbu_mask: + case Intrinsic::riscv_th_vlxhu_mask: + case Intrinsic::riscv_th_vlxwu_mask: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/true, @@ -2036,31 +2036,31 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, Load); return; } - case Intrinsic::riscv_xvlb: - case Intrinsic::riscv_xvlh: - case Intrinsic::riscv_xvlw: - case Intrinsic::riscv_xvle: { + case Intrinsic::riscv_th_vlb: + case Intrinsic::riscv_th_vlh: + case Intrinsic::riscv_th_vlw: + case Intrinsic::riscv_th_vle: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ false, /*IsMasked*/ false, /*IsStrided*/ false, /*IsIndexed*/ false, /*IsFF*/ false, - /*IsE*/ IntNo == Intrinsic::riscv_xvle); + /*IsE*/ IntNo == Intrinsic::riscv_th_vle); return; } - case Intrinsic::riscv_xvlsb: - case Intrinsic::riscv_xvlsh: - case Intrinsic::riscv_xvlsw: - case Intrinsic::riscv_xvlse: { + case Intrinsic::riscv_th_vlsb: + case Intrinsic::riscv_th_vlsh: + case Intrinsic::riscv_th_vlsw: + case Intrinsic::riscv_th_vlse: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ false, /*IsMasked*/ false, /*IsStrided*/ true, /*IsIndexed*/ false, /*IsFF*/ false, - /*IsE*/ IntNo == Intrinsic::riscv_xvlse); + /*IsE*/ IntNo == Intrinsic::riscv_th_vlse); return; } - case Intrinsic::riscv_xvlbu: - case Intrinsic::riscv_xvlhu: - case Intrinsic::riscv_xvlwu: { + case Intrinsic::riscv_th_vlbu: + case Intrinsic::riscv_th_vlhu: + case Intrinsic::riscv_th_vlwu: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ true, @@ -2068,9 +2068,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { /*IsIndexed*/ false, /*IsFF*/ false, /*IsE*/ false); return; } - case Intrinsic::riscv_xvlsbu: - case Intrinsic::riscv_xvlshu: - case Intrinsic::riscv_xvlswu: { + case Intrinsic::riscv_th_vlsbu: + case Intrinsic::riscv_th_vlshu: + case Intrinsic::riscv_th_vlswu: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ true, @@ -2078,20 +2078,20 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { /*IsIndexed*/ false, /*IsFF*/ false, /*IsE*/ false); return; } - case Intrinsic::riscv_xvlb_mask: - case Intrinsic::riscv_xvlh_mask: - case Intrinsic::riscv_xvlw_mask: - case Intrinsic::riscv_xvle_mask: { + case Intrinsic::riscv_th_vlb_mask: + case Intrinsic::riscv_th_vlh_mask: + case Intrinsic::riscv_th_vlw_mask: + case Intrinsic::riscv_th_vle_mask: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ false, /*IsMasked*/ true, /*IsStrided*/ false, /*IsIndexed*/ false, /*IsFF*/ false, - /*IsE*/ IntNo == Intrinsic::riscv_xvle_mask); + /*IsE*/ IntNo == Intrinsic::riscv_th_vle_mask); return; } - case Intrinsic::riscv_xvlbu_mask: - case Intrinsic::riscv_xvlhu_mask: - case Intrinsic::riscv_xvlwu_mask: { + case Intrinsic::riscv_th_vlbu_mask: + case Intrinsic::riscv_th_vlhu_mask: + case Intrinsic::riscv_th_vlwu_mask: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ true, @@ -2099,20 +2099,20 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { /*IsIndexed*/ false, /*IsFF*/ false, /*IsE*/ false); return; } - case Intrinsic::riscv_xvlsb_mask: - case Intrinsic::riscv_xvlsh_mask: - case Intrinsic::riscv_xvlsw_mask: - case Intrinsic::riscv_xvlse_mask: { + case Intrinsic::riscv_th_vlsb_mask: + case Intrinsic::riscv_th_vlsh_mask: + case Intrinsic::riscv_th_vlsw_mask: + case Intrinsic::riscv_th_vlse_mask: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvlse_mask; + bool IsE = IntNo == Intrinsic::riscv_th_vlse_mask; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ false, /*IsMasked*/ true, /*IsStrided*/ true, /*IsIndexed*/ false, /*IsFF*/ false, IsE); return; } - case Intrinsic::riscv_xvlsbu_mask: - case Intrinsic::riscv_xvlshu_mask: - case Intrinsic::riscv_xvlswu_mask: { + case Intrinsic::riscv_th_vlsbu_mask: + case Intrinsic::riscv_th_vlshu_mask: + case Intrinsic::riscv_th_vlswu_mask: { if (!Subtarget->hasVendorXTHeadV()) return; selectXVL(Node, DL, IntNo, /*IsUnsigned*/ true, @@ -2281,24 +2281,24 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, Store); return; } - case Intrinsic::riscv_xvsxb: - case Intrinsic::riscv_xvsxh: - case Intrinsic::riscv_xvsxw: - case Intrinsic::riscv_xvsxe: { + case Intrinsic::riscv_th_vsxb: + case Intrinsic::riscv_th_vsxh: + case Intrinsic::riscv_th_vsxw: + case Intrinsic::riscv_th_vsxe: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvsxe; + bool IsE = IntNo == Intrinsic::riscv_th_vsxe; selectXVS(Node, DL, IntNo, /*IsMask*/ false, /*IsStrided*/ false, /*IsIndexed*/ true, IsE); return; } - case Intrinsic::riscv_xvsxb_mask: - case Intrinsic::riscv_xvsxh_mask: - case Intrinsic::riscv_xvsxw_mask: - case Intrinsic::riscv_xvsxe_mask: { + case Intrinsic::riscv_th_vsxb_mask: + case Intrinsic::riscv_th_vsxh_mask: + case Intrinsic::riscv_th_vsxw_mask: + case Intrinsic::riscv_th_vsxe_mask: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvsxe_mask; + bool IsE = IntNo == Intrinsic::riscv_th_vsxe_mask; selectXVS(Node, DL, IntNo, /*IsMask*/ true, /*IsStrided*/ false, /*IsIndexed*/ true, IsE); return; @@ -2334,46 +2334,46 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, Store); return; } - case Intrinsic::riscv_xvsb: - case Intrinsic::riscv_xvsh: - case Intrinsic::riscv_xvsw: - case Intrinsic::riscv_xvse: { + case Intrinsic::riscv_th_vsb: + case Intrinsic::riscv_th_vsh: + case Intrinsic::riscv_th_vsw: + case Intrinsic::riscv_th_vse: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvse; + bool IsE = IntNo == Intrinsic::riscv_th_vse; selectXVS(Node, DL, IntNo, /*IsMask*/ false, /*IsStrided*/ false, /*IsIndexed*/ false, IsE); return; } - case Intrinsic::riscv_xvssb: - case Intrinsic::riscv_xvssh: - case Intrinsic::riscv_xvssw: - case Intrinsic::riscv_xvsse: { + case Intrinsic::riscv_th_vssb: + case Intrinsic::riscv_th_vssh: + case Intrinsic::riscv_th_vssw: + case Intrinsic::riscv_th_vsse: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvsse; + bool IsE = IntNo == Intrinsic::riscv_th_vsse; selectXVS(Node, DL, IntNo, /*IsMask*/ false, /*IsStrided*/ true, /*IsIndexed*/ false, IsE); return; } - case Intrinsic::riscv_xvsb_mask: - case Intrinsic::riscv_xvsh_mask: - case Intrinsic::riscv_xvsw_mask: - case Intrinsic::riscv_xvse_mask: { + case Intrinsic::riscv_th_vsb_mask: + case Intrinsic::riscv_th_vsh_mask: + case Intrinsic::riscv_th_vsw_mask: + case Intrinsic::riscv_th_vse_mask: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvse_mask; + bool IsE = IntNo == Intrinsic::riscv_th_vse_mask; selectXVS(Node, DL, IntNo, /*IsMask*/ true, /*IsStrided*/ false, /*IsIndexed*/ false, IsE); return; } - case Intrinsic::riscv_xvssb_mask: - case Intrinsic::riscv_xvssh_mask: - case Intrinsic::riscv_xvssw_mask: - case Intrinsic::riscv_xvsse_mask: { + case Intrinsic::riscv_th_vssb_mask: + case Intrinsic::riscv_th_vssh_mask: + case Intrinsic::riscv_th_vssw_mask: + case Intrinsic::riscv_th_vsse_mask: { if (!Subtarget->hasVendorXTHeadV()) return; - bool IsE = IntNo == Intrinsic::riscv_xvsse_mask; + bool IsE = IntNo == Intrinsic::riscv_th_vsse_mask; selectXVS(Node, DL, IntNo, /*IsMask*/ true, /*IsStrided*/ true, /*IsIndexed*/ false, IsE); return; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index f84aafbc8a2c4..02d8f380c5b7f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1324,20 +1324,20 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, return SetRVVLoadStoreInfo(/*PtrOp*/ 1, /*IsStore*/ false, /*IsUnitStrided*/ true); - case Intrinsic::riscv_xvlb: - case Intrinsic::riscv_xvlbu: - case Intrinsic::riscv_xvlb_mask: - case Intrinsic::riscv_xvlbu_mask: - case Intrinsic::riscv_xvlh: - case Intrinsic::riscv_xvlhu: - case Intrinsic::riscv_xvlh_mask: - case Intrinsic::riscv_xvlhu_mask: - case Intrinsic::riscv_xvlw: - case Intrinsic::riscv_xvlwu: - case Intrinsic::riscv_xvlw_mask: - case Intrinsic::riscv_xvlwu_mask: - case Intrinsic::riscv_xvle: - case Intrinsic::riscv_xvle_mask: + case Intrinsic::riscv_th_vlb: + case Intrinsic::riscv_th_vlbu: + case Intrinsic::riscv_th_vlb_mask: + case Intrinsic::riscv_th_vlbu_mask: + case Intrinsic::riscv_th_vlh: + case Intrinsic::riscv_th_vlhu: + case Intrinsic::riscv_th_vlh_mask: + case Intrinsic::riscv_th_vlhu_mask: + case Intrinsic::riscv_th_vlw: + case Intrinsic::riscv_th_vlwu: + case Intrinsic::riscv_th_vlw_mask: + case Intrinsic::riscv_th_vlwu_mask: + case Intrinsic::riscv_th_vle: + case Intrinsic::riscv_th_vle_mask: if (!Subtarget.hasVendorXTHeadV()) return false; return SetRVVLoadStoreInfo(/*PtrOp*/ 1, @@ -1348,14 +1348,14 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, return SetRVVLoadStoreInfo(/*PtrOp*/ 1, /*IsStore*/ true, /*IsUnitStrided*/ true); - case Intrinsic::riscv_xvsb: - case Intrinsic::riscv_xvsh: - case Intrinsic::riscv_xvsw: - case Intrinsic::riscv_xvse: - case Intrinsic::riscv_xvsb_mask: - case Intrinsic::riscv_xvsh_mask: - case Intrinsic::riscv_xvsw_mask: - case Intrinsic::riscv_xvse_mask: + case Intrinsic::riscv_th_vsb: + case Intrinsic::riscv_th_vsh: + case Intrinsic::riscv_th_vsw: + case Intrinsic::riscv_th_vse: + case Intrinsic::riscv_th_vsb_mask: + case Intrinsic::riscv_th_vsh_mask: + case Intrinsic::riscv_th_vsw_mask: + case Intrinsic::riscv_th_vse_mask: if (!Subtarget.hasVendorXTHeadV()) return false; return SetRVVLoadStoreInfo(/*PtrOp*/ 1, @@ -1370,34 +1370,34 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, return SetRVVLoadStoreInfo(/*PtrOp*/ 1, /*IsStore*/ false, /*IsUnitStrided*/ false); - case Intrinsic::riscv_xvlsb: - case Intrinsic::riscv_xvlsbu: - case Intrinsic::riscv_xvlsb_mask: - case Intrinsic::riscv_xvlsbu_mask: - case Intrinsic::riscv_xvlsh: - case Intrinsic::riscv_xvlshu: - case Intrinsic::riscv_xvlsh_mask: - case Intrinsic::riscv_xvlshu_mask: - case Intrinsic::riscv_xvlsw: - case Intrinsic::riscv_xvlswu: - case Intrinsic::riscv_xvlsw_mask: - case Intrinsic::riscv_xvlswu_mask: - case Intrinsic::riscv_xvlse: - case Intrinsic::riscv_xvlse_mask: - case Intrinsic::riscv_xvlxb: - case Intrinsic::riscv_xvlxbu: - case Intrinsic::riscv_xvlxb_mask: - case Intrinsic::riscv_xvlxbu_mask: - case Intrinsic::riscv_xvlxh: - case Intrinsic::riscv_xvlxhu: - case Intrinsic::riscv_xvlxh_mask: - case Intrinsic::riscv_xvlxhu_mask: - case Intrinsic::riscv_xvlxw: - case Intrinsic::riscv_xvlxwu: - case Intrinsic::riscv_xvlxw_mask: - case Intrinsic::riscv_xvlxwu_mask: - case Intrinsic::riscv_xvlxe: - case Intrinsic::riscv_xvlxe_mask: + case Intrinsic::riscv_th_vlsb: + case Intrinsic::riscv_th_vlsbu: + case Intrinsic::riscv_th_vlsb_mask: + case Intrinsic::riscv_th_vlsbu_mask: + case Intrinsic::riscv_th_vlsh: + case Intrinsic::riscv_th_vlshu: + case Intrinsic::riscv_th_vlsh_mask: + case Intrinsic::riscv_th_vlshu_mask: + case Intrinsic::riscv_th_vlsw: + case Intrinsic::riscv_th_vlswu: + case Intrinsic::riscv_th_vlsw_mask: + case Intrinsic::riscv_th_vlswu_mask: + case Intrinsic::riscv_th_vlse: + case Intrinsic::riscv_th_vlse_mask: + case Intrinsic::riscv_th_vlxb: + case Intrinsic::riscv_th_vlxbu: + case Intrinsic::riscv_th_vlxb_mask: + case Intrinsic::riscv_th_vlxbu_mask: + case Intrinsic::riscv_th_vlxh: + case Intrinsic::riscv_th_vlxhu: + case Intrinsic::riscv_th_vlxh_mask: + case Intrinsic::riscv_th_vlxhu_mask: + case Intrinsic::riscv_th_vlxw: + case Intrinsic::riscv_th_vlxwu: + case Intrinsic::riscv_th_vlxw_mask: + case Intrinsic::riscv_th_vlxwu_mask: + case Intrinsic::riscv_th_vlxe: + case Intrinsic::riscv_th_vlxe_mask: if (!Subtarget.hasVendorXTHeadV()) return false; return SetRVVLoadStoreInfo(/*PtrOp*/ 1, @@ -1412,22 +1412,22 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, return SetRVVLoadStoreInfo(/*PtrOp*/ 1, /*IsStore*/ true, /*IsUnitStrided*/ false); - case Intrinsic::riscv_xvssb: - case Intrinsic::riscv_xvssb_mask: - case Intrinsic::riscv_xvssh: - case Intrinsic::riscv_xvssh_mask: - case Intrinsic::riscv_xvssw: - case Intrinsic::riscv_xvssw_mask: - case Intrinsic::riscv_xvsse: - case Intrinsic::riscv_xvsse_mask: - case Intrinsic::riscv_xvsxb: - case Intrinsic::riscv_xvsxb_mask: - case Intrinsic::riscv_xvsxh: - case Intrinsic::riscv_xvsxh_mask: - case Intrinsic::riscv_xvsxw: - case Intrinsic::riscv_xvsxw_mask: - case Intrinsic::riscv_xvsxe: - case Intrinsic::riscv_xvsxe_mask: + case Intrinsic::riscv_th_vssb: + case Intrinsic::riscv_th_vssb_mask: + case Intrinsic::riscv_th_vssh: + case Intrinsic::riscv_th_vssh_mask: + case Intrinsic::riscv_th_vssw: + case Intrinsic::riscv_th_vssw_mask: + case Intrinsic::riscv_th_vsse: + case Intrinsic::riscv_th_vsse_mask: + case Intrinsic::riscv_th_vsxb: + case Intrinsic::riscv_th_vsxb_mask: + case Intrinsic::riscv_th_vsxh: + case Intrinsic::riscv_th_vsxh_mask: + case Intrinsic::riscv_th_vsxw: + case Intrinsic::riscv_th_vsxw_mask: + case Intrinsic::riscv_th_vsxe: + case Intrinsic::riscv_th_vsxe_mask: if (!Subtarget.hasVendorXTHeadV()) return false; return SetRVVLoadStoreInfo(/*PtrOp*/ 1, @@ -14644,7 +14644,7 @@ static MachineBasicBlock *emitXWholeLoadStore(MachineInstr &MI, // Generate `vsetvli x0, x0, e, m` auto VTypeI = RISCVVType::encodeXTHeadVTYPE(SEW, LMUL, 1); - BuildMI(*BB, MI, DL, TII->get(RISCV::XVSETVLI)) + BuildMI(*BB, MI, DL, TII->get(RISCV::TH_VSETVLI)) .addReg(RISCV::X0, RegState::Define | RegState::Dead) .addReg(RISCV::X0) .addImm(VTypeI) @@ -14658,7 +14658,7 @@ static MachineBasicBlock *emitXWholeLoadStore(MachineInstr &MI, .add(MI.getOperand(1)); // rs, the load/store address // Restore vl, vtype with `vsetvl x0, SavedVL, SavedVType` - BuildMI(*BB, MI, DL, TII->get(RISCV::XVSETVL)) + BuildMI(*BB, MI, DL, TII->get(RISCV::TH_VSETVL)) .addReg(RISCV::X0, RegState::Define | RegState::Dead) .addReg(SavedVL, RegState::Kill) .addReg(SavedVType, RegState::Kill); @@ -14710,7 +14710,7 @@ static MachineBasicBlock *emitXWholeMove(MachineInstr &MI, for (unsigned I = 0; I < NREGS; ++I) { auto DstReg = TRI->getSubReg(DstRegNo, RISCV::sub_vrm1_0 + I); auto SrcReg = TRI->getSubReg(SrcRegNo, RISCV::sub_vrm1_0 + I); - BuildMI(*BB, MI, DL, TII->get(RISCV::XVMV_V_V), DstReg) + BuildMI(*BB, MI, DL, TII->get(RISCV::TH_VMV_V_V), DstReg) .addReg(SrcReg); } @@ -14839,19 +14839,19 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return emitFROUND(MI, BB, Subtarget); // Emulated whole move instructions for RVV 0.7 - case RISCV::PseudoXVMV1R_V: + case RISCV::PseudoTH_VMV1R_V: return emitXWholeMove(MI, BB, 1); - case RISCV::PseudoXVMV2R_V: + case RISCV::PseudoTH_VMV2R_V: return emitXWholeMove(MI, BB, 2); - case RISCV::PseudoXVMV4R_V: + case RISCV::PseudoTH_VMV4R_V: return emitXWholeMove(MI, BB, 4); - case RISCV::PseudoXVMV8R_V: + case RISCV::PseudoTH_VMV8R_V: return emitXWholeMove(MI, BB, 8); #define PseudoXVL_CASE_SEW_LMUL(SEW_val, LMUL_val) \ - case RISCV::PseudoXVL##LMUL_val##RE##SEW_val##_V: \ + case RISCV::PseudoTH_VL##LMUL_val##RE##SEW_val##_V: \ return emitXWholeLoad(MI, BB, SEW_val, LMUL_val, \ - RISCV::PseudoXVLE_V_M##LMUL_val); + RISCV::PseudoTH_VLE_V_M##LMUL_val); #define PseudoXVL_CASE_SEW(SEW_val) \ PseudoXVL_CASE_SEW_LMUL(SEW_val, 1); \ @@ -14866,9 +14866,9 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, PseudoXVL_CASE_SEW(64); #define PseudoXVS_CASE_SEW_LMUL(SEW_val, LMUL_val) \ - case RISCV::PseudoXVS##LMUL_val##RE##SEW_val##_V: \ + case RISCV::PseudoTH_VS##LMUL_val##RE##SEW_val##_V: \ return emitXWholeStore(MI, BB, SEW_val, LMUL_val, \ - RISCV::PseudoXVSE_V_M##LMUL_val); + RISCV::PseudoTH_VSE_V_M##LMUL_val); #define PseudoXVS_CASE_SEW(SEW_val) \ PseudoXVS_CASE_SEW_LMUL(SEW_val, 1); \ diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 7df27feb4e9c8..ea26158453508 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -56,15 +56,15 @@ static bool isVectorConfigInstr(const MachineInstr &MI) { return MI.getOpcode() == RISCV::PseudoVSETVLI || MI.getOpcode() == RISCV::PseudoVSETVLIX0 || MI.getOpcode() == RISCV::PseudoVSETIVLI || - MI.getOpcode() == RISCV::PseudoXVSETVLI || - MI.getOpcode() == RISCV::PseudoXVSETVLIX0; + MI.getOpcode() == RISCV::PseudoTH_VSETVLI || + MI.getOpcode() == RISCV::PseudoTH_VSETVLIX0; } /// Return true if this is 'vsetvli x0, x0, vtype' which preserves /// VL and only sets VTYPE. static bool isVLPreservingConfig(const MachineInstr &MI) { if (MI.getOpcode() != RISCV::PseudoVSETVLIX0 && - MI.getOpcode() != RISCV::PseudoXVSETVLIX0) + MI.getOpcode() != RISCV::PseudoTH_VSETVLIX0) return false; assert(RISCV::X0 == MI.getOperand(1).getReg()); return RISCV::X0 == MI.getOperand(0).getReg(); @@ -839,8 +839,8 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI, bool XTHeadV) { } else { assert(MI.getOpcode() == RISCV::PseudoVSETVLI || MI.getOpcode() == RISCV::PseudoVSETVLIX0 || - MI.getOpcode() == RISCV::PseudoXVSETVLI || - MI.getOpcode() == RISCV::PseudoXVSETVLIX0); + MI.getOpcode() == RISCV::PseudoTH_VSETVLI || + MI.getOpcode() == RISCV::PseudoTH_VSETVLIX0); Register AVLReg = MI.getOperand(1).getReg(); assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) && "Can't handle X0, X0 vsetvli yet"); @@ -863,7 +863,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, // VLMAX. if (Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) { auto Opcode = - HasVendorXTHeadV ? RISCV::PseudoXVSETVLIX0 : RISCV::PseudoVSETVLIX0; + HasVendorXTHeadV ? RISCV::PseudoTH_VSETVLIX0 : RISCV::PseudoVSETVLIX0; auto TypeI = HasVendorXTHeadV ? Info.encodeXTHeadVTYPE() : Info.encodeVTYPE(); BuildMI(MBB, InsertPt, DL, TII->get(Opcode)) @@ -883,7 +883,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, if (isVectorConfigInstr(*DefMI)) { VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, HasVendorXTHeadV); if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) { - auto Opcode = HasVendorXTHeadV ? RISCV::PseudoXVSETVLIX0 + auto Opcode = HasVendorXTHeadV ? RISCV::PseudoTH_VSETVLIX0 : RISCV::PseudoVSETVLIX0; auto TypeI = HasVendorXTHeadV ? Info.encodeXTHeadVTYPE() : Info.encodeVTYPE(); @@ -915,7 +915,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, if (PrevInfo.isValid() && !PrevInfo.isUnknown() && Info.hasSameVLMAX(PrevInfo)) { auto Opcode = - HasVendorXTHeadV ? RISCV::PseudoXVSETVLIX0 : RISCV::PseudoVSETVLIX0; + HasVendorXTHeadV ? RISCV::PseudoTH_VSETVLIX0 : RISCV::PseudoVSETVLIX0; auto TypeI = HasVendorXTHeadV ? Info.encodeXTHeadVTYPE() : Info.encodeVTYPE(); BuildMI(MBB, InsertPt, DL, TII->get(Opcode)) @@ -932,7 +932,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoLI)) .addReg(UImmR, RegState::Define) .addImm(0); - BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoXVSETVLI)) + BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoTH_VSETVLI)) .addReg(RISCV::X0, RegState::Define | RegState::Dead) .addReg(UImmR, RegState::Kill) .addImm(Info.encodeXTHeadVTYPE()); @@ -952,11 +952,11 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, // opcode if the AVLReg is X0 as they have different register classes for // the AVL operand. Register DestReg = RISCV::X0; - unsigned Opcode = HasVendorXTHeadV ? RISCV::PseudoXVSETVLI : RISCV::PseudoVSETVLI; + unsigned Opcode = HasVendorXTHeadV ? RISCV::PseudoTH_VSETVLI : RISCV::PseudoVSETVLI; auto TypeI = HasVendorXTHeadV ? Info.encodeXTHeadVTYPE() : Info.encodeVTYPE(); if (AVLReg == RISCV::X0) { DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); - Opcode = HasVendorXTHeadV ? RISCV::PseudoXVSETVLIX0 : RISCV::PseudoVSETVLIX0; + Opcode = HasVendorXTHeadV ? RISCV::PseudoTH_VSETVLIX0 : RISCV::PseudoVSETVLIX0; } BuildMI(MBB, InsertPt, DL, TII->get(Opcode)) .addReg(DestReg, RegState::Define | RegState::Dead) @@ -1627,7 +1627,7 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) { for (MachineInstr &MI : MBB) { if (MI.getOpcode() == RISCV::PseudoVSETVLI || MI.getOpcode() == RISCV::PseudoVSETIVLI || - MI.getOpcode() == RISCV::PseudoXVSETVLI) { + MI.getOpcode() == RISCV::PseudoTH_VSETVLI) { Register VRegDef = MI.getOperand(0).getReg(); if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef)) MI.getOperand(0).setReg(RISCV::X0); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 73d406c2fc667..7a6f2af1f09b9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -187,8 +187,8 @@ static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI, if (MBBI->getOpcode() == RISCV::PseudoVSETVLI || MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 || MBBI->getOpcode() == RISCV::PseudoVSETIVLI || - MBBI->getOpcode() == RISCV::PseudoXVSETVLI || - MBBI->getOpcode() == RISCV::PseudoXVSETVLIX0) { + MBBI->getOpcode() == RISCV::PseudoTH_VSETVLI || + MBBI->getOpcode() == RISCV::PseudoTH_VSETVLIX0) { // There is a vsetvli between COPY and source define instruction. // vy = def_vop ... (producing instruction) // ... @@ -359,16 +359,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, Opc = RISCV::FSGNJ_D; IsScalableVector = false; } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { - Opc = XTHeadV ? RISCV::PseudoXVMV1R_V : RISCV::VMV1R_V; + Opc = XTHeadV ? RISCV::PseudoTH_VMV1R_V : RISCV::VMV1R_V; LMul = RISCVII::LMUL_1; } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { - Opc = XTHeadV ? RISCV::PseudoXVMV2R_V : RISCV::VMV2R_V; + Opc = XTHeadV ? RISCV::PseudoTH_VMV2R_V : RISCV::VMV2R_V; LMul = RISCVII::LMUL_2; } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { - Opc = XTHeadV ? RISCV::PseudoXVMV4R_V : RISCV::VMV4R_V; + Opc = XTHeadV ? RISCV::PseudoTH_VMV4R_V : RISCV::VMV4R_V; LMul = RISCVII::LMUL_4; } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { - Opc = XTHeadV ? RISCV::PseudoXVMV8R_V : RISCV::VMV8R_V; + Opc = XTHeadV ? RISCV::PseudoTH_VMV8R_V : RISCV::VMV8R_V; LMul = RISCVII::LMUL_8; } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) { Opc = RISCV::VMV1R_V; @@ -443,20 +443,20 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, default: llvm_unreachable("Impossible LMUL for vector register copy."); case RISCVII::LMUL_1: - Opc = XTHeadV ? RISCV::PseudoXVMV_V_V_M1 : RISCV::PseudoVMV_V_V_M1; - VIOpc = XTHeadV ? RISCV::PseudoXVMV_V_I_M1 : RISCV::PseudoVMV_V_I_M1; + Opc = XTHeadV ? RISCV::PseudoTH_VMV_V_V_M1 : RISCV::PseudoVMV_V_V_M1; + VIOpc = XTHeadV ? RISCV::PseudoTH_VMV_V_I_M1 : RISCV::PseudoVMV_V_I_M1; break; case RISCVII::LMUL_2: - Opc = XTHeadV ? RISCV::PseudoXVMV_V_V_M2 : RISCV::PseudoVMV_V_V_M2; - VIOpc = XTHeadV ? RISCV::PseudoXVMV_V_I_M2 : RISCV::PseudoVMV_V_I_M2; + Opc = XTHeadV ? RISCV::PseudoTH_VMV_V_V_M2 : RISCV::PseudoVMV_V_V_M2; + VIOpc = XTHeadV ? RISCV::PseudoTH_VMV_V_I_M2 : RISCV::PseudoVMV_V_I_M2; break; case RISCVII::LMUL_4: - Opc = XTHeadV ? RISCV::PseudoXVMV_V_V_M4 : RISCV::PseudoVMV_V_V_M4; - VIOpc = XTHeadV ? RISCV::PseudoXVMV_V_I_M4 : RISCV::PseudoVMV_V_I_M4; + Opc = XTHeadV ? RISCV::PseudoTH_VMV_V_V_M4 : RISCV::PseudoVMV_V_V_M4; + VIOpc = XTHeadV ? RISCV::PseudoTH_VMV_V_I_M4 : RISCV::PseudoVMV_V_I_M4; break; case RISCVII::LMUL_8: - Opc = XTHeadV ? RISCV::PseudoXVMV_V_V_M8 : RISCV::PseudoVMV_V_V_M8; - VIOpc = XTHeadV ? RISCV::PseudoXVMV_V_I_M8 : RISCV::PseudoVMV_V_I_M8; + Opc = XTHeadV ? RISCV::PseudoTH_VMV_V_V_M8 : RISCV::PseudoVMV_V_V_M8; + VIOpc = XTHeadV ? RISCV::PseudoTH_VMV_V_I_M8 : RISCV::PseudoVMV_V_I_M8; break; } @@ -562,13 +562,13 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, // The vector whole register store instructions are encoded // similar to unmasked unit-stride store of elements with EEW=8. // Same for the following similar cases. - Opcode = XTHeadV ? RISCV::PseudoXVS1RE8_V : RISCV::VS1R_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VS1RE8_V : RISCV::VS1R_V; } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVS2RE8_V : RISCV::VS2R_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VS2RE8_V : RISCV::VS2R_V; } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVS4RE8_V : RISCV::VS4R_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VS4RE8_V : RISCV::VS4R_V; } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVS8RE8_V : RISCV::VS8R_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VS8RE8_V : RISCV::VS8R_V; } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) Opcode = RISCV::PseudoVSPILL2_M1; else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) @@ -650,13 +650,13 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Opcode = RISCV::FLD; IsScalableVector = false; } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVL1RE8_V : RISCV::VL1RE8_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VL1RE8_V : RISCV::VL1RE8_V; } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVL2RE8_V : RISCV::VL2RE8_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VL2RE8_V : RISCV::VL2RE8_V; } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVL4RE8_V : RISCV::VL4RE8_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VL4RE8_V : RISCV::VL4RE8_V; } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { - Opcode = XTHeadV ? RISCV::PseudoXVL8RE8_V : RISCV::VL8RE8_V; + Opcode = XTHeadV ? RISCV::PseudoTH_VL8RE8_V : RISCV::VL8RE8_V; } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) Opcode = RISCV::PseudoVRELOAD2_M1; else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td index ef05fa1c419a1..1bc0d6b9b07dd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td @@ -41,9 +41,9 @@ def XTHeadVTypeI : Operand { // Instruction class templates //===----------------------------------------------------------------------===// -class XVLoadStore nf, RISCVOpcode opcode, - bits<3> mop, bits<3> width, dag outs, dag ins, - string opcodestr, string argstr> +class TH_VLoadStore nf, RISCVOpcode opcode, + bits<3> mop, bits<3> width, dag outs, dag ins, + string opcodestr, string argstr> : RVInst { bits<5> rs2; bits<5> rs1; @@ -63,70 +63,70 @@ class XVLoadStore nf, RISCVOpcode opcode, } let hasSideEffects = 0, mayLoad = 1, mayStore = 0, RVVConstraint = VMConstraint in { - class XVLxU nf, bits<3> width, string opcodestr> - : XVLoadStore { + class TH_VLxU nf, bits<3> width, string opcodestr> + : TH_VLoadStore { let rs2 = 0b00000; } - class XVLx nf, bits<3> width, string opcodestr> - : XVLoadStore { + class TH_VLx nf, bits<3> width, string opcodestr> + : TH_VLoadStore { let rs2 = 0b00000; } - class XVLxUFF nf, bits<3> width, string opcodestr> - : XVLoadStore { + class TH_VLxUFF nf, bits<3> width, string opcodestr> + : TH_VLoadStore { let rs2 = 0b10000; } - class XVLxFF nf, bits<3> width, string opcodestr> - : XVLoadStore { + class TH_VLxFF nf, bits<3> width, string opcodestr> + : TH_VLoadStore { let rs2 = 0b10000; } - class XVLSxU nf, bits<3> width, string opcodestr> - : XVLoadStore; - class XVLSx nf, bits<3> width, string opcodestr> - : XVLoadStore; - class XVLXxU nf, bits<3> width, string opcodestr> - : XVLoadStore; - class XVLXx nf, bits<3> width, string opcodestr> - : XVLoadStore; + class TH_VLSxU nf, bits<3> width, string opcodestr> + : TH_VLoadStore; + class TH_VLSx nf, bits<3> width, string opcodestr> + : TH_VLoadStore; + class TH_VLXxU nf, bits<3> width, string opcodestr> + : TH_VLoadStore; + class TH_VLXx nf, bits<3> width, string opcodestr> + : TH_VLoadStore; } let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { - class XVSx nf, bits<3> width, string opcodestr> - : XVLoadStore { + class TH_VSx nf, bits<3> width, string opcodestr> + : TH_VLoadStore { let rs2 = 0b00000; } - class XVSSx nf, bits<3> width, string opcodestr> - : XVLoadStore; - class XVSXx nf, bits<3> width, string opcodestr> - : XVLoadStore; - class XVSUXx nf, bits<3> width, string opcodestr> - : XVLoadStore; -} - -multiclass VWSMAC_V_X funct6> { + class TH_VSSx nf, bits<3> width, string opcodestr> + : TH_VLoadStore; + class TH_VSXx nf, bits<3> width, string opcodestr> + : TH_VLoadStore; + class TH_VSUXx nf, bits<3> width, string opcodestr> + : TH_VLoadStore; +} + +multiclass TH_VWSMAC_V_X funct6> { def V : VALUrVV, Sched<[WriteVIWMulAddV_WorstCase, ReadVIWMulAddV_WorstCase, ReadVIWMulAddV_WorstCase, ReadVMask]>; @@ -135,13 +135,13 @@ multiclass VWSMAC_V_X funct6> { ReadVIWMulAddX_WorstCase, ReadVMask]>; } -multiclass VWSMAC_X funct6> { +multiclass TH_VWSMAC_X funct6> { def X : VALUrVX, Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase, ReadVIWMulAddX_WorstCase, ReadVMask]>; } -multiclass XVNCLP_IV_V_X_I funct6> { +multiclass TH_VNCLP_IV_V_X_I funct6> { def V : VALUVV, Sched<[WriteVNClipV_WorstCase, ReadVNClipV_WorstCase, ReadVNClipV_WorstCase, ReadVMask]>; @@ -153,7 +153,7 @@ multiclass XVNCLP_IV_V_X_I funct6> { ReadVMask]>; } -multiclass XVNSHT_IV_V_X_I funct6> { +multiclass TH_VNSHT_IV_V_X_I funct6> { def V : VALUVV, Sched<[WriteVNShiftV_WorstCase, ReadVNShiftV_WorstCase, ReadVNShiftV_WorstCase, ReadVMask]>; @@ -167,48 +167,48 @@ multiclass XVNSHT_IV_V_X_I funct6> { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // rvv 0.7.1 set vm=1 for `op vd, vs2, vs1, v0` -class XVALUmVV funct6, RISCVVFormat opv, string opcodestr> +class TH_VALUmVV funct6, RISCVVFormat opv, string opcodestr> : RVInstVV { + (ins VR:$vs2, VR:$vs1, VMV0:$v0), + opcodestr, "$vd, $vs2, $vs1, v0"> { let vm = 1; } // rvv 0.7.1 set vm=1 for `op vd, vs2, rs1, v0` -class XVALUmVX funct6, RISCVVFormat opv, string opcodestr> +class TH_VALUmVX funct6, RISCVVFormat opv, string opcodestr> : RVInstVX { + (ins VR:$vs2, GPR:$rs1, VMV0:$v0), + opcodestr, "$vd, $vs2, $rs1, v0"> { let vm = 1; } // rvv 0.7.1 set vm=1 for `op vd, vs2, imm, v0` -class XVALUmVI funct6, string opcodestr, Operand optype = simm5> +class TH_VALUmVI funct6, string opcodestr, Operand optype = simm5> : RVInstIVI { let vm = 1; } -multiclass XVALUm_IV_V_X funct6> { - def VM : XVALUmVV, +multiclass TH_VALUm_IV_V_X funct6> { + def VM : TH_VALUmVV, Sched<[WriteVICALUV_WorstCase, ReadVICALUV_WorstCase, ReadVICALUV_WorstCase, ReadVMask]>; - def XM : XVALUmVX, + def XM : TH_VALUmVX, Sched<[WriteVICALUX_WorstCase, ReadVICALUV_WorstCase, ReadVICALUX_WorstCase, ReadVMask]>; } -multiclass XVALUm_IV_V_X_I funct6> - : XVALUm_IV_V_X { - def IM : XVALUmVI, +multiclass TH_VALUm_IV_V_X_I funct6> + : TH_VALUm_IV_V_X { + def IM : TH_VALUmVI, Sched<[WriteVICALUI_WorstCase, ReadVICALUV_WorstCase, ReadVMask]>; } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 -class XInstVAMO amoop, bits<3> width, dag outs, - dag ins, string opcodestr, string argstr> +class TH_InstVAMO amoop, bits<3> width, dag outs, + dag ins, string opcodestr, string argstr> : RVInst { bits<5> vs2; bits<5> rs1; @@ -228,10 +228,10 @@ class XInstVAMO amoop, bits<3> width, dag outs, let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { // vamo vd, vs2, (rs1), vd, vm -class XVAMOWd amoop, bits<3> width, string opcodestr> - : XInstVAMO { +class TH_VAMOWd amoop, bits<3> width, string opcodestr> + : TH_InstVAMO { let Constraints = "$vd_wd = $vd"; let wd = 1; bits<5> vd; @@ -239,10 +239,10 @@ class XVAMOWd amoop, bits<3> width, string opcodestr> } // vamo x0, vs2, (rs1), vs3, vm -class XVAMONoWd amoop, bits<3> width, string opcodestr> - : XInstVAMO { +class TH_VAMONoWd amoop, bits<3> width, string opcodestr> + : TH_InstVAMO { let wd = 0; bits<5> vs3; let Inst{11-7} = vs3; @@ -250,168 +250,168 @@ class XVAMONoWd amoop, bits<3> width, string opcodestr> } // hasSideEffects = 0, mayLoad = 1, mayStore = 1 -multiclass XVAMO amoop, bits<3> width, string opcodestr> { - def _WD_V : XVAMOWd; - def _UNWD_V : XVAMONoWd; +multiclass TH_VAMO amoop, bits<3> width, string opcodestr> { + def _WD_V : TH_VAMOWd; + def _UNWD_V : TH_VAMONoWd; } //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// -let AsmVariantName = "RVV0p71", DecoderNamespace = "RVV0p71" in { +let DecoderNamespace = "RVV0p71" in { let Predicates = [HasVendorXTHeadV] in { // Configuration-Setting Instructions let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { -def XVSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, XTHeadVTypeI:$vtypei), - "vsetvli", "$rd, $rs1, $vtypei">, - Sched<[WriteVSETVLI, ReadVSETVLI]>; -def XVSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), - "vsetvl", "$rd, $rs1, $rs2">, - Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>; +def TH_VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, XTHeadVTypeI:$vtypei), + "th.vsetvli", "$rd, $rs1, $vtypei">, + Sched<[WriteVSETVLI, ReadVSETVLI]>; +def TH_VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "th.vsetvl", "$rd, $rs1, $rs2">, + Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>; } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 // Vector Unit-Stride Instructions -def XVLB_V : XVLx<0b000, 0b000, "vlb.v">; -def XVLH_V : XVLx<0b000, 0b101, "vlh.v">; -def XVLW_V : XVLx<0b000, 0b110, "vlw.v">; -def XVLBU_V : XVLxU<0b000, 0b000, "vlbu.v">; -def XVLHU_V : XVLxU<0b000, 0b101, "vlhu.v">; -def XVLWU_V : XVLxU<0b000, 0b110, "vlwu.v">; -def XVLE_V : XVLxU<0b000, 0b111, "vle.v">; -def XVSB_V : XVSx<0b000, 0b000, "vsb.v">; -def XVSH_V : XVSx<0b000, 0b101, "vsh.v">; -def XVSW_V : XVSx<0b000, 0b110, "vsw.v">; -def XVSE_V : XVSx<0b000, 0b111, "vse.v">; +def TH_VLB_V : TH_VLx<0b000, 0b000, "th.vlb.v">; +def TH_VLH_V : TH_VLx<0b000, 0b101, "th.vlh.v">; +def TH_VLW_V : TH_VLx<0b000, 0b110, "th.vlw.v">; +def TH_VLBU_V : TH_VLxU<0b000, 0b000, "th.vlbu.v">; +def TH_VLHU_V : TH_VLxU<0b000, 0b101, "th.vlhu.v">; +def TH_VLWU_V : TH_VLxU<0b000, 0b110, "th.vlwu.v">; +def TH_VLE_V : TH_VLxU<0b000, 0b111, "th.vle.v">; +def TH_VSB_V : TH_VSx<0b000, 0b000, "th.vsb.v">; +def TH_VSH_V : TH_VSx<0b000, 0b101, "th.vsh.v">; +def TH_VSW_V : TH_VSx<0b000, 0b110, "th.vsw.v">; +def TH_VSE_V : TH_VSx<0b000, 0b111, "th.vse.v">; // Vector Strided Instructions -def XVLSB_V : XVLSx<0b000, 0b000, "vlsb.v">; -def XVLSH_V : XVLSx<0b000, 0b101, "vlsh.v">; -def XVLSW_V : XVLSx<0b000, 0b110, "vlsw.v">; -def XVLSBU_V : XVLSxU<0b000, 0b000, "vlsbu.v">; -def XVLSHU_V : XVLSxU<0b000, 0b101, "vlshu.v">; -def XVLSWU_V : XVLSxU<0b000, 0b110, "vlswu.v">; -def XVLSE_V : XVLSxU<0b000, 0b111, "vlse.v">; -def XVSSB_V : XVSSx<0b000, 0b000, "vssb.v">; -def XVSSH_V : XVSSx<0b000, 0b101, "vssh.v">; -def XVSSW_V : XVSSx<0b000, 0b110, "vssw.v">; -def XVSSE_V : XVSSx<0b000, 0b111, "vsse.v">; +def TH_VLSB_V : TH_VLSx<0b000, 0b000, "th.vlsb.v">; +def TH_VLSH_V : TH_VLSx<0b000, 0b101, "th.vlsh.v">; +def TH_VLSW_V : TH_VLSx<0b000, 0b110, "th.vlsw.v">; +def TH_VLSBU_V : TH_VLSxU<0b000, 0b000, "th.vlsbu.v">; +def TH_VLSHU_V : TH_VLSxU<0b000, 0b101, "th.vlshu.v">; +def TH_VLSWU_V : TH_VLSxU<0b000, 0b110, "th.vlswu.v">; +def TH_VLSE_V : TH_VLSxU<0b000, 0b111, "th.vlse.v">; +def TH_VSSB_V : TH_VSSx<0b000, 0b000, "th.vssb.v">; +def TH_VSSH_V : TH_VSSx<0b000, 0b101, "th.vssh.v">; +def TH_VSSW_V : TH_VSSx<0b000, 0b110, "th.vssw.v">; +def TH_VSSE_V : TH_VSSx<0b000, 0b111, "th.vsse.v">; // Vector indexed loads and stores -def XVLXB_V : XVLXx<0b000, 0b000, "vlxb.v">; -def XVLXH_V : XVLXx<0b000, 0b101, "vlxh.v">; -def XVLXW_V : XVLXx<0b000, 0b110, "vlxw.v">; -def XVLXBU_V : XVLXxU<0b000, 0b000, "vlxbu.v">; -def XVLXHU_V : XVLXxU<0b000, 0b101, "vlxhu.v">; -def XVLXWU_V : XVLXxU<0b000, 0b110, "vlxwu.v">; -def XVLXE_V : XVLXxU<0b000, 0b111, "vlxe.v">; -def XVSXB_V : XVSXx<0b000, 0b000, "vsxb.v">; -def XVSXH_V : XVSXx<0b000, 0b101, "vsxh.v">; -def XVSXW_V : XVSXx<0b000, 0b110, "vsxw.v">; -def XVSXE_V : XVSXx<0b000, 0b111, "vsxe.v">; -def XVSUXB_V : XVSUXx<0b000, 0b000, "vsuxb.v">; -def XVSUXH_V : XVSUXx<0b000, 0b101, "vsuxh.v">; -def XVSUXW_V : XVSUXx<0b000, 0b110, "vsuxw.v">; -def XVSUXE_V : XVSUXx<0b000, 0b111, "vsuxe.v">; +def TH_VLXB_V : TH_VLXx<0b000, 0b000, "th.vlxb.v">; +def TH_VLXH_V : TH_VLXx<0b000, 0b101, "th.vlxh.v">; +def TH_VLXW_V : TH_VLXx<0b000, 0b110, "th.vlxw.v">; +def TH_VLXBU_V : TH_VLXxU<0b000, 0b000, "th.vlxbu.v">; +def TH_VLXHU_V : TH_VLXxU<0b000, 0b101, "th.vlxhu.v">; +def TH_VLXWU_V : TH_VLXxU<0b000, 0b110, "th.vlxwu.v">; +def TH_VLXE_V : TH_VLXxU<0b000, 0b111, "th.vlxe.v">; +def TH_VSXB_V : TH_VSXx<0b000, 0b000, "th.vsxb.v">; +def TH_VSXH_V : TH_VSXx<0b000, 0b101, "th.vsxh.v">; +def TH_VSXW_V : TH_VSXx<0b000, 0b110, "th.vsxw.v">; +def TH_VSXE_V : TH_VSXx<0b000, 0b111, "th.vsxe.v">; +def TH_VSUXB_V : TH_VSUXx<0b000, 0b000, "th.vsuxb.v">; +def TH_VSUXH_V : TH_VSUXx<0b000, 0b101, "th.vsuxh.v">; +def TH_VSUXW_V : TH_VSUXx<0b000, 0b110, "th.vsuxw.v">; +def TH_VSUXE_V : TH_VSUXx<0b000, 0b111, "th.vsuxe.v">; // Unit-stride Fault-Only-First Loads -def XVLBFF_V : XVLxFF<0b000, 0b000, "vlbff.v">; -def XVLHFF_V : XVLxFF<0b000, 0b101, "vlhff.v">; -def XVLWFF_V : XVLxFF<0b000, 0b110, "vlwff.v">; -def XVLBUFF_V : XVLxUFF<0b000, 0b000, "vlbuff.v">; -def XVLHUFF_V : XVLxUFF<0b000, 0b101, "vlhuff.v">; -def XVLWUFF_V : XVLxUFF<0b000, 0b110, "vlwuff.v">; -def XVLEFF_V : XVLxUFF<0b000, 0b111, "vleff.v">; +def TH_VLBFF_V : TH_VLxFF<0b000, 0b000, "th.vlbff.v">; +def TH_VLHFF_V : TH_VLxFF<0b000, 0b101, "th.vlhff.v">; +def TH_VLWFF_V : TH_VLxFF<0b000, 0b110, "th.vlwff.v">; +def TH_VLBUFF_V : TH_VLxUFF<0b000, 0b000, "th.vlbuff.v">; +def TH_VLHUFF_V : TH_VLxUFF<0b000, 0b101, "th.vlhuff.v">; +def TH_VLWUFF_V : TH_VLxUFF<0b000, 0b110, "th.vlwuff.v">; +def TH_VLEFF_V : TH_VLxUFF<0b000, 0b111, "th.vleff.v">; } // Predicates = [HasVendorXTHeadV] let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg] in { foreach nf=2-8 in { // Vector Unit-Stride Segment Loads and Stores - def XVLSEG#nf#B_V : XVLx; - def XVLSEG#nf#H_V : XVLx; - def XVLSEG#nf#W_V : XVLx; - def XVLSEG#nf#BU_V : XVLxU; - def XVLSEG#nf#HU_V : XVLxU; - def XVLSEG#nf#WU_V : XVLxU; - def XVLSEG#nf#E_V : XVLxU; - def XVSSEG#nf#B_V : XVSx; - def XVSSEG#nf#H_V : XVSx; - def XVSSEG#nf#W_V : XVSx; - def XVSSEG#nf#E_V : XVSx; - def XVLSEG#nf#BFF_V : XVLxFF; - def XVLSEG#nf#HFF_V : XVLxFF; - def XVLSEG#nf#WFF_V : XVLxFF; - def XVLSEG#nf#BUFF_V : XVLxUFF; - def XVLSEG#nf#HUFF_V : XVLxUFF; - def XVLSEG#nf#WUFF_V : XVLxUFF; - def XVLSEG#nf#EFF_V : XVLxUFF; + def TH_VLSEG#nf#B_V : TH_VLx; + def TH_VLSEG#nf#H_V : TH_VLx; + def TH_VLSEG#nf#W_V : TH_VLx; + def TH_VLSEG#nf#BU_V : TH_VLxU; + def TH_VLSEG#nf#HU_V : TH_VLxU; + def TH_VLSEG#nf#WU_V : TH_VLxU; + def TH_VLSEG#nf#E_V : TH_VLxU; + def TH_VSSEG#nf#B_V : TH_VSx; + def TH_VSSEG#nf#H_V : TH_VSx; + def TH_VSSEG#nf#W_V : TH_VSx; + def TH_VSSEG#nf#E_V : TH_VSx; + def TH_VLSEG#nf#BFF_V : TH_VLxFF; + def TH_VLSEG#nf#HFF_V : TH_VLxFF; + def TH_VLSEG#nf#WFF_V : TH_VLxFF; + def TH_VLSEG#nf#BUFF_V : TH_VLxUFF; + def TH_VLSEG#nf#HUFF_V : TH_VLxUFF; + def TH_VLSEG#nf#WUFF_V : TH_VLxUFF; + def TH_VLSEG#nf#EFF_V : TH_VLxUFF; // Vector Strided Segment Loads and Stores - def XVLSSEG#nf#B_V : XVLSx; - def XVLSSEG#nf#H_V : XVLSx; - def XVLSSEG#nf#W_V : XVLSx; - def XVLSSEG#nf#BU_V : XVLSxU; - def XVLSSEG#nf#HU_V : XVLSxU; - def XVLSSEG#nf#WU_V : XVLSxU; - def XVLSSEG#nf#E_V : XVLSxU; - def XVSSSEG#nf#B_V : XVSSx; - def XVSSSEG#nf#H_V : XVSSx; - def XVSSSEG#nf#W_V : XVSSx; - def XVSSSEG#nf#E_V : XVSSx; + def TH_VLSSEG#nf#B_V : TH_VLSx; + def TH_VLSSEG#nf#H_V : TH_VLSx; + def TH_VLSSEG#nf#W_V : TH_VLSx; + def TH_VLSSEG#nf#BU_V : TH_VLSxU; + def TH_VLSSEG#nf#HU_V : TH_VLSxU; + def TH_VLSSEG#nf#WU_V : TH_VLSxU; + def TH_VLSSEG#nf#E_V : TH_VLSxU; + def TH_VSSSEG#nf#B_V : TH_VSSx; + def TH_VSSSEG#nf#H_V : TH_VSSx; + def TH_VSSSEG#nf#W_V : TH_VSSx; + def TH_VSSSEG#nf#E_V : TH_VSSx; // Vector Indexed Segment Loads and Stores - def XVLXSEG#nf#B_V : XVLXx; - def XVLXSEG#nf#H_V : XVLXx; - def XVLXSEG#nf#W_V : XVLXx; - def XVLXSEG#nf#BU_V : XVLXxU; - def XVLXSEG#nf#HU_V : XVLXxU; - def XVLXSEG#nf#WU_V : XVLXxU; - def XVLXSEG#nf#E_V : XVLXxU; - def XVSXSEG#nf#B_V : XVSXx; - def XVSXSEG#nf#H_V : XVSXx; - def XVSXSEG#nf#W_V : XVSXx; - def XVSXSEG#nf#E_V : XVSXx; + def TH_VLXSEG#nf#B_V : TH_VLXx; + def TH_VLXSEG#nf#H_V : TH_VLXx; + def TH_VLXSEG#nf#W_V : TH_VLXx; + def TH_VLXSEG#nf#BU_V : TH_VLXxU; + def TH_VLXSEG#nf#HU_V : TH_VLXxU; + def TH_VLXSEG#nf#WU_V : TH_VLXxU; + def TH_VLXSEG#nf#E_V : TH_VLXxU; + def TH_VSXSEG#nf#B_V : TH_VSXx; + def TH_VSXSEG#nf#H_V : TH_VSXx; + def TH_VSXSEG#nf#W_V : TH_VSXx; + def TH_VSXSEG#nf#E_V : TH_VSXx; } } // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg] let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in { // Vector AMO Instruction - defm XVAMOSWAPW : XVAMO<0b00001, 0b110, "vamoswapw.v">; - defm XVAMOADDW : XVAMO<0b00000, 0b110, "vamoaddw.v">; - defm XVAMOXORW : XVAMO<0b00100, 0b110, "vamoxorw.v">; - defm XVAMOANDW : XVAMO<0b01100, 0b110, "vamoandw.v">; - defm XVAMOORW : XVAMO<0b01000, 0b110, "vamoorw.v">; - defm XVAMOMINW : XVAMO<0b10000, 0b110, "vamominw.v">; - defm XVAMOMAXW : XVAMO<0b10100, 0b110, "vamomaxw.v">; - defm XVAMOMINUW : XVAMO<0b11000, 0b110, "vamominuw.v">; - defm XVAMOMAXUW : XVAMO<0b11100, 0b110, "vamomaxuw.v">; - - defm XVAMOSWAPD : XVAMO<0b00001, 0b111, "vamoswapd.v">; - defm XVAMOADDD : XVAMO<0b00000, 0b111, "vamoaddd.v">; - defm XVAMOXORD : XVAMO<0b00100, 0b111, "vamoxord.v">; - defm XVAMOANDD : XVAMO<0b01100, 0b111, "vamoandd.v">; - defm XVAMOORD : XVAMO<0b01000, 0b111, "vamoord.v">; - defm XVAMOMIND : XVAMO<0b10000, 0b111, "vamomind.v">; - defm XVAMOMAXD : XVAMO<0b10100, 0b111, "vamomaxd.v">; - defm XVAMOMINUD : XVAMO<0b11000, 0b111, "vamominud.v">; - defm XVAMOMAXUD : XVAMO<0b11100, 0b111, "vamomaxud.v">; - - defm XVAMOSWAPQ : XVAMO<0b00001, 0b000, "vamoswapq.v">; - defm XVAMOADDQ : XVAMO<0b00000, 0b000, "vamoaddq.v">; - defm XVAMOXORQ : XVAMO<0b00100, 0b000, "vamoxorq.v">; - defm XVAMOANDQ : XVAMO<0b01100, 0b000, "vamoandq.v">; - defm XVAMOORQ : XVAMO<0b01000, 0b000, "vamoorq.v">; - defm XVAMOMINQ : XVAMO<0b10000, 0b000, "vamominq.v">; - defm XVAMOMAXQ : XVAMO<0b10100, 0b000, "vamomaxq.v">; - defm XVAMOMINUQ : XVAMO<0b11000, 0b000, "vamominuq.v">; - defm XVAMOMAXUQ : XVAMO<0b11100, 0b000, "vamomaxuq.v">; + defm TH_VAMOSWAPW : TH_VAMO<0b00001, 0b110, "th.vamoswapw.v">; + defm TH_VAMOADDW : TH_VAMO<0b00000, 0b110, "th.vamoaddw.v">; + defm TH_VAMOXORW : TH_VAMO<0b00100, 0b110, "th.vamoxorw.v">; + defm TH_VAMOANDW : TH_VAMO<0b01100, 0b110, "th.vamoandw.v">; + defm TH_VAMOORW : TH_VAMO<0b01000, 0b110, "th.vamoorw.v">; + defm TH_VAMOMINW : TH_VAMO<0b10000, 0b110, "th.vamominw.v">; + defm TH_VAMOMAXW : TH_VAMO<0b10100, 0b110, "th.vamomaxw.v">; + defm TH_VAMOMINUW : TH_VAMO<0b11000, 0b110, "th.vamominuw.v">; + defm TH_VAMOMAXUW : TH_VAMO<0b11100, 0b110, "th.vamomaxuw.v">; + + defm TH_VAMOSWAPD : TH_VAMO<0b00001, 0b111, "th.vamoswapd.v">; + defm TH_VAMOADDD : TH_VAMO<0b00000, 0b111, "th.vamoaddd.v">; + defm TH_VAMOXORD : TH_VAMO<0b00100, 0b111, "th.vamoxord.v">; + defm TH_VAMOANDD : TH_VAMO<0b01100, 0b111, "th.vamoandd.v">; + defm TH_VAMOORD : TH_VAMO<0b01000, 0b111, "th.vamoord.v">; + defm TH_VAMOMIND : TH_VAMO<0b10000, 0b111, "th.vamomind.v">; + defm TH_VAMOMAXD : TH_VAMO<0b10100, 0b111, "th.vamomaxd.v">; + defm TH_VAMOMINUD : TH_VAMO<0b11000, 0b111, "th.vamominud.v">; + defm TH_VAMOMAXUD : TH_VAMO<0b11100, 0b111, "th.vamomaxud.v">; + + defm TH_VAMOSWAPQ : TH_VAMO<0b00001, 0b000, "th.vamoswapq.v">; + defm TH_VAMOADDQ : TH_VAMO<0b00000, 0b000, "th.vamoaddq.v">; + defm TH_VAMOXORQ : TH_VAMO<0b00100, 0b000, "th.vamoxorq.v">; + defm TH_VAMOANDQ : TH_VAMO<0b01100, 0b000, "th.vamoandq.v">; + defm TH_VAMOORQ : TH_VAMO<0b01000, 0b000, "th.vamoorq.v">; + defm TH_VAMOMINQ : TH_VAMO<0b10000, 0b000, "th.vamominq.v">; + defm TH_VAMOMAXQ : TH_VAMO<0b10100, 0b000, "th.vamomaxq.v">; + defm TH_VAMOMINUQ : TH_VAMO<0b11000, 0b000, "th.vamominuq.v">; + defm TH_VAMOMAXUQ : TH_VAMO<0b11100, 0b000, "th.vamomaxuq.v">; } // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] let Predicates = [HasVendorXTHeadV] in { // Vector Single-Width Integer Add and Subtract -defm XVADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; -defm XVSUB_V : VALU_IV_V_X<"vsub", 0b000010>; -defm XVRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; +defm TH_VADD_V : VALU_IV_V_X_I<"th.vadd", 0b000000>; +defm TH_VSUB_V : VALU_IV_V_X<"th.vsub", 0b000010>; +defm TH_VRSUB_V : VALU_IV_X_I<"th.vrsub", 0b000011>; // Vector Widening Integer Add/Subtract // Refer to 11.2 Widening Vector Arithmetic Instructions @@ -420,42 +420,42 @@ defm XVRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; // if masked), otherwise an illegal instruction exception is raised. let Constraints = "@earlyclobber $vd" in { let RVVConstraint = WidenV in { -defm XVWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, "v">; -defm XVWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, "v">; -defm XVWADD_V : VALU_MV_V_X<"vwadd", 0b110001, "v">; -defm XVWSUB_V : VALU_MV_V_X<"vwsub", 0b110011, "v">; +defm TH_VWADDU_V : VALU_MV_V_X<"th.vwaddu", 0b110000, "v">; +defm TH_VWSUBU_V : VALU_MV_V_X<"th.vwsubu", 0b110010, "v">; +defm TH_VWADD_V : VALU_MV_V_X<"th.vwadd", 0b110001, "v">; +defm TH_VWSUB_V : VALU_MV_V_X<"th.vwsub", 0b110011, "v">; } // RVVConstraint = WidenV // Set earlyclobber for following instructions for second and mask operands. // This has the downside that the earlyclobber constraint is too coarse and // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. let RVVConstraint = WidenW in { -defm XVWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">; -defm XVWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">; -defm XVWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">; -defm XVWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">; +defm TH_VWADDU_W : VALU_MV_V_X<"th.vwaddu", 0b110100, "w">; +defm TH_VWSUBU_W : VALU_MV_V_X<"th.vwsubu", 0b110110, "w">; +defm TH_VWADD_W : VALU_MV_V_X<"th.vwadd", 0b110101, "w">; +defm TH_VWSUB_W : VALU_MV_V_X<"th.vwsub", 0b110111, "w">; } // RVVConstraint = WidenW } // Constraints = "@earlyclobber $vd" // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions -defm XVADC_V : XVALUm_IV_V_X_I<"vadc", 0b010000>; +defm TH_VADC_V : TH_VALUm_IV_V_X_I<"th.vadc", 0b010000>; let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { -defm XVMADC_V : XVALUm_IV_V_X_I<"vmadc", 0b010001>; +defm TH_VMADC_V : TH_VALUm_IV_V_X_I<"th.vmadc", 0b010001>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint -defm XVSBC_V : XVALUm_IV_V_X<"vsbc", 0b010010>; +defm TH_VSBC_V : TH_VALUm_IV_V_X<"th.vsbc", 0b010010>; let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { -defm XVMSBC_V : XVALUm_IV_V_X<"vmsbc", 0b010011>; +defm TH_VMSBC_V : TH_VALUm_IV_V_X<"th.vmsbc", 0b010011>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint // Vector Bitwise Logical Instructions -defm XVAND_V : VALU_IV_V_X_I<"vand", 0b001001>; -defm XVOR_V : VALU_IV_V_X_I<"vor", 0b001010>; -defm XVXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>; +defm TH_VAND_V : VALU_IV_V_X_I<"th.vand", 0b001001>; +defm TH_VOR_V : VALU_IV_V_X_I<"th.vor", 0b001010>; +defm TH_VXOR_V : VALU_IV_V_X_I<"th.vxor", 0b001011>; // Vector Single-Width Bit Shift Instructions -defm XVSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101>; -defm XVSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000>; -defm XVSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001>; +defm TH_VSLL_V : VSHT_IV_V_X_I<"th.vsll", 0b100101>; +defm TH_VSRL_V : VSHT_IV_V_X_I<"th.vsrl", 0b101000>; +defm TH_VSRA_V : VSHT_IV_V_X_I<"th.vsra", 0b101001>; // Vector Narrowing Integer Right Shift Instructions // Refer to 11.3. Narrowing Vector Arithmetic Instructions @@ -463,119 +463,119 @@ defm XVSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001>; // vector register group (specified by vs2). The destination vector register // group cannot overlap the mask register if used, unless LMUL=1. let Constraints = "@earlyclobber $vd" in { -defm XVNSRL_W : XVNSHT_IV_V_X_I<"vnsrl", 0b101100>; -defm XVNSRA_W : XVNSHT_IV_V_X_I<"vnsra", 0b101101>; +defm TH_VNSRL_W : TH_VNSHT_IV_V_X_I<"th.vnsrl", 0b101100>; +defm TH_VNSRA_W : TH_VNSHT_IV_V_X_I<"th.vnsra", 0b101101>; } // Constraints = "@earlyclobber $vd" // Vector Integer Comparison Instructions let RVVConstraint = NoConstraint in { -defm XVMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>; -defm XVMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>; -defm XVMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>; -defm XVMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>; -defm XVMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>; -defm XVMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>; -defm XVMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>; -defm XVMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>; +defm TH_VMSEQ_V : VCMP_IV_V_X_I<"th.vmseq", 0b011000>; +defm TH_VMSNE_V : VCMP_IV_V_X_I<"th.vmsne", 0b011001>; +defm TH_VMSLTU_V : VCMP_IV_V_X<"th.vmsltu", 0b011010>; +defm TH_VMSLT_V : VCMP_IV_V_X<"th.vmslt", 0b011011>; +defm TH_VMSLEU_V : VCMP_IV_V_X_I<"th.vmsleu", 0b011100>; +defm TH_VMSLE_V : VCMP_IV_V_X_I<"th.vmsle", 0b011101>; +defm TH_VMSGTU_V : VCMP_IV_X_I<"th.vmsgtu", 0b011110>; +defm TH_VMSGT_V : VCMP_IV_X_I<"th.vmsgt", 0b011111>; } // RVVConstraint = NoConstraint // Vector Integer Min/Max Instructions -defm XVMINU_V : VCMP_IV_V_X<"vminu", 0b000100>; -defm XVMIN_V : VCMP_IV_V_X<"vmin", 0b000101>; -defm XVMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>; -defm XVMAX_V : VCMP_IV_V_X<"vmax", 0b000111>; +defm TH_VMINU_V : VCMP_IV_V_X<"th.vminu", 0b000100>; +defm TH_VMIN_V : VCMP_IV_V_X<"th.vmin", 0b000101>; +defm TH_VMAXU_V : VCMP_IV_V_X<"th.vmaxu", 0b000110>; +defm TH_VMAX_V : VCMP_IV_V_X<"th.vmax", 0b000111>; // Vector Single-Width Integer Multiply Instructions -defm XVMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; -defm XVMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; -defm XVMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; -defm XVMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; +defm TH_VMUL_V : VMUL_MV_V_X<"th.vmul", 0b100101>; +defm TH_VMULH_V : VMUL_MV_V_X<"th.vmulh", 0b100111>; +defm TH_VMULHU_V : VMUL_MV_V_X<"th.vmulhu", 0b100100>; +defm TH_VMULHSU_V : VMUL_MV_V_X<"th.vmulhsu", 0b100110>; // Vector Integer Divide Instructions -defm XVDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>; -defm XVDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>; -defm XVREMU_V : VDIV_MV_V_X<"vremu", 0b100010>; -defm XVREM_V : VDIV_MV_V_X<"vrem", 0b100011>; +defm TH_VDIVU_V : VDIV_MV_V_X<"th.vdivu", 0b100000>; +defm TH_VDIV_V : VDIV_MV_V_X<"th.vdiv", 0b100001>; +defm TH_VREMU_V : VDIV_MV_V_X<"th.vremu", 0b100010>; +defm TH_VREM_V : VDIV_MV_V_X<"th.vrem", 0b100011>; // Vector Widening Integer Multiply Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm XVWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>; -defm XVWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>; -defm XVWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>; +defm TH_VWMUL_V : VWMUL_MV_V_X<"th.vwmul", 0b111011>; +defm TH_VWMULU_V : VWMUL_MV_V_X<"th.vwmulu", 0b111000>; +defm TH_VWMULSU_V : VWMUL_MV_V_X<"th.vwmulsu", 0b111010>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Single-Width Integer Multiply-Add Instructions -defm XVMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>; -defm XVNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>; -defm XVMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>; -defm XVNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>; +defm TH_VMACC_V : VMAC_MV_V_X<"th.vmacc", 0b101101>; +defm TH_VNMSAC_V : VMAC_MV_V_X<"th.vnmsac", 0b101111>; +defm TH_VMADD_V : VMAC_MV_V_X<"th.vmadd", 0b101001>; +defm TH_VNMSUB_V : VMAC_MV_V_X<"th.vnmsub", 0b101011>; // Vector Widening Integer Multiply-Add Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm XVWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>; -defm XVWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>; -defm XVWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111110>; -defm XVWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111111>; +defm TH_VWMACCU_V : VWMAC_MV_V_X<"th.vwmaccu", 0b111100>; +defm TH_VWMACC_V : VWMAC_MV_V_X<"th.vwmacc", 0b111101>; +defm TH_VWMACCSU_V : VWMAC_MV_V_X<"th.vwmaccsu", 0b111110>; +defm TH_VWMACCUS_V : VWMAC_MV_X<"th.vwmaccus", 0b111111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Integer Merge Instructions -defm XVMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>; +defm TH_VMERGE_V : VMRG_IV_V_X_I<"th.vmerge", 0b010111>; // Vector Integer Move Instructions let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1, RVVConstraint = NoConstraint in { // op vd, vs1 -def XVMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), - (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">, - Sched<[WriteVIMovV_WorstCase, ReadVIMovV_WorstCase]>; +def TH_VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), + (ins VR:$vs1), "th.vmv.v.v", "$vd, $vs1">, + Sched<[WriteVIMovV_WorstCase, ReadVIMovV_WorstCase]>; // op vd, rs1 -def XVMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), - (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">, - Sched<[WriteVIMovX_WorstCase, ReadVIMovX_WorstCase]>; +def TH_VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), + (ins GPR:$rs1), "th.vmv.v.x", "$vd, $rs1">, + Sched<[WriteVIMovX_WorstCase, ReadVIMovX_WorstCase]>; // op vd, imm -def XVMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), - (ins simm5:$imm), "vmv.v.i", "$vd, $imm">, - Sched<[WriteVIMovI_WorstCase]>; +def TH_VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), + (ins simm5:$imm), "th.vmv.v.i", "$vd, $imm">, + Sched<[WriteVIMovI_WorstCase]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 // Vector Fixed-Point Arithmetic Instructions -defm XVSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>; -defm XVSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>; -defm XVSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>; -defm XVSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>; +defm TH_VSADDU_V : VSALU_IV_V_X_I<"th.vsaddu", 0b100000>; +defm TH_VSADD_V : VSALU_IV_V_X_I<"th.vsadd", 0b100001>; +defm TH_VSSUBU_V : VSALU_IV_V_X<"th.vssubu", 0b100010>; +defm TH_VSSUB_V : VSALU_IV_V_X<"th.vssub", 0b100011>; // Vector Single-Width Averaging Add and Subtract -defm XVAADD_V : VSALU_IV_V_X_I<"vaadd", 0b100100>; -defm XVASUB_V : VSALU_IV_V_X<"vasub", 0b100110>; +defm TH_VAADD_V : VSALU_IV_V_X_I<"th.vaadd", 0b100100>; +defm TH_VASUB_V : VSALU_IV_V_X<"th.vasub", 0b100110>; // Vector Single-Width Fractional Multiply with Rounding and Saturation -defm XVSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; +defm TH_VSMUL_V : VSMUL_IV_V_X<"th.vsmul", 0b100111>; // Vector Widening Saturating Scaled Multiply-Add let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm XVWSMACCU_V : VWSMAC_V_X<"vwsmaccu", 0b111100>; -defm XVWSMACC_V : VWSMAC_V_X<"vwsmacc", 0b111101>; -defm XVWSMACCSU_V : VWSMAC_V_X<"vwsmaccsu", 0b111110>; -defm XVWSMACCUS_V : VWSMAC_X<"vwsmaccus", 0b111111>; +defm TH_VWSMACCU_V : TH_VWSMAC_V_X<"th.vwsmaccu", 0b111100>; +defm TH_VWSMACC_V : TH_VWSMAC_V_X<"th.vwsmacc", 0b111101>; +defm TH_VWSMACCSU_V : TH_VWSMAC_V_X<"th.vwsmaccsu", 0b111110>; +defm TH_VWSMACCUS_V : TH_VWSMAC_X<"th.vwsmaccus", 0b111111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Single-Width Scaling Shift Instructions -defm XVSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010>; -defm XVSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011>; +defm TH_VSSRL_V : VSSHF_IV_V_X_I<"th.vssrl", 0b101010>; +defm TH_VSSRA_V : VSSHF_IV_V_X_I<"th.vssra", 0b101011>; // Vector Narrowing Fixed-Point Clip Instructions let Constraints = "@earlyclobber $vd" in { -defm XVNCLIPU_W : XVNCLP_IV_V_X_I<"vnclipu", 0b101110>; -defm XVNCLIP_W : XVNCLP_IV_V_X_I<"vnclip", 0b101111>; +defm TH_VNCLIPU_W : TH_VNCLP_IV_V_X_I<"th.vnclipu", 0b101110>; +defm TH_VNCLIP_W : TH_VNCLP_IV_V_X_I<"th.vnclip", 0b101111>; } // Constraints = "@earlyclobber $vd" } // Predicates = [HasVendorXTHeadV] let Predicates = [HasVendorXTHeadV, HasStdExtF] in { // Vector Single-Width Floating-Point Add/Subtract Instructions let Uses = [FRM], mayRaiseFPException = true in { -defm XVFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; -defm XVFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; -defm XVFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>; +defm TH_VFADD_V : VALU_FV_V_F<"th.vfadd", 0b000000>; +defm TH_VFSUB_V : VALU_FV_V_F<"th.vfsub", 0b000010>; +defm TH_VFRSUB_V : VALU_FV_F<"th.vfrsub", 0b100111>; } // Vector Widening Floating-Point Add/Subtract Instructions @@ -583,109 +583,109 @@ let Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true in { let RVVConstraint = WidenV in { -defm XVFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000, "v">; -defm XVFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010, "v">; +defm TH_VFWADD_V : VWALU_FV_V_F<"th.vfwadd", 0b110000, "v">; +defm TH_VFWSUB_V : VWALU_FV_V_F<"th.vfwsub", 0b110010, "v">; } // RVVConstraint = WidenV // Set earlyclobber for following instructions for second and mask operands. // This has the downside that the earlyclobber constraint is too coarse and // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. let RVVConstraint = WidenW in { -defm XVFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">; -defm XVFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">; +defm TH_VFWADD_W : VWALU_FV_V_F<"th.vfwadd", 0b110100, "w">; +defm TH_VFWSUB_W : VWALU_FV_V_F<"th.vfwsub", 0b110110, "w">; } // RVVConstraint = WidenW } // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true // Vector Single-Width Floating-Point Multiply/Divide Instructions let Uses = [FRM], mayRaiseFPException = true in { -defm XVFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>; -defm XVFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>; -defm XVFRDIV_V : VDIV_FV_F<"vfrdiv", 0b100001>; +defm TH_VFMUL_V : VMUL_FV_V_F<"th.vfmul", 0b100100>; +defm TH_VFDIV_V : VDIV_FV_V_F<"th.vfdiv", 0b100000>; +defm TH_VFRDIV_V : VDIV_FV_F<"th.vfrdiv", 0b100001>; } // Vector Widening Floating-Point Multiply let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true in { -defm XVFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>; +defm TH_VFWMUL_V : VWMUL_FV_V_F<"th.vfwmul", 0b111000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true // Vector Single-Width Floating-Point Fused Multiply-Add Instructions let Uses = [FRM], mayRaiseFPException = true in { -defm XVFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>; -defm XVFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>; -defm XVFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>; -defm XVFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>; -defm XVFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>; -defm XVFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>; -defm XVFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>; -defm XVFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>; +defm TH_VFMACC_V : VMAC_FV_V_F<"th.vfmacc", 0b101100>; +defm TH_VFNMACC_V : VMAC_FV_V_F<"th.vfnmacc", 0b101101>; +defm TH_VFMSAC_V : VMAC_FV_V_F<"th.vfmsac", 0b101110>; +defm TH_VFNMSAC_V : VMAC_FV_V_F<"th.vfnmsac", 0b101111>; +defm TH_VFMADD_V : VMAC_FV_V_F<"th.vfmadd", 0b101000>; +defm TH_VFNMADD_V : VMAC_FV_V_F<"th.vfnmadd", 0b101001>; +defm TH_VFMSUB_V : VMAC_FV_V_F<"th.vfmsub", 0b101010>; +defm TH_VFNMSUB_V : VMAC_FV_V_F<"th.vfnmsub", 0b101011>; } // Vector Widening Floating-Point Fused Multiply-Add Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true in { -defm XVFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>; -defm XVFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>; -defm XVFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>; -defm XVFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>; +defm TH_VFWMACC_V : VWMAC_FV_V_F<"th.vfwmacc", 0b111100>; +defm TH_VFWNMACC_V : VWMAC_FV_V_F<"th.vfwnmacc", 0b111101>; +defm TH_VFWMSAC_V : VWMAC_FV_V_F<"th.vfwmsac", 0b111110>; +defm TH_VFWNMSAC_V : VWMAC_FV_V_F<"th.vfwnmsac", 0b111111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true // Vector Floating-Point Square-Root Instruction let Uses = [FRM], mayRaiseFPException = true in { -defm XVFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>; +defm TH_VFSQRT_V : VSQR_FV_VS2<"th.vfsqrt.v", 0b100011, 0b00000>; } // Vector Floating-Point MIN/MAX Instructions let mayRaiseFPException = true in { -defm XVFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>; -defm XVFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>; +defm TH_VFMIN_V : VCMP_FV_V_F<"th.vfmin", 0b000100>; +defm TH_VFMAX_V : VCMP_FV_V_F<"th.vfmax", 0b000110>; } // Vector Floating-Point Sign-Injection Instructions -defm XVFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>; -defm XVFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>; -defm XVFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>; +defm TH_VFSGNJ_V : VSGNJ_FV_V_F<"th.vfsgnj", 0b001000>; +defm TH_VFSGNJN_V : VSGNJ_FV_V_F<"th.vfsgnjn", 0b001001>; +defm TH_VFSGNJX_V : VSGNJ_FV_V_F<"th.vfsgnjx", 0b001010>; // Vector Floating-Point Compare Instructions let RVVConstraint = NoConstraint, mayRaiseFPException = true in { -defm XVMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>; -defm XVMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>; -defm XVMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>; -defm XVMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>; -defm XVMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>; -defm XVMFGE_V : VCMP_FV_F<"vmfge", 0b011111>; -defm XVMFORD_V : VCMP_FV_V_F<"vmford", 0b011010>; +defm TH_VMFEQ_V : VCMP_FV_V_F<"th.vmfeq", 0b011000>; +defm TH_VMFNE_V : VCMP_FV_V_F<"th.vmfne", 0b011100>; +defm TH_VMFLT_V : VCMP_FV_V_F<"th.vmflt", 0b011011>; +defm TH_VMFLE_V : VCMP_FV_V_F<"th.vmfle", 0b011001>; +defm TH_VMFGT_V : VCMP_FV_F<"th.vmfgt", 0b011101>; +defm TH_VMFGE_V : VCMP_FV_F<"th.vmfge", 0b011111>; +defm TH_VMFORD_V : VCMP_FV_V_F<"th.vmford", 0b011010>; } // RVVConstraint = NoConstraint, mayRaiseFPException = true // Vector Floating-Point Classify Instruction -defm XVFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b100011, 0b10000>; +defm TH_VFCLASS_V : VCLS_FV_VS2<"th.vfclass.v", 0b100011, 0b10000>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Vector Floating-Point Merge Instruction let vm = 0 in -def XVFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), - (ins VR:$vs2, FPR32:$rs1, VMV0:$v0), - "vfmerge.vfm", "$vd, $vs2, $rs1, v0">, - Sched<[WriteVFMergeV_WorstCase, ReadVFMergeV_WorstCase, - ReadVFMergeF_WorstCase, ReadVMask]>; +def TH_VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), + (ins VR:$vs2, FPR32:$rs1, VMV0:$v0), + "th.vfmerge.vfm", "$vd, $vs2, $rs1, v0">, + Sched<[WriteVFMergeV_WorstCase, ReadVFMergeV_WorstCase, + ReadVFMergeF_WorstCase, ReadVMask]>; // Vector Floating-Point Move Instruction let RVVConstraint = NoConstraint in let vm = 1, vs2 = 0 in -def XVFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), - (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, - Sched<[WriteVFMovV_WorstCase, ReadVFMovF_WorstCase]>; +def TH_VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), + (ins FPR32:$rs1), "th.vfmv.v.f", "$vd, $rs1">, + Sched<[WriteVFMovV_WorstCase, ReadVFMovF_WorstCase]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 // Single-Width Floating-Point/Integer Type-Convert Instructions let mayRaiseFPException = true in { let Uses = [FRM] in { -defm XVFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>; -defm XVFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>; -defm XVFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>; -defm XVFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>; +defm TH_VFCVT_XU_F_V : VCVTI_FV_VS2<"th.vfcvt.xu.f.v", 0b100010, 0b00000>; +defm TH_VFCVT_X_F_V : VCVTI_FV_VS2<"th.vfcvt.x.f.v", 0b100010, 0b00001>; +defm TH_VFCVT_F_XU_V : VCVTF_IV_VS2<"th.vfcvt.f.xu.v", 0b100010, 0b00010>; +defm TH_VFCVT_F_X_V : VCVTF_IV_VS2<"th.vfcvt.f.x.v", 0b100010, 0b00011>; } } // mayRaiseFPException = true @@ -693,22 +693,22 @@ defm XVFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>; let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt, mayRaiseFPException = true in { let Uses = [FRM] in { -defm XVFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>; -defm XVFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>; +defm TH_VFWCVT_XU_F_V : VWCVTI_FV_VS2<"th.vfwcvt.xu.f.v", 0b100010, 0b01000>; +defm TH_VFWCVT_X_F_V : VWCVTI_FV_VS2<"th.vfwcvt.x.f.v", 0b100010, 0b01001>; } -defm XVFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>; -defm XVFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>; -defm XVFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>; +defm TH_VFWCVT_F_XU_V : VWCVTF_IV_VS2<"th.vfwcvt.f.xu.v", 0b100010, 0b01010>; +defm TH_VFWCVT_F_X_V : VWCVTF_IV_VS2<"th.vfwcvt.f.x.v", 0b100010, 0b01011>; +defm TH_VFWCVT_F_F_V : VWCVTF_FV_VS2<"th.vfwcvt.f.f.v", 0b100010, 0b01100>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt // Narrowing Floating-Point/Integer Type-Convert Instructions let Constraints = "@earlyclobber $vd", mayRaiseFPException = true in { let Uses = [FRM] in { -defm XVFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.v", 0b100010, 0b10000>; -defm XVFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.v", 0b100010, 0b10001>; -defm XVFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.v", 0b100010, 0b10010>; -defm XVFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.v", 0b100010, 0b10011>; -defm XVFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.v", 0b100010, 0b10100>; +defm TH_VFNCVT_XU_F_W : VNCVTI_FV_VS2<"th.vfncvt.xu.f.v", 0b100010, 0b10000>; +defm TH_VFNCVT_X_F_W : VNCVTI_FV_VS2<"th.vfncvt.x.f.v", 0b100010, 0b10001>; +defm TH_VFNCVT_F_XU_W : VNCVTF_IV_VS2<"th.vfncvt.f.xu.v", 0b100010, 0b10010>; +defm TH_VFNCVT_F_X_W : VNCVTF_IV_VS2<"th.vfncvt.f.x.v", 0b100010, 0b10011>; +defm TH_VFNCVT_F_F_W : VNCVTF_FV_VS2<"th.vfncvt.f.f.v", 0b100010, 0b10100>; } } // Constraints = "@earlyclobber $vd", mayRaiseFPException = true } // Predicates = [HasVendorXTHeadV, HasStdExtF] @@ -716,14 +716,14 @@ defm XVFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.v", 0b100010, 0b10100>; let Predicates = [HasVendorXTHeadV] in { // Vector Single-Width Integer Reduction Instructions let RVVConstraint = NoConstraint in { -defm XVREDSUM : VRED_MV_V<"vredsum", 0b000000>; -defm XVREDMAXU : VRED_MV_V<"vredmaxu", 0b000110>; -defm XVREDMAX : VRED_MV_V<"vredmax", 0b000111>; -defm XVREDMINU : VRED_MV_V<"vredminu", 0b000100>; -defm XVREDMIN : VRED_MV_V<"vredmin", 0b000101>; -defm XVREDAND : VRED_MV_V<"vredand", 0b000001>; -defm XVREDOR : VRED_MV_V<"vredor", 0b000010>; -defm XVREDXOR : VRED_MV_V<"vredxor", 0b000011>; +defm TH_VREDSUM : VRED_MV_V<"th.vredsum", 0b000000>; +defm TH_VREDMAXU : VRED_MV_V<"th.vredmaxu", 0b000110>; +defm TH_VREDMAX : VRED_MV_V<"th.vredmax", 0b000111>; +defm TH_VREDMINU : VRED_MV_V<"th.vredminu", 0b000100>; +defm TH_VREDMIN : VRED_MV_V<"th.vredmin", 0b000101>; +defm TH_VREDAND : VRED_MV_V<"th.vredand", 0b000001>; +defm TH_VREDOR : VRED_MV_V<"th.vredor", 0b000010>; +defm TH_VREDXOR : VRED_MV_V<"th.vredxor", 0b000011>; } // RVVConstraint = NoConstraint // Vector Widening Integer Reduction Instructions @@ -732,8 +732,8 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { // This has the downside that the earlyclobber constraint is too coarse and // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. -defm XVWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>; -defm XVWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>; +defm TH_VWREDSUMU : VWRED_IV_V<"th.vwredsumu", 0b110000>; +defm TH_VWREDSUM : VWRED_IV_V<"th.vwredsum", 0b110001>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint } // Predicates = [HasVendorXTHeadV] @@ -742,12 +742,12 @@ let Predicates = [HasVendorXTHeadV, HasStdExtF] in { // Vector Single-Width Floating-Point Reduction Instructions let RVVConstraint = NoConstraint in { let Uses = [FRM], mayRaiseFPException = true in { -defm XVFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; -defm XVFREDUSUM : VRED_FV_V<"vfredsum", 0b000001>; +defm TH_VFREDOSUM : VREDO_FV_V<"th.vfredosum", 0b000011>; +defm TH_VFREDUSUM : VRED_FV_V<"th.vfredsum", 0b000001>; } let mayRaiseFPException = true in { -defm XVFREDMAX : VRED_FV_V<"vfredmax", 0b000111>; -defm XVFREDMIN : VRED_FV_V<"vfredmin", 0b000101>; +defm TH_VFREDMAX : VRED_FV_V<"th.vfredmax", 0b000111>; +defm TH_VFREDMIN : VRED_FV_V<"th.vfredmin", 0b000101>; } } // RVVConstraint = NoConstraint @@ -758,8 +758,8 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. let Uses = [FRM], mayRaiseFPException = true in { -defm XVFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>; -defm XVFWREDUSUM : VWRED_FV_V<"vfwredsum", 0b110001>; +defm TH_VFWREDOSUM : VWREDO_FV_V<"th.vfwredosum", 0b110011>; +defm TH_VFWREDUSUM : VWRED_FV_V<"th.vfwredsum", 0b110001>; } } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint } // Predicates = [HasVendorXTHeadV, HasStdExtF] @@ -767,69 +767,69 @@ defm XVFWREDUSUM : VWRED_FV_V<"vfwredsum", 0b110001>; let Predicates = [HasVendorXTHeadV] in { // Vector Mask-Register Logical Instructions let RVVConstraint = NoConstraint in { -defm XVMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">; -defm XVMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">; -defm XVMANDN_M : VMALU_MV_Mask<"vmandnot", 0b011000, "m">; -defm XVMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">; -defm XVMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">; -defm XVMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">; -defm XVMORN_M : VMALU_MV_Mask<"vmornot", 0b011100, "m">; -defm XVMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">; +defm TH_VMAND_M : VMALU_MV_Mask<"th.vmand", 0b011001, "m">; +defm TH_VMNAND_M : VMALU_MV_Mask<"th.vmnand", 0b011101, "m">; +defm TH_VMANDN_M : VMALU_MV_Mask<"th.vmandnot", 0b011000, "m">; +defm TH_VMXOR_M : VMALU_MV_Mask<"th.vmxor", 0b011011, "m">; +defm TH_VMOR_M : VMALU_MV_Mask<"th.vmor", 0b011010, "m">; +defm TH_VMNOR_M : VMALU_MV_Mask<"th.vmnor", 0b011110, "m">; +defm TH_VMORN_M : VMALU_MV_Mask<"th.vmornot", 0b011100, "m">; +defm TH_VMXNOR_M : VMALU_MV_Mask<"th.vmxnor", 0b011111, "m">; } let hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint in { // Vector mask population count vmpopc -def XVMPOPC_M : RVInstV<0b010100, 0b00000, OPMVV, (outs GPR:$vd), - (ins VR:$vs2, VMaskOp:$vm), - "vmpopc.m", "$vd, $vs2$vm">, - Sched<[WriteVMPopV_WorstCase, ReadVMPopV_WorstCase, - ReadVMask]>; +def TH_VMPOPC_M : RVInstV<0b010100, 0b00000, OPMVV, (outs GPR:$vd), + (ins VR:$vs2, VMaskOp:$vm), + "th.vmpopc.m", "$vd, $vs2$vm">, + Sched<[WriteVMPopV_WorstCase, ReadVMPopV_WorstCase, + ReadVMask]>; // vmfirst find-first-set mask bit -def XVMFIRST_M : RVInstV<0b010101, 0b00000, OPMVV, (outs GPR:$vd), - (ins VR:$vs2, VMaskOp:$vm), - "vmfirst.m", "$vd, $vs2$vm">, - Sched<[WriteVMFFSV_WorstCase, ReadVMFFSV_WorstCase, - ReadVMask]>; +def TH_VMFIRST_M : RVInstV<0b010101, 0b00000, OPMVV, (outs GPR:$vd), + (ins VR:$vs2, VMaskOp:$vm), + "th.vmfirst.m", "$vd, $vs2$vm">, + Sched<[WriteVMFFSV_WorstCase, ReadVMFFSV_WorstCase, + ReadVMask]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { // vmsbf.m set-before-first mask bit -defm XVMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010110, 0b00001>; +defm TH_VMSBF_M : VMSFS_MV_V<"th.vmsbf.m", 0b010110, 0b00001>; // vmsif.m set-including-first mask bit -defm XVMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010110, 0b00011>; +defm TH_VMSIF_M : VMSFS_MV_V<"th.vmsif.m", 0b010110, 0b00011>; // vmsof.m set-only-first mask bit -defm XVMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010110, 0b00010>; +defm TH_VMSOF_M : VMSFS_MV_V<"th.vmsof.m", 0b010110, 0b00010>; // Vector Iota Instruction -defm XVIOTA_M : VMIOT_MV_V<"viota.m", 0b010110, 0b10000>; +defm TH_VIOTA_M : VMIOT_MV_V<"th.viota.m", 0b010110, 0b10000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Vector Element Index Instruction let vs2 = 0 in -def XVID_V : RVInstV<0b010110, 0b10001, OPMVV, (outs VR:$vd), - (ins VMaskOp:$vm), "vid.v", "$vd$vm">, - Sched<[WriteVMIdxV_WorstCase, ReadVMask]>; +def TH_VID_V : RVInstV<0b010110, 0b10001, OPMVV, (outs VR:$vd), + (ins VMaskOp:$vm), + "th.vid.v", "$vd$vm">, + Sched<[WriteVMIdxV_WorstCase, ReadVMask]>; let vm = 1, RVVConstraint = NoConstraint in { // Integer Extract Instruction -def XVEXT_X_V : RVInstVX<0b001100, OPMVV, (outs GPR:$vd), - (ins VR:$vs2, GPR:$rs1), - "vext.x.v", "$vd, $vs2, $rs1">, - Sched<[WriteVIMovVX, ReadVIMovVX, - ReadVIMovXX]>; +def TH_VEXT_X_V : RVInstVX<0b001100, OPMVV, (outs GPR:$vd), + (ins VR:$vs2, GPR:$rs1), + "th.vext.x.v", "$vd, $vs2, $rs1">, + Sched<[WriteVIMovVX, ReadVIMovVX, ReadVIMovXX]>; // Integer Scalar Move Instruction let Constraints = "$vd = $vd_wb" in -def XVMV_S_X : RVInstV2<0b001101, 0b00000, OPMVX, (outs VR:$vd_wb), - (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, - Sched<[WriteVIMovXV, ReadVIMovXV, - ReadVIMovXX]>; +def TH_VMV_S_X : RVInstV2<0b001101, 0b00000, OPMVX, (outs VR:$vd_wb), + (ins VR:$vd, GPR:$rs1), + "th.vmv.s.x", "$vd, $rs1">, + Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>; } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXTHeadV] @@ -838,14 +838,15 @@ let Predicates = [HasVendorXTHeadV, HasStdExtF] in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, RVVConstraint = NoConstraint in { // Floating-Point Scalar Move Instructions -def XVFMV_F_S : RVInstV<0b001100, 0b00000, OPFVV, (outs FPR32:$vd), - (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, - Sched<[WriteVFMovVF, ReadVFMovVF]>; +def TH_VFMV_F_S : RVInstV<0b001100, 0b00000, OPFVV, (outs FPR32:$vd), + (ins VR:$vs2), + "th.vfmv.f.s", "$vd, $vs2">, + Sched<[WriteVFMovVF, ReadVFMovVF]>; let Constraints = "$vd = $vd_wb" in -def XVFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb), - (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">, - Sched<[WriteVFMovFV, ReadVFMovFV, - ReadVFMovFX]>; +def TH_VFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb), + (ins VR:$vd, FPR32:$rs1), + "th.vfmv.s.f", "$vd, $rs1">, + Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 } // Predicates = [HasVendorXTHeadV, HasStdExtF] @@ -853,36 +854,35 @@ def XVFMV_S_F : RVInstV2<0b001101, 0b00000, OPFVF, (outs VR:$vd_wb), let Predicates = [HasVendorXTHeadV] in { // Vector Slide Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { -defm XVSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110>; -defm XVSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>; +defm TH_VSLIDEUP_V : VSLD_IV_X_I<"th.vslideup", 0b001110>; +defm TH_VSLIDE1UP_V : VSLD1_MV_X<"th.vslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp -defm XVSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111>; -defm XVSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>; +defm TH_VSLIDEDOWN_V : VSLD_IV_X_I<"th.vslidedown", 0b001111>; +defm TH_VSLIDE1DOWN_V : VSLD1_MV_X<"th.vslide1down", 0b001111>; // Vector Register Gather Instruction let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { -defm XVRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>; +defm TH_VRGATHER_V : VGTR_IV_V_X_I<"th.vrgather", 0b001100>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather // Vector Compress Instruction let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { -defm XVCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>; +defm TH_VCOMPRESS_V : VCPR_MV_Mask<"th.vcompress", 0b010111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress } // Predicates = [HasVendorXTHeadV] -} // AsmVariantName = "RVV0p71", DecoderNamespace = "RVV0p71" +} // DecoderNamespace = "RVV0p71" // Pseudo instructions -let AsmVariantName = "RVV0p71" in { let Predicates = [HasVendorXTHeadV] in { // Vector Integer Comparison Instructions -def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm", - (XVMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; -def : InstAlias<"vmsgt.vv $vd, $va, $vb$vm", - (XVMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; -def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm", - (XVMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; -def : InstAlias<"vmsge.vv $vd, $va, $vb$vm", - (XVMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; +def : InstAlias<"th.vmsgtu.vv $vd, $va, $vb$vm", + (TH_VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; +def : InstAlias<"th.vmsgt.vv $vd, $va, $vb$vm", + (TH_VMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; +def : InstAlias<"th.vmsgeu.vv $vd, $va, $vb$vm", + (TH_VMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; +def : InstAlias<"th.vmsge.vv $vd, $va, $vb$vm", + (TH_VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; // These pseudos need to be handled in RISCVAsmParser::processInstruction let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, @@ -892,83 +892,82 @@ let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, // immediate like we do for signed. To match the GNU assembler we will use // vmseq/vmsne.vv with the same register for both operands which we can't do // from an InstAlias. -def PseudoXVMSGEU_VI : Pseudo<(outs VR:$vd), - (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), - [], "vmsgeu.vi", "$vd, $vs2, $imm$vm">; -def PseudoXVMSLTU_VI : Pseudo<(outs VR:$vd), - (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), - [], "vmsltu.vi", "$vd, $vs2, $imm$vm">; +def PseudoTH_VMSGEU_VI : Pseudo<(outs VR:$vd), + (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), + [], "th.vmsgeu.vi", "$vd, $vs2, $imm$vm">; +def PseudoTH_VMSLTU_VI : Pseudo<(outs VR:$vd), + (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), + [], "th.vmsltu.vi", "$vd, $vs2, $imm$vm">; // Handle signed with pseudos as well for more consistency in the // implementation. -def PseudoXVMSGE_VI : Pseudo<(outs VR:$vd), - (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), - [], "vmsge.vi", "$vd, $vs2, $imm$vm">; -def PseudoXVMSLT_VI : Pseudo<(outs VR:$vd), - (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), - [], "vmslt.vi", "$vd, $vs2, $imm$vm">; +def PseudoTH_VMSGE_VI : Pseudo<(outs VR:$vd), + (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), + [], "th.vmsge.vi", "$vd, $vs2, $imm$vm">; +def PseudoTH_VMSLT_VI : Pseudo<(outs VR:$vd), + (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), + [], "th.vmslt.vi", "$vd, $vs2, $imm$vm">; } // These pseudos need to be handled in RISCVAsmParser::processInstruction let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { -def PseudoXVMSGEU_VX : Pseudo<(outs VR:$vd), - (ins VR:$vs2, GPR:$rs1), - [], "vmsgeu.vx", "$vd, $vs2, $rs1">; -def PseudoXVMSGE_VX : Pseudo<(outs VR:$vd), - (ins VR:$vs2, GPR:$rs1), - [], "vmsge.vx", "$vd, $vs2, $rs1">; -def PseudoXVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd), - (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), - [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">; -def PseudoXVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd), - (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), - [], "vmsge.vx", "$vd, $vs2, $rs1$vm">; -def PseudoXVMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), +def PseudoTH_VMSGEU_VX : Pseudo<(outs VR:$vd), + (ins VR:$vs2, GPR:$rs1), + [], "th.vmsgeu.vx", "$vd, $vs2, $rs1">; +def PseudoTH_VMSGE_VX : Pseudo<(outs VR:$vd), + (ins VR:$vs2, GPR:$rs1), + [], "th.vmsge.vx", "$vd, $vs2, $rs1">; +def PseudoTH_VMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd), (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), - [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">; -def PseudoXVMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), + [], "th.vmsgeu.vx", "$vd, $vs2, $rs1$vm">; +def PseudoTH_VMSGE_VX_M : Pseudo<(outs VRNoV0:$vd), (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), - [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; + [], "th.vmsge.vx", "$vd, $vs2, $rs1$vm">; +def PseudoTH_VMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), + (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), + [], "th.vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">; +def PseudoTH_VMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), + (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), + [], "th.vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; } // isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 // Vector Floating-Point Compare Instructions -def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm", - (XVMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; -def : InstAlias<"vmfge.vv $vd, $va, $vb$vm", - (XVMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; +def : InstAlias<"th.vmfgt.vv $vd, $va, $vb$vm", + (TH_VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; +def : InstAlias<"th.vmfge.vv $vd, $va, $vb$vm", + (TH_VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; // Vector Bitwise Logical Instructions -def : InstAlias<"vnot.v $vd, $vs$vm", - (XVXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>; -def : InstAlias<"vnot.v $vd, $vs", - (XVXOR_VI VR:$vd, VR:$vs, -1, zero_reg)>; +def : InstAlias<"th.vnot.v $vd, $vs$vm", + (TH_VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>; +def : InstAlias<"th.vnot.v $vd, $vs", + (TH_VXOR_VI VR:$vd, VR:$vs, -1, zero_reg)>; // Vector Widening Integer Add/Subtract -def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm", - (XVWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; -def : InstAlias<"vwcvt.x.x.v $vd, $vs", - (XVWADD_VX VR:$vd, VR:$vs, X0, zero_reg)>; -def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm", - (XVWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; -def : InstAlias<"vwcvtu.x.x.v $vd, $vs", - (XVWADDU_VX VR:$vd, VR:$vs, X0, zero_reg)>; +def : InstAlias<"th.vwcvt.x.x.v $vd, $vs$vm", + (TH_VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; +def : InstAlias<"th.vwcvt.x.x.v $vd, $vs", + (TH_VWADD_VX VR:$vd, VR:$vs, X0, zero_reg)>; +def : InstAlias<"th.vwcvtu.x.x.v $vd, $vs$vm", + (TH_VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; +def : InstAlias<"th.vwcvtu.x.x.v $vd, $vs", + (TH_VWADDU_VX VR:$vd, VR:$vs, X0, zero_reg)>; // Integer Extract Instruction -def : InstAlias<"vmv.x.s $rd, $vs", - (XVEXT_X_V GPR:$rd, VR:$vs, X0)>; +def : InstAlias<"th.vmv.x.s $rd, $vs", + (TH_VEXT_X_V GPR:$rd, VR:$vs, X0)>; // Vector Mask-Register Logical Instructions -def : InstAlias<"vmcpy.m $vd, $vs", - (XVMAND_MM VR:$vd, VR:$vs, VR:$vs)>; -def : InstAlias<"vmclr.m $vd", - (XVMXOR_MM VR:$vd, VR:$vd, VR:$vd)>; -def : InstAlias<"vmset.m $vd", - (XVMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>; -def : InstAlias<"vmnot.m $vd, $vs", - (XVMNAND_MM VR:$vd, VR:$vs, VR:$vs)>; +def : InstAlias<"th.vmcpy.m $vd, $vs", + (TH_VMAND_MM VR:$vd, VR:$vs, VR:$vs)>; +def : InstAlias<"th.vmclr.m $vd", + (TH_VMXOR_MM VR:$vd, VR:$vd, VR:$vd)>; +def : InstAlias<"th.vmset.m $vd", + (TH_VMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>; +def : InstAlias<"th.vmnot.m $vd, $vs", + (TH_VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>; } // Predicates = [HasVendorXTHeadV] -} // AsmVariantName = "RVV0p71" include "RISCVInstrInfoXTHeadVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td index 9a51a9828b589..190201161c51d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td @@ -144,7 +144,7 @@ def XTHeadVVSTable : GenericTable { // // Some intrinsics may be lowered manually (for example, `RSICVISelDAGToDAG.cpp`). // Patterns are not needed for these instructions, like -// `int_riscv_xvsetvl` and `int_riscv_xvsetvlmax` in `IntrinsicRISCVXTHeadV.td`. +// `int_riscv_th_vsetvl` and `int_riscv_th_vsetvlmax` in `IntrinsicRISCVXTHeadV.td`. //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// @@ -154,10 +154,10 @@ def XTHeadVVSTable : GenericTable { // These can't be reused, since the vtypei in rvv 0.7 differs from the one in rvv 1.0 let Predicates = [HasVendorXTHeadV] in { let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in { - def PseudoXVSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, XTHeadVTypeI:$vtypei), []>, - Sched<[WriteVSETVLI, ReadVSETVLI]>; - def PseudoXVSETVLIX0 : Pseudo<(outs GPR:$rd), (ins GPRX0:$rs1, XTHeadVTypeI:$vtypei), []>, + def PseudoTH_VSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, XTHeadVTypeI:$vtypei), []>, Sched<[WriteVSETVLI, ReadVSETVLI]>; + def PseudoTH_VSETVLIX0 : Pseudo<(outs GPR:$rd), (ins GPRX0:$rs1, XTHeadVTypeI:$vtypei), []>, + Sched<[WriteVSETVLI, ReadVSETVLI]>; } } // Predicates = [HasVendorXTHeadV] @@ -640,15 +640,15 @@ multiclass XVPseudoFFLoad { } let Predicates = [HasVendorXTHeadV] in { - defm PseudoXVL : XVPseudoUSLoad; - defm PseudoXVS : XVPseudoUSStore; - defm PseudoXVL : XVPseudoSLoad; - defm PseudoXVS : XVPseudoSStore; - defm PseudoXVL : XVPseudoILoad; - defm PseudoXVS : XVPseudoIStore; + defm PseudoTH_VL : XVPseudoUSLoad; + defm PseudoTH_VS : XVPseudoUSStore; + defm PseudoTH_VL : XVPseudoSLoad; + defm PseudoTH_VS : XVPseudoSStore; + defm PseudoTH_VL : XVPseudoILoad; + defm PseudoTH_VS : XVPseudoIStore; let hasSideEffects = 1, Defs = [VL] in - defm PseudoXVL : XVPseudoFFLoad; + defm PseudoTH_VL : XVPseudoFFLoad; } // Predicates = [HasVendorXTHeadV] //===----------------------------------------------------------------------===// @@ -656,17 +656,17 @@ let Predicates = [HasVendorXTHeadV] in { // for emulating Vector Load/Store Whole Register Instructions in RVV 1.0 //===----------------------------------------------------------------------===// -// This part defines the pseudo `PseudoXVLE_V_M*` and `PseudoXVSE_V_M*`, +// This part defines the pseudo `PseudoTH_VLE_V_M*` and `PseudoTH_VSE_V_M*`, // with the type of operands being VRM2, VRM4 and VRM8. -// We cannot directly convert `PseudoXVLR` or `PseudoXVSR` to `XVLE_V` or `XVSE_V`, +// We cannot directly convert `PseudoTH_VLR` or `PseudoTH_VSR` to `TH_VLE_V` or `TH_VSE_V`, // which will be reported as ill-typed program by the type checker. // See https://github.com/ruyisdk/llvm-project/pull/23#issuecomment-1816071060 for details. // In the following, we define such pseudos only to make the type checker happy. // As the types in these pseudos are always erased when lowering to MCInst. -// TODO: consider using `PseudoXVLE_V_E*_M*` and `PseudoXVSE_V_E*_M*` defined above, +// TODO: consider using `PseudoTH_VLE_V_E*_M*` and `PseudoTH_VSE_V_E*_M*` defined above, // but these pseudos seems to require more operands like `AVL:$vl, ixlenimm:$sew`, -// some of which are not available in the original `PseudoXVLR` and `PseudoXVSR`. +// some of which are not available in the original `PseudoTH_VLR` and `PseudoTH_VSR`. multiclass XVPseudoWellTypedUSLoadStore_VLE { foreach lmul = MxListXTHeadV in { @@ -695,12 +695,12 @@ multiclass XVPseudoWellTypedUSLoadStore_VSE { // Set `isCodeGenOnly = 1` to hide them from the tablegened assembly parser, // to avoid decoding conflict with the original `vle.v` and `vse.v` in RISCVInstraInfoXTHeadV.td let Predicates = [HasVendorXTHeadV], isCodeGenOnly = 1 in { - defm PseudoXVLE_V : XVPseudoWellTypedUSLoadStore_VLE; - defm PseudoXVSE_V : XVPseudoWellTypedUSLoadStore_VSE; + defm PseudoTH_VLE_V : XVPseudoWellTypedUSLoadStore_VLE; + defm PseudoTH_VSE_V : XVPseudoWellTypedUSLoadStore_VSE; } // Predicates = [HasVendorXTHeadV], isCodeGenOnly = 1 // This part defines the pseudo version of `vlr.v` and `vsr.v`, -// that is, `PseudoXVLR` and `PseudoXVSR`, +// that is, `PseudoTH_VLR` and `PseudoTH_VSR`, // and explcitly binds them to LLVM IR `load`/`store` intrinsic calls // in the instruction selection process, which enables directly // loading/storing a vector register in LLVM IR with builtin `load`/`store`, @@ -715,7 +715,7 @@ multiclass XVPseudoWholeLoadN nf, LMULInfo m, RegisterClass VRC> { foreach l = EEWList in { defvar s = !cast("WriteVLD" # !add(nf, 1) # "R"); - def E # l # _V : XVPseudoWholeLoad, + def E # l # _V : XVPseudoWholeLoad, Sched<[s, ReadVLDX]>; } } @@ -729,29 +729,29 @@ multiclass XVPseudoWholeStoreN nf, LMULInfo m, RegisterClass VRC> { defvar sw = !cast("WriteVST" # !add(nf, 1) # "R"); defvar sr = !cast("ReadVST" # !add(nf, 1) # "R"); - def E # l # _V : XVPseudoWholeStore, + def E # l # _V : XVPseudoWholeStore, Sched<[sw, sr, ReadVSTX]>; } } // Set `usesCustomInserter = 1` to lower these manually -// to `PseudoXVLE_V_M*` or `PseudoXVSE_V_M*` defined above. +// to `PseudoTH_VLE_V_M*` or `PseudoTH_VSE_V_M*` defined above. // See: RISCVISelLowering.cpp, function `RISCVTargetLowering::EmitInstrWithCustomInserter` // and `emitXWholeLoadStore`. let Predicates = [HasVendorXTHeadV] in { // Whole register load let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1, usesCustomInserter = 1 in { - defm PseudoXVL1R : XVPseudoWholeLoadN<0, V_M1, VR>; - defm PseudoXVL2R : XVPseudoWholeLoadN<1, V_M2, VRM2>; - defm PseudoXVL4R : XVPseudoWholeLoadN<3, V_M4, VRM4>; - defm PseudoXVL8R : XVPseudoWholeLoadN<7, V_M8, VRM8>; + defm PseudoTH_VL1R : XVPseudoWholeLoadN<0, V_M1, VR>; + defm PseudoTH_VL2R : XVPseudoWholeLoadN<1, V_M2, VRM2>; + defm PseudoTH_VL4R : XVPseudoWholeLoadN<3, V_M4, VRM4>; + defm PseudoTH_VL8R : XVPseudoWholeLoadN<7, V_M8, VRM8>; } // Whole register store let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { - defm PseudoXVS1R : XVPseudoWholeStoreN<0, V_M1, VR>; - defm PseudoXVS2R : XVPseudoWholeStoreN<1, V_M2, VRM2>; - defm PseudoXVS4R : XVPseudoWholeStoreN<3, V_M4, VRM4>; - defm PseudoXVS8R : XVPseudoWholeStoreN<7, V_M8, VRM8>; + defm PseudoTH_VS1R : XVPseudoWholeStoreN<0, V_M1, VR>; + defm PseudoTH_VS2R : XVPseudoWholeStoreN<1, V_M2, VRM2>; + defm PseudoTH_VS4R : XVPseudoWholeStoreN<3, V_M4, VRM4>; + defm PseudoTH_VS8R : XVPseudoWholeStoreN<7, V_M8, VRM8>; } } // Predicates = [HasVendorXTHeadV] @@ -762,9 +762,9 @@ multiclass XVPatUSLoadStoreWholeVRSDNode { defvar load_instr = - !cast("PseudoXVL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V"); + !cast("PseudoTH_VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V"); defvar store_instr = - !cast("PseudoXVS"#!substr(vlmul.MX, 1)#"RE"#sew#"_V"); + !cast("PseudoTH_VS"#!substr(vlmul.MX, 1)#"RE"#sew#"_V"); // Load def : Pat<(type (load GPR:$rs1)), @@ -851,15 +851,15 @@ multiclass XVPseudoAMO { } let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in { - defm PseudoXVAMOSWAP : XVPseudoAMO; - defm PseudoXVAMOADD : XVPseudoAMO; - defm PseudoXVAMOXOR : XVPseudoAMO; - defm PseudoXVAMOAND : XVPseudoAMO; - defm PseudoXVAMOOR : XVPseudoAMO; - defm PseudoXVAMOMIN : XVPseudoAMO; - defm PseudoXVAMOMAX : XVPseudoAMO; - defm PseudoXVAMOMINU : XVPseudoAMO; - defm PseudoXVAMOMAXU : XVPseudoAMO; + defm PseudoTH_VAMOSWAP : XVPseudoAMO; + defm PseudoTH_VAMOADD : XVPseudoAMO; + defm PseudoTH_VAMOXOR : XVPseudoAMO; + defm PseudoTH_VAMOAND : XVPseudoAMO; + defm PseudoTH_VAMOOR : XVPseudoAMO; + defm PseudoTH_VAMOMIN : XVPseudoAMO; + defm PseudoTH_VAMOMAX : XVPseudoAMO; + defm PseudoTH_VAMOMINU : XVPseudoAMO; + defm PseudoTH_VAMOMAXU : XVPseudoAMO; } // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] // Patterns for vamo intrinsics. @@ -939,15 +939,15 @@ multiclass XVPatAMOV_WD; - defm : XVPatAMOV_WD<"int_riscv_xvamoadd", "PseudoXVAMOADD", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamoxor", "PseudoXVAMOXOR", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamoand", "PseudoXVAMOAND", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamoor", "PseudoXVAMOOR", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamomin", "PseudoXVAMOMIN", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamomax", "PseudoXVAMOMAX", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamominu", "PseudoXVAMOMINU", AllIntegerXVectors>; - defm : XVPatAMOV_WD<"int_riscv_xvamomaxu", "PseudoXVAMOMAXU", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamoswap", "PseudoTH_VAMOSWAP", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamoadd", "PseudoTH_VAMOADD", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamoxor", "PseudoTH_VAMOXOR", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamoand", "PseudoTH_VAMOAND", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamoor", "PseudoTH_VAMOOR", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamomin", "PseudoTH_VAMOMIN", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamomax", "PseudoTH_VAMOMAX", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamominu", "PseudoTH_VAMOMINU", AllIntegerXVectors>; + defm : XVPatAMOV_WD<"int_riscv_th_vamomaxu", "PseudoTH_VAMOMAXU", AllIntegerXVectors>; } // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] //===----------------------------------------------------------------------===// @@ -972,11 +972,11 @@ multiclass XVPseudoVALU_VV_VX_VI; + defm : VPatBinaryV_VV_VX_VI<"int_riscv_th_vadd", "PseudoTH_VADD", AllIntegerXVectors>; } // Predicates = [HasVendorXTHeadV] //===----------------------------------------------------------------------===// @@ -1005,17 +1005,17 @@ multiclass XVPseudoUnaryVMV_V_X_I { } let Predicates = [HasVendorXTHeadV] in { - defm PseudoXVMV_V : XVPseudoUnaryVMV_V_X_I; + defm PseudoTH_VMV_V : XVPseudoUnaryVMV_V_X_I; } // Predicates = [HasVendorXTHeadV] -// Patterns for `int_riscv_vmv_v_v` -> `PseudoXVMV_V_V_` +// Patterns for `int_riscv_vmv_v_v` -> `PseudoTH_VMV_V_V_` foreach vti = AllXVectors in { let Predicates = GetXVTypePredicates.Predicates in { // vmv.v.v - def : Pat<(vti.Vector (int_riscv_xvmv_v_v (vti.Vector vti.RegClass:$passthru), - (vti.Vector vti.RegClass:$rs1), - VLOpFrag)), - (!cast("PseudoXVMV_V_V_"#vti.LMul.MX) + def : Pat<(vti.Vector (int_riscv_th_vmv_v_v (vti.Vector vti.RegClass:$passthru), + (vti.Vector vti.RegClass:$rs1), + VLOpFrag)), + (!cast("PseudoTH_VMV_V_V_"#vti.LMul.MX) $passthru, $rs1, GPR:$vl, vti.Log2SEW, TU_MU)>; // TODO: vmv.v.x, vmv.v.i @@ -1038,9 +1038,9 @@ let Predicates = [HasVendorXTHeadV] in { // shuffle vector registers without needing to know or change vl or vtype." // The 1, 2, 4, 8 in suffixes are "the number of individual vector registers, NREG, to copy", // rather than LMUL. - def PseudoXVMV1R_V : XVPseudoWholeMove; - def PseudoXVMV2R_V : XVPseudoWholeMove; - def PseudoXVMV4R_V : XVPseudoWholeMove; - def PseudoXVMV8R_V : XVPseudoWholeMove; + def PseudoTH_VMV1R_V : XVPseudoWholeMove; + def PseudoTH_VMV2R_V : XVPseudoWholeMove; + def PseudoTH_VMV4R_V : XVPseudoWholeMove; + def PseudoTH_VMV8R_V : XVPseudoWholeMove; } } // Predicates = [HasVendorXTHeadV] diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vadd.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vadd.ll index 8f2a84b6b1f80..8f8ef7c73776d 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vadd.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK -declare @llvm.riscv.xvadd.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vadd.nxv8i8.nxv8i8( , , , @@ -13,11 +13,11 @@ declare @llvm.riscv.xvadd.nxv8i8.nxv8i8( define @intrinsic_xvadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvadd_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, d1 -; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvadd.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vadd.nxv8i8.nxv8i8( undef, %0, %1, @@ -26,7 +26,7 @@ entry: ret %a } -declare @llvm.riscv.xvadd.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vadd.mask.nxv8i8.nxv8i8( , , , @@ -36,11 +36,11 @@ declare @llvm.riscv.xvadd.mask.nxv8i8.nxv8i8( define @intrinsic_xvadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, d1 -; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvadd.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vadd.mask.nxv8i8.nxv8i8( %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamoadd.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamoadd.ll index abf405a7f9230..105081d3924b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamoadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamoadd.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamoadd.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoadd.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamoadd.nxv2i32.nxv2i32( define @intrinsic_xvamoadd_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoaddw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoaddw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoadd.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoadd.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv2i32.nxv2i32( define @intrinsic_xvamoadd_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoaddw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoaddw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoadd.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamoadd.nxv4i32.nxv4i32( define @intrinsic_xvamoadd_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoaddw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoaddw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoadd.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoadd.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv4i32.nxv4i32( define @intrinsic_xvamoadd_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoaddw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoaddw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoadd.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamoadd.nxv8i32.nxv8i32( define @intrinsic_xvamoadd_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoaddw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoaddw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoadd.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoadd.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv8i32.nxv8i32( define @intrinsic_xvamoadd_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoaddw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoaddw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoadd.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamoadd.nxv16i32.nxv16i32( define @intrinsic_xvamoadd_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoaddw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoaddw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoadd.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoadd.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv16i32.nxv16i32( define @intrinsic_xvamoadd_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoaddw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoaddw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoadd.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamoadd.nxv2i64.nxv2i32( define @intrinsic_xvamoadd_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoaddd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoaddd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoadd.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoadd.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv2i64.nxv2i32( define @intrinsic_xvamoadd_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoaddd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoaddd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoadd.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamoadd.nxv4i64.nxv4i32( define @intrinsic_xvamoadd_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoaddd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoaddd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoadd.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoadd.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv4i64.nxv4i32( define @intrinsic_xvamoadd_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoaddd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoaddd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoadd.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamoadd.nxv8i64.nxv8i32( define @intrinsic_xvamoadd_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoaddd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoaddd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoadd.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoadd.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv8i64.nxv8i32( define @intrinsic_xvamoadd_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoaddd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoaddd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoadd.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoadd.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamoadd.nxv2i32.nxv2i64( define @intrinsic_xvamoadd_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoaddw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoaddw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoadd.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoadd.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv2i32.nxv2i64( define @intrinsic_xvamoadd_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoaddw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoaddw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoadd.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamoadd.nxv4i32.nxv4i64( define @intrinsic_xvamoadd_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoaddw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoaddw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoadd.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoadd.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv4i32.nxv4i64( define @intrinsic_xvamoadd_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoaddw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoaddw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoadd.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamoadd.nxv8i32.nxv8i64( define @intrinsic_xvamoadd_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoaddw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoaddw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoadd.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoadd.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv8i32.nxv8i64( define @intrinsic_xvamoadd_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoaddw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoaddw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoadd.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamoadd.nxv1i64.nxv1i64( define @intrinsic_xvamoadd_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoaddd.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoaddd.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoadd.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoadd.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv1i64.nxv1i64( define @intrinsic_xvamoadd_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoaddd.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoaddd.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoadd.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamoadd.nxv2i64.nxv2i64( define @intrinsic_xvamoadd_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoaddd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoaddd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoadd.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoadd.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv2i64.nxv2i64( define @intrinsic_xvamoadd_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoaddd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoaddd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoadd.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamoadd.nxv4i64.nxv4i64( define @intrinsic_xvamoadd_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoaddd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoaddd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoadd.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoadd.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv4i64.nxv4i64( define @intrinsic_xvamoadd_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoaddd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoaddd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoadd.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamoadd.nxv8i64.nxv8i64( define @intrinsic_xvamoadd_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoaddd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoaddd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoadd.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoadd.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoadd.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamoadd.mask.nxv8i64.nxv8i64( define @intrinsic_xvamoadd_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoadd_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoaddd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoaddd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoadd.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoadd.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamoand.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamoand.ll index a0f6149db697a..83fedb29ee4c1 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamoand.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamoand.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamoand.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoand.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamoand.nxv2i32.nxv2i32( define @intrinsic_xvamoand_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoandw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoandw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoand.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoand.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamoand.mask.nxv2i32.nxv2i32( define @intrinsic_xvamoand_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoandw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoandw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoand.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamoand.nxv4i32.nxv4i32( define @intrinsic_xvamoand_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoandw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoandw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoand.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoand.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamoand.mask.nxv4i32.nxv4i32( define @intrinsic_xvamoand_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoandw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoandw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoand.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamoand.nxv8i32.nxv8i32( define @intrinsic_xvamoand_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoandw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoandw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoand.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoand.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamoand.mask.nxv8i32.nxv8i32( define @intrinsic_xvamoand_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoandw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoandw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoand.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamoand.nxv16i32.nxv16i32( define @intrinsic_xvamoand_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoandw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoandw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoand.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoand.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamoand.mask.nxv16i32.nxv16i32( define @intrinsic_xvamoand_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoandw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoandw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoand.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamoand.nxv2i64.nxv2i32( define @intrinsic_xvamoand_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoandd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoandd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoand.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoand.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamoand.mask.nxv2i64.nxv2i32( define @intrinsic_xvamoand_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoandd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoandd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoand.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamoand.nxv4i64.nxv4i32( define @intrinsic_xvamoand_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoandd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoandd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoand.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoand.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamoand.mask.nxv4i64.nxv4i32( define @intrinsic_xvamoand_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoandd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoandd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoand.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamoand.nxv8i64.nxv8i32( define @intrinsic_xvamoand_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoandd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoandd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoand.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoand.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamoand.mask.nxv8i64.nxv8i32( define @intrinsic_xvamoand_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoandd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoandd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoand.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoand.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamoand.nxv2i32.nxv2i64( define @intrinsic_xvamoand_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoandw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoandw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoand.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoand.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamoand.mask.nxv2i32.nxv2i64( define @intrinsic_xvamoand_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoandw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoandw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoand.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamoand.nxv4i32.nxv4i64( define @intrinsic_xvamoand_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoandw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoandw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoand.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoand.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamoand.mask.nxv4i32.nxv4i64( define @intrinsic_xvamoand_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoandw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoandw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoand.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamoand.nxv8i32.nxv8i64( define @intrinsic_xvamoand_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoandw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoandw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoand.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoand.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamoand.mask.nxv8i32.nxv8i64( define @intrinsic_xvamoand_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoandw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoandw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoand.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamoand.nxv1i64.nxv1i64( define @intrinsic_xvamoand_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoandd.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoandd.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoand.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoand.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamoand.mask.nxv1i64.nxv1i64( define @intrinsic_xvamoand_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoandd.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoandd.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoand.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamoand.nxv2i64.nxv2i64( define @intrinsic_xvamoand_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoandd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoandd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoand.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoand.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamoand.mask.nxv2i64.nxv2i64( define @intrinsic_xvamoand_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoandd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoandd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoand.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamoand.nxv4i64.nxv4i64( define @intrinsic_xvamoand_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoandd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoandd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoand.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoand.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamoand.mask.nxv4i64.nxv4i64( define @intrinsic_xvamoand_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoandd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoandd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoand.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamoand.nxv8i64.nxv8i64( define @intrinsic_xvamoand_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoandd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoandd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoand.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoand.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoand.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamoand.mask.nxv8i64.nxv8i64( define @intrinsic_xvamoand_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoand_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoandd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoandd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoand.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoand.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamomax.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamomax.ll index d203cc801dd7b..34927be2588a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamomax.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamomax.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamomax.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamomax.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamomax.nxv2i32.nxv2i32( define @intrinsic_xvamomax_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamomax.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamomax.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamomax.mask.nxv2i32.nxv2i32( define @intrinsic_xvamomax_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamomax.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamomax.nxv4i32.nxv4i32( define @intrinsic_xvamomax_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamomax.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamomax.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamomax.mask.nxv4i32.nxv4i32( define @intrinsic_xvamomax_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamomax.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamomax.nxv8i32.nxv8i32( define @intrinsic_xvamomax_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamomax.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamomax.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamomax.mask.nxv8i32.nxv8i32( define @intrinsic_xvamomax_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamomax.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamomax.nxv16i32.nxv16i32( define @intrinsic_xvamomax_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamomaxw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamomaxw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamomax.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamomax.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamomax.mask.nxv16i32.nxv16i32( define @intrinsic_xvamomax_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamomaxw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamomaxw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamomax.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamomax.nxv2i64.nxv2i32( define @intrinsic_xvamomax_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamomax.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamomax.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamomax.mask.nxv2i64.nxv2i32( define @intrinsic_xvamomax_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamomax.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamomax.nxv4i64.nxv4i32( define @intrinsic_xvamomax_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamomax.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamomax.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamomax.mask.nxv4i64.nxv4i32( define @intrinsic_xvamomax_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamomax.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamomax.nxv8i64.nxv8i32( define @intrinsic_xvamomax_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamomax.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamomax.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamomax.mask.nxv8i64.nxv8i32( define @intrinsic_xvamomax_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamomax.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamomax.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamomax.nxv2i32.nxv2i64( define @intrinsic_xvamomax_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamomax.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamomax.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamomax.mask.nxv2i32.nxv2i64( define @intrinsic_xvamomax_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamomax.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamomax.nxv4i32.nxv4i64( define @intrinsic_xvamomax_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamomax.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamomax.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamomax.mask.nxv4i32.nxv4i64( define @intrinsic_xvamomax_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamomax.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamomax.nxv8i32.nxv8i64( define @intrinsic_xvamomax_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamomax.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamomax.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamomax.mask.nxv8i32.nxv8i64( define @intrinsic_xvamomax_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamomax.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamomax.nxv1i64.nxv1i64( define @intrinsic_xvamomax_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamomaxd.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamomaxd.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamomax.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamomax.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamomax.mask.nxv1i64.nxv1i64( define @intrinsic_xvamomax_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamomaxd.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamomaxd.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamomax.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamomax.nxv2i64.nxv2i64( define @intrinsic_xvamomax_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamomax.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamomax.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamomax.mask.nxv2i64.nxv2i64( define @intrinsic_xvamomax_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamomax.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamomax.nxv4i64.nxv4i64( define @intrinsic_xvamomax_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamomax.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamomax.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamomax.mask.nxv4i64.nxv4i64( define @intrinsic_xvamomax_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamomax.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamomax.nxv8i64.nxv8i64( define @intrinsic_xvamomax_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamomax.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomax.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamomax.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamomax.mask.nxv8i64.nxv8i64( define @intrinsic_xvamomax_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomax_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomax.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamomax.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamomaxu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamomaxu.ll index 319c58b35639b..dc9a37d4bfe98 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamomaxu.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamomaxu.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamomaxu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamomaxu.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamomaxu.nxv2i32.nxv2i32( define @intrinsic_xvamomaxu_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxuw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxuw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamomaxu.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv2i32.nxv2i32( define @intrinsic_xvamomaxu_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxuw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxuw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamomaxu.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamomaxu.nxv4i32.nxv4i32( define @intrinsic_xvamomaxu_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxuw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxuw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamomaxu.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv4i32.nxv4i32( define @intrinsic_xvamomaxu_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxuw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxuw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamomaxu.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamomaxu.nxv8i32.nxv8i32( define @intrinsic_xvamomaxu_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxuw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxuw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamomaxu.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv8i32.nxv8i32( define @intrinsic_xvamomaxu_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxuw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxuw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamomaxu.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamomaxu.nxv16i32.nxv16i32( define @intrinsic_xvamomaxu_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamomaxuw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamomaxuw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamomaxu.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv16i32.nxv16i32( define @intrinsic_xvamomaxu_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamomaxuw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamomaxuw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamomaxu.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamomaxu.nxv2i64.nxv2i32( define @intrinsic_xvamomaxu_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxud.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxud.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamomaxu.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv2i64.nxv2i32( define @intrinsic_xvamomaxu_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxud.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxud.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamomaxu.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamomaxu.nxv4i64.nxv4i32( define @intrinsic_xvamomaxu_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxud.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxud.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamomaxu.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv4i64.nxv4i32( define @intrinsic_xvamomaxu_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxud.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxud.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamomaxu.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamomaxu.nxv8i64.nxv8i32( define @intrinsic_xvamomaxu_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxud.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxud.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamomaxu.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamomaxu.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv8i64.nxv8i32( define @intrinsic_xvamomaxu_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxud.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxud.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamomaxu.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamomaxu.nxv2i32.nxv2i64( define @intrinsic_xvamomaxu_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxuw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxuw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamomaxu.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv2i32.nxv2i64( define @intrinsic_xvamomaxu_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamomaxuw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamomaxuw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamomaxu.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamomaxu.nxv4i32.nxv4i64( define @intrinsic_xvamomaxu_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxuw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxuw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamomaxu.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv4i32.nxv4i64( define @intrinsic_xvamomaxu_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamomaxuw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamomaxuw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamomaxu.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamomaxu.nxv8i32.nxv8i64( define @intrinsic_xvamomaxu_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxuw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxuw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamomaxu.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv8i32.nxv8i64( define @intrinsic_xvamomaxu_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamomaxuw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamomaxuw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamomaxu.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamomaxu.nxv1i64.nxv1i64( define @intrinsic_xvamomaxu_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamomaxud.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamomaxud.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamomaxu.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv1i64.nxv1i64( define @intrinsic_xvamomaxu_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamomaxud.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamomaxud.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamomaxu.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamomaxu.nxv2i64.nxv2i64( define @intrinsic_xvamomaxu_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxud.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxud.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamomaxu.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv2i64.nxv2i64( define @intrinsic_xvamomaxu_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomaxud.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomaxud.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamomaxu.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamomaxu.nxv4i64.nxv4i64( define @intrinsic_xvamomaxu_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxud.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxud.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamomaxu.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv4i64.nxv4i64( define @intrinsic_xvamomaxu_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomaxud.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomaxud.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamomaxu.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamomaxu.nxv8i64.nxv8i64( define @intrinsic_xvamomaxu_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxud.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxud.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamomaxu.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomaxu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamomaxu.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamomaxu.mask.nxv8i64.nxv8i64( define @intrinsic_xvamomaxu_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomaxu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomaxud.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomaxud.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomaxu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamomaxu.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamomin.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamomin.ll index 0ee8eeb3584a8..5147fda219ef2 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamomin.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamomin.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamomin.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamomin.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamomin.nxv2i32.nxv2i32( define @intrinsic_xvamomin_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamomin.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamomin.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamomin.mask.nxv2i32.nxv2i32( define @intrinsic_xvamomin_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamomin.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamomin.nxv4i32.nxv4i32( define @intrinsic_xvamomin_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamomin.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamomin.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamomin.mask.nxv4i32.nxv4i32( define @intrinsic_xvamomin_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamomin.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamomin.nxv8i32.nxv8i32( define @intrinsic_xvamomin_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamomin.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamomin.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamomin.mask.nxv8i32.nxv8i32( define @intrinsic_xvamomin_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamomin.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamomin.nxv16i32.nxv16i32( define @intrinsic_xvamomin_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamominw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamominw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamomin.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamomin.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamomin.mask.nxv16i32.nxv16i32( define @intrinsic_xvamomin_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamominw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamominw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamomin.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamomin.nxv2i64.nxv2i32( define @intrinsic_xvamomin_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomind.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomind.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamomin.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamomin.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamomin.mask.nxv2i64.nxv2i32( define @intrinsic_xvamomin_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomind.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomind.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamomin.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamomin.nxv4i64.nxv4i32( define @intrinsic_xvamomin_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomind.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomind.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamomin.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamomin.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamomin.mask.nxv4i64.nxv4i32( define @intrinsic_xvamomin_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomind.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomind.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamomin.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamomin.nxv8i64.nxv8i32( define @intrinsic_xvamomin_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomind.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomind.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamomin.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamomin.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamomin.mask.nxv8i64.nxv8i32( define @intrinsic_xvamomin_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomind.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomind.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamomin.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamomin.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamomin.nxv2i32.nxv2i64( define @intrinsic_xvamomin_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamomin.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamomin.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamomin.mask.nxv2i32.nxv2i64( define @intrinsic_xvamomin_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamomin.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamomin.nxv4i32.nxv4i64( define @intrinsic_xvamomin_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamomin.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamomin.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamomin.mask.nxv4i32.nxv4i64( define @intrinsic_xvamomin_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamomin.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamomin.nxv8i32.nxv8i64( define @intrinsic_xvamomin_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamomin.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamomin.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamomin.mask.nxv8i32.nxv8i64( define @intrinsic_xvamomin_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamomin.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamomin.nxv1i64.nxv1i64( define @intrinsic_xvamomin_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamomind.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamomind.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamomin.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamomin.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamomin.mask.nxv1i64.nxv1i64( define @intrinsic_xvamomin_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamomind.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamomind.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamomin.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamomin.nxv2i64.nxv2i64( define @intrinsic_xvamomin_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomind.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomind.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamomin.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamomin.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamomin.mask.nxv2i64.nxv2i64( define @intrinsic_xvamomin_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamomind.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamomind.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamomin.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamomin.nxv4i64.nxv4i64( define @intrinsic_xvamomin_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomind.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomind.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamomin.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamomin.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamomin.mask.nxv4i64.nxv4i64( define @intrinsic_xvamomin_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamomind.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamomind.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamomin.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamomin.nxv8i64.nxv8i64( define @intrinsic_xvamomin_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomind.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomind.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamomin.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamomin.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamomin.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamomin.mask.nxv8i64.nxv8i64( define @intrinsic_xvamomin_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamomin_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamomind.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamomind.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamomin.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamomin.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamominu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamominu.ll index 5ece9769f50de..61553b14245c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamominu.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamominu.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamominu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamominu.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamominu.nxv2i32.nxv2i32( define @intrinsic_xvamominu_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominuw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominuw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamominu.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamominu.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamominu.mask.nxv2i32.nxv2i32( define @intrinsic_xvamominu_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominuw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominuw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamominu.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamominu.nxv4i32.nxv4i32( define @intrinsic_xvamominu_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominuw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominuw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamominu.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamominu.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamominu.mask.nxv4i32.nxv4i32( define @intrinsic_xvamominu_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominuw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominuw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamominu.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamominu.nxv8i32.nxv8i32( define @intrinsic_xvamominu_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominuw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominuw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamominu.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamominu.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamominu.mask.nxv8i32.nxv8i32( define @intrinsic_xvamominu_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominuw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominuw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamominu.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamominu.nxv16i32.nxv16i32( define @intrinsic_xvamominu_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamominuw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamominuw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamominu.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamominu.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamominu.mask.nxv16i32.nxv16i32( define @intrinsic_xvamominu_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamominuw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamominuw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamominu.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamominu.nxv2i64.nxv2i32( define @intrinsic_xvamominu_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamominud.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamominud.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamominu.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamominu.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamominu.mask.nxv2i64.nxv2i32( define @intrinsic_xvamominu_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamominud.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamominud.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamominu.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamominu.nxv4i64.nxv4i32( define @intrinsic_xvamominu_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamominud.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamominud.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamominu.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamominu.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamominu.mask.nxv4i64.nxv4i32( define @intrinsic_xvamominu_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamominud.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamominud.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamominu.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamominu.nxv8i64.nxv8i32( define @intrinsic_xvamominu_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamominud.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamominud.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamominu.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamominu.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamominu.mask.nxv8i64.nxv8i32( define @intrinsic_xvamominu_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamominud.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamominud.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamominu.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamominu.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamominu.nxv2i32.nxv2i64( define @intrinsic_xvamominu_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominuw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominuw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamominu.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamominu.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamominu.mask.nxv2i32.nxv2i64( define @intrinsic_xvamominu_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamominuw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamominuw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamominu.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamominu.nxv4i32.nxv4i64( define @intrinsic_xvamominu_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominuw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominuw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamominu.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamominu.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamominu.mask.nxv4i32.nxv4i64( define @intrinsic_xvamominu_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamominuw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamominuw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamominu.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamominu.nxv8i32.nxv8i64( define @intrinsic_xvamominu_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominuw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominuw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamominu.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamominu.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamominu.mask.nxv8i32.nxv8i64( define @intrinsic_xvamominu_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamominuw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamominuw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamominu.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamominu.nxv1i64.nxv1i64( define @intrinsic_xvamominu_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamominud.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamominud.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamominu.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamominu.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamominu.mask.nxv1i64.nxv1i64( define @intrinsic_xvamominu_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamominud.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamominud.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamominu.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamominu.nxv2i64.nxv2i64( define @intrinsic_xvamominu_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamominud.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamominud.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamominu.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamominu.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamominu.mask.nxv2i64.nxv2i64( define @intrinsic_xvamominu_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamominud.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamominud.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamominu.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamominu.nxv4i64.nxv4i64( define @intrinsic_xvamominu_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamominud.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamominud.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamominu.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamominu.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamominu.mask.nxv4i64.nxv4i64( define @intrinsic_xvamominu_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamominud.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamominud.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamominu.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamominu.nxv8i64.nxv8i64( define @intrinsic_xvamominu_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamominud.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamominud.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamominu.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamominu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamominu.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamominu.mask.nxv8i64.nxv8i64( define @intrinsic_xvamominu_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamominu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamominud.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamominud.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamominu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamominu.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamoor.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamoor.ll index 72692aa545110..04f68cbe25dfd 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamoor.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamoor.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamoor.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoor.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamoor.nxv2i32.nxv2i32( define @intrinsic_xvamoor_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoorw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoorw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoor.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoor.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamoor.mask.nxv2i32.nxv2i32( define @intrinsic_xvamoor_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoorw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoorw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoor.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamoor.nxv4i32.nxv4i32( define @intrinsic_xvamoor_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoorw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoorw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoor.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoor.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamoor.mask.nxv4i32.nxv4i32( define @intrinsic_xvamoor_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoorw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoorw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoor.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamoor.nxv8i32.nxv8i32( define @intrinsic_xvamoor_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoorw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoorw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoor.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoor.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamoor.mask.nxv8i32.nxv8i32( define @intrinsic_xvamoor_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoorw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoorw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoor.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamoor.nxv16i32.nxv16i32( define @intrinsic_xvamoor_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoorw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoorw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoor.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoor.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamoor.mask.nxv16i32.nxv16i32( define @intrinsic_xvamoor_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoorw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoorw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoor.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamoor.nxv2i64.nxv2i32( define @intrinsic_xvamoor_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoord.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoord.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoor.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoor.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamoor.mask.nxv2i64.nxv2i32( define @intrinsic_xvamoor_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoord.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoord.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoor.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamoor.nxv4i64.nxv4i32( define @intrinsic_xvamoor_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoord.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoord.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoor.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoor.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamoor.mask.nxv4i64.nxv4i32( define @intrinsic_xvamoor_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoord.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoord.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoor.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamoor.nxv8i64.nxv8i32( define @intrinsic_xvamoor_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoord.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoord.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoor.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoor.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamoor.mask.nxv8i64.nxv8i32( define @intrinsic_xvamoor_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoord.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoord.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoor.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoor.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamoor.nxv2i32.nxv2i64( define @intrinsic_xvamoor_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoorw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoorw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoor.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoor.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamoor.mask.nxv2i32.nxv2i64( define @intrinsic_xvamoor_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoorw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoorw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoor.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamoor.nxv4i32.nxv4i64( define @intrinsic_xvamoor_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoorw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoorw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoor.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoor.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamoor.mask.nxv4i32.nxv4i64( define @intrinsic_xvamoor_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoorw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoorw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoor.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamoor.nxv8i32.nxv8i64( define @intrinsic_xvamoor_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoorw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoorw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoor.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoor.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamoor.mask.nxv8i32.nxv8i64( define @intrinsic_xvamoor_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoorw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoorw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoor.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamoor.nxv1i64.nxv1i64( define @intrinsic_xvamoor_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoord.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoord.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoor.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoor.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamoor.mask.nxv1i64.nxv1i64( define @intrinsic_xvamoor_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoord.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoord.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoor.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamoor.nxv2i64.nxv2i64( define @intrinsic_xvamoor_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoord.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoord.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoor.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoor.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamoor.mask.nxv2i64.nxv2i64( define @intrinsic_xvamoor_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoord.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoord.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoor.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamoor.nxv4i64.nxv4i64( define @intrinsic_xvamoor_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoord.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoord.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoor.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoor.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamoor.mask.nxv4i64.nxv4i64( define @intrinsic_xvamoor_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoord.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoord.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoor.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamoor.nxv8i64.nxv8i64( define @intrinsic_xvamoor_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoord.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoord.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoor.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoor.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoor.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamoor.mask.nxv8i64.nxv8i64( define @intrinsic_xvamoor_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoor_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoord.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoord.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoor.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoor.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamoswap.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamoswap.ll index 6ee6668136a3c..55943a9f40720 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamoswap.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamoswap.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamoswap.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoswap.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamoswap.nxv2i32.nxv2i32( define @intrinsic_xvamoswap_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoswapw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoswapw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoswap.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoswap.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv2i32.nxv2i32( define @intrinsic_xvamoswap_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoswapw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoswapw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoswap.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamoswap.nxv4i32.nxv4i32( define @intrinsic_xvamoswap_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoswapw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoswapw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoswap.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoswap.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv4i32.nxv4i32( define @intrinsic_xvamoswap_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoswapw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoswapw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoswap.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamoswap.nxv8i32.nxv8i32( define @intrinsic_xvamoswap_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoswapw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoswapw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoswap.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoswap.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv8i32.nxv8i32( define @intrinsic_xvamoswap_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoswapw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoswapw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoswap.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamoswap.nxv16i32.nxv16i32( define @intrinsic_xvamoswap_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoswapw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoswapw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoswap.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoswap.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv16i32.nxv16i32( define @intrinsic_xvamoswap_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoswapw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoswapw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoswap.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamoswap.nxv2i64.nxv2i32( define @intrinsic_xvamoswap_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoswapd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoswapd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoswap.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoswap.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv2i64.nxv2i32( define @intrinsic_xvamoswap_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoswapd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoswapd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoswap.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamoswap.nxv4i64.nxv4i32( define @intrinsic_xvamoswap_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoswapd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoswapd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoswap.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoswap.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv4i64.nxv4i32( define @intrinsic_xvamoswap_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoswapd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoswapd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoswap.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamoswap.nxv8i64.nxv8i32( define @intrinsic_xvamoswap_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoswapd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoswapd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoswap.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoswap.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv8i64.nxv8i32( define @intrinsic_xvamoswap_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoswapd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoswapd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoswap.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoswap.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamoswap.nxv2i32.nxv2i64( define @intrinsic_xvamoswap_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoswapw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoswapw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoswap.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoswap.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv2i32.nxv2i64( define @intrinsic_xvamoswap_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoswapw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoswapw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoswap.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamoswap.nxv4i32.nxv4i64( define @intrinsic_xvamoswap_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoswapw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoswapw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoswap.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoswap.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv4i32.nxv4i64( define @intrinsic_xvamoswap_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoswapw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoswapw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoswap.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamoswap.nxv8i32.nxv8i64( define @intrinsic_xvamoswap_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoswapw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoswapw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoswap.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoswap.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv8i32.nxv8i64( define @intrinsic_xvamoswap_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoswapw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoswapw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoswap.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamoswap.nxv1i64.nxv1i64( define @intrinsic_xvamoswap_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoswapd.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoswapd.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoswap.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoswap.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv1i64.nxv1i64( define @intrinsic_xvamoswap_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoswapd.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoswapd.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoswap.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamoswap.nxv2i64.nxv2i64( define @intrinsic_xvamoswap_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoswapd.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoswapd.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoswap.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoswap.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv2i64.nxv2i64( define @intrinsic_xvamoswap_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoswapd.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoswapd.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoswap.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamoswap.nxv4i64.nxv4i64( define @intrinsic_xvamoswap_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoswapd.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoswapd.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoswap.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoswap.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv4i64.nxv4i64( define @intrinsic_xvamoswap_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoswapd.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoswapd.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoswap.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamoswap.nxv8i64.nxv8i64( define @intrinsic_xvamoswap_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoswapd.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoswapd.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoswap.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoswap.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoswap.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamoswap.mask.nxv8i64.nxv8i64( define @intrinsic_xvamoswap_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoswap_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoswapd.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoswapd.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoswap.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoswap.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vamoxor.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vamoxor.ll index 88e3a9207427d..5cf41a0360bf8 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vamoxor.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vamoxor.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadv,+xtheadvamo \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvamoxor.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoxor.nxv2i32.nxv2i32( *, , , @@ -12,13 +12,13 @@ declare @llvm.riscv.xvamoxor.nxv2i32.nxv2i32( define @intrinsic_xvamoxor_v_nxv2i32_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoxorw.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoxorw.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoxor.nxv2i32.nxv2i32( * %0, %1, %2, @@ -27,7 +27,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vamoxor.mask.nxv2i32.nxv2i32( *, , , @@ -37,13 +37,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv2i32.nxv2i32( define @intrinsic_xvamoxor_mask_v_nxv2i32_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoxorw.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoxorw.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv2i32.nxv2i32( * %0, %1, %2, @@ -53,7 +53,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoxor.nxv4i32.nxv4i32( *, , , @@ -62,13 +62,13 @@ declare @llvm.riscv.xvamoxor.nxv4i32.nxv4i32( define @intrinsic_xvamoxor_v_nxv4i32_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoxorw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoxorw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoxor.nxv4i32.nxv4i32( * %0, %1, %2, @@ -77,7 +77,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vamoxor.mask.nxv4i32.nxv4i32( *, , , @@ -87,13 +87,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv4i32.nxv4i32( define @intrinsic_xvamoxor_mask_v_nxv4i32_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoxorw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoxorw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv4i32.nxv4i32( * %0, %1, %2, @@ -103,7 +103,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoxor.nxv8i32.nxv8i32( *, , , @@ -112,13 +112,13 @@ declare @llvm.riscv.xvamoxor.nxv8i32.nxv8i32( define @intrinsic_xvamoxor_v_nxv8i32_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoxorw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoxorw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoxor.nxv8i32.nxv8i32( * %0, %1, %2, @@ -127,7 +127,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vamoxor.mask.nxv8i32.nxv8i32( *, , , @@ -137,13 +137,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv8i32.nxv8i32( define @intrinsic_xvamoxor_mask_v_nxv8i32_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoxorw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoxorw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv8i32.nxv8i32( * %0, %1, %2, @@ -153,7 +153,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoxor.nxv16i32.nxv16i32( *, , , @@ -162,13 +162,13 @@ declare @llvm.riscv.xvamoxor.nxv16i32.nxv16i32( define @intrinsic_xvamoxor_v_nxv16i32_nxv16i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoxorw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoxorw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoxor.nxv16i32.nxv16i32( * %0, %1, %2, @@ -177,7 +177,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vamoxor.mask.nxv16i32.nxv16i32( *, , , @@ -187,13 +187,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv16i32.nxv16i32( define @intrinsic_xvamoxor_mask_v_nxv16i32_nxv16i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vamoxorw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vamoxorw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv16i32.nxv16i32( * %0, %1, %2, @@ -203,7 +203,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoxor.nxv2i64.nxv2i32( *, , , @@ -212,13 +212,13 @@ declare @llvm.riscv.xvamoxor.nxv2i64.nxv2i32( define @intrinsic_xvamoxor_v_nxv2i64_nxv2i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoxord.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoxord.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoxor.nxv2i64.nxv2i32( * %0, %1, %2, @@ -227,7 +227,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv2i64.nxv2i32( +declare @llvm.riscv.th.vamoxor.mask.nxv2i64.nxv2i32( *, , , @@ -237,13 +237,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv2i64.nxv2i32( define @intrinsic_xvamoxor_mask_v_nxv2i64_nxv2i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv2i64_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoxord.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoxord.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv2i64.nxv2i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv2i64.nxv2i32( * %0, %1, %2, @@ -253,7 +253,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoxor.nxv4i64.nxv4i32( *, , , @@ -262,13 +262,13 @@ declare @llvm.riscv.xvamoxor.nxv4i64.nxv4i32( define @intrinsic_xvamoxor_v_nxv4i64_nxv4i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoxord.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoxord.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoxor.nxv4i64.nxv4i32( * %0, %1, %2, @@ -277,7 +277,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv4i64.nxv4i32( +declare @llvm.riscv.th.vamoxor.mask.nxv4i64.nxv4i32( *, , , @@ -287,13 +287,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv4i64.nxv4i32( define @intrinsic_xvamoxor_mask_v_nxv4i64_nxv4i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv4i64_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoxord.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoxord.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv4i64.nxv4i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv4i64.nxv4i32( * %0, %1, %2, @@ -303,7 +303,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoxor.nxv8i64.nxv8i32( *, , , @@ -312,13 +312,13 @@ declare @llvm.riscv.xvamoxor.nxv8i64.nxv8i32( define @intrinsic_xvamoxor_v_nxv8i64_nxv8i32(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoxord.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoxord.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoxor.nxv8i64.nxv8i32( * %0, %1, %2, @@ -327,7 +327,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv8i64.nxv8i32( +declare @llvm.riscv.th.vamoxor.mask.nxv8i64.nxv8i32( *, , , @@ -337,13 +337,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv8i64.nxv8i32( define @intrinsic_xvamoxor_mask_v_nxv8i64_nxv8i32(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv8i64_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoxord.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoxord.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv8i64.nxv8i32( + %a = call @llvm.riscv.th.vamoxor.mask.nxv8i64.nxv8i32( * %0, %1, %2, @@ -353,7 +353,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoxor.nxv2i32.nxv2i64( *, , , @@ -362,13 +362,13 @@ declare @llvm.riscv.xvamoxor.nxv2i32.nxv2i64( define @intrinsic_xvamoxor_v_nxv2i32_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoxorw.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoxorw.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoxor.nxv2i32.nxv2i64( * %0, %1, %2, @@ -377,7 +377,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv2i32.nxv2i64( +declare @llvm.riscv.th.vamoxor.mask.nxv2i32.nxv2i64( *, , , @@ -387,13 +387,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv2i32.nxv2i64( define @intrinsic_xvamoxor_mask_v_nxv2i32_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv2i32_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vamoxorw.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vamoxorw.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv2i32.nxv2i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv2i32.nxv2i64( * %0, %1, %2, @@ -403,7 +403,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoxor.nxv4i32.nxv4i64( *, , , @@ -412,13 +412,13 @@ declare @llvm.riscv.xvamoxor.nxv4i32.nxv4i64( define @intrinsic_xvamoxor_v_nxv4i32_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoxorw.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoxorw.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoxor.nxv4i32.nxv4i64( * %0, %1, %2, @@ -427,7 +427,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv4i32.nxv4i64( +declare @llvm.riscv.th.vamoxor.mask.nxv4i32.nxv4i64( *, , , @@ -437,13 +437,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv4i32.nxv4i64( define @intrinsic_xvamoxor_mask_v_nxv4i32_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv4i32_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vamoxorw.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vamoxorw.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv4i32.nxv4i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv4i32.nxv4i64( * %0, %1, %2, @@ -453,7 +453,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoxor.nxv8i32.nxv8i64( *, , , @@ -462,13 +462,13 @@ declare @llvm.riscv.xvamoxor.nxv8i32.nxv8i64( define @intrinsic_xvamoxor_v_nxv8i32_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoxorw.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoxorw.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoxor.nxv8i32.nxv8i64( * %0, %1, %2, @@ -477,7 +477,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv8i32.nxv8i64( +declare @llvm.riscv.th.vamoxor.mask.nxv8i32.nxv8i64( *, , , @@ -487,13 +487,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv8i32.nxv8i64( define @intrinsic_xvamoxor_mask_v_nxv8i32_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv8i32_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vamoxorw.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vamoxorw.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv8i32.nxv8i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv8i32.nxv8i64( * %0, %1, %2, @@ -503,7 +503,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoxor.nxv1i64.nxv1i64( *, , , @@ -512,13 +512,13 @@ declare @llvm.riscv.xvamoxor.nxv1i64.nxv1i64( define @intrinsic_xvamoxor_v_nxv1i64_nxv1i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoxord.v v9, v8, (a0), v9 -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoxord.v v9, v8, (a0), v9 +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoxor.nxv1i64.nxv1i64( * %0, %1, %2, @@ -527,7 +527,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vamoxor.mask.nxv1i64.nxv1i64( *, , , @@ -537,13 +537,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv1i64.nxv1i64( define @intrinsic_xvamoxor_mask_v_nxv1i64_nxv1i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vamoxord.v v9, v8, (a0), v9, v0.t -; CHECK-NEXT: vmv.v.v v8, v9 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vamoxord.v v9, v8, (a0), v9, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv1i64.nxv1i64( * %0, %1, %2, @@ -553,7 +553,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoxor.nxv2i64.nxv2i64( *, , , @@ -562,13 +562,13 @@ declare @llvm.riscv.xvamoxor.nxv2i64.nxv2i64( define @intrinsic_xvamoxor_v_nxv2i64_nxv2i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoxord.v v10, v8, (a0), v10 -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoxord.v v10, v8, (a0), v10 +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoxor.nxv2i64.nxv2i64( * %0, %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vamoxor.mask.nxv2i64.nxv2i64( *, , , @@ -587,13 +587,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv2i64.nxv2i64( define @intrinsic_xvamoxor_mask_v_nxv2i64_nxv2i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vamoxord.v v10, v8, (a0), v10, v0.t -; CHECK-NEXT: vmv.v.v v8, v10 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vamoxord.v v10, v8, (a0), v10, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv2i64.nxv2i64( * %0, %1, %2, @@ -603,7 +603,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoxor.nxv4i64.nxv4i64( *, , , @@ -612,13 +612,13 @@ declare @llvm.riscv.xvamoxor.nxv4i64.nxv4i64( define @intrinsic_xvamoxor_v_nxv4i64_nxv4i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoxord.v v12, v8, (a0), v12 -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoxord.v v12, v8, (a0), v12 +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoxor.nxv4i64.nxv4i64( * %0, %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vamoxor.mask.nxv4i64.nxv4i64( *, , , @@ -637,13 +637,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv4i64.nxv4i64( define @intrinsic_xvamoxor_mask_v_nxv4i64_nxv4i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vamoxord.v v12, v8, (a0), v12, v0.t -; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vamoxord.v v12, v8, (a0), v12, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv4i64.nxv4i64( * %0, %1, %2, @@ -653,7 +653,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoxor.nxv8i64.nxv8i64( *, , , @@ -662,13 +662,13 @@ declare @llvm.riscv.xvamoxor.nxv8i64.nxv8i64( define @intrinsic_xvamoxor_v_nxv8i64_nxv8i64(* %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoxord.v v16, v8, (a0), v16 -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoxord.v v16, v8, (a0), v16 +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoxor.nxv8i64.nxv8i64( * %0, %1, %2, @@ -677,7 +677,7 @@ entry: ret %a } -declare @llvm.riscv.xvamoxor.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vamoxor.mask.nxv8i64.nxv8i64( *, , , @@ -687,13 +687,13 @@ declare @llvm.riscv.xvamoxor.mask.nxv8i64.nxv8i64( define @intrinsic_xvamoxor_mask_v_nxv8i64_nxv8i64(* %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvamoxor_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vamoxord.v v16, v8, (a0), v16, v0.t -; CHECK-NEXT: vmv.v.v v8, v16 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vamoxord.v v16, v8, (a0), v16, v0.t +; CHECK-NEXT: th.vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvamoxor.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vamoxor.mask.nxv8i64.nxv8i64( * %0, %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vl.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vl.ll index 18171e38c7e76..a50e8ad3e662b 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vl.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vl.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlb.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlb.nxv8i8.nxv8i8( , *, iXLen); @@ -11,12 +11,12 @@ declare @llvm.riscv.xvlb.nxv8i8.nxv8i8( define @intrinsic_xvlb_v_nxv8i8_nxv8i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlb.nxv8i8.nxv8i8( undef, * %0, iXLen %1) @@ -24,7 +24,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlb.mask.nxv8i8.nxv8i8( , *, , @@ -33,12 +33,12 @@ declare @llvm.riscv.xvlb.mask.nxv8i8.nxv8i8( define @intrinsic_xvlb_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlb.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -47,7 +47,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlb.nxv16i8.nxv16i8( , *, iXLen); @@ -55,12 +55,12 @@ declare @llvm.riscv.xvlb.nxv16i8.nxv16i8( define @intrinsic_xvlb_v_nxv16i8_nxv16i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlb.nxv16i8.nxv16i8( undef, * %0, iXLen %1) @@ -68,7 +68,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlb.mask.nxv16i8.nxv16i8( , *, , @@ -77,12 +77,12 @@ declare @llvm.riscv.xvlb.mask.nxv16i8.nxv16i8( define @intrinsic_xvlb_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlb.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -91,7 +91,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlb.nxv32i8.nxv32i8( , *, iXLen); @@ -99,12 +99,12 @@ declare @llvm.riscv.xvlb.nxv32i8.nxv32i8( define @intrinsic_xvlb_v_nxv32i8_nxv32i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlb.nxv32i8.nxv32i8( undef, * %0, iXLen %1) @@ -112,7 +112,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlb.mask.nxv32i8.nxv32i8( , *, , @@ -121,12 +121,12 @@ declare @llvm.riscv.xvlb.mask.nxv32i8.nxv32i8( define @intrinsic_xvlb_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlb.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -135,7 +135,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlb.nxv64i8.nxv64i8( , *, iXLen); @@ -143,12 +143,12 @@ declare @llvm.riscv.xvlb.nxv64i8.nxv64i8( define @intrinsic_xvlb_v_nxv64i8_nxv64i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlb.nxv64i8.nxv64i8( undef, * %0, iXLen %1) @@ -156,7 +156,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlb.mask.nxv64i8.nxv64i8( , *, , @@ -165,12 +165,12 @@ declare @llvm.riscv.xvlb.mask.nxv64i8.nxv64i8( define @intrinsic_xvlb_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlb.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -179,7 +179,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlb.nxv4i16.nxv4i16( , *, iXLen); @@ -187,12 +187,12 @@ declare @llvm.riscv.xvlb.nxv4i16.nxv4i16( define @intrinsic_xvlb_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlb.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -200,7 +200,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlb.mask.nxv4i16.nxv4i16( , *, , @@ -209,12 +209,12 @@ declare @llvm.riscv.xvlb.mask.nxv4i16.nxv4i16( define @intrinsic_xvlb_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlb.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -223,7 +223,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlb.nxv8i16.nxv8i16( , *, iXLen); @@ -231,12 +231,12 @@ declare @llvm.riscv.xvlb.nxv8i16.nxv8i16( define @intrinsic_xvlb_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlb.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -244,7 +244,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlb.mask.nxv8i16.nxv8i16( , *, , @@ -253,12 +253,12 @@ declare @llvm.riscv.xvlb.mask.nxv8i16.nxv8i16( define @intrinsic_xvlb_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlb.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -267,7 +267,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlb.nxv16i16.nxv16i16( , *, iXLen); @@ -275,12 +275,12 @@ declare @llvm.riscv.xvlb.nxv16i16.nxv16i16( define @intrinsic_xvlb_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlb.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -288,7 +288,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlb.mask.nxv16i16.nxv16i16( , *, , @@ -297,12 +297,12 @@ declare @llvm.riscv.xvlb.mask.nxv16i16.nxv16i16( define @intrinsic_xvlb_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlb.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -311,7 +311,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlb.nxv32i16.nxv32i16( , *, iXLen); @@ -319,12 +319,12 @@ declare @llvm.riscv.xvlb.nxv32i16.nxv32i16( define @intrinsic_xvlb_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlb.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -332,7 +332,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlb.mask.nxv32i16.nxv32i16( , *, , @@ -341,12 +341,12 @@ declare @llvm.riscv.xvlb.mask.nxv32i16.nxv32i16( define @intrinsic_xvlb_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlb.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -355,7 +355,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlb.nxv2i32.nxv2i32( , *, iXLen); @@ -363,12 +363,12 @@ declare @llvm.riscv.xvlb.nxv2i32.nxv2i32( define @intrinsic_xvlb_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlb.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -376,7 +376,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlb.mask.nxv2i32.nxv2i32( , *, , @@ -385,12 +385,12 @@ declare @llvm.riscv.xvlb.mask.nxv2i32.nxv2i32( define @intrinsic_xvlb_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlb.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -399,7 +399,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlb.nxv4i32.nxv4i32( , *, iXLen); @@ -407,12 +407,12 @@ declare @llvm.riscv.xvlb.nxv4i32.nxv4i32( define @intrinsic_xvlb_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlb.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -420,7 +420,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlb.mask.nxv4i32.nxv4i32( , *, , @@ -429,12 +429,12 @@ declare @llvm.riscv.xvlb.mask.nxv4i32.nxv4i32( define @intrinsic_xvlb_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlb.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -443,7 +443,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlb.nxv8i32.nxv8i32( , *, iXLen); @@ -451,12 +451,12 @@ declare @llvm.riscv.xvlb.nxv8i32.nxv8i32( define @intrinsic_xvlb_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlb.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -464,7 +464,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlb.mask.nxv8i32.nxv8i32( , *, , @@ -473,12 +473,12 @@ declare @llvm.riscv.xvlb.mask.nxv8i32.nxv8i32( define @intrinsic_xvlb_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlb.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -487,7 +487,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlb.nxv16i32.nxv16i32( , *, iXLen); @@ -495,12 +495,12 @@ declare @llvm.riscv.xvlb.nxv16i32.nxv16i32( define @intrinsic_xvlb_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlb.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -508,7 +508,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlb.mask.nxv16i32.nxv16i32( , *, , @@ -517,12 +517,12 @@ declare @llvm.riscv.xvlb.mask.nxv16i32.nxv16i32( define @intrinsic_xvlb_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlb.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -531,7 +531,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlb.nxv1i64.nxv1i64( , *, iXLen); @@ -539,12 +539,12 @@ declare @llvm.riscv.xvlb.nxv1i64.nxv1i64( define @intrinsic_xvlb_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlb.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -552,7 +552,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlb.mask.nxv1i64.nxv1i64( , *, , @@ -561,12 +561,12 @@ declare @llvm.riscv.xvlb.mask.nxv1i64.nxv1i64( define @intrinsic_xvlb_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlb.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -575,7 +575,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlb.nxv2i64.nxv2i64( , *, iXLen); @@ -583,12 +583,12 @@ declare @llvm.riscv.xvlb.nxv2i64.nxv2i64( define @intrinsic_xvlb_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlb.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -596,7 +596,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlb.mask.nxv2i64.nxv2i64( , *, , @@ -605,12 +605,12 @@ declare @llvm.riscv.xvlb.mask.nxv2i64.nxv2i64( define @intrinsic_xvlb_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlb.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -619,7 +619,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlb.nxv4i64.nxv4i64( , *, iXLen); @@ -627,12 +627,12 @@ declare @llvm.riscv.xvlb.nxv4i64.nxv4i64( define @intrinsic_xvlb_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlb.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -640,7 +640,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlb.mask.nxv4i64.nxv4i64( , *, , @@ -649,12 +649,12 @@ declare @llvm.riscv.xvlb.mask.nxv4i64.nxv4i64( define @intrinsic_xvlb_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlb.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -663,7 +663,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlb.nxv8i64.nxv8i64( , *, iXLen); @@ -671,12 +671,12 @@ declare @llvm.riscv.xvlb.nxv8i64.nxv8i64( define @intrinsic_xvlb_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlb_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlb.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -684,7 +684,7 @@ entry: ret %a } -declare @llvm.riscv.xvlb.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlb.mask.nxv8i64.nxv8i64( , *, , @@ -693,12 +693,12 @@ declare @llvm.riscv.xvlb.mask.nxv8i64.nxv8i64( define @intrinsic_xvlb_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlb_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlb.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlb.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -707,7 +707,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlh.nxv4i16.nxv4i16( , *, iXLen); @@ -715,12 +715,12 @@ declare @llvm.riscv.xvlh.nxv4i16.nxv4i16( define @intrinsic_xvlh_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlh.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -728,7 +728,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlh.mask.nxv4i16.nxv4i16( , *, , @@ -737,12 +737,12 @@ declare @llvm.riscv.xvlh.mask.nxv4i16.nxv4i16( define @intrinsic_xvlh_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlh.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -751,7 +751,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlh.nxv8i16.nxv8i16( , *, iXLen); @@ -759,12 +759,12 @@ declare @llvm.riscv.xvlh.nxv8i16.nxv8i16( define @intrinsic_xvlh_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlh.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -772,7 +772,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlh.mask.nxv8i16.nxv8i16( , *, , @@ -781,12 +781,12 @@ declare @llvm.riscv.xvlh.mask.nxv8i16.nxv8i16( define @intrinsic_xvlh_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlh.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -795,7 +795,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlh.nxv16i16.nxv16i16( , *, iXLen); @@ -803,12 +803,12 @@ declare @llvm.riscv.xvlh.nxv16i16.nxv16i16( define @intrinsic_xvlh_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlh.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -816,7 +816,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlh.mask.nxv16i16.nxv16i16( , *, , @@ -825,12 +825,12 @@ declare @llvm.riscv.xvlh.mask.nxv16i16.nxv16i16( define @intrinsic_xvlh_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlh.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -839,7 +839,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlh.nxv32i16.nxv32i16( , *, iXLen); @@ -847,12 +847,12 @@ declare @llvm.riscv.xvlh.nxv32i16.nxv32i16( define @intrinsic_xvlh_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlh.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -860,7 +860,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlh.mask.nxv32i16.nxv32i16( , *, , @@ -869,12 +869,12 @@ declare @llvm.riscv.xvlh.mask.nxv32i16.nxv32i16( define @intrinsic_xvlh_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlh.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -883,7 +883,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlh.nxv2i32.nxv2i32( , *, iXLen); @@ -891,12 +891,12 @@ declare @llvm.riscv.xvlh.nxv2i32.nxv2i32( define @intrinsic_xvlh_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlh.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -904,7 +904,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlh.mask.nxv2i32.nxv2i32( , *, , @@ -913,12 +913,12 @@ declare @llvm.riscv.xvlh.mask.nxv2i32.nxv2i32( define @intrinsic_xvlh_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlh.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -927,7 +927,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlh.nxv4i32.nxv4i32( , *, iXLen); @@ -935,12 +935,12 @@ declare @llvm.riscv.xvlh.nxv4i32.nxv4i32( define @intrinsic_xvlh_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlh.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -948,7 +948,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlh.mask.nxv4i32.nxv4i32( , *, , @@ -957,12 +957,12 @@ declare @llvm.riscv.xvlh.mask.nxv4i32.nxv4i32( define @intrinsic_xvlh_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlh.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -971,7 +971,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlh.nxv8i32.nxv8i32( , *, iXLen); @@ -979,12 +979,12 @@ declare @llvm.riscv.xvlh.nxv8i32.nxv8i32( define @intrinsic_xvlh_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlh.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -992,7 +992,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlh.mask.nxv8i32.nxv8i32( , *, , @@ -1001,12 +1001,12 @@ declare @llvm.riscv.xvlh.mask.nxv8i32.nxv8i32( define @intrinsic_xvlh_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlh.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1015,7 +1015,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlh.nxv16i32.nxv16i32( , *, iXLen); @@ -1023,12 +1023,12 @@ declare @llvm.riscv.xvlh.nxv16i32.nxv16i32( define @intrinsic_xvlh_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlh.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -1036,7 +1036,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlh.mask.nxv16i32.nxv16i32( , *, , @@ -1045,12 +1045,12 @@ declare @llvm.riscv.xvlh.mask.nxv16i32.nxv16i32( define @intrinsic_xvlh_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlh.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1059,7 +1059,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlh.nxv1i64.nxv1i64( , *, iXLen); @@ -1067,12 +1067,12 @@ declare @llvm.riscv.xvlh.nxv1i64.nxv1i64( define @intrinsic_xvlh_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlh.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -1080,7 +1080,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlh.mask.nxv1i64.nxv1i64( , *, , @@ -1089,12 +1089,12 @@ declare @llvm.riscv.xvlh.mask.nxv1i64.nxv1i64( define @intrinsic_xvlh_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlh.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -1103,7 +1103,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlh.nxv2i64.nxv2i64( , *, iXLen); @@ -1111,12 +1111,12 @@ declare @llvm.riscv.xvlh.nxv2i64.nxv2i64( define @intrinsic_xvlh_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlh.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -1124,7 +1124,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlh.mask.nxv2i64.nxv2i64( , *, , @@ -1133,12 +1133,12 @@ declare @llvm.riscv.xvlh.mask.nxv2i64.nxv2i64( define @intrinsic_xvlh_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlh.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -1147,7 +1147,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlh.nxv4i64.nxv4i64( , *, iXLen); @@ -1155,12 +1155,12 @@ declare @llvm.riscv.xvlh.nxv4i64.nxv4i64( define @intrinsic_xvlh_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlh.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -1168,7 +1168,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlh.mask.nxv4i64.nxv4i64( , *, , @@ -1177,12 +1177,12 @@ declare @llvm.riscv.xvlh.mask.nxv4i64.nxv4i64( define @intrinsic_xvlh_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlh.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -1191,7 +1191,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlh.nxv8i64.nxv8i64( , *, iXLen); @@ -1199,12 +1199,12 @@ declare @llvm.riscv.xvlh.nxv8i64.nxv8i64( define @intrinsic_xvlh_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlh_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlh.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlh.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -1212,7 +1212,7 @@ entry: ret %a } -declare @llvm.riscv.xvlh.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlh.mask.nxv8i64.nxv8i64( , *, , @@ -1221,12 +1221,12 @@ declare @llvm.riscv.xvlh.mask.nxv8i64.nxv8i64( define @intrinsic_xvlh_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlh_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlh.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlh.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -1235,7 +1235,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlw.nxv2i32.nxv2i32( , *, iXLen); @@ -1243,12 +1243,12 @@ declare @llvm.riscv.xvlw.nxv2i32.nxv2i32( define @intrinsic_xvlw_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlw.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -1256,7 +1256,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlw.mask.nxv2i32.nxv2i32( , *, , @@ -1265,12 +1265,12 @@ declare @llvm.riscv.xvlw.mask.nxv2i32.nxv2i32( define @intrinsic_xvlw_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlw.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1279,7 +1279,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlw.nxv4i32.nxv4i32( , *, iXLen); @@ -1287,12 +1287,12 @@ declare @llvm.riscv.xvlw.nxv4i32.nxv4i32( define @intrinsic_xvlw_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlw.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -1300,7 +1300,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlw.mask.nxv4i32.nxv4i32( , *, , @@ -1309,12 +1309,12 @@ declare @llvm.riscv.xvlw.mask.nxv4i32.nxv4i32( define @intrinsic_xvlw_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlw.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1323,7 +1323,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlw.nxv8i32.nxv8i32( , *, iXLen); @@ -1331,12 +1331,12 @@ declare @llvm.riscv.xvlw.nxv8i32.nxv8i32( define @intrinsic_xvlw_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlw.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -1344,7 +1344,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlw.mask.nxv8i32.nxv8i32( , *, , @@ -1353,12 +1353,12 @@ declare @llvm.riscv.xvlw.mask.nxv8i32.nxv8i32( define @intrinsic_xvlw_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlw.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1367,7 +1367,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlw.nxv16i32.nxv16i32( , *, iXLen); @@ -1375,12 +1375,12 @@ declare @llvm.riscv.xvlw.nxv16i32.nxv16i32( define @intrinsic_xvlw_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlw.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -1388,7 +1388,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlw.mask.nxv16i32.nxv16i32( , *, , @@ -1397,12 +1397,12 @@ declare @llvm.riscv.xvlw.mask.nxv16i32.nxv16i32( define @intrinsic_xvlw_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlw.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1411,7 +1411,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlw.nxv1i64.nxv1i64( , *, iXLen); @@ -1419,12 +1419,12 @@ declare @llvm.riscv.xvlw.nxv1i64.nxv1i64( define @intrinsic_xvlw_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlw.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -1432,7 +1432,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlw.mask.nxv1i64.nxv1i64( , *, , @@ -1441,12 +1441,12 @@ declare @llvm.riscv.xvlw.mask.nxv1i64.nxv1i64( define @intrinsic_xvlw_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlw.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -1455,7 +1455,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlw.nxv2i64.nxv2i64( , *, iXLen); @@ -1463,12 +1463,12 @@ declare @llvm.riscv.xvlw.nxv2i64.nxv2i64( define @intrinsic_xvlw_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlw.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -1476,7 +1476,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlw.mask.nxv2i64.nxv2i64( , *, , @@ -1485,12 +1485,12 @@ declare @llvm.riscv.xvlw.mask.nxv2i64.nxv2i64( define @intrinsic_xvlw_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlw.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -1499,7 +1499,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlw.nxv4i64.nxv4i64( , *, iXLen); @@ -1507,12 +1507,12 @@ declare @llvm.riscv.xvlw.nxv4i64.nxv4i64( define @intrinsic_xvlw_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlw.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -1520,7 +1520,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlw.mask.nxv4i64.nxv4i64( , *, , @@ -1529,12 +1529,12 @@ declare @llvm.riscv.xvlw.mask.nxv4i64.nxv4i64( define @intrinsic_xvlw_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlw.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -1543,7 +1543,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlw.nxv8i64.nxv8i64( , *, iXLen); @@ -1551,12 +1551,12 @@ declare @llvm.riscv.xvlw.nxv8i64.nxv8i64( define @intrinsic_xvlw_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlw_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlw.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlw.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -1564,7 +1564,7 @@ entry: ret %a } -declare @llvm.riscv.xvlw.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlw.mask.nxv8i64.nxv8i64( , *, , @@ -1573,12 +1573,12 @@ declare @llvm.riscv.xvlw.mask.nxv8i64.nxv8i64( define @intrinsic_xvlw_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlw_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlw.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlw.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -1587,7 +1587,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vle.nxv8i8.nxv8i8( , *, iXLen); @@ -1595,12 +1595,12 @@ declare @llvm.riscv.xvle.nxv8i8.nxv8i8( define @intrinsic_xvle_v_nxv8i8_nxv8i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vle.nxv8i8.nxv8i8( undef, * %0, iXLen %1) @@ -1608,7 +1608,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vle.mask.nxv8i8.nxv8i8( , *, , @@ -1617,12 +1617,12 @@ declare @llvm.riscv.xvle.mask.nxv8i8.nxv8i8( define @intrinsic_xvle_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vle.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -1631,7 +1631,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vle.nxv16i8.nxv16i8( , *, iXLen); @@ -1639,12 +1639,12 @@ declare @llvm.riscv.xvle.nxv16i8.nxv16i8( define @intrinsic_xvle_v_nxv16i8_nxv16i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vle.nxv16i8.nxv16i8( undef, * %0, iXLen %1) @@ -1652,7 +1652,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vle.mask.nxv16i8.nxv16i8( , *, , @@ -1661,12 +1661,12 @@ declare @llvm.riscv.xvle.mask.nxv16i8.nxv16i8( define @intrinsic_xvle_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vle.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -1675,7 +1675,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vle.nxv32i8.nxv32i8( , *, iXLen); @@ -1683,12 +1683,12 @@ declare @llvm.riscv.xvle.nxv32i8.nxv32i8( define @intrinsic_xvle_v_nxv32i8_nxv32i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vle.nxv32i8.nxv32i8( undef, * %0, iXLen %1) @@ -1696,7 +1696,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vle.mask.nxv32i8.nxv32i8( , *, , @@ -1705,12 +1705,12 @@ declare @llvm.riscv.xvle.mask.nxv32i8.nxv32i8( define @intrinsic_xvle_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vle.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -1719,7 +1719,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vle.nxv64i8.nxv64i8( , *, iXLen); @@ -1727,12 +1727,12 @@ declare @llvm.riscv.xvle.nxv64i8.nxv64i8( define @intrinsic_xvle_v_nxv64i8_nxv64i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vle.nxv64i8.nxv64i8( undef, * %0, iXLen %1) @@ -1740,7 +1740,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vle.mask.nxv64i8.nxv64i8( , *, , @@ -1749,12 +1749,12 @@ declare @llvm.riscv.xvle.mask.nxv64i8.nxv64i8( define @intrinsic_xvle_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vle.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -1763,7 +1763,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vle.nxv4i16.nxv4i16( , *, iXLen); @@ -1771,12 +1771,12 @@ declare @llvm.riscv.xvle.nxv4i16.nxv4i16( define @intrinsic_xvle_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vle.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -1784,7 +1784,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vle.mask.nxv4i16.nxv4i16( , *, , @@ -1793,12 +1793,12 @@ declare @llvm.riscv.xvle.mask.nxv4i16.nxv4i16( define @intrinsic_xvle_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vle.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -1807,7 +1807,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vle.nxv8i16.nxv8i16( , *, iXLen); @@ -1815,12 +1815,12 @@ declare @llvm.riscv.xvle.nxv8i16.nxv8i16( define @intrinsic_xvle_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vle.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -1828,7 +1828,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vle.mask.nxv8i16.nxv8i16( , *, , @@ -1837,12 +1837,12 @@ declare @llvm.riscv.xvle.mask.nxv8i16.nxv8i16( define @intrinsic_xvle_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vle.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -1851,7 +1851,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vle.nxv16i16.nxv16i16( , *, iXLen); @@ -1859,12 +1859,12 @@ declare @llvm.riscv.xvle.nxv16i16.nxv16i16( define @intrinsic_xvle_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vle.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -1872,7 +1872,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vle.mask.nxv16i16.nxv16i16( , *, , @@ -1881,12 +1881,12 @@ declare @llvm.riscv.xvle.mask.nxv16i16.nxv16i16( define @intrinsic_xvle_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vle.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -1895,7 +1895,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vle.nxv32i16.nxv32i16( , *, iXLen); @@ -1903,12 +1903,12 @@ declare @llvm.riscv.xvle.nxv32i16.nxv32i16( define @intrinsic_xvle_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vle.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -1916,7 +1916,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vle.mask.nxv32i16.nxv32i16( , *, , @@ -1925,12 +1925,12 @@ declare @llvm.riscv.xvle.mask.nxv32i16.nxv32i16( define @intrinsic_xvle_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vle.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -1939,7 +1939,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv4f16.nxv4f16( +declare @llvm.riscv.th.vle.nxv4f16.nxv4f16( , *, iXLen); @@ -1947,12 +1947,12 @@ declare @llvm.riscv.xvle.nxv4f16.nxv4f16( define @intrinsic_xvle_v_nxv4f16_nxv4f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv4f16.nxv4f16( + %a = call @llvm.riscv.th.vle.nxv4f16.nxv4f16( undef, * %0, iXLen %1) @@ -1960,7 +1960,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv4f16.nxv4f16( +declare @llvm.riscv.th.vle.mask.nxv4f16.nxv4f16( , *, , @@ -1969,12 +1969,12 @@ declare @llvm.riscv.xvle.mask.nxv4f16.nxv4f16( define @intrinsic_xvle_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv4f16.nxv4f16( + %a = call @llvm.riscv.th.vle.mask.nxv4f16.nxv4f16( %0, * %1, %2, @@ -1983,7 +1983,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8f16.nxv8f16( +declare @llvm.riscv.th.vle.nxv8f16.nxv8f16( , *, iXLen); @@ -1991,12 +1991,12 @@ declare @llvm.riscv.xvle.nxv8f16.nxv8f16( define @intrinsic_xvle_v_nxv8f16_nxv8f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8f16.nxv8f16( + %a = call @llvm.riscv.th.vle.nxv8f16.nxv8f16( undef, * %0, iXLen %1) @@ -2004,7 +2004,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8f16.nxv8f16( +declare @llvm.riscv.th.vle.mask.nxv8f16.nxv8f16( , *, , @@ -2013,12 +2013,12 @@ declare @llvm.riscv.xvle.mask.nxv8f16.nxv8f16( define @intrinsic_xvle_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8f16.nxv8f16( + %a = call @llvm.riscv.th.vle.mask.nxv8f16.nxv8f16( %0, * %1, %2, @@ -2027,7 +2027,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv16f16.nxv16f16( +declare @llvm.riscv.th.vle.nxv16f16.nxv16f16( , *, iXLen); @@ -2035,12 +2035,12 @@ declare @llvm.riscv.xvle.nxv16f16.nxv16f16( define @intrinsic_xvle_v_nxv16f16_nxv16f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv16f16.nxv16f16( + %a = call @llvm.riscv.th.vle.nxv16f16.nxv16f16( undef, * %0, iXLen %1) @@ -2048,7 +2048,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv16f16.nxv16f16( +declare @llvm.riscv.th.vle.mask.nxv16f16.nxv16f16( , *, , @@ -2057,12 +2057,12 @@ declare @llvm.riscv.xvle.mask.nxv16f16.nxv16f16( define @intrinsic_xvle_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv16f16.nxv16f16( + %a = call @llvm.riscv.th.vle.mask.nxv16f16.nxv16f16( %0, * %1, %2, @@ -2071,7 +2071,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv32f16.nxv32f16( +declare @llvm.riscv.th.vle.nxv32f16.nxv32f16( , *, iXLen); @@ -2079,12 +2079,12 @@ declare @llvm.riscv.xvle.nxv32f16.nxv32f16( define @intrinsic_xvle_v_nxv32f16_nxv32f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv32f16.nxv32f16( + %a = call @llvm.riscv.th.vle.nxv32f16.nxv32f16( undef, * %0, iXLen %1) @@ -2092,7 +2092,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv32f16.nxv32f16( +declare @llvm.riscv.th.vle.mask.nxv32f16.nxv32f16( , *, , @@ -2101,12 +2101,12 @@ declare @llvm.riscv.xvle.mask.nxv32f16.nxv32f16( define @intrinsic_xvle_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv32f16.nxv32f16( + %a = call @llvm.riscv.th.vle.mask.nxv32f16.nxv32f16( %0, * %1, %2, @@ -2115,7 +2115,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vle.nxv2i32.nxv2i32( , *, iXLen); @@ -2123,12 +2123,12 @@ declare @llvm.riscv.xvle.nxv2i32.nxv2i32( define @intrinsic_xvle_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vle.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -2136,7 +2136,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vle.mask.nxv2i32.nxv2i32( , *, , @@ -2145,12 +2145,12 @@ declare @llvm.riscv.xvle.mask.nxv2i32.nxv2i32( define @intrinsic_xvle_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vle.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -2159,7 +2159,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vle.nxv4i32.nxv4i32( , *, iXLen); @@ -2167,12 +2167,12 @@ declare @llvm.riscv.xvle.nxv4i32.nxv4i32( define @intrinsic_xvle_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vle.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -2180,7 +2180,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vle.mask.nxv4i32.nxv4i32( , *, , @@ -2189,12 +2189,12 @@ declare @llvm.riscv.xvle.mask.nxv4i32.nxv4i32( define @intrinsic_xvle_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vle.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -2203,7 +2203,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vle.nxv8i32.nxv8i32( , *, iXLen); @@ -2211,12 +2211,12 @@ declare @llvm.riscv.xvle.nxv8i32.nxv8i32( define @intrinsic_xvle_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vle.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -2224,7 +2224,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vle.mask.nxv8i32.nxv8i32( , *, , @@ -2233,12 +2233,12 @@ declare @llvm.riscv.xvle.mask.nxv8i32.nxv8i32( define @intrinsic_xvle_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vle.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -2247,7 +2247,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vle.nxv16i32.nxv16i32( , *, iXLen); @@ -2255,12 +2255,12 @@ declare @llvm.riscv.xvle.nxv16i32.nxv16i32( define @intrinsic_xvle_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vle.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -2268,7 +2268,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vle.mask.nxv16i32.nxv16i32( , *, , @@ -2277,12 +2277,12 @@ declare @llvm.riscv.xvle.mask.nxv16i32.nxv16i32( define @intrinsic_xvle_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vle.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -2291,7 +2291,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv2f32.nxv2f32( +declare @llvm.riscv.th.vle.nxv2f32.nxv2f32( , *, iXLen); @@ -2299,12 +2299,12 @@ declare @llvm.riscv.xvle.nxv2f32.nxv2f32( define @intrinsic_xvle_v_nxv2f32_nxv2f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv2f32.nxv2f32( + %a = call @llvm.riscv.th.vle.nxv2f32.nxv2f32( undef, * %0, iXLen %1) @@ -2312,7 +2312,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv2f32.nxv2f32( +declare @llvm.riscv.th.vle.mask.nxv2f32.nxv2f32( , *, , @@ -2321,12 +2321,12 @@ declare @llvm.riscv.xvle.mask.nxv2f32.nxv2f32( define @intrinsic_xvle_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv2f32.nxv2f32( + %a = call @llvm.riscv.th.vle.mask.nxv2f32.nxv2f32( %0, * %1, %2, @@ -2335,7 +2335,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv4f32.nxv4f32( +declare @llvm.riscv.th.vle.nxv4f32.nxv4f32( , *, iXLen); @@ -2343,12 +2343,12 @@ declare @llvm.riscv.xvle.nxv4f32.nxv4f32( define @intrinsic_xvle_v_nxv4f32_nxv4f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv4f32.nxv4f32( + %a = call @llvm.riscv.th.vle.nxv4f32.nxv4f32( undef, * %0, iXLen %1) @@ -2356,7 +2356,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv4f32.nxv4f32( +declare @llvm.riscv.th.vle.mask.nxv4f32.nxv4f32( , *, , @@ -2365,12 +2365,12 @@ declare @llvm.riscv.xvle.mask.nxv4f32.nxv4f32( define @intrinsic_xvle_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv4f32.nxv4f32( + %a = call @llvm.riscv.th.vle.mask.nxv4f32.nxv4f32( %0, * %1, %2, @@ -2379,7 +2379,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8f32.nxv8f32( +declare @llvm.riscv.th.vle.nxv8f32.nxv8f32( , *, iXLen); @@ -2387,12 +2387,12 @@ declare @llvm.riscv.xvle.nxv8f32.nxv8f32( define @intrinsic_xvle_v_nxv8f32_nxv8f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8f32.nxv8f32( + %a = call @llvm.riscv.th.vle.nxv8f32.nxv8f32( undef, * %0, iXLen %1) @@ -2400,7 +2400,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8f32.nxv8f32( +declare @llvm.riscv.th.vle.mask.nxv8f32.nxv8f32( , *, , @@ -2409,12 +2409,12 @@ declare @llvm.riscv.xvle.mask.nxv8f32.nxv8f32( define @intrinsic_xvle_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8f32.nxv8f32( + %a = call @llvm.riscv.th.vle.mask.nxv8f32.nxv8f32( %0, * %1, %2, @@ -2423,7 +2423,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv16f32.nxv16f32( +declare @llvm.riscv.th.vle.nxv16f32.nxv16f32( , *, iXLen); @@ -2431,12 +2431,12 @@ declare @llvm.riscv.xvle.nxv16f32.nxv16f32( define @intrinsic_xvle_v_nxv16f32_nxv16f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv16f32.nxv16f32( + %a = call @llvm.riscv.th.vle.nxv16f32.nxv16f32( undef, * %0, iXLen %1) @@ -2444,7 +2444,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv16f32.nxv16f32( +declare @llvm.riscv.th.vle.mask.nxv16f32.nxv16f32( , *, , @@ -2453,12 +2453,12 @@ declare @llvm.riscv.xvle.mask.nxv16f32.nxv16f32( define @intrinsic_xvle_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv16f32.nxv16f32( + %a = call @llvm.riscv.th.vle.mask.nxv16f32.nxv16f32( %0, * %1, %2, @@ -2467,7 +2467,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vle.nxv1i64.nxv1i64( , *, iXLen); @@ -2475,12 +2475,12 @@ declare @llvm.riscv.xvle.nxv1i64.nxv1i64( define @intrinsic_xvle_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vle.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -2488,7 +2488,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vle.mask.nxv1i64.nxv1i64( , *, , @@ -2497,12 +2497,12 @@ declare @llvm.riscv.xvle.mask.nxv1i64.nxv1i64( define @intrinsic_xvle_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vle.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -2511,7 +2511,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vle.nxv2i64.nxv2i64( , *, iXLen); @@ -2519,12 +2519,12 @@ declare @llvm.riscv.xvle.nxv2i64.nxv2i64( define @intrinsic_xvle_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vle.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -2532,7 +2532,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vle.mask.nxv2i64.nxv2i64( , *, , @@ -2541,12 +2541,12 @@ declare @llvm.riscv.xvle.mask.nxv2i64.nxv2i64( define @intrinsic_xvle_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vle.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -2555,7 +2555,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vle.nxv4i64.nxv4i64( , *, iXLen); @@ -2563,12 +2563,12 @@ declare @llvm.riscv.xvle.nxv4i64.nxv4i64( define @intrinsic_xvle_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vle.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -2576,7 +2576,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vle.mask.nxv4i64.nxv4i64( , *, , @@ -2585,12 +2585,12 @@ declare @llvm.riscv.xvle.mask.nxv4i64.nxv4i64( define @intrinsic_xvle_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vle.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -2599,7 +2599,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vle.nxv8i64.nxv8i64( , *, iXLen); @@ -2607,12 +2607,12 @@ declare @llvm.riscv.xvle.nxv8i64.nxv8i64( define @intrinsic_xvle_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vle.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -2620,7 +2620,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vle.mask.nxv8i64.nxv8i64( , *, , @@ -2629,12 +2629,12 @@ declare @llvm.riscv.xvle.mask.nxv8i64.nxv8i64( define @intrinsic_xvle_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vle.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -2643,7 +2643,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv1f64.nxv1f64( +declare @llvm.riscv.th.vle.nxv1f64.nxv1f64( , *, iXLen); @@ -2651,12 +2651,12 @@ declare @llvm.riscv.xvle.nxv1f64.nxv1f64( define @intrinsic_xvle_v_nxv1f64_nxv1f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv1f64.nxv1f64( + %a = call @llvm.riscv.th.vle.nxv1f64.nxv1f64( undef, * %0, iXLen %1) @@ -2664,7 +2664,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv1f64.nxv1f64( +declare @llvm.riscv.th.vle.mask.nxv1f64.nxv1f64( , *, , @@ -2673,12 +2673,12 @@ declare @llvm.riscv.xvle.mask.nxv1f64.nxv1f64( define @intrinsic_xvle_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv1f64.nxv1f64( + %a = call @llvm.riscv.th.vle.mask.nxv1f64.nxv1f64( %0, * %1, %2, @@ -2687,7 +2687,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv2f64.nxv2f64( +declare @llvm.riscv.th.vle.nxv2f64.nxv2f64( , *, iXLen); @@ -2695,12 +2695,12 @@ declare @llvm.riscv.xvle.nxv2f64.nxv2f64( define @intrinsic_xvle_v_nxv2f64_nxv2f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv2f64.nxv2f64( + %a = call @llvm.riscv.th.vle.nxv2f64.nxv2f64( undef, * %0, iXLen %1) @@ -2708,7 +2708,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv2f64.nxv2f64( +declare @llvm.riscv.th.vle.mask.nxv2f64.nxv2f64( , *, , @@ -2717,12 +2717,12 @@ declare @llvm.riscv.xvle.mask.nxv2f64.nxv2f64( define @intrinsic_xvle_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv2f64.nxv2f64( + %a = call @llvm.riscv.th.vle.mask.nxv2f64.nxv2f64( %0, * %1, %2, @@ -2731,7 +2731,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv4f64.nxv4f64( +declare @llvm.riscv.th.vle.nxv4f64.nxv4f64( , *, iXLen); @@ -2739,12 +2739,12 @@ declare @llvm.riscv.xvle.nxv4f64.nxv4f64( define @intrinsic_xvle_v_nxv4f64_nxv4f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv4f64.nxv4f64( + %a = call @llvm.riscv.th.vle.nxv4f64.nxv4f64( undef, * %0, iXLen %1) @@ -2752,7 +2752,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv4f64.nxv4f64( +declare @llvm.riscv.th.vle.mask.nxv4f64.nxv4f64( , *, , @@ -2761,12 +2761,12 @@ declare @llvm.riscv.xvle.mask.nxv4f64.nxv4f64( define @intrinsic_xvle_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv4f64.nxv4f64( + %a = call @llvm.riscv.th.vle.mask.nxv4f64.nxv4f64( %0, * %1, %2, @@ -2775,7 +2775,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.nxv8f64.nxv8f64( +declare @llvm.riscv.th.vle.nxv8f64.nxv8f64( , *, iXLen); @@ -2783,12 +2783,12 @@ declare @llvm.riscv.xvle.nxv8f64.nxv8f64( define @intrinsic_xvle_v_nxv8f64_nxv8f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvle_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vle.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.nxv8f64.nxv8f64( + %a = call @llvm.riscv.th.vle.nxv8f64.nxv8f64( undef, * %0, iXLen %1) @@ -2796,7 +2796,7 @@ entry: ret %a } -declare @llvm.riscv.xvle.mask.nxv8f64.nxv8f64( +declare @llvm.riscv.th.vle.mask.nxv8f64.nxv8f64( , *, , @@ -2805,12 +2805,12 @@ declare @llvm.riscv.xvle.mask.nxv8f64.nxv8f64( define @intrinsic_xvle_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvle_mask_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vle.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvle.mask.nxv8f64.nxv8f64( + %a = call @llvm.riscv.th.vle.mask.nxv8f64.nxv8f64( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vleff.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vleff.ll index 9fbd3133d8856..e9c1c03f7b533 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vleff.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vleff.ll @@ -1,6 +1,6 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64 declare { , iXLen } @llvm.riscv.th.vleff.nxv8i8.nxv8i8( @@ -11,16 +11,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8i8.nxv8i8( define @intrinsic_vleff_v_nxv8i8_nxv8i8(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -45,16 +45,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8i8.nxv8i8( define @intrinsic_vleff_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -79,16 +79,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv16i8.nxv16i8( define @intrinsic_vleff_v_nxv16i8_nxv16i8(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -113,16 +113,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv16i8.nxv16i8( define @intrinsic_vleff_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -147,16 +147,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv32i8.nxv32i8( define @intrinsic_vleff_v_nxv32i8_nxv32i8(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -181,16 +181,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv32i8.nxv32i8( define @intrinsic_vleff_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -215,16 +215,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv64i8.nxv64i8( define @intrinsic_vleff_v_nxv64i8_nxv64i8(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -249,16 +249,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv64i8.nxv64i8( define @intrinsic_vleff_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e8, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e8, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -283,16 +283,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv4i16.nxv4i16( define @intrinsic_vleff_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -317,16 +317,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv4i16.nxv4i16( define @intrinsic_vleff_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -351,16 +351,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8i16.nxv8i16( define @intrinsic_vleff_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -385,16 +385,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8i16.nxv8i16( define @intrinsic_vleff_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -419,16 +419,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv16i16.nxv16i16( define @intrinsic_vleff_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -453,16 +453,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv16i16.nxv16i define @intrinsic_vleff_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -487,16 +487,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv32i16.nxv32i16( define @intrinsic_vleff_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -521,16 +521,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv32i16.nxv32i define @intrinsic_vleff_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -555,16 +555,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv4f16.nxv4f16( define @intrinsic_vleff_v_nxv4f16_nxv4f16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv4f16_nxv4f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv4f16_nxv4f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -589,16 +589,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv4f16.nxv4f16 define @intrinsic_vleff_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv4f16_nxv4f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv4f16_nxv4f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -623,16 +623,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8f16.nxv8f16( define @intrinsic_vleff_v_nxv8f16_nxv8f16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8f16_nxv8f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8f16_nxv8f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -657,16 +657,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8f16.nxv8f16 define @intrinsic_vleff_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8f16_nxv8f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8f16_nxv8f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -691,16 +691,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv16f16.nxv16f16( define @intrinsic_vleff_v_nxv16f16_nxv16f16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv16f16_nxv16f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv16f16_nxv16f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -725,16 +725,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv16f16.nxv16 define @intrinsic_vleff_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv16f16_nxv16f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv16f16_nxv16f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -759,16 +759,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv32f16.nxv32f16( define @intrinsic_vleff_v_nxv32f16_nxv32f16(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv32f16_nxv32f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv32f16_nxv32f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -793,16 +793,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv32f16.nxv32 define @intrinsic_vleff_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv32f16_nxv32f16: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv32f16_nxv32f16: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e16, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -827,16 +827,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv2i32.nxv2i32( define @intrinsic_vleff_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -861,16 +861,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv2i32.nxv2i32( define @intrinsic_vleff_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -895,16 +895,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv4i32.nxv4i32( define @intrinsic_vleff_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -929,16 +929,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv4i32.nxv4i32( define @intrinsic_vleff_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -963,16 +963,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8i32.nxv8i32( define @intrinsic_vleff_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -997,16 +997,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8i32.nxv8i32( define @intrinsic_vleff_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1031,16 +1031,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv16i32.nxv16i32( define @intrinsic_vleff_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1065,16 +1065,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv16i32.nxv16i define @intrinsic_vleff_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1099,16 +1099,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv2f32.nxv2f32( define @intrinsic_vleff_v_nxv2f32_nxv2f32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1133,16 +1133,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv2f32.nxv2f3 define @intrinsic_vleff_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1167,16 +1167,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv4f32.nxv4f32( define @intrinsic_vleff_v_nxv4f32_nxv4f32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1201,16 +1201,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv4f32.nxv4f3 define @intrinsic_vleff_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1235,16 +1235,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8f32.nxv8f32( define @intrinsic_vleff_v_nxv8f32_nxv8f32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1269,16 +1269,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8f32.nxv8f3 define @intrinsic_vleff_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1303,16 +1303,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv16f32.nxv16f32( define @intrinsic_vleff_v_nxv16f32_nxv16f32(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1337,16 +1337,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv16f32.nxv1 define @intrinsic_vleff_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e32, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1371,16 +1371,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv1i64.nxv1i64( define @intrinsic_vleff_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1405,16 +1405,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv1i64.nxv1i64( define @intrinsic_vleff_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1439,16 +1439,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv2i64.nxv2i64( define @intrinsic_vleff_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1473,16 +1473,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv2i64.nxv2i64( define @intrinsic_vleff_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv2i64_nxv2i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv2i64_nxv2i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1507,16 +1507,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv4i64.nxv4i64( define @intrinsic_vleff_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1541,16 +1541,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv4i64.nxv4i64( define @intrinsic_vleff_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i64_nxv4i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i64_nxv4i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1575,16 +1575,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8i64.nxv8i64( define @intrinsic_vleff_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1609,16 +1609,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8i64.nxv8i64( define @intrinsic_vleff_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i64_nxv8i64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i64_nxv8i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1643,16 +1643,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv1f64.nxv1f64( define @intrinsic_vleff_v_nxv1f64_nxv1f64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1677,16 +1677,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv1f64.nxv1f define @intrinsic_vleff_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv1f64_nxv1f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv1f64_nxv1f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1711,16 +1711,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv2f64.nxv2f64( define @intrinsic_vleff_v_nxv2f64_nxv2f64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1745,16 +1745,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv2f64.nxv2f define @intrinsic_vleff_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv2f64_nxv2f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv2f64_nxv2f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m2, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1779,16 +1779,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv4f64.nxv4f64( define @intrinsic_vleff_v_nxv4f64_nxv4f64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1813,16 +1813,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv4f64.nxv4f define @intrinsic_vleff_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv4f64_nxv4f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv4f64_nxv4f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m4, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1847,16 +1847,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.nxv8f64.nxv8f64( define @intrinsic_vleff_v_nxv8f64_nxv8f64(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1881,16 +1881,16 @@ declare { , iXLen } @llvm.riscv.th.vleff.mask.nxv8f64.nxv8f define @intrinsic_vleff_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_v_nxv8f64_nxv8f64: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_v_nxv8f64_nxv8f64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m8, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1911,8 +1911,8 @@ entry: define @intrinsic_vleff_dead_vl(* %0, iXLen %1, iXLen* %2) nounwind { ; CHECK-LABEL: intrinsic_vleff_dead_vl: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vleff.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vleff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call { , iXLen } @llvm.riscv.th.vleff.nxv1f64.nxv1f64( @@ -1926,8 +1926,8 @@ entry: define @intrinsic_vleff_mask_dead_vl( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vleff_mask_dead_vl: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vleff.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vleff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call { , iXLen } @llvm.riscv.th.vleff.mask.nxv1f64.nxv1f64( @@ -1944,16 +1944,16 @@ entry: define void @intrinsic_vleff_dead_value(* %0, iXLen %1, iXLen* %2) nounwind { ; RV32-LABEL: intrinsic_vleff_dead_value: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV32-NEXT: vleff.v v8, (a0) +; RV32-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0) ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_dead_value: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV64-NEXT: vleff.v v8, (a0) +; RV64-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0) ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1970,16 +1970,16 @@ entry: define void @intrinsic_vleff_mask_dead_value( %0, * %1, %2, iXLen %3, iXLen* %4) nounwind { ; RV32-LABEL: intrinsic_vleff_mask_dead_value: ; RV32: # %bb.0: # %entry -; RV32-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV32-NEXT: vleff.v v8, (a0), v0.t +; RV32-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV32-NEXT: th.vleff.v v8, (a0), v0.t ; RV32-NEXT: csrr a0, vl ; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vleff_mask_dead_value: ; RV64: # %bb.0: # %entry -; RV64-NEXT: vsetvli zero, a1, e64, m1, d1 -; RV64-NEXT: vleff.v v8, (a0), v0.t +; RV64-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; RV64-NEXT: th.vleff.v v8, (a0), v0.t ; RV64-NEXT: csrr a0, vl ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret @@ -1999,8 +1999,8 @@ entry: define void @intrinsic_vleff_dead_all(* %0, iXLen %1, iXLen* %2) nounwind { ; CHECK-LABEL: intrinsic_vleff_dead_all: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vleff.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vleff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call { , iXLen } @llvm.riscv.th.vleff.nxv1f64.nxv1f64( @@ -2013,8 +2013,8 @@ entry: define void @intrinsic_vleff_mask_dead_all( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vleff_mask_dead_all: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vleff.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vleff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call { , iXLen } @llvm.riscv.th.vleff.mask.nxv1f64.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vls.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vls.ll index 80f8bcf9acc6a..107bdb7f17dea 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vls.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vls.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlsb.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlsb.nxv8i8.nxv8i8( , *, iXLen, @@ -12,12 +12,12 @@ declare @llvm.riscv.xvlsb.nxv8i8.nxv8i8( define @intrinsic_xvlsb_v_nxv8i8_nxv8i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlsb.nxv8i8.nxv8i8( undef, * %0, iXLen %1, @@ -26,7 +26,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlsb.mask.nxv8i8.nxv8i8( , *, iXLen, @@ -36,12 +36,12 @@ declare @llvm.riscv.xvlsb.mask.nxv8i8.nxv8i8( define @intrinsic_xvlsb_mask_v_nxv8i8_nxv8i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlsb.mask.nxv8i8.nxv8i8( %0, * %1, iXLen %2, @@ -51,7 +51,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlsb.nxv16i8.nxv16i8( , *, iXLen, @@ -60,12 +60,12 @@ declare @llvm.riscv.xvlsb.nxv16i8.nxv16i8( define @intrinsic_xvlsb_v_nxv16i8_nxv16i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlsb.nxv16i8.nxv16i8( undef, * %0, iXLen %1, @@ -74,7 +74,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlsb.mask.nxv16i8.nxv16i8( , *, iXLen, @@ -84,12 +84,12 @@ declare @llvm.riscv.xvlsb.mask.nxv16i8.nxv16i8( define @intrinsic_xvlsb_mask_v_nxv16i8_nxv16i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlsb.mask.nxv16i8.nxv16i8( %0, * %1, iXLen %2, @@ -99,7 +99,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlsb.nxv32i8.nxv32i8( , *, iXLen, @@ -108,12 +108,12 @@ declare @llvm.riscv.xvlsb.nxv32i8.nxv32i8( define @intrinsic_xvlsb_v_nxv32i8_nxv32i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlsb.nxv32i8.nxv32i8( undef, * %0, iXLen %1, @@ -122,7 +122,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlsb.mask.nxv32i8.nxv32i8( , *, iXLen, @@ -132,12 +132,12 @@ declare @llvm.riscv.xvlsb.mask.nxv32i8.nxv32i8( define @intrinsic_xvlsb_mask_v_nxv32i8_nxv32i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlsb.mask.nxv32i8.nxv32i8( %0, * %1, iXLen %2, @@ -147,7 +147,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlsb.nxv64i8.nxv64i8( , *, iXLen, @@ -156,12 +156,12 @@ declare @llvm.riscv.xvlsb.nxv64i8.nxv64i8( define @intrinsic_xvlsb_v_nxv64i8_nxv64i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlsb.nxv64i8.nxv64i8( undef, * %0, iXLen %1, @@ -170,7 +170,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlsb.mask.nxv64i8.nxv64i8( , *, iXLen, @@ -180,12 +180,12 @@ declare @llvm.riscv.xvlsb.mask.nxv64i8.nxv64i8( define @intrinsic_xvlsb_mask_v_nxv64i8_nxv64i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlsb.mask.nxv64i8.nxv64i8( %0, * %1, iXLen %2, @@ -195,7 +195,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlsb.nxv4i16.nxv4i16( , *, iXLen, @@ -204,12 +204,12 @@ declare @llvm.riscv.xvlsb.nxv4i16.nxv4i16( define @intrinsic_xvlsb_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlsb.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -218,7 +218,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlsb.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -228,12 +228,12 @@ declare @llvm.riscv.xvlsb.mask.nxv4i16.nxv4i16( define @intrinsic_xvlsb_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlsb.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -243,7 +243,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlsb.nxv8i16.nxv8i16( , *, iXLen, @@ -252,12 +252,12 @@ declare @llvm.riscv.xvlsb.nxv8i16.nxv8i16( define @intrinsic_xvlsb_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlsb.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -266,7 +266,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlsb.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -276,12 +276,12 @@ declare @llvm.riscv.xvlsb.mask.nxv8i16.nxv8i16( define @intrinsic_xvlsb_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlsb.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -291,7 +291,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlsb.nxv16i16.nxv16i16( , *, iXLen, @@ -300,12 +300,12 @@ declare @llvm.riscv.xvlsb.nxv16i16.nxv16i16( define @intrinsic_xvlsb_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlsb.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -314,7 +314,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlsb.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -324,12 +324,12 @@ declare @llvm.riscv.xvlsb.mask.nxv16i16.nxv16i16( define @intrinsic_xvlsb_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlsb.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -339,7 +339,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlsb.nxv32i16.nxv32i16( , *, iXLen, @@ -348,12 +348,12 @@ declare @llvm.riscv.xvlsb.nxv32i16.nxv32i16( define @intrinsic_xvlsb_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlsb.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -362,7 +362,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlsb.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -372,12 +372,12 @@ declare @llvm.riscv.xvlsb.mask.nxv32i16.nxv32i16( define @intrinsic_xvlsb_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlsb.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -387,7 +387,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsb.nxv2i32.nxv2i32( , *, iXLen, @@ -396,12 +396,12 @@ declare @llvm.riscv.xvlsb.nxv2i32.nxv2i32( define @intrinsic_xvlsb_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsb.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -410,7 +410,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsb.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -420,12 +420,12 @@ declare @llvm.riscv.xvlsb.mask.nxv2i32.nxv2i32( define @intrinsic_xvlsb_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsb.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -435,7 +435,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsb.nxv4i32.nxv4i32( , *, iXLen, @@ -444,12 +444,12 @@ declare @llvm.riscv.xvlsb.nxv4i32.nxv4i32( define @intrinsic_xvlsb_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsb.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -458,7 +458,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsb.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -468,12 +468,12 @@ declare @llvm.riscv.xvlsb.mask.nxv4i32.nxv4i32( define @intrinsic_xvlsb_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsb.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -483,7 +483,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsb.nxv8i32.nxv8i32( , *, iXLen, @@ -492,12 +492,12 @@ declare @llvm.riscv.xvlsb.nxv8i32.nxv8i32( define @intrinsic_xvlsb_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsb.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -506,7 +506,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsb.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -516,12 +516,12 @@ declare @llvm.riscv.xvlsb.mask.nxv8i32.nxv8i32( define @intrinsic_xvlsb_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsb.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -531,7 +531,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsb.nxv16i32.nxv16i32( , *, iXLen, @@ -540,12 +540,12 @@ declare @llvm.riscv.xvlsb.nxv16i32.nxv16i32( define @intrinsic_xvlsb_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsb.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -554,7 +554,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsb.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -564,12 +564,12 @@ declare @llvm.riscv.xvlsb.mask.nxv16i32.nxv16i32( define @intrinsic_xvlsb_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsb.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -579,7 +579,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsb.nxv1i64.nxv1i64( , *, iXLen, @@ -588,12 +588,12 @@ declare @llvm.riscv.xvlsb.nxv1i64.nxv1i64( define @intrinsic_xvlsb_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsb.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -602,7 +602,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsb.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -612,12 +612,12 @@ declare @llvm.riscv.xvlsb.mask.nxv1i64.nxv1i64( define @intrinsic_xvlsb_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsb.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsb.nxv2i64.nxv2i64( , *, iXLen, @@ -636,12 +636,12 @@ declare @llvm.riscv.xvlsb.nxv2i64.nxv2i64( define @intrinsic_xvlsb_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsb.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -650,7 +650,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsb.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -660,12 +660,12 @@ declare @llvm.riscv.xvlsb.mask.nxv2i64.nxv2i64( define @intrinsic_xvlsb_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsb.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -675,7 +675,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsb.nxv4i64.nxv4i64( , *, iXLen, @@ -684,12 +684,12 @@ declare @llvm.riscv.xvlsb.nxv4i64.nxv4i64( define @intrinsic_xvlsb_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsb.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -698,7 +698,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsb.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -708,12 +708,12 @@ declare @llvm.riscv.xvlsb.mask.nxv4i64.nxv4i64( define @intrinsic_xvlsb_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsb.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -723,7 +723,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsb.nxv8i64.nxv8i64( , *, iXLen, @@ -732,12 +732,12 @@ declare @llvm.riscv.xvlsb.nxv8i64.nxv8i64( define @intrinsic_xvlsb_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsb.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -746,7 +746,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsb.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsb.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -756,12 +756,12 @@ declare @llvm.riscv.xvlsb.mask.nxv8i64.nxv8i64( define @intrinsic_xvlsb_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsb_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsb.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsb.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -771,7 +771,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlsh.nxv4i16.nxv4i16( , *, iXLen, @@ -780,12 +780,12 @@ declare @llvm.riscv.xvlsh.nxv4i16.nxv4i16( define @intrinsic_xvlsh_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlsh.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -794,7 +794,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlsh.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -804,12 +804,12 @@ declare @llvm.riscv.xvlsh.mask.nxv4i16.nxv4i16( define @intrinsic_xvlsh_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlsh.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -819,7 +819,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlsh.nxv8i16.nxv8i16( , *, iXLen, @@ -828,12 +828,12 @@ declare @llvm.riscv.xvlsh.nxv8i16.nxv8i16( define @intrinsic_xvlsh_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlsh.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -842,7 +842,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlsh.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -852,12 +852,12 @@ declare @llvm.riscv.xvlsh.mask.nxv8i16.nxv8i16( define @intrinsic_xvlsh_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlsh.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -867,7 +867,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlsh.nxv16i16.nxv16i16( , *, iXLen, @@ -876,12 +876,12 @@ declare @llvm.riscv.xvlsh.nxv16i16.nxv16i16( define @intrinsic_xvlsh_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlsh.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -890,7 +890,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlsh.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -900,12 +900,12 @@ declare @llvm.riscv.xvlsh.mask.nxv16i16.nxv16i16( define @intrinsic_xvlsh_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlsh.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -915,7 +915,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlsh.nxv32i16.nxv32i16( , *, iXLen, @@ -924,12 +924,12 @@ declare @llvm.riscv.xvlsh.nxv32i16.nxv32i16( define @intrinsic_xvlsh_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlsh.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -938,7 +938,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlsh.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -948,12 +948,12 @@ declare @llvm.riscv.xvlsh.mask.nxv32i16.nxv32i16( define @intrinsic_xvlsh_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlsh.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -963,7 +963,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsh.nxv2i32.nxv2i32( , *, iXLen, @@ -972,12 +972,12 @@ declare @llvm.riscv.xvlsh.nxv2i32.nxv2i32( define @intrinsic_xvlsh_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsh.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -986,7 +986,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsh.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -996,12 +996,12 @@ declare @llvm.riscv.xvlsh.mask.nxv2i32.nxv2i32( define @intrinsic_xvlsh_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsh.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -1011,7 +1011,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsh.nxv4i32.nxv4i32( , *, iXLen, @@ -1020,12 +1020,12 @@ declare @llvm.riscv.xvlsh.nxv4i32.nxv4i32( define @intrinsic_xvlsh_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsh.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -1034,7 +1034,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsh.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -1044,12 +1044,12 @@ declare @llvm.riscv.xvlsh.mask.nxv4i32.nxv4i32( define @intrinsic_xvlsh_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsh.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -1059,7 +1059,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsh.nxv8i32.nxv8i32( , *, iXLen, @@ -1068,12 +1068,12 @@ declare @llvm.riscv.xvlsh.nxv8i32.nxv8i32( define @intrinsic_xvlsh_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsh.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -1082,7 +1082,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsh.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -1092,12 +1092,12 @@ declare @llvm.riscv.xvlsh.mask.nxv8i32.nxv8i32( define @intrinsic_xvlsh_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsh.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -1107,7 +1107,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsh.nxv16i32.nxv16i32( , *, iXLen, @@ -1116,12 +1116,12 @@ declare @llvm.riscv.xvlsh.nxv16i32.nxv16i32( define @intrinsic_xvlsh_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsh.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -1130,7 +1130,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsh.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -1140,12 +1140,12 @@ declare @llvm.riscv.xvlsh.mask.nxv16i32.nxv16i32( define @intrinsic_xvlsh_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsh.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -1155,7 +1155,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsh.nxv1i64.nxv1i64( , *, iXLen, @@ -1164,12 +1164,12 @@ declare @llvm.riscv.xvlsh.nxv1i64.nxv1i64( define @intrinsic_xvlsh_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsh.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -1178,7 +1178,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsh.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -1188,12 +1188,12 @@ declare @llvm.riscv.xvlsh.mask.nxv1i64.nxv1i64( define @intrinsic_xvlsh_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsh.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -1203,7 +1203,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsh.nxv2i64.nxv2i64( , *, iXLen, @@ -1212,12 +1212,12 @@ declare @llvm.riscv.xvlsh.nxv2i64.nxv2i64( define @intrinsic_xvlsh_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsh.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -1226,7 +1226,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsh.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -1236,12 +1236,12 @@ declare @llvm.riscv.xvlsh.mask.nxv2i64.nxv2i64( define @intrinsic_xvlsh_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsh.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -1251,7 +1251,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsh.nxv4i64.nxv4i64( , *, iXLen, @@ -1260,12 +1260,12 @@ declare @llvm.riscv.xvlsh.nxv4i64.nxv4i64( define @intrinsic_xvlsh_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsh.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -1274,7 +1274,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsh.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -1284,12 +1284,12 @@ declare @llvm.riscv.xvlsh.mask.nxv4i64.nxv4i64( define @intrinsic_xvlsh_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsh.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -1299,7 +1299,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsh.nxv8i64.nxv8i64( , *, iXLen, @@ -1308,12 +1308,12 @@ declare @llvm.riscv.xvlsh.nxv8i64.nxv8i64( define @intrinsic_xvlsh_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsh.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -1322,7 +1322,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsh.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsh.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -1332,12 +1332,12 @@ declare @llvm.riscv.xvlsh.mask.nxv8i64.nxv8i64( define @intrinsic_xvlsh_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsh_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsh.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsh.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -1347,7 +1347,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsw.nxv2i32.nxv2i32( , *, iXLen, @@ -1356,12 +1356,12 @@ declare @llvm.riscv.xvlsw.nxv2i32.nxv2i32( define @intrinsic_xvlsw_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsw.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -1370,7 +1370,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsw.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -1380,12 +1380,12 @@ declare @llvm.riscv.xvlsw.mask.nxv2i32.nxv2i32( define @intrinsic_xvlsw_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsw.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -1395,7 +1395,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsw.nxv4i32.nxv4i32( , *, iXLen, @@ -1404,12 +1404,12 @@ declare @llvm.riscv.xvlsw.nxv4i32.nxv4i32( define @intrinsic_xvlsw_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsw.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -1418,7 +1418,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsw.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -1428,12 +1428,12 @@ declare @llvm.riscv.xvlsw.mask.nxv4i32.nxv4i32( define @intrinsic_xvlsw_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsw.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -1443,7 +1443,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsw.nxv8i32.nxv8i32( , *, iXLen, @@ -1452,12 +1452,12 @@ declare @llvm.riscv.xvlsw.nxv8i32.nxv8i32( define @intrinsic_xvlsw_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsw.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -1466,7 +1466,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsw.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -1476,12 +1476,12 @@ declare @llvm.riscv.xvlsw.mask.nxv8i32.nxv8i32( define @intrinsic_xvlsw_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsw.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -1491,7 +1491,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsw.nxv16i32.nxv16i32( , *, iXLen, @@ -1500,12 +1500,12 @@ declare @llvm.riscv.xvlsw.nxv16i32.nxv16i32( define @intrinsic_xvlsw_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsw.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -1514,7 +1514,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsw.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -1524,12 +1524,12 @@ declare @llvm.riscv.xvlsw.mask.nxv16i32.nxv16i32( define @intrinsic_xvlsw_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsw.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -1539,7 +1539,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsw.nxv1i64.nxv1i64( , *, iXLen, @@ -1548,12 +1548,12 @@ declare @llvm.riscv.xvlsw.nxv1i64.nxv1i64( define @intrinsic_xvlsw_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsw.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -1562,7 +1562,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsw.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -1572,12 +1572,12 @@ declare @llvm.riscv.xvlsw.mask.nxv1i64.nxv1i64( define @intrinsic_xvlsw_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsw.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -1587,7 +1587,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsw.nxv2i64.nxv2i64( , *, iXLen, @@ -1596,12 +1596,12 @@ declare @llvm.riscv.xvlsw.nxv2i64.nxv2i64( define @intrinsic_xvlsw_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsw.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -1610,7 +1610,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsw.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -1620,12 +1620,12 @@ declare @llvm.riscv.xvlsw.mask.nxv2i64.nxv2i64( define @intrinsic_xvlsw_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsw.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -1635,7 +1635,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsw.nxv4i64.nxv4i64( , *, iXLen, @@ -1644,12 +1644,12 @@ declare @llvm.riscv.xvlsw.nxv4i64.nxv4i64( define @intrinsic_xvlsw_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsw.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -1658,7 +1658,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsw.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -1668,12 +1668,12 @@ declare @llvm.riscv.xvlsw.mask.nxv4i64.nxv4i64( define @intrinsic_xvlsw_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsw.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -1683,7 +1683,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsw.nxv8i64.nxv8i64( , *, iXLen, @@ -1692,12 +1692,12 @@ declare @llvm.riscv.xvlsw.nxv8i64.nxv8i64( define @intrinsic_xvlsw_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsw.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -1706,7 +1706,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsw.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsw.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -1716,12 +1716,12 @@ declare @llvm.riscv.xvlsw.mask.nxv8i64.nxv8i64( define @intrinsic_xvlsw_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsw_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsw.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsw.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -1731,7 +1731,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlse.nxv8i8.nxv8i8( , *, iXLen, @@ -1740,12 +1740,12 @@ declare @llvm.riscv.xvlse.nxv8i8.nxv8i8( define @intrinsic_xvlse_v_nxv8i8_nxv8i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlse.nxv8i8.nxv8i8( undef, * %0, iXLen %1, @@ -1754,7 +1754,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlse.mask.nxv8i8.nxv8i8( , *, iXLen, @@ -1764,12 +1764,12 @@ declare @llvm.riscv.xvlse.mask.nxv8i8.nxv8i8( define @intrinsic_xvlse_mask_v_nxv8i8_nxv8i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlse.mask.nxv8i8.nxv8i8( %0, * %1, iXLen %2, @@ -1779,7 +1779,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlse.nxv16i8.nxv16i8( , *, iXLen, @@ -1788,12 +1788,12 @@ declare @llvm.riscv.xvlse.nxv16i8.nxv16i8( define @intrinsic_xvlse_v_nxv16i8_nxv16i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlse.nxv16i8.nxv16i8( undef, * %0, iXLen %1, @@ -1802,7 +1802,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlse.mask.nxv16i8.nxv16i8( , *, iXLen, @@ -1812,12 +1812,12 @@ declare @llvm.riscv.xvlse.mask.nxv16i8.nxv16i8( define @intrinsic_xvlse_mask_v_nxv16i8_nxv16i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlse.mask.nxv16i8.nxv16i8( %0, * %1, iXLen %2, @@ -1827,7 +1827,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlse.nxv32i8.nxv32i8( , *, iXLen, @@ -1836,12 +1836,12 @@ declare @llvm.riscv.xvlse.nxv32i8.nxv32i8( define @intrinsic_xvlse_v_nxv32i8_nxv32i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlse.nxv32i8.nxv32i8( undef, * %0, iXLen %1, @@ -1850,7 +1850,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlse.mask.nxv32i8.nxv32i8( , *, iXLen, @@ -1860,12 +1860,12 @@ declare @llvm.riscv.xvlse.mask.nxv32i8.nxv32i8( define @intrinsic_xvlse_mask_v_nxv32i8_nxv32i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlse.mask.nxv32i8.nxv32i8( %0, * %1, iXLen %2, @@ -1875,7 +1875,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlse.nxv64i8.nxv64i8( , *, iXLen, @@ -1884,12 +1884,12 @@ declare @llvm.riscv.xvlse.nxv64i8.nxv64i8( define @intrinsic_xvlse_v_nxv64i8_nxv64i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlse.nxv64i8.nxv64i8( undef, * %0, iXLen %1, @@ -1898,7 +1898,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlse.mask.nxv64i8.nxv64i8( , *, iXLen, @@ -1908,12 +1908,12 @@ declare @llvm.riscv.xvlse.mask.nxv64i8.nxv64i8( define @intrinsic_xvlse_mask_v_nxv64i8_nxv64i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlse.mask.nxv64i8.nxv64i8( %0, * %1, iXLen %2, @@ -1923,7 +1923,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlse.nxv4i16.nxv4i16( , *, iXLen, @@ -1932,12 +1932,12 @@ declare @llvm.riscv.xvlse.nxv4i16.nxv4i16( define @intrinsic_xvlse_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlse.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -1946,7 +1946,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlse.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -1956,12 +1956,12 @@ declare @llvm.riscv.xvlse.mask.nxv4i16.nxv4i16( define @intrinsic_xvlse_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlse.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -1971,7 +1971,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlse.nxv8i16.nxv8i16( , *, iXLen, @@ -1980,12 +1980,12 @@ declare @llvm.riscv.xvlse.nxv8i16.nxv8i16( define @intrinsic_xvlse_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlse.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -1994,7 +1994,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlse.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -2004,12 +2004,12 @@ declare @llvm.riscv.xvlse.mask.nxv8i16.nxv8i16( define @intrinsic_xvlse_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlse.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -2019,7 +2019,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlse.nxv16i16.nxv16i16( , *, iXLen, @@ -2028,12 +2028,12 @@ declare @llvm.riscv.xvlse.nxv16i16.nxv16i16( define @intrinsic_xvlse_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlse.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -2042,7 +2042,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlse.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -2052,12 +2052,12 @@ declare @llvm.riscv.xvlse.mask.nxv16i16.nxv16i16( define @intrinsic_xvlse_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlse.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -2067,7 +2067,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlse.nxv32i16.nxv32i16( , *, iXLen, @@ -2076,12 +2076,12 @@ declare @llvm.riscv.xvlse.nxv32i16.nxv32i16( define @intrinsic_xvlse_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlse.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -2090,7 +2090,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlse.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -2100,12 +2100,12 @@ declare @llvm.riscv.xvlse.mask.nxv32i16.nxv32i16( define @intrinsic_xvlse_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlse.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -2115,7 +2115,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv4f16.nxv4f16( +declare @llvm.riscv.th.vlse.nxv4f16.nxv4f16( , *, iXLen, @@ -2124,12 +2124,12 @@ declare @llvm.riscv.xvlse.nxv4f16.nxv4f16( define @intrinsic_xvlse_v_nxv4f16_nxv4f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv4f16.nxv4f16( + %a = call @llvm.riscv.th.vlse.nxv4f16.nxv4f16( undef, * %0, iXLen %1, @@ -2138,7 +2138,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv4f16.nxv4f16( +declare @llvm.riscv.th.vlse.mask.nxv4f16.nxv4f16( , *, iXLen, @@ -2148,12 +2148,12 @@ declare @llvm.riscv.xvlse.mask.nxv4f16.nxv4f16( define @intrinsic_xvlse_mask_v_nxv4f16_nxv4f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv4f16.nxv4f16( + %a = call @llvm.riscv.th.vlse.mask.nxv4f16.nxv4f16( %0, * %1, iXLen %2, @@ -2163,7 +2163,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8f16.nxv8f16( +declare @llvm.riscv.th.vlse.nxv8f16.nxv8f16( , *, iXLen, @@ -2172,12 +2172,12 @@ declare @llvm.riscv.xvlse.nxv8f16.nxv8f16( define @intrinsic_xvlse_v_nxv8f16_nxv8f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8f16.nxv8f16( + %a = call @llvm.riscv.th.vlse.nxv8f16.nxv8f16( undef, * %0, iXLen %1, @@ -2186,7 +2186,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8f16.nxv8f16( +declare @llvm.riscv.th.vlse.mask.nxv8f16.nxv8f16( , *, iXLen, @@ -2196,12 +2196,12 @@ declare @llvm.riscv.xvlse.mask.nxv8f16.nxv8f16( define @intrinsic_xvlse_mask_v_nxv8f16_nxv8f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8f16.nxv8f16( + %a = call @llvm.riscv.th.vlse.mask.nxv8f16.nxv8f16( %0, * %1, iXLen %2, @@ -2211,7 +2211,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv16f16.nxv16f16( +declare @llvm.riscv.th.vlse.nxv16f16.nxv16f16( , *, iXLen, @@ -2220,12 +2220,12 @@ declare @llvm.riscv.xvlse.nxv16f16.nxv16f16( define @intrinsic_xvlse_v_nxv16f16_nxv16f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv16f16.nxv16f16( + %a = call @llvm.riscv.th.vlse.nxv16f16.nxv16f16( undef, * %0, iXLen %1, @@ -2234,7 +2234,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv16f16.nxv16f16( +declare @llvm.riscv.th.vlse.mask.nxv16f16.nxv16f16( , *, iXLen, @@ -2244,12 +2244,12 @@ declare @llvm.riscv.xvlse.mask.nxv16f16.nxv16f16( define @intrinsic_xvlse_mask_v_nxv16f16_nxv16f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv16f16.nxv16f16( + %a = call @llvm.riscv.th.vlse.mask.nxv16f16.nxv16f16( %0, * %1, iXLen %2, @@ -2259,7 +2259,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv32f16.nxv32f16( +declare @llvm.riscv.th.vlse.nxv32f16.nxv32f16( , *, iXLen, @@ -2268,12 +2268,12 @@ declare @llvm.riscv.xvlse.nxv32f16.nxv32f16( define @intrinsic_xvlse_v_nxv32f16_nxv32f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv32f16.nxv32f16( + %a = call @llvm.riscv.th.vlse.nxv32f16.nxv32f16( undef, * %0, iXLen %1, @@ -2282,7 +2282,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv32f16.nxv32f16( +declare @llvm.riscv.th.vlse.mask.nxv32f16.nxv32f16( , *, iXLen, @@ -2292,12 +2292,12 @@ declare @llvm.riscv.xvlse.mask.nxv32f16.nxv32f16( define @intrinsic_xvlse_mask_v_nxv32f16_nxv32f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv32f16.nxv32f16( + %a = call @llvm.riscv.th.vlse.mask.nxv32f16.nxv32f16( %0, * %1, iXLen %2, @@ -2307,7 +2307,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlse.nxv2i32.nxv2i32( , *, iXLen, @@ -2316,12 +2316,12 @@ declare @llvm.riscv.xvlse.nxv2i32.nxv2i32( define @intrinsic_xvlse_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlse.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -2330,7 +2330,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlse.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -2340,12 +2340,12 @@ declare @llvm.riscv.xvlse.mask.nxv2i32.nxv2i32( define @intrinsic_xvlse_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlse.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -2355,7 +2355,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlse.nxv4i32.nxv4i32( , *, iXLen, @@ -2364,12 +2364,12 @@ declare @llvm.riscv.xvlse.nxv4i32.nxv4i32( define @intrinsic_xvlse_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlse.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -2378,7 +2378,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlse.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -2388,12 +2388,12 @@ declare @llvm.riscv.xvlse.mask.nxv4i32.nxv4i32( define @intrinsic_xvlse_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlse.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -2403,7 +2403,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlse.nxv8i32.nxv8i32( , *, iXLen, @@ -2412,12 +2412,12 @@ declare @llvm.riscv.xvlse.nxv8i32.nxv8i32( define @intrinsic_xvlse_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlse.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -2426,7 +2426,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlse.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -2436,12 +2436,12 @@ declare @llvm.riscv.xvlse.mask.nxv8i32.nxv8i32( define @intrinsic_xvlse_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlse.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -2451,7 +2451,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlse.nxv16i32.nxv16i32( , *, iXLen, @@ -2460,12 +2460,12 @@ declare @llvm.riscv.xvlse.nxv16i32.nxv16i32( define @intrinsic_xvlse_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlse.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -2474,7 +2474,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlse.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -2484,12 +2484,12 @@ declare @llvm.riscv.xvlse.mask.nxv16i32.nxv16i32( define @intrinsic_xvlse_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlse.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -2499,7 +2499,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv2f32.nxv2f32( +declare @llvm.riscv.th.vlse.nxv2f32.nxv2f32( , *, iXLen, @@ -2508,12 +2508,12 @@ declare @llvm.riscv.xvlse.nxv2f32.nxv2f32( define @intrinsic_xvlse_v_nxv2f32_nxv2f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv2f32.nxv2f32( + %a = call @llvm.riscv.th.vlse.nxv2f32.nxv2f32( undef, * %0, iXLen %1, @@ -2522,7 +2522,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv2f32.nxv2f32( +declare @llvm.riscv.th.vlse.mask.nxv2f32.nxv2f32( , *, iXLen, @@ -2532,12 +2532,12 @@ declare @llvm.riscv.xvlse.mask.nxv2f32.nxv2f32( define @intrinsic_xvlse_mask_v_nxv2f32_nxv2f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv2f32.nxv2f32( + %a = call @llvm.riscv.th.vlse.mask.nxv2f32.nxv2f32( %0, * %1, iXLen %2, @@ -2547,7 +2547,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv4f32.nxv4f32( +declare @llvm.riscv.th.vlse.nxv4f32.nxv4f32( , *, iXLen, @@ -2556,12 +2556,12 @@ declare @llvm.riscv.xvlse.nxv4f32.nxv4f32( define @intrinsic_xvlse_v_nxv4f32_nxv4f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv4f32.nxv4f32( + %a = call @llvm.riscv.th.vlse.nxv4f32.nxv4f32( undef, * %0, iXLen %1, @@ -2570,7 +2570,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv4f32.nxv4f32( +declare @llvm.riscv.th.vlse.mask.nxv4f32.nxv4f32( , *, iXLen, @@ -2580,12 +2580,12 @@ declare @llvm.riscv.xvlse.mask.nxv4f32.nxv4f32( define @intrinsic_xvlse_mask_v_nxv4f32_nxv4f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv4f32.nxv4f32( + %a = call @llvm.riscv.th.vlse.mask.nxv4f32.nxv4f32( %0, * %1, iXLen %2, @@ -2595,7 +2595,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8f32.nxv8f32( +declare @llvm.riscv.th.vlse.nxv8f32.nxv8f32( , *, iXLen, @@ -2604,12 +2604,12 @@ declare @llvm.riscv.xvlse.nxv8f32.nxv8f32( define @intrinsic_xvlse_v_nxv8f32_nxv8f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8f32.nxv8f32( + %a = call @llvm.riscv.th.vlse.nxv8f32.nxv8f32( undef, * %0, iXLen %1, @@ -2618,7 +2618,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8f32.nxv8f32( +declare @llvm.riscv.th.vlse.mask.nxv8f32.nxv8f32( , *, iXLen, @@ -2628,12 +2628,12 @@ declare @llvm.riscv.xvlse.mask.nxv8f32.nxv8f32( define @intrinsic_xvlse_mask_v_nxv8f32_nxv8f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8f32.nxv8f32( + %a = call @llvm.riscv.th.vlse.mask.nxv8f32.nxv8f32( %0, * %1, iXLen %2, @@ -2643,7 +2643,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv16f32.nxv16f32( +declare @llvm.riscv.th.vlse.nxv16f32.nxv16f32( , *, iXLen, @@ -2652,12 +2652,12 @@ declare @llvm.riscv.xvlse.nxv16f32.nxv16f32( define @intrinsic_xvlse_v_nxv16f32_nxv16f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv16f32.nxv16f32( + %a = call @llvm.riscv.th.vlse.nxv16f32.nxv16f32( undef, * %0, iXLen %1, @@ -2666,7 +2666,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv16f32.nxv16f32( +declare @llvm.riscv.th.vlse.mask.nxv16f32.nxv16f32( , *, iXLen, @@ -2676,12 +2676,12 @@ declare @llvm.riscv.xvlse.mask.nxv16f32.nxv16f32( define @intrinsic_xvlse_mask_v_nxv16f32_nxv16f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv16f32.nxv16f32( + %a = call @llvm.riscv.th.vlse.mask.nxv16f32.nxv16f32( %0, * %1, iXLen %2, @@ -2691,7 +2691,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlse.nxv1i64.nxv1i64( , *, iXLen, @@ -2700,12 +2700,12 @@ declare @llvm.riscv.xvlse.nxv1i64.nxv1i64( define @intrinsic_xvlse_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlse.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -2714,7 +2714,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlse.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -2724,12 +2724,12 @@ declare @llvm.riscv.xvlse.mask.nxv1i64.nxv1i64( define @intrinsic_xvlse_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlse.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -2739,7 +2739,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlse.nxv2i64.nxv2i64( , *, iXLen, @@ -2748,12 +2748,12 @@ declare @llvm.riscv.xvlse.nxv2i64.nxv2i64( define @intrinsic_xvlse_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlse.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -2762,7 +2762,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlse.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -2772,12 +2772,12 @@ declare @llvm.riscv.xvlse.mask.nxv2i64.nxv2i64( define @intrinsic_xvlse_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlse.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -2787,7 +2787,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlse.nxv4i64.nxv4i64( , *, iXLen, @@ -2796,12 +2796,12 @@ declare @llvm.riscv.xvlse.nxv4i64.nxv4i64( define @intrinsic_xvlse_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlse.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -2810,7 +2810,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlse.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -2820,12 +2820,12 @@ declare @llvm.riscv.xvlse.mask.nxv4i64.nxv4i64( define @intrinsic_xvlse_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlse.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -2835,7 +2835,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlse.nxv8i64.nxv8i64( , *, iXLen, @@ -2844,12 +2844,12 @@ declare @llvm.riscv.xvlse.nxv8i64.nxv8i64( define @intrinsic_xvlse_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlse.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -2858,7 +2858,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlse.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -2868,12 +2868,12 @@ declare @llvm.riscv.xvlse.mask.nxv8i64.nxv8i64( define @intrinsic_xvlse_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlse.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -2883,7 +2883,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv1f64.nxv1f64( +declare @llvm.riscv.th.vlse.nxv1f64.nxv1f64( , *, iXLen, @@ -2892,12 +2892,12 @@ declare @llvm.riscv.xvlse.nxv1f64.nxv1f64( define @intrinsic_xvlse_v_nxv1f64_nxv1f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv1f64.nxv1f64( + %a = call @llvm.riscv.th.vlse.nxv1f64.nxv1f64( undef, * %0, iXLen %1, @@ -2906,7 +2906,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv1f64.nxv1f64( +declare @llvm.riscv.th.vlse.mask.nxv1f64.nxv1f64( , *, iXLen, @@ -2916,12 +2916,12 @@ declare @llvm.riscv.xvlse.mask.nxv1f64.nxv1f64( define @intrinsic_xvlse_mask_v_nxv1f64_nxv1f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv1f64.nxv1f64( + %a = call @llvm.riscv.th.vlse.mask.nxv1f64.nxv1f64( %0, * %1, iXLen %2, @@ -2931,7 +2931,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv2f64.nxv2f64( +declare @llvm.riscv.th.vlse.nxv2f64.nxv2f64( , *, iXLen, @@ -2940,12 +2940,12 @@ declare @llvm.riscv.xvlse.nxv2f64.nxv2f64( define @intrinsic_xvlse_v_nxv2f64_nxv2f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv2f64.nxv2f64( + %a = call @llvm.riscv.th.vlse.nxv2f64.nxv2f64( undef, * %0, iXLen %1, @@ -2954,7 +2954,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv2f64.nxv2f64( +declare @llvm.riscv.th.vlse.mask.nxv2f64.nxv2f64( , *, iXLen, @@ -2964,12 +2964,12 @@ declare @llvm.riscv.xvlse.mask.nxv2f64.nxv2f64( define @intrinsic_xvlse_mask_v_nxv2f64_nxv2f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv2f64.nxv2f64( + %a = call @llvm.riscv.th.vlse.mask.nxv2f64.nxv2f64( %0, * %1, iXLen %2, @@ -2979,7 +2979,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv4f64.nxv4f64( +declare @llvm.riscv.th.vlse.nxv4f64.nxv4f64( , *, iXLen, @@ -2988,12 +2988,12 @@ declare @llvm.riscv.xvlse.nxv4f64.nxv4f64( define @intrinsic_xvlse_v_nxv4f64_nxv4f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv4f64.nxv4f64( + %a = call @llvm.riscv.th.vlse.nxv4f64.nxv4f64( undef, * %0, iXLen %1, @@ -3002,7 +3002,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv4f64.nxv4f64( +declare @llvm.riscv.th.vlse.mask.nxv4f64.nxv4f64( , *, iXLen, @@ -3012,12 +3012,12 @@ declare @llvm.riscv.xvlse.mask.nxv4f64.nxv4f64( define @intrinsic_xvlse_mask_v_nxv4f64_nxv4f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv4f64.nxv4f64( + %a = call @llvm.riscv.th.vlse.mask.nxv4f64.nxv4f64( %0, * %1, iXLen %2, @@ -3027,7 +3027,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.nxv8f64.nxv8f64( +declare @llvm.riscv.th.vlse.nxv8f64.nxv8f64( , *, iXLen, @@ -3036,12 +3036,12 @@ declare @llvm.riscv.xvlse.nxv8f64.nxv8f64( define @intrinsic_xvlse_v_nxv8f64_nxv8f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlse_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.nxv8f64.nxv8f64( + %a = call @llvm.riscv.th.vlse.nxv8f64.nxv8f64( undef, * %0, iXLen %1, @@ -3050,7 +3050,7 @@ entry: ret %a } -declare @llvm.riscv.xvlse.mask.nxv8f64.nxv8f64( +declare @llvm.riscv.th.vlse.mask.nxv8f64.nxv8f64( , *, iXLen, @@ -3060,12 +3060,12 @@ declare @llvm.riscv.xvlse.mask.nxv8f64.nxv8f64( define @intrinsic_xvlse_mask_v_nxv8f64_nxv8f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlse_mask_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlse.mask.nxv8f64.nxv8f64( + %a = call @llvm.riscv.th.vlse.mask.nxv8f64.nxv8f64( %0, * %1, iXLen %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vlsu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vlsu.ll index 3d95e4e85dd93..41c164ca6694d 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vlsu.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vlsu.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlsbu.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlsbu.nxv8i8.nxv8i8( , *, iXLen, @@ -12,12 +12,12 @@ declare @llvm.riscv.xvlsbu.nxv8i8.nxv8i8( define @intrinsic_xvlsbu_v_nxv8i8_nxv8i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlsbu.nxv8i8.nxv8i8( undef, * %0, iXLen %1, @@ -26,7 +26,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlsbu.mask.nxv8i8.nxv8i8( , *, iXLen, @@ -36,12 +36,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv8i8.nxv8i8( define @intrinsic_xvlsbu_mask_v_nxv8i8_nxv8i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlsbu.mask.nxv8i8.nxv8i8( %0, * %1, iXLen %2, @@ -51,7 +51,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlsbu.nxv16i8.nxv16i8( , *, iXLen, @@ -60,12 +60,12 @@ declare @llvm.riscv.xvlsbu.nxv16i8.nxv16i8( define @intrinsic_xvlsbu_v_nxv16i8_nxv16i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlsbu.nxv16i8.nxv16i8( undef, * %0, iXLen %1, @@ -74,7 +74,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlsbu.mask.nxv16i8.nxv16i8( , *, iXLen, @@ -84,12 +84,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv16i8.nxv16i8( define @intrinsic_xvlsbu_mask_v_nxv16i8_nxv16i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlsbu.mask.nxv16i8.nxv16i8( %0, * %1, iXLen %2, @@ -99,7 +99,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlsbu.nxv32i8.nxv32i8( , *, iXLen, @@ -108,12 +108,12 @@ declare @llvm.riscv.xvlsbu.nxv32i8.nxv32i8( define @intrinsic_xvlsbu_v_nxv32i8_nxv32i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlsbu.nxv32i8.nxv32i8( undef, * %0, iXLen %1, @@ -122,7 +122,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlsbu.mask.nxv32i8.nxv32i8( , *, iXLen, @@ -132,12 +132,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv32i8.nxv32i8( define @intrinsic_xvlsbu_mask_v_nxv32i8_nxv32i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlsbu.mask.nxv32i8.nxv32i8( %0, * %1, iXLen %2, @@ -147,7 +147,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlsbu.nxv64i8.nxv64i8( , *, iXLen, @@ -156,12 +156,12 @@ declare @llvm.riscv.xvlsbu.nxv64i8.nxv64i8( define @intrinsic_xvlsbu_v_nxv64i8_nxv64i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlsbu.nxv64i8.nxv64i8( undef, * %0, iXLen %1, @@ -170,7 +170,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlsbu.mask.nxv64i8.nxv64i8( , *, iXLen, @@ -180,12 +180,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv64i8.nxv64i8( define @intrinsic_xvlsbu_mask_v_nxv64i8_nxv64i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlsbu.mask.nxv64i8.nxv64i8( %0, * %1, iXLen %2, @@ -195,7 +195,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlsbu.nxv4i16.nxv4i16( , *, iXLen, @@ -204,12 +204,12 @@ declare @llvm.riscv.xvlsbu.nxv4i16.nxv4i16( define @intrinsic_xvlsbu_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlsbu.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -218,7 +218,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlsbu.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -228,12 +228,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv4i16.nxv4i16( define @intrinsic_xvlsbu_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlsbu.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -243,7 +243,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlsbu.nxv8i16.nxv8i16( , *, iXLen, @@ -252,12 +252,12 @@ declare @llvm.riscv.xvlsbu.nxv8i16.nxv8i16( define @intrinsic_xvlsbu_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlsbu.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -266,7 +266,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlsbu.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -276,12 +276,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv8i16.nxv8i16( define @intrinsic_xvlsbu_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlsbu.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -291,7 +291,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlsbu.nxv16i16.nxv16i16( , *, iXLen, @@ -300,12 +300,12 @@ declare @llvm.riscv.xvlsbu.nxv16i16.nxv16i16( define @intrinsic_xvlsbu_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlsbu.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -314,7 +314,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlsbu.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -324,12 +324,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv16i16.nxv16i16( define @intrinsic_xvlsbu_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlsbu.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -339,7 +339,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlsbu.nxv32i16.nxv32i16( , *, iXLen, @@ -348,12 +348,12 @@ declare @llvm.riscv.xvlsbu.nxv32i16.nxv32i16( define @intrinsic_xvlsbu_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlsbu.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -362,7 +362,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlsbu.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -372,12 +372,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv32i16.nxv32i16( define @intrinsic_xvlsbu_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlsbu.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -387,7 +387,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsbu.nxv2i32.nxv2i32( , *, iXLen, @@ -396,12 +396,12 @@ declare @llvm.riscv.xvlsbu.nxv2i32.nxv2i32( define @intrinsic_xvlsbu_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsbu.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -410,7 +410,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlsbu.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -420,12 +420,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlsbu_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlsbu.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -435,7 +435,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsbu.nxv4i32.nxv4i32( , *, iXLen, @@ -444,12 +444,12 @@ declare @llvm.riscv.xvlsbu.nxv4i32.nxv4i32( define @intrinsic_xvlsbu_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsbu.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -458,7 +458,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlsbu.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -468,12 +468,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlsbu_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlsbu.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -483,7 +483,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsbu.nxv8i32.nxv8i32( , *, iXLen, @@ -492,12 +492,12 @@ declare @llvm.riscv.xvlsbu.nxv8i32.nxv8i32( define @intrinsic_xvlsbu_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsbu.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -506,7 +506,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlsbu.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -516,12 +516,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlsbu_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlsbu.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -531,7 +531,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsbu.nxv16i32.nxv16i32( , *, iXLen, @@ -540,12 +540,12 @@ declare @llvm.riscv.xvlsbu.nxv16i32.nxv16i32( define @intrinsic_xvlsbu_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsbu.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -554,7 +554,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlsbu.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -564,12 +564,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlsbu_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlsbu.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -579,7 +579,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsbu.nxv1i64.nxv1i64( , *, iXLen, @@ -588,12 +588,12 @@ declare @llvm.riscv.xvlsbu.nxv1i64.nxv1i64( define @intrinsic_xvlsbu_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsbu.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -602,7 +602,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlsbu.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -612,12 +612,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlsbu_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlsbu.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsbu.nxv2i64.nxv2i64( , *, iXLen, @@ -636,12 +636,12 @@ declare @llvm.riscv.xvlsbu.nxv2i64.nxv2i64( define @intrinsic_xvlsbu_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsbu.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -650,7 +650,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlsbu.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -660,12 +660,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlsbu_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlsbu.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -675,7 +675,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsbu.nxv4i64.nxv4i64( , *, iXLen, @@ -684,12 +684,12 @@ declare @llvm.riscv.xvlsbu.nxv4i64.nxv4i64( define @intrinsic_xvlsbu_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsbu.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -698,7 +698,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlsbu.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -708,12 +708,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlsbu_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlsbu.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -723,7 +723,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsbu.nxv8i64.nxv8i64( , *, iXLen, @@ -732,12 +732,12 @@ declare @llvm.riscv.xvlsbu.nxv8i64.nxv8i64( define @intrinsic_xvlsbu_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsbu.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -746,7 +746,7 @@ entry: ret %a } -declare @llvm.riscv.xvlsbu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlsbu.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -756,12 +756,12 @@ declare @llvm.riscv.xvlsbu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlsbu_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlsbu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlsbu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlsbu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlsbu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlsbu.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -771,7 +771,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlshu.nxv4i16.nxv4i16( , *, iXLen, @@ -780,12 +780,12 @@ declare @llvm.riscv.xvlshu.nxv4i16.nxv4i16( define @intrinsic_xvlshu_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlshu.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -794,7 +794,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlshu.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -804,12 +804,12 @@ declare @llvm.riscv.xvlshu.mask.nxv4i16.nxv4i16( define @intrinsic_xvlshu_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlshu.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -819,7 +819,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlshu.nxv8i16.nxv8i16( , *, iXLen, @@ -828,12 +828,12 @@ declare @llvm.riscv.xvlshu.nxv8i16.nxv8i16( define @intrinsic_xvlshu_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlshu.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -842,7 +842,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlshu.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -852,12 +852,12 @@ declare @llvm.riscv.xvlshu.mask.nxv8i16.nxv8i16( define @intrinsic_xvlshu_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlshu.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -867,7 +867,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlshu.nxv16i16.nxv16i16( , *, iXLen, @@ -876,12 +876,12 @@ declare @llvm.riscv.xvlshu.nxv16i16.nxv16i16( define @intrinsic_xvlshu_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlshu.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -890,7 +890,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlshu.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -900,12 +900,12 @@ declare @llvm.riscv.xvlshu.mask.nxv16i16.nxv16i16( define @intrinsic_xvlshu_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlshu.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -915,7 +915,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlshu.nxv32i16.nxv32i16( , *, iXLen, @@ -924,12 +924,12 @@ declare @llvm.riscv.xvlshu.nxv32i16.nxv32i16( define @intrinsic_xvlshu_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlshu.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -938,7 +938,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlshu.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -948,12 +948,12 @@ declare @llvm.riscv.xvlshu.mask.nxv32i16.nxv32i16( define @intrinsic_xvlshu_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlshu.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -963,7 +963,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlshu.nxv2i32.nxv2i32( , *, iXLen, @@ -972,12 +972,12 @@ declare @llvm.riscv.xvlshu.nxv2i32.nxv2i32( define @intrinsic_xvlshu_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlshu.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -986,7 +986,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlshu.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -996,12 +996,12 @@ declare @llvm.riscv.xvlshu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlshu_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlshu.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -1011,7 +1011,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlshu.nxv4i32.nxv4i32( , *, iXLen, @@ -1020,12 +1020,12 @@ declare @llvm.riscv.xvlshu.nxv4i32.nxv4i32( define @intrinsic_xvlshu_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlshu.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -1034,7 +1034,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlshu.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -1044,12 +1044,12 @@ declare @llvm.riscv.xvlshu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlshu_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlshu.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -1059,7 +1059,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlshu.nxv8i32.nxv8i32( , *, iXLen, @@ -1068,12 +1068,12 @@ declare @llvm.riscv.xvlshu.nxv8i32.nxv8i32( define @intrinsic_xvlshu_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlshu.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -1082,7 +1082,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlshu.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -1092,12 +1092,12 @@ declare @llvm.riscv.xvlshu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlshu_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlshu.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -1107,7 +1107,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlshu.nxv16i32.nxv16i32( , *, iXLen, @@ -1116,12 +1116,12 @@ declare @llvm.riscv.xvlshu.nxv16i32.nxv16i32( define @intrinsic_xvlshu_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlshu.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -1130,7 +1130,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlshu.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -1140,12 +1140,12 @@ declare @llvm.riscv.xvlshu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlshu_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlshu.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -1155,7 +1155,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlshu.nxv1i64.nxv1i64( , *, iXLen, @@ -1164,12 +1164,12 @@ declare @llvm.riscv.xvlshu.nxv1i64.nxv1i64( define @intrinsic_xvlshu_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlshu.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -1178,7 +1178,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlshu.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -1188,12 +1188,12 @@ declare @llvm.riscv.xvlshu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlshu_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlshu.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -1203,7 +1203,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlshu.nxv2i64.nxv2i64( , *, iXLen, @@ -1212,12 +1212,12 @@ declare @llvm.riscv.xvlshu.nxv2i64.nxv2i64( define @intrinsic_xvlshu_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlshu.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -1226,7 +1226,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlshu.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -1236,12 +1236,12 @@ declare @llvm.riscv.xvlshu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlshu_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlshu.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -1251,7 +1251,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlshu.nxv4i64.nxv4i64( , *, iXLen, @@ -1260,12 +1260,12 @@ declare @llvm.riscv.xvlshu.nxv4i64.nxv4i64( define @intrinsic_xvlshu_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlshu.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -1274,7 +1274,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlshu.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -1284,12 +1284,12 @@ declare @llvm.riscv.xvlshu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlshu_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlshu.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -1299,7 +1299,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlshu.nxv8i64.nxv8i64( , *, iXLen, @@ -1308,12 +1308,12 @@ declare @llvm.riscv.xvlshu.nxv8i64.nxv8i64( define @intrinsic_xvlshu_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlshu.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -1322,7 +1322,7 @@ entry: ret %a } -declare @llvm.riscv.xvlshu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlshu.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -1332,12 +1332,12 @@ declare @llvm.riscv.xvlshu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlshu_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlshu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlshu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlshu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlshu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlshu.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -1347,7 +1347,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlswu.nxv2i32.nxv2i32( , *, iXLen, @@ -1356,12 +1356,12 @@ declare @llvm.riscv.xvlswu.nxv2i32.nxv2i32( define @intrinsic_xvlswu_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlswu.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -1370,7 +1370,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlswu.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -1380,12 +1380,12 @@ declare @llvm.riscv.xvlswu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlswu_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlswu.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -1395,7 +1395,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlswu.nxv4i32.nxv4i32( , *, iXLen, @@ -1404,12 +1404,12 @@ declare @llvm.riscv.xvlswu.nxv4i32.nxv4i32( define @intrinsic_xvlswu_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlswu.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -1418,7 +1418,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlswu.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -1428,12 +1428,12 @@ declare @llvm.riscv.xvlswu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlswu_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlswu.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -1443,7 +1443,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlswu.nxv8i32.nxv8i32( , *, iXLen, @@ -1452,12 +1452,12 @@ declare @llvm.riscv.xvlswu.nxv8i32.nxv8i32( define @intrinsic_xvlswu_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlswu.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -1466,7 +1466,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlswu.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -1476,12 +1476,12 @@ declare @llvm.riscv.xvlswu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlswu_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlswu.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -1491,7 +1491,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlswu.nxv16i32.nxv16i32( , *, iXLen, @@ -1500,12 +1500,12 @@ declare @llvm.riscv.xvlswu.nxv16i32.nxv16i32( define @intrinsic_xvlswu_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlswu.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -1514,7 +1514,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlswu.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -1524,12 +1524,12 @@ declare @llvm.riscv.xvlswu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlswu_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlswu.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -1539,7 +1539,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlswu.nxv1i64.nxv1i64( , *, iXLen, @@ -1548,12 +1548,12 @@ declare @llvm.riscv.xvlswu.nxv1i64.nxv1i64( define @intrinsic_xvlswu_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlswu.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -1562,7 +1562,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlswu.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -1572,12 +1572,12 @@ declare @llvm.riscv.xvlswu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlswu_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlswu.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -1587,7 +1587,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlswu.nxv2i64.nxv2i64( , *, iXLen, @@ -1596,12 +1596,12 @@ declare @llvm.riscv.xvlswu.nxv2i64.nxv2i64( define @intrinsic_xvlswu_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlswu.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -1610,7 +1610,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlswu.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -1620,12 +1620,12 @@ declare @llvm.riscv.xvlswu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlswu_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlswu.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -1635,7 +1635,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlswu.nxv4i64.nxv4i64( , *, iXLen, @@ -1644,12 +1644,12 @@ declare @llvm.riscv.xvlswu.nxv4i64.nxv4i64( define @intrinsic_xvlswu_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlswu.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -1658,7 +1658,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlswu.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -1668,12 +1668,12 @@ declare @llvm.riscv.xvlswu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlswu_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlswu.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -1683,7 +1683,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlswu.nxv8i64.nxv8i64( , *, iXLen, @@ -1692,12 +1692,12 @@ declare @llvm.riscv.xvlswu.nxv8i64.nxv8i64( define @intrinsic_xvlswu_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlswu.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -1706,7 +1706,7 @@ entry: ret %a } -declare @llvm.riscv.xvlswu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlswu.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -1716,12 +1716,12 @@ declare @llvm.riscv.xvlswu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlswu_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlswu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vlswu.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vlswu.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlswu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlswu.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vlu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vlu.ll index c13fd4a16c90b..52450fdd040d2 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vlu.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vlu.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlbu.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlbu.nxv8i8.nxv8i8( , *, iXLen); @@ -11,12 +11,12 @@ declare @llvm.riscv.xvlbu.nxv8i8.nxv8i8( define @intrinsic_xvlbu_v_nxv8i8_nxv8i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlbu.nxv8i8.nxv8i8( undef, * %0, iXLen %1) @@ -24,7 +24,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlbu.mask.nxv8i8.nxv8i8( , *, , @@ -33,12 +33,12 @@ declare @llvm.riscv.xvlbu.mask.nxv8i8.nxv8i8( define @intrinsic_xvlbu_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlbu.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -47,7 +47,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlbu.nxv16i8.nxv16i8( , *, iXLen); @@ -55,12 +55,12 @@ declare @llvm.riscv.xvlbu.nxv16i8.nxv16i8( define @intrinsic_xvlbu_v_nxv16i8_nxv16i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlbu.nxv16i8.nxv16i8( undef, * %0, iXLen %1) @@ -68,7 +68,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlbu.mask.nxv16i8.nxv16i8( , *, , @@ -77,12 +77,12 @@ declare @llvm.riscv.xvlbu.mask.nxv16i8.nxv16i8( define @intrinsic_xvlbu_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlbu.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -91,7 +91,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlbu.nxv32i8.nxv32i8( , *, iXLen); @@ -99,12 +99,12 @@ declare @llvm.riscv.xvlbu.nxv32i8.nxv32i8( define @intrinsic_xvlbu_v_nxv32i8_nxv32i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlbu.nxv32i8.nxv32i8( undef, * %0, iXLen %1) @@ -112,7 +112,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlbu.mask.nxv32i8.nxv32i8( , *, , @@ -121,12 +121,12 @@ declare @llvm.riscv.xvlbu.mask.nxv32i8.nxv32i8( define @intrinsic_xvlbu_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlbu.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -135,7 +135,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlbu.nxv64i8.nxv64i8( , *, iXLen); @@ -143,12 +143,12 @@ declare @llvm.riscv.xvlbu.nxv64i8.nxv64i8( define @intrinsic_xvlbu_v_nxv64i8_nxv64i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlbu.nxv64i8.nxv64i8( undef, * %0, iXLen %1) @@ -156,7 +156,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlbu.mask.nxv64i8.nxv64i8( , *, , @@ -165,12 +165,12 @@ declare @llvm.riscv.xvlbu.mask.nxv64i8.nxv64i8( define @intrinsic_xvlbu_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlbu.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -179,7 +179,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlbu.nxv4i16.nxv4i16( , *, iXLen); @@ -187,12 +187,12 @@ declare @llvm.riscv.xvlbu.nxv4i16.nxv4i16( define @intrinsic_xvlbu_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlbu.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -200,7 +200,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlbu.mask.nxv4i16.nxv4i16( , *, , @@ -209,12 +209,12 @@ declare @llvm.riscv.xvlbu.mask.nxv4i16.nxv4i16( define @intrinsic_xvlbu_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlbu.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -223,7 +223,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlbu.nxv8i16.nxv8i16( , *, iXLen); @@ -231,12 +231,12 @@ declare @llvm.riscv.xvlbu.nxv8i16.nxv8i16( define @intrinsic_xvlbu_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlbu.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -244,7 +244,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlbu.mask.nxv8i16.nxv8i16( , *, , @@ -253,12 +253,12 @@ declare @llvm.riscv.xvlbu.mask.nxv8i16.nxv8i16( define @intrinsic_xvlbu_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlbu.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -267,7 +267,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlbu.nxv16i16.nxv16i16( , *, iXLen); @@ -275,12 +275,12 @@ declare @llvm.riscv.xvlbu.nxv16i16.nxv16i16( define @intrinsic_xvlbu_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlbu.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -288,7 +288,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlbu.mask.nxv16i16.nxv16i16( , *, , @@ -297,12 +297,12 @@ declare @llvm.riscv.xvlbu.mask.nxv16i16.nxv16i16( define @intrinsic_xvlbu_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlbu.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -311,7 +311,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlbu.nxv32i16.nxv32i16( , *, iXLen); @@ -319,12 +319,12 @@ declare @llvm.riscv.xvlbu.nxv32i16.nxv32i16( define @intrinsic_xvlbu_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlbu.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -332,7 +332,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlbu.mask.nxv32i16.nxv32i16( , *, , @@ -341,12 +341,12 @@ declare @llvm.riscv.xvlbu.mask.nxv32i16.nxv32i16( define @intrinsic_xvlbu_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlbu.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -355,7 +355,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlbu.nxv2i32.nxv2i32( , *, iXLen); @@ -363,12 +363,12 @@ declare @llvm.riscv.xvlbu.nxv2i32.nxv2i32( define @intrinsic_xvlbu_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlbu.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -376,7 +376,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlbu.mask.nxv2i32.nxv2i32( , *, , @@ -385,12 +385,12 @@ declare @llvm.riscv.xvlbu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlbu_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlbu.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -399,7 +399,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlbu.nxv4i32.nxv4i32( , *, iXLen); @@ -407,12 +407,12 @@ declare @llvm.riscv.xvlbu.nxv4i32.nxv4i32( define @intrinsic_xvlbu_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlbu.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -420,7 +420,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlbu.mask.nxv4i32.nxv4i32( , *, , @@ -429,12 +429,12 @@ declare @llvm.riscv.xvlbu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlbu_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlbu.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -443,7 +443,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlbu.nxv8i32.nxv8i32( , *, iXLen); @@ -451,12 +451,12 @@ declare @llvm.riscv.xvlbu.nxv8i32.nxv8i32( define @intrinsic_xvlbu_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlbu.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -464,7 +464,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlbu.mask.nxv8i32.nxv8i32( , *, , @@ -473,12 +473,12 @@ declare @llvm.riscv.xvlbu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlbu_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlbu.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -487,7 +487,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlbu.nxv16i32.nxv16i32( , *, iXLen); @@ -495,12 +495,12 @@ declare @llvm.riscv.xvlbu.nxv16i32.nxv16i32( define @intrinsic_xvlbu_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlbu.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -508,7 +508,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlbu.mask.nxv16i32.nxv16i32( , *, , @@ -517,12 +517,12 @@ declare @llvm.riscv.xvlbu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlbu_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlbu.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -531,7 +531,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlbu.nxv1i64.nxv1i64( , *, iXLen); @@ -539,12 +539,12 @@ declare @llvm.riscv.xvlbu.nxv1i64.nxv1i64( define @intrinsic_xvlbu_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlbu.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -552,7 +552,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlbu.mask.nxv1i64.nxv1i64( , *, , @@ -561,12 +561,12 @@ declare @llvm.riscv.xvlbu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlbu_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlbu.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -575,7 +575,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlbu.nxv2i64.nxv2i64( , *, iXLen); @@ -583,12 +583,12 @@ declare @llvm.riscv.xvlbu.nxv2i64.nxv2i64( define @intrinsic_xvlbu_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlbu.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -596,7 +596,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlbu.mask.nxv2i64.nxv2i64( , *, , @@ -605,12 +605,12 @@ declare @llvm.riscv.xvlbu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlbu_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlbu.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -619,7 +619,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlbu.nxv4i64.nxv4i64( , *, iXLen); @@ -627,12 +627,12 @@ declare @llvm.riscv.xvlbu.nxv4i64.nxv4i64( define @intrinsic_xvlbu_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlbu.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -640,7 +640,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlbu.mask.nxv4i64.nxv4i64( , *, , @@ -649,12 +649,12 @@ declare @llvm.riscv.xvlbu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlbu_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlbu.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -663,7 +663,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlbu.nxv8i64.nxv8i64( , *, iXLen); @@ -671,12 +671,12 @@ declare @llvm.riscv.xvlbu.nxv8i64.nxv8i64( define @intrinsic_xvlbu_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlbu.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -684,7 +684,7 @@ entry: ret %a } -declare @llvm.riscv.xvlbu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlbu.mask.nxv8i64.nxv8i64( , *, , @@ -693,12 +693,12 @@ declare @llvm.riscv.xvlbu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlbu_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlbu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlbu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlbu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlbu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlbu.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -707,7 +707,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlhu.nxv4i16.nxv4i16( , *, iXLen); @@ -715,12 +715,12 @@ declare @llvm.riscv.xvlhu.nxv4i16.nxv4i16( define @intrinsic_xvlhu_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlhu.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -728,7 +728,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlhu.mask.nxv4i16.nxv4i16( , *, , @@ -737,12 +737,12 @@ declare @llvm.riscv.xvlhu.mask.nxv4i16.nxv4i16( define @intrinsic_xvlhu_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlhu.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -751,7 +751,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlhu.nxv8i16.nxv8i16( , *, iXLen); @@ -759,12 +759,12 @@ declare @llvm.riscv.xvlhu.nxv8i16.nxv8i16( define @intrinsic_xvlhu_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlhu.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -772,7 +772,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlhu.mask.nxv8i16.nxv8i16( , *, , @@ -781,12 +781,12 @@ declare @llvm.riscv.xvlhu.mask.nxv8i16.nxv8i16( define @intrinsic_xvlhu_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlhu.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -795,7 +795,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlhu.nxv16i16.nxv16i16( , *, iXLen); @@ -803,12 +803,12 @@ declare @llvm.riscv.xvlhu.nxv16i16.nxv16i16( define @intrinsic_xvlhu_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlhu.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -816,7 +816,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlhu.mask.nxv16i16.nxv16i16( , *, , @@ -825,12 +825,12 @@ declare @llvm.riscv.xvlhu.mask.nxv16i16.nxv16i16( define @intrinsic_xvlhu_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlhu.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -839,7 +839,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlhu.nxv32i16.nxv32i16( , *, iXLen); @@ -847,12 +847,12 @@ declare @llvm.riscv.xvlhu.nxv32i16.nxv32i16( define @intrinsic_xvlhu_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlhu.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -860,7 +860,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlhu.mask.nxv32i16.nxv32i16( , *, , @@ -869,12 +869,12 @@ declare @llvm.riscv.xvlhu.mask.nxv32i16.nxv32i16( define @intrinsic_xvlhu_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlhu.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -883,7 +883,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlhu.nxv2i32.nxv2i32( , *, iXLen); @@ -891,12 +891,12 @@ declare @llvm.riscv.xvlhu.nxv2i32.nxv2i32( define @intrinsic_xvlhu_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlhu.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -904,7 +904,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlhu.mask.nxv2i32.nxv2i32( , *, , @@ -913,12 +913,12 @@ declare @llvm.riscv.xvlhu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlhu_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlhu.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -927,7 +927,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlhu.nxv4i32.nxv4i32( , *, iXLen); @@ -935,12 +935,12 @@ declare @llvm.riscv.xvlhu.nxv4i32.nxv4i32( define @intrinsic_xvlhu_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlhu.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -948,7 +948,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlhu.mask.nxv4i32.nxv4i32( , *, , @@ -957,12 +957,12 @@ declare @llvm.riscv.xvlhu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlhu_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlhu.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -971,7 +971,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlhu.nxv8i32.nxv8i32( , *, iXLen); @@ -979,12 +979,12 @@ declare @llvm.riscv.xvlhu.nxv8i32.nxv8i32( define @intrinsic_xvlhu_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlhu.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -992,7 +992,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlhu.mask.nxv8i32.nxv8i32( , *, , @@ -1001,12 +1001,12 @@ declare @llvm.riscv.xvlhu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlhu_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlhu.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1015,7 +1015,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlhu.nxv16i32.nxv16i32( , *, iXLen); @@ -1023,12 +1023,12 @@ declare @llvm.riscv.xvlhu.nxv16i32.nxv16i32( define @intrinsic_xvlhu_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlhu.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -1036,7 +1036,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlhu.mask.nxv16i32.nxv16i32( , *, , @@ -1045,12 +1045,12 @@ declare @llvm.riscv.xvlhu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlhu_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlhu.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1059,7 +1059,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlhu.nxv1i64.nxv1i64( , *, iXLen); @@ -1067,12 +1067,12 @@ declare @llvm.riscv.xvlhu.nxv1i64.nxv1i64( define @intrinsic_xvlhu_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlhu.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -1080,7 +1080,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlhu.mask.nxv1i64.nxv1i64( , *, , @@ -1089,12 +1089,12 @@ declare @llvm.riscv.xvlhu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlhu_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlhu.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -1103,7 +1103,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlhu.nxv2i64.nxv2i64( , *, iXLen); @@ -1111,12 +1111,12 @@ declare @llvm.riscv.xvlhu.nxv2i64.nxv2i64( define @intrinsic_xvlhu_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlhu.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -1124,7 +1124,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlhu.mask.nxv2i64.nxv2i64( , *, , @@ -1133,12 +1133,12 @@ declare @llvm.riscv.xvlhu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlhu_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlhu.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -1147,7 +1147,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlhu.nxv4i64.nxv4i64( , *, iXLen); @@ -1155,12 +1155,12 @@ declare @llvm.riscv.xvlhu.nxv4i64.nxv4i64( define @intrinsic_xvlhu_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlhu.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -1168,7 +1168,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlhu.mask.nxv4i64.nxv4i64( , *, , @@ -1177,12 +1177,12 @@ declare @llvm.riscv.xvlhu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlhu_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlhu.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -1191,7 +1191,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlhu.nxv8i64.nxv8i64( , *, iXLen); @@ -1199,12 +1199,12 @@ declare @llvm.riscv.xvlhu.nxv8i64.nxv8i64( define @intrinsic_xvlhu_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlhu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlhu.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -1212,7 +1212,7 @@ entry: ret %a } -declare @llvm.riscv.xvlhu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlhu.mask.nxv8i64.nxv8i64( , *, , @@ -1221,12 +1221,12 @@ declare @llvm.riscv.xvlhu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlhu_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlhu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlhu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlhu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlhu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlhu.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -1235,7 +1235,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlwu.nxv2i32.nxv2i32( , *, iXLen); @@ -1243,12 +1243,12 @@ declare @llvm.riscv.xvlwu.nxv2i32.nxv2i32( define @intrinsic_xvlwu_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlwu.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -1256,7 +1256,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlwu.mask.nxv2i32.nxv2i32( , *, , @@ -1265,12 +1265,12 @@ declare @llvm.riscv.xvlwu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlwu_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlwu.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1279,7 +1279,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlwu.nxv4i32.nxv4i32( , *, iXLen); @@ -1287,12 +1287,12 @@ declare @llvm.riscv.xvlwu.nxv4i32.nxv4i32( define @intrinsic_xvlwu_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlwu.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -1300,7 +1300,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlwu.mask.nxv4i32.nxv4i32( , *, , @@ -1309,12 +1309,12 @@ declare @llvm.riscv.xvlwu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlwu_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlwu.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1323,7 +1323,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlwu.nxv8i32.nxv8i32( , *, iXLen); @@ -1331,12 +1331,12 @@ declare @llvm.riscv.xvlwu.nxv8i32.nxv8i32( define @intrinsic_xvlwu_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlwu.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -1344,7 +1344,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlwu.mask.nxv8i32.nxv8i32( , *, , @@ -1353,12 +1353,12 @@ declare @llvm.riscv.xvlwu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlwu_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlwu.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1367,7 +1367,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlwu.nxv16i32.nxv16i32( , *, iXLen); @@ -1375,12 +1375,12 @@ declare @llvm.riscv.xvlwu.nxv16i32.nxv16i32( define @intrinsic_xvlwu_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlwu.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -1388,7 +1388,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlwu.mask.nxv16i32.nxv16i32( , *, , @@ -1397,12 +1397,12 @@ declare @llvm.riscv.xvlwu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlwu_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlwu.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1411,7 +1411,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlwu.nxv1i64.nxv1i64( , *, iXLen); @@ -1419,12 +1419,12 @@ declare @llvm.riscv.xvlwu.nxv1i64.nxv1i64( define @intrinsic_xvlwu_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlwu.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -1432,7 +1432,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlwu.mask.nxv1i64.nxv1i64( , *, , @@ -1441,12 +1441,12 @@ declare @llvm.riscv.xvlwu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlwu_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlwu.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -1455,7 +1455,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlwu.nxv2i64.nxv2i64( , *, iXLen); @@ -1463,12 +1463,12 @@ declare @llvm.riscv.xvlwu.nxv2i64.nxv2i64( define @intrinsic_xvlwu_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlwu.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -1476,7 +1476,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlwu.mask.nxv2i64.nxv2i64( , *, , @@ -1485,12 +1485,12 @@ declare @llvm.riscv.xvlwu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlwu_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlwu.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -1499,7 +1499,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlwu.nxv4i64.nxv4i64( , *, iXLen); @@ -1507,12 +1507,12 @@ declare @llvm.riscv.xvlwu.nxv4i64.nxv4i64( define @intrinsic_xvlwu_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlwu.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -1520,7 +1520,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlwu.mask.nxv4i64.nxv4i64( , *, , @@ -1529,12 +1529,12 @@ declare @llvm.riscv.xvlwu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlwu_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlwu.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -1543,7 +1543,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlwu.nxv8i64.nxv8i64( , *, iXLen); @@ -1551,12 +1551,12 @@ declare @llvm.riscv.xvlwu.nxv8i64.nxv8i64( define @intrinsic_xvlwu_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlwu.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0) ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlwu.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -1564,7 +1564,7 @@ entry: ret %a } -declare @llvm.riscv.xvlwu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlwu.mask.nxv8i64.nxv8i64( , *, , @@ -1573,12 +1573,12 @@ declare @llvm.riscv.xvlwu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlwu_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvlwu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlwu.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlwu.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlwu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlwu.mask.nxv8i64.nxv8i64( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vlx-64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vlx-64.ll index 6bee8dda1e302..00782601b2a3f 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vlx-64.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vlx-64.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=riscv64 -mattr=+xtheadv -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector -verify-machineinstrs < %s | \ ; RUN: FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlxb.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxb.nxv1i64.nxv1i64( , *, , @@ -10,12 +10,12 @@ declare @llvm.riscv.xvlxb.nxv1i64.nxv1i64( define @intrinsic_xvlxb_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxb.nxv1i64.nxv1i64( undef, * %0, %1, @@ -24,7 +24,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxb.mask.nxv1i64.nxv1i64( , *, , @@ -34,12 +34,12 @@ declare @llvm.riscv.xvlxb.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxb_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxb.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -49,7 +49,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxb.nxv2i64.nxv2i64( , *, , @@ -58,12 +58,12 @@ declare @llvm.riscv.xvlxb.nxv2i64.nxv2i64( define @intrinsic_xvlxb_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxb.nxv2i64.nxv2i64( undef, * %0, %1, @@ -72,7 +72,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxb.mask.nxv2i64.nxv2i64( , *, , @@ -82,12 +82,12 @@ declare @llvm.riscv.xvlxb.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxb_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxb.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -97,7 +97,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxb.nxv4i64.nxv4i64( , *, , @@ -106,12 +106,12 @@ declare @llvm.riscv.xvlxb.nxv4i64.nxv4i64( define @intrinsic_xvlxb_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxb.nxv4i64.nxv4i64( undef, * %0, %1, @@ -120,7 +120,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxb.mask.nxv4i64.nxv4i64( , *, , @@ -130,12 +130,12 @@ declare @llvm.riscv.xvlxb.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxb_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxb.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -145,7 +145,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxb.nxv8i64.nxv8i64( , *, , @@ -154,12 +154,12 @@ declare @llvm.riscv.xvlxb.nxv8i64.nxv8i64( define @intrinsic_xvlxb_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxb.nxv8i64.nxv8i64( undef, * %0, %1, @@ -168,7 +168,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxb.mask.nxv8i64.nxv8i64( , *, , @@ -178,12 +178,12 @@ declare @llvm.riscv.xvlxb.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxb_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxb.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -193,7 +193,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxh.nxv1i64.nxv1i64( , *, , @@ -202,12 +202,12 @@ declare @llvm.riscv.xvlxh.nxv1i64.nxv1i64( define @intrinsic_xvlxh_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxh.nxv1i64.nxv1i64( undef, * %0, %1, @@ -216,7 +216,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxh.mask.nxv1i64.nxv1i64( , *, , @@ -226,12 +226,12 @@ declare @llvm.riscv.xvlxh.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxh_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxh.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -241,7 +241,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxh.nxv2i64.nxv2i64( , *, , @@ -250,12 +250,12 @@ declare @llvm.riscv.xvlxh.nxv2i64.nxv2i64( define @intrinsic_xvlxh_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxh.nxv2i64.nxv2i64( undef, * %0, %1, @@ -264,7 +264,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxh.mask.nxv2i64.nxv2i64( , *, , @@ -274,12 +274,12 @@ declare @llvm.riscv.xvlxh.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxh_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxh.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -289,7 +289,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxh.nxv4i64.nxv4i64( , *, , @@ -298,12 +298,12 @@ declare @llvm.riscv.xvlxh.nxv4i64.nxv4i64( define @intrinsic_xvlxh_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxh.nxv4i64.nxv4i64( undef, * %0, %1, @@ -312,7 +312,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxh.mask.nxv4i64.nxv4i64( , *, , @@ -322,12 +322,12 @@ declare @llvm.riscv.xvlxh.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxh_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxh.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -337,7 +337,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxh.nxv8i64.nxv8i64( , *, , @@ -346,12 +346,12 @@ declare @llvm.riscv.xvlxh.nxv8i64.nxv8i64( define @intrinsic_xvlxh_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxh.nxv8i64.nxv8i64( undef, * %0, %1, @@ -360,7 +360,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxh.mask.nxv8i64.nxv8i64( , *, , @@ -370,12 +370,12 @@ declare @llvm.riscv.xvlxh.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxh_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxh.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -385,7 +385,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxw.nxv1i64.nxv1i64( , *, , @@ -394,12 +394,12 @@ declare @llvm.riscv.xvlxw.nxv1i64.nxv1i64( define @intrinsic_xvlxw_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxw.nxv1i64.nxv1i64( undef, * %0, %1, @@ -408,7 +408,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxw.mask.nxv1i64.nxv1i64( , *, , @@ -418,12 +418,12 @@ declare @llvm.riscv.xvlxw.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxw_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxw.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -433,7 +433,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxw.nxv2i64.nxv2i64( , *, , @@ -442,12 +442,12 @@ declare @llvm.riscv.xvlxw.nxv2i64.nxv2i64( define @intrinsic_xvlxw_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxw.nxv2i64.nxv2i64( undef, * %0, %1, @@ -456,7 +456,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxw.mask.nxv2i64.nxv2i64( , *, , @@ -466,12 +466,12 @@ declare @llvm.riscv.xvlxw.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxw_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxw.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -481,7 +481,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxw.nxv4i64.nxv4i64( , *, , @@ -490,12 +490,12 @@ declare @llvm.riscv.xvlxw.nxv4i64.nxv4i64( define @intrinsic_xvlxw_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxw.nxv4i64.nxv4i64( undef, * %0, %1, @@ -504,7 +504,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxw.mask.nxv4i64.nxv4i64( , *, , @@ -514,12 +514,12 @@ declare @llvm.riscv.xvlxw.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxw_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxw.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -529,7 +529,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxw.nxv8i64.nxv8i64( , *, , @@ -538,12 +538,12 @@ declare @llvm.riscv.xvlxw.nxv8i64.nxv8i64( define @intrinsic_xvlxw_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxw.nxv8i64.nxv8i64( undef, * %0, %1, @@ -552,7 +552,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxw.mask.nxv8i64.nxv8i64( , *, , @@ -562,12 +562,12 @@ declare @llvm.riscv.xvlxw.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxw_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxw.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -577,7 +577,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxe.nxv1i64.nxv1i64( , *, , @@ -586,12 +586,12 @@ declare @llvm.riscv.xvlxe.nxv1i64.nxv1i64( define @intrinsic_xvlxe_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxe.nxv1i64.nxv1i64( undef, * %0, %1, @@ -600,7 +600,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxe.mask.nxv1i64.nxv1i64( , *, , @@ -610,12 +610,12 @@ declare @llvm.riscv.xvlxe.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxe_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxe.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -625,7 +625,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxe.nxv2i64.nxv2i64( , *, , @@ -634,12 +634,12 @@ declare @llvm.riscv.xvlxe.nxv2i64.nxv2i64( define @intrinsic_xvlxe_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxe.nxv2i64.nxv2i64( undef, * %0, %1, @@ -648,7 +648,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxe.mask.nxv2i64.nxv2i64( , *, , @@ -658,12 +658,12 @@ declare @llvm.riscv.xvlxe.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxe_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxe.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -673,7 +673,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxe.nxv4i64.nxv4i64( , *, , @@ -682,12 +682,12 @@ declare @llvm.riscv.xvlxe.nxv4i64.nxv4i64( define @intrinsic_xvlxe_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxe.nxv4i64.nxv4i64( undef, * %0, %1, @@ -696,7 +696,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxe.mask.nxv4i64.nxv4i64( , *, , @@ -706,12 +706,12 @@ declare @llvm.riscv.xvlxe.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxe_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxe.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -721,7 +721,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxe.nxv8i64.nxv8i64( , *, , @@ -730,12 +730,12 @@ declare @llvm.riscv.xvlxe.nxv8i64.nxv8i64( define @intrinsic_xvlxe_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxe.nxv8i64.nxv8i64( undef, * %0, %1, @@ -744,7 +744,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxe.mask.nxv8i64.nxv8i64( , *, , @@ -754,12 +754,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxe_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxe.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -769,7 +769,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv1f64.nxv1f64( +declare @llvm.riscv.th.vlxe.nxv1f64.nxv1f64( , *, , @@ -778,12 +778,12 @@ declare @llvm.riscv.xvlxe.nxv1f64.nxv1f64( define @intrinsic_xvlxe_v_nxv1f64_nxv1f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv1f64.nxv1f64( + %a = call @llvm.riscv.th.vlxe.nxv1f64.nxv1f64( undef, * %0, %1, @@ -792,7 +792,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv1f64.nxv1f64( +declare @llvm.riscv.th.vlxe.mask.nxv1f64.nxv1f64( , *, , @@ -802,12 +802,12 @@ declare @llvm.riscv.xvlxe.mask.nxv1f64.nxv1f64( define @intrinsic_xvlxe_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv1f64.nxv1f64( + %a = call @llvm.riscv.th.vlxe.mask.nxv1f64.nxv1f64( %0, * %1, %2, @@ -817,7 +817,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv2f64.nxv2f64( +declare @llvm.riscv.th.vlxe.nxv2f64.nxv2f64( , *, , @@ -826,12 +826,12 @@ declare @llvm.riscv.xvlxe.nxv2f64.nxv2f64( define @intrinsic_xvlxe_v_nxv2f64_nxv2f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv2f64.nxv2f64( + %a = call @llvm.riscv.th.vlxe.nxv2f64.nxv2f64( undef, * %0, %1, @@ -840,7 +840,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv2f64.nxv2f64( +declare @llvm.riscv.th.vlxe.mask.nxv2f64.nxv2f64( , *, , @@ -850,12 +850,12 @@ declare @llvm.riscv.xvlxe.mask.nxv2f64.nxv2f64( define @intrinsic_xvlxe_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv2f64.nxv2f64( + %a = call @llvm.riscv.th.vlxe.mask.nxv2f64.nxv2f64( %0, * %1, %2, @@ -865,7 +865,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv4f64.nxv4f64( +declare @llvm.riscv.th.vlxe.nxv4f64.nxv4f64( , *, , @@ -874,12 +874,12 @@ declare @llvm.riscv.xvlxe.nxv4f64.nxv4f64( define @intrinsic_xvlxe_v_nxv4f64_nxv4f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv4f64.nxv4f64( + %a = call @llvm.riscv.th.vlxe.nxv4f64.nxv4f64( undef, * %0, %1, @@ -888,7 +888,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv4f64.nxv4f64( +declare @llvm.riscv.th.vlxe.mask.nxv4f64.nxv4f64( , *, , @@ -898,12 +898,12 @@ declare @llvm.riscv.xvlxe.mask.nxv4f64.nxv4f64( define @intrinsic_xvlxe_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv4f64.nxv4f64( + %a = call @llvm.riscv.th.vlxe.mask.nxv4f64.nxv4f64( %0, * %1, %2, @@ -913,7 +913,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8f64.nxv8f64( +declare @llvm.riscv.th.vlxe.nxv8f64.nxv8f64( , *, , @@ -922,12 +922,12 @@ declare @llvm.riscv.xvlxe.nxv8f64.nxv8f64( define @intrinsic_xvlxe_v_nxv8f64_nxv8f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8f64.nxv8f64( + %a = call @llvm.riscv.th.vlxe.nxv8f64.nxv8f64( undef, * %0, %1, @@ -936,7 +936,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8f64.nxv8f64( +declare @llvm.riscv.th.vlxe.mask.nxv8f64.nxv8f64( , *, , @@ -946,12 +946,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8f64.nxv8f64( define @intrinsic_xvlxe_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8f64.nxv8f64( + %a = call @llvm.riscv.th.vlxe.mask.nxv8f64.nxv8f64( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vlx.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vlx.ll index 0fb88e6d844c7..abe528e244c38 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vlx.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vlx.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlxb.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlxb.nxv8i8.nxv8i8( , *, , @@ -12,12 +12,12 @@ declare @llvm.riscv.xvlxb.nxv8i8.nxv8i8( define @intrinsic_xvlxb_v_nxv8i8_nxv8i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlxb.nxv8i8.nxv8i8( undef, * %0, %1, @@ -26,7 +26,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlxb.mask.nxv8i8.nxv8i8( , *, , @@ -36,12 +36,12 @@ declare @llvm.riscv.xvlxb.mask.nxv8i8.nxv8i8( define @intrinsic_xvlxb_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlxb.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -51,7 +51,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlxb.nxv16i8.nxv16i8( , *, , @@ -60,12 +60,12 @@ declare @llvm.riscv.xvlxb.nxv16i8.nxv16i8( define @intrinsic_xvlxb_v_nxv16i8_nxv16i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlxb.nxv16i8.nxv16i8( undef, * %0, %1, @@ -74,7 +74,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlxb.mask.nxv16i8.nxv16i8( , *, , @@ -84,12 +84,12 @@ declare @llvm.riscv.xvlxb.mask.nxv16i8.nxv16i8( define @intrinsic_xvlxb_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlxb.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -99,7 +99,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlxb.nxv32i8.nxv32i8( , *, , @@ -108,12 +108,12 @@ declare @llvm.riscv.xvlxb.nxv32i8.nxv32i8( define @intrinsic_xvlxb_v_nxv32i8_nxv32i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlxb.nxv32i8.nxv32i8( undef, * %0, %1, @@ -122,7 +122,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlxb.mask.nxv32i8.nxv32i8( , *, , @@ -132,12 +132,12 @@ declare @llvm.riscv.xvlxb.mask.nxv32i8.nxv32i8( define @intrinsic_xvlxb_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlxb.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -147,7 +147,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlxb.nxv64i8.nxv64i8( , *, , @@ -156,12 +156,12 @@ declare @llvm.riscv.xvlxb.nxv64i8.nxv64i8( define @intrinsic_xvlxb_v_nxv64i8_nxv64i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlxb.nxv64i8.nxv64i8( undef, * %0, %1, @@ -170,7 +170,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlxb.mask.nxv64i8.nxv64i8( , *, , @@ -180,12 +180,12 @@ declare @llvm.riscv.xvlxb.mask.nxv64i8.nxv64i8( define @intrinsic_xvlxb_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlxb.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -195,7 +195,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxb.nxv4i16.nxv4i16( , *, , @@ -204,12 +204,12 @@ declare @llvm.riscv.xvlxb.nxv4i16.nxv4i16( define @intrinsic_xvlxb_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxb.nxv4i16.nxv4i16( undef, * %0, %1, @@ -218,7 +218,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxb.mask.nxv4i16.nxv4i16( , *, , @@ -228,12 +228,12 @@ declare @llvm.riscv.xvlxb.mask.nxv4i16.nxv4i16( define @intrinsic_xvlxb_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxb.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -243,7 +243,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxb.nxv8i16.nxv8i16( , *, , @@ -252,12 +252,12 @@ declare @llvm.riscv.xvlxb.nxv8i16.nxv8i16( define @intrinsic_xvlxb_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxb.nxv8i16.nxv8i16( undef, * %0, %1, @@ -266,7 +266,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxb.mask.nxv8i16.nxv8i16( , *, , @@ -276,12 +276,12 @@ declare @llvm.riscv.xvlxb.mask.nxv8i16.nxv8i16( define @intrinsic_xvlxb_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxb.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -291,7 +291,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxb.nxv16i16.nxv16i16( , *, , @@ -300,12 +300,12 @@ declare @llvm.riscv.xvlxb.nxv16i16.nxv16i16( define @intrinsic_xvlxb_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxb.nxv16i16.nxv16i16( undef, * %0, %1, @@ -314,7 +314,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxb.mask.nxv16i16.nxv16i16( , *, , @@ -324,12 +324,12 @@ declare @llvm.riscv.xvlxb.mask.nxv16i16.nxv16i16( define @intrinsic_xvlxb_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxb.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -339,7 +339,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxb.nxv32i16.nxv32i16( , *, , @@ -348,12 +348,12 @@ declare @llvm.riscv.xvlxb.nxv32i16.nxv32i16( define @intrinsic_xvlxb_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxb.nxv32i16.nxv32i16( undef, * %0, %1, @@ -362,7 +362,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxb.mask.nxv32i16.nxv32i16( , *, , @@ -372,12 +372,12 @@ declare @llvm.riscv.xvlxb.mask.nxv32i16.nxv32i16( define @intrinsic_xvlxb_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxb.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -387,7 +387,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxb.nxv2i32.nxv2i32( , *, , @@ -396,12 +396,12 @@ declare @llvm.riscv.xvlxb.nxv2i32.nxv2i32( define @intrinsic_xvlxb_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxb.nxv2i32.nxv2i32( undef, * %0, %1, @@ -410,7 +410,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxb.mask.nxv2i32.nxv2i32( , *, , @@ -420,12 +420,12 @@ declare @llvm.riscv.xvlxb.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxb_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxb.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -435,7 +435,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxb.nxv4i32.nxv4i32( , *, , @@ -444,12 +444,12 @@ declare @llvm.riscv.xvlxb.nxv4i32.nxv4i32( define @intrinsic_xvlxb_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxb.nxv4i32.nxv4i32( undef, * %0, %1, @@ -458,7 +458,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxb.mask.nxv4i32.nxv4i32( , *, , @@ -468,12 +468,12 @@ declare @llvm.riscv.xvlxb.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxb_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxb.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -483,7 +483,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxb.nxv8i32.nxv8i32( , *, , @@ -492,12 +492,12 @@ declare @llvm.riscv.xvlxb.nxv8i32.nxv8i32( define @intrinsic_xvlxb_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxb.nxv8i32.nxv8i32( undef, * %0, %1, @@ -506,7 +506,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxb.mask.nxv8i32.nxv8i32( , *, , @@ -516,12 +516,12 @@ declare @llvm.riscv.xvlxb.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxb_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxb.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -531,7 +531,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxb.nxv16i32.nxv16i32( , *, , @@ -540,12 +540,12 @@ declare @llvm.riscv.xvlxb.nxv16i32.nxv16i32( define @intrinsic_xvlxb_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxb.nxv16i32.nxv16i32( undef, * %0, %1, @@ -554,7 +554,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxb.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxb.mask.nxv16i32.nxv16i32( , *, , @@ -564,12 +564,12 @@ declare @llvm.riscv.xvlxb.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxb_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxb_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxb.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxb.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxb.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxb.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -579,7 +579,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxh.nxv4i16.nxv4i16( , *, , @@ -588,12 +588,12 @@ declare @llvm.riscv.xvlxh.nxv4i16.nxv4i16( define @intrinsic_xvlxh_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxh.nxv4i16.nxv4i16( undef, * %0, %1, @@ -602,7 +602,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxh.mask.nxv4i16.nxv4i16( , *, , @@ -612,12 +612,12 @@ declare @llvm.riscv.xvlxh.mask.nxv4i16.nxv4i16( define @intrinsic_xvlxh_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxh.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxh.nxv8i16.nxv8i16( , *, , @@ -636,12 +636,12 @@ declare @llvm.riscv.xvlxh.nxv8i16.nxv8i16( define @intrinsic_xvlxh_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxh.nxv8i16.nxv8i16( undef, * %0, %1, @@ -650,7 +650,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxh.mask.nxv8i16.nxv8i16( , *, , @@ -660,12 +660,12 @@ declare @llvm.riscv.xvlxh.mask.nxv8i16.nxv8i16( define @intrinsic_xvlxh_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxh.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -675,7 +675,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxh.nxv16i16.nxv16i16( , *, , @@ -684,12 +684,12 @@ declare @llvm.riscv.xvlxh.nxv16i16.nxv16i16( define @intrinsic_xvlxh_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxh.nxv16i16.nxv16i16( undef, * %0, %1, @@ -698,7 +698,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxh.mask.nxv16i16.nxv16i16( , *, , @@ -708,12 +708,12 @@ declare @llvm.riscv.xvlxh.mask.nxv16i16.nxv16i16( define @intrinsic_xvlxh_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxh.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -723,7 +723,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxh.nxv32i16.nxv32i16( , *, , @@ -732,12 +732,12 @@ declare @llvm.riscv.xvlxh.nxv32i16.nxv32i16( define @intrinsic_xvlxh_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxh.nxv32i16.nxv32i16( undef, * %0, %1, @@ -746,7 +746,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxh.mask.nxv32i16.nxv32i16( , *, , @@ -756,12 +756,12 @@ declare @llvm.riscv.xvlxh.mask.nxv32i16.nxv32i16( define @intrinsic_xvlxh_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxh.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -771,7 +771,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxh.nxv2i32.nxv2i32( , *, , @@ -780,12 +780,12 @@ declare @llvm.riscv.xvlxh.nxv2i32.nxv2i32( define @intrinsic_xvlxh_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxh.nxv2i32.nxv2i32( undef, * %0, %1, @@ -794,7 +794,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxh.mask.nxv2i32.nxv2i32( , *, , @@ -804,12 +804,12 @@ declare @llvm.riscv.xvlxh.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxh_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxh.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -819,7 +819,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxh.nxv4i32.nxv4i32( , *, , @@ -828,12 +828,12 @@ declare @llvm.riscv.xvlxh.nxv4i32.nxv4i32( define @intrinsic_xvlxh_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxh.nxv4i32.nxv4i32( undef, * %0, %1, @@ -842,7 +842,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxh.mask.nxv4i32.nxv4i32( , *, , @@ -852,12 +852,12 @@ declare @llvm.riscv.xvlxh.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxh_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxh.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -867,7 +867,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxh.nxv8i32.nxv8i32( , *, , @@ -876,12 +876,12 @@ declare @llvm.riscv.xvlxh.nxv8i32.nxv8i32( define @intrinsic_xvlxh_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxh.nxv8i32.nxv8i32( undef, * %0, %1, @@ -890,7 +890,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxh.mask.nxv8i32.nxv8i32( , *, , @@ -900,12 +900,12 @@ declare @llvm.riscv.xvlxh.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxh_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxh.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -915,7 +915,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxh.nxv16i32.nxv16i32( , *, , @@ -924,12 +924,12 @@ declare @llvm.riscv.xvlxh.nxv16i32.nxv16i32( define @intrinsic_xvlxh_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxh.nxv16i32.nxv16i32( undef, * %0, %1, @@ -938,7 +938,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxh.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxh.mask.nxv16i32.nxv16i32( , *, , @@ -948,12 +948,12 @@ declare @llvm.riscv.xvlxh.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxh_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxh_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxh.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxh.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxh.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxh.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -963,7 +963,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxw.nxv2i32.nxv2i32( , *, , @@ -972,12 +972,12 @@ declare @llvm.riscv.xvlxw.nxv2i32.nxv2i32( define @intrinsic_xvlxw_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxw.nxv2i32.nxv2i32( undef, * %0, %1, @@ -986,7 +986,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxw.mask.nxv2i32.nxv2i32( , *, , @@ -996,12 +996,12 @@ declare @llvm.riscv.xvlxw.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxw_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxw.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1011,7 +1011,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxw.nxv4i32.nxv4i32( , *, , @@ -1020,12 +1020,12 @@ declare @llvm.riscv.xvlxw.nxv4i32.nxv4i32( define @intrinsic_xvlxw_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxw.nxv4i32.nxv4i32( undef, * %0, %1, @@ -1034,7 +1034,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxw.mask.nxv4i32.nxv4i32( , *, , @@ -1044,12 +1044,12 @@ declare @llvm.riscv.xvlxw.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxw_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxw.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1059,7 +1059,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxw.nxv8i32.nxv8i32( , *, , @@ -1068,12 +1068,12 @@ declare @llvm.riscv.xvlxw.nxv8i32.nxv8i32( define @intrinsic_xvlxw_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxw.nxv8i32.nxv8i32( undef, * %0, %1, @@ -1082,7 +1082,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxw.mask.nxv8i32.nxv8i32( , *, , @@ -1092,12 +1092,12 @@ declare @llvm.riscv.xvlxw.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxw_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxw.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1107,7 +1107,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxw.nxv16i32.nxv16i32( , *, , @@ -1116,12 +1116,12 @@ declare @llvm.riscv.xvlxw.nxv16i32.nxv16i32( define @intrinsic_xvlxw_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxw.nxv16i32.nxv16i32( undef, * %0, %1, @@ -1130,7 +1130,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxw.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxw.mask.nxv16i32.nxv16i32( , *, , @@ -1140,12 +1140,12 @@ declare @llvm.riscv.xvlxw.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxw_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxw_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxw.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxw.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxw.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxw.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1155,7 +1155,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlxe.nxv8i8.nxv8i8( , *, , @@ -1164,12 +1164,12 @@ declare @llvm.riscv.xvlxe.nxv8i8.nxv8i8( define @intrinsic_xvlxe_v_nxv8i8_nxv8i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlxe.nxv8i8.nxv8i8( undef, * %0, %1, @@ -1178,7 +1178,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlxe.mask.nxv8i8.nxv8i8( , *, , @@ -1188,12 +1188,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8i8.nxv8i8( define @intrinsic_xvlxe_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlxe.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -1203,7 +1203,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlxe.nxv16i8.nxv16i8( , *, , @@ -1212,12 +1212,12 @@ declare @llvm.riscv.xvlxe.nxv16i8.nxv16i8( define @intrinsic_xvlxe_v_nxv16i8_nxv16i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlxe.nxv16i8.nxv16i8( undef, * %0, %1, @@ -1226,7 +1226,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlxe.mask.nxv16i8.nxv16i8( , *, , @@ -1236,12 +1236,12 @@ declare @llvm.riscv.xvlxe.mask.nxv16i8.nxv16i8( define @intrinsic_xvlxe_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlxe.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -1251,7 +1251,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlxe.nxv32i8.nxv32i8( , *, , @@ -1260,12 +1260,12 @@ declare @llvm.riscv.xvlxe.nxv32i8.nxv32i8( define @intrinsic_xvlxe_v_nxv32i8_nxv32i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlxe.nxv32i8.nxv32i8( undef, * %0, %1, @@ -1274,7 +1274,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlxe.mask.nxv32i8.nxv32i8( , *, , @@ -1284,12 +1284,12 @@ declare @llvm.riscv.xvlxe.mask.nxv32i8.nxv32i8( define @intrinsic_xvlxe_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlxe.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -1299,7 +1299,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlxe.nxv64i8.nxv64i8( , *, , @@ -1308,12 +1308,12 @@ declare @llvm.riscv.xvlxe.nxv64i8.nxv64i8( define @intrinsic_xvlxe_v_nxv64i8_nxv64i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlxe.nxv64i8.nxv64i8( undef, * %0, %1, @@ -1322,7 +1322,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlxe.mask.nxv64i8.nxv64i8( , *, , @@ -1332,12 +1332,12 @@ declare @llvm.riscv.xvlxe.mask.nxv64i8.nxv64i8( define @intrinsic_xvlxe_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlxe.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -1347,7 +1347,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxe.nxv4i16.nxv4i16( , *, , @@ -1356,12 +1356,12 @@ declare @llvm.riscv.xvlxe.nxv4i16.nxv4i16( define @intrinsic_xvlxe_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxe.nxv4i16.nxv4i16( undef, * %0, %1, @@ -1370,7 +1370,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxe.mask.nxv4i16.nxv4i16( , *, , @@ -1380,12 +1380,12 @@ declare @llvm.riscv.xvlxe.mask.nxv4i16.nxv4i16( define @intrinsic_xvlxe_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxe.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -1395,7 +1395,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxe.nxv8i16.nxv8i16( , *, , @@ -1404,12 +1404,12 @@ declare @llvm.riscv.xvlxe.nxv8i16.nxv8i16( define @intrinsic_xvlxe_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxe.nxv8i16.nxv8i16( undef, * %0, %1, @@ -1418,7 +1418,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxe.mask.nxv8i16.nxv8i16( , *, , @@ -1428,12 +1428,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8i16.nxv8i16( define @intrinsic_xvlxe_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxe.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -1443,7 +1443,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxe.nxv16i16.nxv16i16( , *, , @@ -1452,12 +1452,12 @@ declare @llvm.riscv.xvlxe.nxv16i16.nxv16i16( define @intrinsic_xvlxe_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxe.nxv16i16.nxv16i16( undef, * %0, %1, @@ -1466,7 +1466,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxe.mask.nxv16i16.nxv16i16( , *, , @@ -1476,12 +1476,12 @@ declare @llvm.riscv.xvlxe.mask.nxv16i16.nxv16i16( define @intrinsic_xvlxe_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxe.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -1491,7 +1491,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxe.nxv32i16.nxv32i16( , *, , @@ -1500,12 +1500,12 @@ declare @llvm.riscv.xvlxe.nxv32i16.nxv32i16( define @intrinsic_xvlxe_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxe.nxv32i16.nxv32i16( undef, * %0, %1, @@ -1514,7 +1514,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxe.mask.nxv32i16.nxv32i16( , *, , @@ -1524,12 +1524,12 @@ declare @llvm.riscv.xvlxe.mask.nxv32i16.nxv32i16( define @intrinsic_xvlxe_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxe.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -1539,7 +1539,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv4f16.nxv4f16( +declare @llvm.riscv.th.vlxe.nxv4f16.nxv4f16( , *, , @@ -1548,12 +1548,12 @@ declare @llvm.riscv.xvlxe.nxv4f16.nxv4f16( define @intrinsic_xvlxe_v_nxv4f16_nxv4f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv4f16.nxv4f16( + %a = call @llvm.riscv.th.vlxe.nxv4f16.nxv4f16( undef, * %0, %1, @@ -1562,7 +1562,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv4f16.nxv4f16( +declare @llvm.riscv.th.vlxe.mask.nxv4f16.nxv4f16( , *, , @@ -1572,12 +1572,12 @@ declare @llvm.riscv.xvlxe.mask.nxv4f16.nxv4f16( define @intrinsic_xvlxe_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv4f16.nxv4f16( + %a = call @llvm.riscv.th.vlxe.mask.nxv4f16.nxv4f16( %0, * %1, %2, @@ -1587,7 +1587,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8f16.nxv8f16( +declare @llvm.riscv.th.vlxe.nxv8f16.nxv8f16( , *, , @@ -1596,12 +1596,12 @@ declare @llvm.riscv.xvlxe.nxv8f16.nxv8f16( define @intrinsic_xvlxe_v_nxv8f16_nxv8f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8f16.nxv8f16( + %a = call @llvm.riscv.th.vlxe.nxv8f16.nxv8f16( undef, * %0, %1, @@ -1610,7 +1610,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8f16.nxv8f16( +declare @llvm.riscv.th.vlxe.mask.nxv8f16.nxv8f16( , *, , @@ -1620,12 +1620,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8f16.nxv8f16( define @intrinsic_xvlxe_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8f16.nxv8f16( + %a = call @llvm.riscv.th.vlxe.mask.nxv8f16.nxv8f16( %0, * %1, %2, @@ -1635,7 +1635,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv16f16.nxv16f16( +declare @llvm.riscv.th.vlxe.nxv16f16.nxv16f16( , *, , @@ -1644,12 +1644,12 @@ declare @llvm.riscv.xvlxe.nxv16f16.nxv16f16( define @intrinsic_xvlxe_v_nxv16f16_nxv16f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv16f16.nxv16f16( + %a = call @llvm.riscv.th.vlxe.nxv16f16.nxv16f16( undef, * %0, %1, @@ -1658,7 +1658,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv16f16.nxv16f16( +declare @llvm.riscv.th.vlxe.mask.nxv16f16.nxv16f16( , *, , @@ -1668,12 +1668,12 @@ declare @llvm.riscv.xvlxe.mask.nxv16f16.nxv16f16( define @intrinsic_xvlxe_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv16f16.nxv16f16( + %a = call @llvm.riscv.th.vlxe.mask.nxv16f16.nxv16f16( %0, * %1, %2, @@ -1683,7 +1683,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv32f16.nxv32f16( +declare @llvm.riscv.th.vlxe.nxv32f16.nxv32f16( , *, , @@ -1692,12 +1692,12 @@ declare @llvm.riscv.xvlxe.nxv32f16.nxv32f16( define @intrinsic_xvlxe_v_nxv32f16_nxv32f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv32f16.nxv32f16( + %a = call @llvm.riscv.th.vlxe.nxv32f16.nxv32f16( undef, * %0, %1, @@ -1706,7 +1706,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv32f16.nxv32f16( +declare @llvm.riscv.th.vlxe.mask.nxv32f16.nxv32f16( , *, , @@ -1716,12 +1716,12 @@ declare @llvm.riscv.xvlxe.mask.nxv32f16.nxv32f16( define @intrinsic_xvlxe_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv32f16.nxv32f16( + %a = call @llvm.riscv.th.vlxe.mask.nxv32f16.nxv32f16( %0, * %1, %2, @@ -1731,7 +1731,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxe.nxv2i32.nxv2i32( , *, , @@ -1740,12 +1740,12 @@ declare @llvm.riscv.xvlxe.nxv2i32.nxv2i32( define @intrinsic_xvlxe_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxe.nxv2i32.nxv2i32( undef, * %0, %1, @@ -1754,7 +1754,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxe.mask.nxv2i32.nxv2i32( , *, , @@ -1764,12 +1764,12 @@ declare @llvm.riscv.xvlxe.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxe_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxe.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1779,7 +1779,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxe.nxv4i32.nxv4i32( , *, , @@ -1788,12 +1788,12 @@ declare @llvm.riscv.xvlxe.nxv4i32.nxv4i32( define @intrinsic_xvlxe_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxe.nxv4i32.nxv4i32( undef, * %0, %1, @@ -1802,7 +1802,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxe.mask.nxv4i32.nxv4i32( , *, , @@ -1812,12 +1812,12 @@ declare @llvm.riscv.xvlxe.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxe_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxe.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1827,7 +1827,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxe.nxv8i32.nxv8i32( , *, , @@ -1836,12 +1836,12 @@ declare @llvm.riscv.xvlxe.nxv8i32.nxv8i32( define @intrinsic_xvlxe_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxe.nxv8i32.nxv8i32( undef, * %0, %1, @@ -1850,7 +1850,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxe.mask.nxv8i32.nxv8i32( , *, , @@ -1860,12 +1860,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxe_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxe.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1875,7 +1875,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxe.nxv16i32.nxv16i32( , *, , @@ -1884,12 +1884,12 @@ declare @llvm.riscv.xvlxe.nxv16i32.nxv16i32( define @intrinsic_xvlxe_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxe.nxv16i32.nxv16i32( undef, * %0, %1, @@ -1898,7 +1898,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxe.mask.nxv16i32.nxv16i32( , *, , @@ -1908,12 +1908,12 @@ declare @llvm.riscv.xvlxe.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxe_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxe.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1923,7 +1923,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv2f32.nxv2f32( +declare @llvm.riscv.th.vlxe.nxv2f32.nxv2f32( , *, , @@ -1932,12 +1932,12 @@ declare @llvm.riscv.xvlxe.nxv2f32.nxv2f32( define @intrinsic_xvlxe_v_nxv2f32_nxv2f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv2f32.nxv2f32( + %a = call @llvm.riscv.th.vlxe.nxv2f32.nxv2f32( undef, * %0, %1, @@ -1946,7 +1946,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv2f32.nxv2f32( +declare @llvm.riscv.th.vlxe.mask.nxv2f32.nxv2f32( , *, , @@ -1956,12 +1956,12 @@ declare @llvm.riscv.xvlxe.mask.nxv2f32.nxv2f32( define @intrinsic_xvlxe_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv2f32.nxv2f32( + %a = call @llvm.riscv.th.vlxe.mask.nxv2f32.nxv2f32( %0, * %1, %2, @@ -1971,7 +1971,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv4f32.nxv4f32( +declare @llvm.riscv.th.vlxe.nxv4f32.nxv4f32( , *, , @@ -1980,12 +1980,12 @@ declare @llvm.riscv.xvlxe.nxv4f32.nxv4f32( define @intrinsic_xvlxe_v_nxv4f32_nxv4f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv4f32.nxv4f32( + %a = call @llvm.riscv.th.vlxe.nxv4f32.nxv4f32( undef, * %0, %1, @@ -1994,7 +1994,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv4f32.nxv4f32( +declare @llvm.riscv.th.vlxe.mask.nxv4f32.nxv4f32( , *, , @@ -2004,12 +2004,12 @@ declare @llvm.riscv.xvlxe.mask.nxv4f32.nxv4f32( define @intrinsic_xvlxe_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv4f32.nxv4f32( + %a = call @llvm.riscv.th.vlxe.mask.nxv4f32.nxv4f32( %0, * %1, %2, @@ -2019,7 +2019,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv8f32.nxv8f32( +declare @llvm.riscv.th.vlxe.nxv8f32.nxv8f32( , *, , @@ -2028,12 +2028,12 @@ declare @llvm.riscv.xvlxe.nxv8f32.nxv8f32( define @intrinsic_xvlxe_v_nxv8f32_nxv8f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv8f32.nxv8f32( + %a = call @llvm.riscv.th.vlxe.nxv8f32.nxv8f32( undef, * %0, %1, @@ -2042,7 +2042,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv8f32.nxv8f32( +declare @llvm.riscv.th.vlxe.mask.nxv8f32.nxv8f32( , *, , @@ -2052,12 +2052,12 @@ declare @llvm.riscv.xvlxe.mask.nxv8f32.nxv8f32( define @intrinsic_xvlxe_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv8f32.nxv8f32( + %a = call @llvm.riscv.th.vlxe.mask.nxv8f32.nxv8f32( %0, * %1, %2, @@ -2067,7 +2067,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.nxv16f32.nxv16f32( +declare @llvm.riscv.th.vlxe.nxv16f32.nxv16f32( , *, , @@ -2076,12 +2076,12 @@ declare @llvm.riscv.xvlxe.nxv16f32.nxv16f32( define @intrinsic_xvlxe_v_nxv16f32_nxv16f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.nxv16f32.nxv16f32( + %a = call @llvm.riscv.th.vlxe.nxv16f32.nxv16f32( undef, * %0, %1, @@ -2090,7 +2090,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxe.mask.nxv16f32.nxv16f32( +declare @llvm.riscv.th.vlxe.mask.nxv16f32.nxv16f32( , *, , @@ -2100,12 +2100,12 @@ declare @llvm.riscv.xvlxe.mask.nxv16f32.nxv16f32( define @intrinsic_xvlxe_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxe_mask_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxe.mask.nxv16f32.nxv16f32( + %a = call @llvm.riscv.th.vlxe.mask.nxv16f32.nxv16f32( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vlxu-64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vlxu-64.ll index 3632703172f87..7ad709f767099 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vlxu-64.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vlxu-64.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=riscv64 -mattr=+xtheadv -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector -verify-machineinstrs < %s | \ ; RUN: FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlxbu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxbu.nxv1i64.nxv1i64( , *, , @@ -10,12 +10,12 @@ declare @llvm.riscv.xvlxbu.nxv1i64.nxv1i64( define @intrinsic_xvlxbu_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxbu.nxv1i64.nxv1i64( undef, * %0, %1, @@ -24,7 +24,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxbu.mask.nxv1i64.nxv1i64( , *, , @@ -34,12 +34,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxbu_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxbu.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -49,7 +49,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxbu.nxv2i64.nxv2i64( , *, , @@ -58,12 +58,12 @@ declare @llvm.riscv.xvlxbu.nxv2i64.nxv2i64( define @intrinsic_xvlxbu_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxbu.nxv2i64.nxv2i64( undef, * %0, %1, @@ -72,7 +72,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxbu.mask.nxv2i64.nxv2i64( , *, , @@ -82,12 +82,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxbu_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxbu.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -97,7 +97,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxbu.nxv4i64.nxv4i64( , *, , @@ -106,12 +106,12 @@ declare @llvm.riscv.xvlxbu.nxv4i64.nxv4i64( define @intrinsic_xvlxbu_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxbu.nxv4i64.nxv4i64( undef, * %0, %1, @@ -120,7 +120,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxbu.mask.nxv4i64.nxv4i64( , *, , @@ -130,12 +130,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxbu_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxbu.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -145,7 +145,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxbu.nxv8i64.nxv8i64( , *, , @@ -154,12 +154,12 @@ declare @llvm.riscv.xvlxbu.nxv8i64.nxv8i64( define @intrinsic_xvlxbu_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxbu.nxv8i64.nxv8i64( undef, * %0, %1, @@ -168,7 +168,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxbu.mask.nxv8i64.nxv8i64( , *, , @@ -178,12 +178,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxbu_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxbu.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -193,7 +193,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxhu.nxv1i64.nxv1i64( , *, , @@ -202,12 +202,12 @@ declare @llvm.riscv.xvlxhu.nxv1i64.nxv1i64( define @intrinsic_xvlxhu_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxhu.nxv1i64.nxv1i64( undef, * %0, %1, @@ -216,7 +216,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxhu.mask.nxv1i64.nxv1i64( , *, , @@ -226,12 +226,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxhu_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxhu.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -241,7 +241,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxhu.nxv2i64.nxv2i64( , *, , @@ -250,12 +250,12 @@ declare @llvm.riscv.xvlxhu.nxv2i64.nxv2i64( define @intrinsic_xvlxhu_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxhu.nxv2i64.nxv2i64( undef, * %0, %1, @@ -264,7 +264,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxhu.mask.nxv2i64.nxv2i64( , *, , @@ -274,12 +274,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxhu_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxhu.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -289,7 +289,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxhu.nxv4i64.nxv4i64( , *, , @@ -298,12 +298,12 @@ declare @llvm.riscv.xvlxhu.nxv4i64.nxv4i64( define @intrinsic_xvlxhu_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxhu.nxv4i64.nxv4i64( undef, * %0, %1, @@ -312,7 +312,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxhu.mask.nxv4i64.nxv4i64( , *, , @@ -322,12 +322,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxhu_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxhu.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -337,7 +337,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxhu.nxv8i64.nxv8i64( , *, , @@ -346,12 +346,12 @@ declare @llvm.riscv.xvlxhu.nxv8i64.nxv8i64( define @intrinsic_xvlxhu_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxhu.nxv8i64.nxv8i64( undef, * %0, %1, @@ -360,7 +360,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxhu.mask.nxv8i64.nxv8i64( , *, , @@ -370,12 +370,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxhu_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxhu.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -385,7 +385,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxwu.nxv1i64.nxv1i64( , *, , @@ -394,12 +394,12 @@ declare @llvm.riscv.xvlxwu.nxv1i64.nxv1i64( define @intrinsic_xvlxwu_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxwu.nxv1i64.nxv1i64( undef, * %0, %1, @@ -408,7 +408,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vlxwu.mask.nxv1i64.nxv1i64( , *, , @@ -418,12 +418,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv1i64.nxv1i64( define @intrinsic_xvlxwu_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv1i64.nxv1i64( + %a = call @llvm.riscv.th.vlxwu.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -433,7 +433,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxwu.nxv2i64.nxv2i64( , *, , @@ -442,12 +442,12 @@ declare @llvm.riscv.xvlxwu.nxv2i64.nxv2i64( define @intrinsic_xvlxwu_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxwu.nxv2i64.nxv2i64( undef, * %0, %1, @@ -456,7 +456,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vlxwu.mask.nxv2i64.nxv2i64( , *, , @@ -466,12 +466,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv2i64.nxv2i64( define @intrinsic_xvlxwu_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv2i64.nxv2i64( + %a = call @llvm.riscv.th.vlxwu.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -481,7 +481,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxwu.nxv4i64.nxv4i64( , *, , @@ -490,12 +490,12 @@ declare @llvm.riscv.xvlxwu.nxv4i64.nxv4i64( define @intrinsic_xvlxwu_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxwu.nxv4i64.nxv4i64( undef, * %0, %1, @@ -504,7 +504,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vlxwu.mask.nxv4i64.nxv4i64( , *, , @@ -514,12 +514,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv4i64.nxv4i64( define @intrinsic_xvlxwu_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv4i64.nxv4i64( + %a = call @llvm.riscv.th.vlxwu.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -529,7 +529,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxwu.nxv8i64.nxv8i64( , *, , @@ -538,12 +538,12 @@ declare @llvm.riscv.xvlxwu.nxv8i64.nxv8i64( define @intrinsic_xvlxwu_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxwu.nxv8i64.nxv8i64( undef, * %0, %1, @@ -552,7 +552,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vlxwu.mask.nxv8i64.nxv8i64( , *, , @@ -562,12 +562,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv8i64.nxv8i64( define @intrinsic_xvlxwu_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv8i64.nxv8i64( + %a = call @llvm.riscv.th.vlxwu.mask.nxv8i64.nxv8i64( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vlxu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vlxu.ll index 51a2dca5b883d..b1c6fc335ceaf 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vlxu.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vlxu.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvlxbu.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlxbu.nxv8i8.nxv8i8( , *, , @@ -12,12 +12,12 @@ declare @llvm.riscv.xvlxbu.nxv8i8.nxv8i8( define @intrinsic_xvlxbu_v_nxv8i8_nxv8i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlxbu.nxv8i8.nxv8i8( undef, * %0, %1, @@ -26,7 +26,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vlxbu.mask.nxv8i8.nxv8i8( , *, , @@ -36,12 +36,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv8i8.nxv8i8( define @intrinsic_xvlxbu_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv8i8.nxv8i8( + %a = call @llvm.riscv.th.vlxbu.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -51,7 +51,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlxbu.nxv16i8.nxv16i8( , *, , @@ -60,12 +60,12 @@ declare @llvm.riscv.xvlxbu.nxv16i8.nxv16i8( define @intrinsic_xvlxbu_v_nxv16i8_nxv16i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlxbu.nxv16i8.nxv16i8( undef, * %0, %1, @@ -74,7 +74,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vlxbu.mask.nxv16i8.nxv16i8( , *, , @@ -84,12 +84,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv16i8.nxv16i8( define @intrinsic_xvlxbu_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv16i8.nxv16i8( + %a = call @llvm.riscv.th.vlxbu.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -99,7 +99,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlxbu.nxv32i8.nxv32i8( , *, , @@ -108,12 +108,12 @@ declare @llvm.riscv.xvlxbu.nxv32i8.nxv32i8( define @intrinsic_xvlxbu_v_nxv32i8_nxv32i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlxbu.nxv32i8.nxv32i8( undef, * %0, %1, @@ -122,7 +122,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vlxbu.mask.nxv32i8.nxv32i8( , *, , @@ -132,12 +132,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv32i8.nxv32i8( define @intrinsic_xvlxbu_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv32i8.nxv32i8( + %a = call @llvm.riscv.th.vlxbu.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -147,7 +147,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlxbu.nxv64i8.nxv64i8( , *, , @@ -156,12 +156,12 @@ declare @llvm.riscv.xvlxbu.nxv64i8.nxv64i8( define @intrinsic_xvlxbu_v_nxv64i8_nxv64i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlxbu.nxv64i8.nxv64i8( undef, * %0, %1, @@ -170,7 +170,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vlxbu.mask.nxv64i8.nxv64i8( , *, , @@ -180,12 +180,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv64i8.nxv64i8( define @intrinsic_xvlxbu_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv64i8.nxv64i8( + %a = call @llvm.riscv.th.vlxbu.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -195,7 +195,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxbu.nxv4i16.nxv4i16( , *, , @@ -204,12 +204,12 @@ declare @llvm.riscv.xvlxbu.nxv4i16.nxv4i16( define @intrinsic_xvlxbu_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxbu.nxv4i16.nxv4i16( undef, * %0, %1, @@ -218,7 +218,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxbu.mask.nxv4i16.nxv4i16( , *, , @@ -228,12 +228,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv4i16.nxv4i16( define @intrinsic_xvlxbu_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxbu.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -243,7 +243,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxbu.nxv8i16.nxv8i16( , *, , @@ -252,12 +252,12 @@ declare @llvm.riscv.xvlxbu.nxv8i16.nxv8i16( define @intrinsic_xvlxbu_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxbu.nxv8i16.nxv8i16( undef, * %0, %1, @@ -266,7 +266,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxbu.mask.nxv8i16.nxv8i16( , *, , @@ -276,12 +276,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv8i16.nxv8i16( define @intrinsic_xvlxbu_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxbu.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -291,7 +291,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxbu.nxv16i16.nxv16i16( , *, , @@ -300,12 +300,12 @@ declare @llvm.riscv.xvlxbu.nxv16i16.nxv16i16( define @intrinsic_xvlxbu_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxbu.nxv16i16.nxv16i16( undef, * %0, %1, @@ -314,7 +314,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxbu.mask.nxv16i16.nxv16i16( , *, , @@ -324,12 +324,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv16i16.nxv16i16( define @intrinsic_xvlxbu_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxbu.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -339,7 +339,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxbu.nxv32i16.nxv32i16( , *, , @@ -348,12 +348,12 @@ declare @llvm.riscv.xvlxbu.nxv32i16.nxv32i16( define @intrinsic_xvlxbu_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxbu.nxv32i16.nxv32i16( undef, * %0, %1, @@ -362,7 +362,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxbu.mask.nxv32i16.nxv32i16( , *, , @@ -372,12 +372,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv32i16.nxv32i16( define @intrinsic_xvlxbu_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxbu.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -387,7 +387,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxbu.nxv2i32.nxv2i32( , *, , @@ -396,12 +396,12 @@ declare @llvm.riscv.xvlxbu.nxv2i32.nxv2i32( define @intrinsic_xvlxbu_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxbu.nxv2i32.nxv2i32( undef, * %0, %1, @@ -410,7 +410,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxbu.mask.nxv2i32.nxv2i32( , *, , @@ -420,12 +420,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxbu_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxbu.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -435,7 +435,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxbu.nxv4i32.nxv4i32( , *, , @@ -444,12 +444,12 @@ declare @llvm.riscv.xvlxbu.nxv4i32.nxv4i32( define @intrinsic_xvlxbu_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxbu.nxv4i32.nxv4i32( undef, * %0, %1, @@ -458,7 +458,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxbu.mask.nxv4i32.nxv4i32( , *, , @@ -468,12 +468,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxbu_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxbu.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -483,7 +483,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxbu.nxv8i32.nxv8i32( , *, , @@ -492,12 +492,12 @@ declare @llvm.riscv.xvlxbu.nxv8i32.nxv8i32( define @intrinsic_xvlxbu_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxbu.nxv8i32.nxv8i32( undef, * %0, %1, @@ -506,7 +506,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxbu.mask.nxv8i32.nxv8i32( , *, , @@ -516,12 +516,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxbu_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxbu.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -531,7 +531,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxbu.nxv16i32.nxv16i32( , *, , @@ -540,12 +540,12 @@ declare @llvm.riscv.xvlxbu.nxv16i32.nxv16i32( define @intrinsic_xvlxbu_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxbu.nxv16i32.nxv16i32( undef, * %0, %1, @@ -554,7 +554,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxbu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxbu.mask.nxv16i32.nxv16i32( , *, , @@ -564,12 +564,12 @@ declare @llvm.riscv.xvlxbu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxbu_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxbu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxbu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxbu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxbu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxbu.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -579,7 +579,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxhu.nxv4i16.nxv4i16( , *, , @@ -588,12 +588,12 @@ declare @llvm.riscv.xvlxhu.nxv4i16.nxv4i16( define @intrinsic_xvlxhu_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxhu.nxv4i16.nxv4i16( undef, * %0, %1, @@ -602,7 +602,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vlxhu.mask.nxv4i16.nxv4i16( , *, , @@ -612,12 +612,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv4i16.nxv4i16( define @intrinsic_xvlxhu_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv4i16.nxv4i16( + %a = call @llvm.riscv.th.vlxhu.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -627,7 +627,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxhu.nxv8i16.nxv8i16( , *, , @@ -636,12 +636,12 @@ declare @llvm.riscv.xvlxhu.nxv8i16.nxv8i16( define @intrinsic_xvlxhu_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxhu.nxv8i16.nxv8i16( undef, * %0, %1, @@ -650,7 +650,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vlxhu.mask.nxv8i16.nxv8i16( , *, , @@ -660,12 +660,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv8i16.nxv8i16( define @intrinsic_xvlxhu_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv8i16.nxv8i16( + %a = call @llvm.riscv.th.vlxhu.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -675,7 +675,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxhu.nxv16i16.nxv16i16( , *, , @@ -684,12 +684,12 @@ declare @llvm.riscv.xvlxhu.nxv16i16.nxv16i16( define @intrinsic_xvlxhu_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxhu.nxv16i16.nxv16i16( undef, * %0, %1, @@ -698,7 +698,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vlxhu.mask.nxv16i16.nxv16i16( , *, , @@ -708,12 +708,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv16i16.nxv16i16( define @intrinsic_xvlxhu_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv16i16.nxv16i16( + %a = call @llvm.riscv.th.vlxhu.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -723,7 +723,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxhu.nxv32i16.nxv32i16( , *, , @@ -732,12 +732,12 @@ declare @llvm.riscv.xvlxhu.nxv32i16.nxv32i16( define @intrinsic_xvlxhu_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxhu.nxv32i16.nxv32i16( undef, * %0, %1, @@ -746,7 +746,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vlxhu.mask.nxv32i16.nxv32i16( , *, , @@ -756,12 +756,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv32i16.nxv32i16( define @intrinsic_xvlxhu_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv32i16.nxv32i16( + %a = call @llvm.riscv.th.vlxhu.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -771,7 +771,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxhu.nxv2i32.nxv2i32( , *, , @@ -780,12 +780,12 @@ declare @llvm.riscv.xvlxhu.nxv2i32.nxv2i32( define @intrinsic_xvlxhu_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxhu.nxv2i32.nxv2i32( undef, * %0, %1, @@ -794,7 +794,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxhu.mask.nxv2i32.nxv2i32( , *, , @@ -804,12 +804,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxhu_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxhu.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -819,7 +819,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxhu.nxv4i32.nxv4i32( , *, , @@ -828,12 +828,12 @@ declare @llvm.riscv.xvlxhu.nxv4i32.nxv4i32( define @intrinsic_xvlxhu_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxhu.nxv4i32.nxv4i32( undef, * %0, %1, @@ -842,7 +842,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxhu.mask.nxv4i32.nxv4i32( , *, , @@ -852,12 +852,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxhu_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxhu.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -867,7 +867,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxhu.nxv8i32.nxv8i32( , *, , @@ -876,12 +876,12 @@ declare @llvm.riscv.xvlxhu.nxv8i32.nxv8i32( define @intrinsic_xvlxhu_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxhu.nxv8i32.nxv8i32( undef, * %0, %1, @@ -890,7 +890,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxhu.mask.nxv8i32.nxv8i32( , *, , @@ -900,12 +900,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxhu_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxhu.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -915,7 +915,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxhu.nxv16i32.nxv16i32( , *, , @@ -924,12 +924,12 @@ declare @llvm.riscv.xvlxhu.nxv16i32.nxv16i32( define @intrinsic_xvlxhu_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxhu.nxv16i32.nxv16i32( undef, * %0, %1, @@ -938,7 +938,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxhu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxhu.mask.nxv16i32.nxv16i32( , *, , @@ -948,12 +948,12 @@ declare @llvm.riscv.xvlxhu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxhu_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxhu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxhu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxhu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxhu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxhu.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -963,7 +963,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxwu.nxv2i32.nxv2i32( , *, , @@ -972,12 +972,12 @@ declare @llvm.riscv.xvlxwu.nxv2i32.nxv2i32( define @intrinsic_xvlxwu_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxwu.nxv2i32.nxv2i32( undef, * %0, %1, @@ -986,7 +986,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vlxwu.mask.nxv2i32.nxv2i32( , *, , @@ -996,12 +996,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv2i32.nxv2i32( define @intrinsic_xvlxwu_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv2i32.nxv2i32( + %a = call @llvm.riscv.th.vlxwu.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1011,7 +1011,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxwu.nxv4i32.nxv4i32( , *, , @@ -1020,12 +1020,12 @@ declare @llvm.riscv.xvlxwu.nxv4i32.nxv4i32( define @intrinsic_xvlxwu_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxwu.nxv4i32.nxv4i32( undef, * %0, %1, @@ -1034,7 +1034,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vlxwu.mask.nxv4i32.nxv4i32( , *, , @@ -1044,12 +1044,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv4i32.nxv4i32( define @intrinsic_xvlxwu_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv4i32.nxv4i32( + %a = call @llvm.riscv.th.vlxwu.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1059,7 +1059,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxwu.nxv8i32.nxv8i32( , *, , @@ -1068,12 +1068,12 @@ declare @llvm.riscv.xvlxwu.nxv8i32.nxv8i32( define @intrinsic_xvlxwu_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxwu.nxv8i32.nxv8i32( undef, * %0, %1, @@ -1082,7 +1082,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vlxwu.mask.nxv8i32.nxv8i32( , *, , @@ -1092,12 +1092,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv8i32.nxv8i32( define @intrinsic_xvlxwu_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv8i32.nxv8i32( + %a = call @llvm.riscv.th.vlxwu.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1107,7 +1107,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxwu.nxv16i32.nxv16i32( , *, , @@ -1116,12 +1116,12 @@ declare @llvm.riscv.xvlxwu.nxv16i32.nxv16i32( define @intrinsic_xvlxwu_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxwu.nxv16i32.nxv16i32( undef, * %0, %1, @@ -1130,7 +1130,7 @@ entry: ret %a } -declare @llvm.riscv.xvlxwu.mask.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vlxwu.mask.nxv16i32.nxv16i32( , *, , @@ -1140,12 +1140,12 @@ declare @llvm.riscv.xvlxwu.mask.nxv16i32.nxv16i32( define @intrinsic_xvlxwu_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvlxwu_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vlxwu.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vlxwu.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - %a = call @llvm.riscv.xvlxwu.mask.nxv16i32.nxv16i32( + %a = call @llvm.riscv.th.vlxwu.mask.nxv16i32.nxv16i32( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vs.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vs.ll index f6ba796fb0137..00bf69982a4b8 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vs.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vs.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare void @llvm.riscv.xvsb.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsb.nxv8i8.nxv8i8( , *, iXLen); @@ -11,12 +11,12 @@ declare void @llvm.riscv.xvsb.nxv8i8.nxv8i8( define void @intrinsic_xvsb_v_nxv8i8_nxv8i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsb_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vsb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vsb.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsb.nxv8i8.nxv8i8( undef, * %0, iXLen %1) @@ -24,7 +24,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.mask.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsb.mask.nxv8i8.nxv8i8( , *, , @@ -33,12 +33,12 @@ declare void @llvm.riscv.xvsb.mask.nxv8i8.nxv8i8( define void @intrinsic_xvsb_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsb_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vsb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vsb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.mask.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsb.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -47,7 +47,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsb.nxv16i8.nxv16i8( , *, iXLen); @@ -55,12 +55,12 @@ declare void @llvm.riscv.xvsb.nxv16i8.nxv16i8( define void @intrinsic_xvsb_v_nxv16i8_nxv16i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsb_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vsb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vsb.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsb.nxv16i8.nxv16i8( undef, * %0, iXLen %1) @@ -68,7 +68,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.mask.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsb.mask.nxv16i8.nxv16i8( , *, , @@ -77,12 +77,12 @@ declare void @llvm.riscv.xvsb.mask.nxv16i8.nxv16i8( define void @intrinsic_xvsb_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsb_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vsb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vsb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.mask.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsb.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -91,7 +91,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsb.nxv32i8.nxv32i8( , *, iXLen); @@ -99,12 +99,12 @@ declare void @llvm.riscv.xvsb.nxv32i8.nxv32i8( define void @intrinsic_xvsb_v_nxv32i8_nxv32i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsb_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vsb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vsb.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsb.nxv32i8.nxv32i8( undef, * %0, iXLen %1) @@ -112,7 +112,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.mask.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsb.mask.nxv32i8.nxv32i8( , *, , @@ -121,12 +121,12 @@ declare void @llvm.riscv.xvsb.mask.nxv32i8.nxv32i8( define void @intrinsic_xvsb_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsb_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vsb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vsb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.mask.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsb.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -135,7 +135,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsb.nxv64i8.nxv64i8( , *, iXLen); @@ -143,12 +143,12 @@ declare void @llvm.riscv.xvsb.nxv64i8.nxv64i8( define void @intrinsic_xvsb_v_nxv64i8_nxv64i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsb_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vsb.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vsb.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsb.nxv64i8.nxv64i8( undef, * %0, iXLen %1) @@ -156,7 +156,7 @@ entry: ret void } -declare void @llvm.riscv.xvsb.mask.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsb.mask.nxv64i8.nxv64i8( , *, , @@ -165,12 +165,12 @@ declare void @llvm.riscv.xvsb.mask.nxv64i8.nxv64i8( define void @intrinsic_xvsb_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsb_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vsb.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vsb.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsb.mask.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsb.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -179,7 +179,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsh.nxv4i16.nxv4i16( , *, iXLen); @@ -187,12 +187,12 @@ declare void @llvm.riscv.xvsh.nxv4i16.nxv4i16( define void @intrinsic_xvsh_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsh_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsh.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsh.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -200,7 +200,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.mask.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsh.mask.nxv4i16.nxv4i16( , *, , @@ -209,12 +209,12 @@ declare void @llvm.riscv.xvsh.mask.nxv4i16.nxv4i16( define void @intrinsic_xvsh_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsh_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.mask.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsh.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -223,7 +223,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsh.nxv8i16.nxv8i16( , *, iXLen); @@ -231,12 +231,12 @@ declare void @llvm.riscv.xvsh.nxv8i16.nxv8i16( define void @intrinsic_xvsh_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsh_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsh.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsh.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -244,7 +244,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.mask.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsh.mask.nxv8i16.nxv8i16( , *, , @@ -253,12 +253,12 @@ declare void @llvm.riscv.xvsh.mask.nxv8i16.nxv8i16( define void @intrinsic_xvsh_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsh_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.mask.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsh.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -267,7 +267,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsh.nxv16i16.nxv16i16( , *, iXLen); @@ -275,12 +275,12 @@ declare void @llvm.riscv.xvsh.nxv16i16.nxv16i16( define void @intrinsic_xvsh_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsh_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsh.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsh.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -288,7 +288,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.mask.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsh.mask.nxv16i16.nxv16i16( , *, , @@ -297,12 +297,12 @@ declare void @llvm.riscv.xvsh.mask.nxv16i16.nxv16i16( define void @intrinsic_xvsh_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsh_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.mask.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsh.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -311,7 +311,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsh.nxv32i16.nxv32i16( , *, iXLen); @@ -319,12 +319,12 @@ declare void @llvm.riscv.xvsh.nxv32i16.nxv32i16( define void @intrinsic_xvsh_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsh_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsh.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsh.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsh.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -332,7 +332,7 @@ entry: ret void } -declare void @llvm.riscv.xvsh.mask.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsh.mask.nxv32i16.nxv32i16( , *, , @@ -341,12 +341,12 @@ declare void @llvm.riscv.xvsh.mask.nxv32i16.nxv32i16( define void @intrinsic_xvsh_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsh_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsh.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsh.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsh.mask.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsh.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -355,7 +355,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsw.nxv2i32.nxv2i32( , *, iXLen); @@ -363,12 +363,12 @@ declare void @llvm.riscv.xvsw.nxv2i32.nxv2i32( define void @intrinsic_xvsw_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsw_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsw.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsw.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -376,7 +376,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.mask.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsw.mask.nxv2i32.nxv2i32( , *, , @@ -385,12 +385,12 @@ declare void @llvm.riscv.xvsw.mask.nxv2i32.nxv2i32( define void @intrinsic_xvsw_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsw_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.mask.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsw.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -399,7 +399,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsw.nxv4i32.nxv4i32( , *, iXLen); @@ -407,12 +407,12 @@ declare void @llvm.riscv.xvsw.nxv4i32.nxv4i32( define void @intrinsic_xvsw_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsw_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsw.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsw.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -420,7 +420,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.mask.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsw.mask.nxv4i32.nxv4i32( , *, , @@ -429,12 +429,12 @@ declare void @llvm.riscv.xvsw.mask.nxv4i32.nxv4i32( define void @intrinsic_xvsw_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsw_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.mask.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsw.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -443,7 +443,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsw.nxv8i32.nxv8i32( , *, iXLen); @@ -451,12 +451,12 @@ declare void @llvm.riscv.xvsw.nxv8i32.nxv8i32( define void @intrinsic_xvsw_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsw_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsw.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsw.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -464,7 +464,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.mask.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsw.mask.nxv8i32.nxv8i32( , *, , @@ -473,12 +473,12 @@ declare void @llvm.riscv.xvsw.mask.nxv8i32.nxv8i32( define void @intrinsic_xvsw_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsw_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.mask.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsw.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -487,7 +487,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsw.nxv16i32.nxv16i32( , *, iXLen); @@ -495,12 +495,12 @@ declare void @llvm.riscv.xvsw.nxv16i32.nxv16i32( define void @intrinsic_xvsw_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvsw_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsw.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsw.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsw.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -508,7 +508,7 @@ entry: ret void } -declare void @llvm.riscv.xvsw.mask.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsw.mask.nxv16i32.nxv16i32( , *, , @@ -517,12 +517,12 @@ declare void @llvm.riscv.xvsw.mask.nxv16i32.nxv16i32( define void @intrinsic_xvsw_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvsw_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsw.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsw.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsw.mask.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsw.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -531,7 +531,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vse.nxv8i8.nxv8i8( , *, iXLen); @@ -539,12 +539,12 @@ declare void @llvm.riscv.xvse.nxv8i8.nxv8i8( define void @intrinsic_xvse_v_nxv8i8_nxv8i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vse.nxv8i8.nxv8i8( undef, * %0, iXLen %1) @@ -552,7 +552,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vse.mask.nxv8i8.nxv8i8( , *, , @@ -561,12 +561,12 @@ declare void @llvm.riscv.xvse.mask.nxv8i8.nxv8i8( define void @intrinsic_xvse_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vse.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -575,7 +575,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vse.nxv16i8.nxv16i8( , *, iXLen); @@ -583,12 +583,12 @@ declare void @llvm.riscv.xvse.nxv16i8.nxv16i8( define void @intrinsic_xvse_v_nxv16i8_nxv16i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vse.nxv16i8.nxv16i8( undef, * %0, iXLen %1) @@ -596,7 +596,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vse.mask.nxv16i8.nxv16i8( , *, , @@ -605,12 +605,12 @@ declare void @llvm.riscv.xvse.mask.nxv16i8.nxv16i8( define void @intrinsic_xvse_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vse.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -619,7 +619,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vse.nxv32i8.nxv32i8( , *, iXLen); @@ -627,12 +627,12 @@ declare void @llvm.riscv.xvse.nxv32i8.nxv32i8( define void @intrinsic_xvse_v_nxv32i8_nxv32i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vse.nxv32i8.nxv32i8( undef, * %0, iXLen %1) @@ -640,7 +640,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vse.mask.nxv32i8.nxv32i8( , *, , @@ -649,12 +649,12 @@ declare void @llvm.riscv.xvse.mask.nxv32i8.nxv32i8( define void @intrinsic_xvse_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vse.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -663,7 +663,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vse.nxv64i8.nxv64i8( , *, iXLen); @@ -671,12 +671,12 @@ declare void @llvm.riscv.xvse.nxv64i8.nxv64i8( define void @intrinsic_xvse_v_nxv64i8_nxv64i8(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vse.nxv64i8.nxv64i8( undef, * %0, iXLen %1) @@ -684,7 +684,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vse.mask.nxv64i8.nxv64i8( , *, , @@ -693,12 +693,12 @@ declare void @llvm.riscv.xvse.mask.nxv64i8.nxv64i8( define void @intrinsic_xvse_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vse.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -707,7 +707,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vse.nxv4i16.nxv4i16( , *, iXLen); @@ -715,12 +715,12 @@ declare void @llvm.riscv.xvse.nxv4i16.nxv4i16( define void @intrinsic_xvse_v_nxv4i16_nxv4i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vse.nxv4i16.nxv4i16( undef, * %0, iXLen %1) @@ -728,7 +728,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vse.mask.nxv4i16.nxv4i16( , *, , @@ -737,12 +737,12 @@ declare void @llvm.riscv.xvse.mask.nxv4i16.nxv4i16( define void @intrinsic_xvse_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vse.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -751,7 +751,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv4f16.nxv4f16( +declare void @llvm.riscv.th.vse.nxv4f16.nxv4f16( , *, iXLen); @@ -759,12 +759,12 @@ declare void @llvm.riscv.xvse.nxv4f16.nxv4f16( define void @intrinsic_xvse_v_nxv4f16_nxv4f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv4f16.nxv4f16( + call void @llvm.riscv.th.vse.nxv4f16.nxv4f16( undef, * %0, iXLen %1) @@ -772,7 +772,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv4f16.nxv4f16( +declare void @llvm.riscv.th.vse.mask.nxv4f16.nxv4f16( , *, , @@ -781,12 +781,12 @@ declare void @llvm.riscv.xvse.mask.nxv4f16.nxv4f16( define void @intrinsic_xvse_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv4f16.nxv4f16( + call void @llvm.riscv.th.vse.mask.nxv4f16.nxv4f16( %0, * %1, %2, @@ -795,7 +795,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vse.nxv8i16.nxv8i16( , *, iXLen); @@ -803,12 +803,12 @@ declare void @llvm.riscv.xvse.nxv8i16.nxv8i16( define void @intrinsic_xvse_v_nxv8i16_nxv8i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vse.nxv8i16.nxv8i16( undef, * %0, iXLen %1) @@ -816,7 +816,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vse.mask.nxv8i16.nxv8i16( , *, , @@ -825,12 +825,12 @@ declare void @llvm.riscv.xvse.mask.nxv8i16.nxv8i16( define void @intrinsic_xvse_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vse.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -839,7 +839,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8f16.nxv8f16( +declare void @llvm.riscv.th.vse.nxv8f16.nxv8f16( , *, iXLen); @@ -847,12 +847,12 @@ declare void @llvm.riscv.xvse.nxv8f16.nxv8f16( define void @intrinsic_xvse_v_nxv8f16_nxv8f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8f16.nxv8f16( + call void @llvm.riscv.th.vse.nxv8f16.nxv8f16( undef, * %0, iXLen %1) @@ -860,7 +860,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8f16.nxv8f16( +declare void @llvm.riscv.th.vse.mask.nxv8f16.nxv8f16( , *, , @@ -869,12 +869,12 @@ declare void @llvm.riscv.xvse.mask.nxv8f16.nxv8f16( define void @intrinsic_xvse_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8f16.nxv8f16( + call void @llvm.riscv.th.vse.mask.nxv8f16.nxv8f16( %0, * %1, %2, @@ -883,7 +883,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vse.nxv16i16.nxv16i16( , *, iXLen); @@ -891,12 +891,12 @@ declare void @llvm.riscv.xvse.nxv16i16.nxv16i16( define void @intrinsic_xvse_v_nxv16i16_nxv16i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vse.nxv16i16.nxv16i16( undef, * %0, iXLen %1) @@ -904,7 +904,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vse.mask.nxv16i16.nxv16i16( , *, , @@ -913,12 +913,12 @@ declare void @llvm.riscv.xvse.mask.nxv16i16.nxv16i16( define void @intrinsic_xvse_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vse.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -927,7 +927,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv16f16.nxv16f16( +declare void @llvm.riscv.th.vse.nxv16f16.nxv16f16( , *, iXLen); @@ -935,12 +935,12 @@ declare void @llvm.riscv.xvse.nxv16f16.nxv16f16( define void @intrinsic_xvse_v_nxv16f16_nxv16f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv16f16.nxv16f16( + call void @llvm.riscv.th.vse.nxv16f16.nxv16f16( undef, * %0, iXLen %1) @@ -948,7 +948,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv16f16.nxv16f16( +declare void @llvm.riscv.th.vse.mask.nxv16f16.nxv16f16( , *, , @@ -957,12 +957,12 @@ declare void @llvm.riscv.xvse.mask.nxv16f16.nxv16f16( define void @intrinsic_xvse_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv16f16.nxv16f16( + call void @llvm.riscv.th.vse.mask.nxv16f16.nxv16f16( %0, * %1, %2, @@ -971,7 +971,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vse.nxv32i16.nxv32i16( , *, iXLen); @@ -979,12 +979,12 @@ declare void @llvm.riscv.xvse.nxv32i16.nxv32i16( define void @intrinsic_xvse_v_nxv32i16_nxv32i16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vse.nxv32i16.nxv32i16( undef, * %0, iXLen %1) @@ -992,7 +992,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vse.mask.nxv32i16.nxv32i16( , *, , @@ -1001,12 +1001,12 @@ declare void @llvm.riscv.xvse.mask.nxv32i16.nxv32i16( define void @intrinsic_xvse_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vse.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -1015,7 +1015,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv32f16.nxv32f16( +declare void @llvm.riscv.th.vse.nxv32f16.nxv32f16( , *, iXLen); @@ -1023,12 +1023,12 @@ declare void @llvm.riscv.xvse.nxv32f16.nxv32f16( define void @intrinsic_xvse_v_nxv32f16_nxv32f16(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv32f16.nxv32f16( + call void @llvm.riscv.th.vse.nxv32f16.nxv32f16( undef, * %0, iXLen %1) @@ -1036,7 +1036,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv32f16.nxv32f16( +declare void @llvm.riscv.th.vse.mask.nxv32f16.nxv32f16( , *, , @@ -1045,12 +1045,12 @@ declare void @llvm.riscv.xvse.mask.nxv32f16.nxv32f16( define void @intrinsic_xvse_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv32f16.nxv32f16( + call void @llvm.riscv.th.vse.mask.nxv32f16.nxv32f16( %0, * %1, %2, @@ -1059,7 +1059,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vse.nxv2i32.nxv2i32( , *, iXLen); @@ -1067,12 +1067,12 @@ declare void @llvm.riscv.xvse.nxv2i32.nxv2i32( define void @intrinsic_xvse_v_nxv2i32_nxv2i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vse.nxv2i32.nxv2i32( undef, * %0, iXLen %1) @@ -1080,7 +1080,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vse.mask.nxv2i32.nxv2i32( , *, , @@ -1089,12 +1089,12 @@ declare void @llvm.riscv.xvse.mask.nxv2i32.nxv2i32( define void @intrinsic_xvse_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vse.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1103,7 +1103,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv2f32.nxv2f32( +declare void @llvm.riscv.th.vse.nxv2f32.nxv2f32( , *, iXLen); @@ -1111,12 +1111,12 @@ declare void @llvm.riscv.xvse.nxv2f32.nxv2f32( define void @intrinsic_xvse_v_nxv2f32_nxv2f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv2f32.nxv2f32( + call void @llvm.riscv.th.vse.nxv2f32.nxv2f32( undef, * %0, iXLen %1) @@ -1124,7 +1124,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv2f32.nxv2f32( +declare void @llvm.riscv.th.vse.mask.nxv2f32.nxv2f32( , *, , @@ -1133,12 +1133,12 @@ declare void @llvm.riscv.xvse.mask.nxv2f32.nxv2f32( define void @intrinsic_xvse_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv2f32.nxv2f32( + call void @llvm.riscv.th.vse.mask.nxv2f32.nxv2f32( %0, * %1, %2, @@ -1147,7 +1147,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vse.nxv4i32.nxv4i32( , *, iXLen); @@ -1155,12 +1155,12 @@ declare void @llvm.riscv.xvse.nxv4i32.nxv4i32( define void @intrinsic_xvse_v_nxv4i32_nxv4i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vse.nxv4i32.nxv4i32( undef, * %0, iXLen %1) @@ -1168,7 +1168,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vse.mask.nxv4i32.nxv4i32( , *, , @@ -1177,12 +1177,12 @@ declare void @llvm.riscv.xvse.mask.nxv4i32.nxv4i32( define void @intrinsic_xvse_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vse.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1191,7 +1191,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv4f32.nxv4f32( +declare void @llvm.riscv.th.vse.nxv4f32.nxv4f32( , *, iXLen); @@ -1199,12 +1199,12 @@ declare void @llvm.riscv.xvse.nxv4f32.nxv4f32( define void @intrinsic_xvse_v_nxv4f32_nxv4f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv4f32.nxv4f32( + call void @llvm.riscv.th.vse.nxv4f32.nxv4f32( undef, * %0, iXLen %1) @@ -1212,7 +1212,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv4f32.nxv4f32( +declare void @llvm.riscv.th.vse.mask.nxv4f32.nxv4f32( , *, , @@ -1221,12 +1221,12 @@ declare void @llvm.riscv.xvse.mask.nxv4f32.nxv4f32( define void @intrinsic_xvse_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv4f32.nxv4f32( + call void @llvm.riscv.th.vse.mask.nxv4f32.nxv4f32( %0, * %1, %2, @@ -1235,7 +1235,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vse.nxv8i32.nxv8i32( , *, iXLen); @@ -1243,12 +1243,12 @@ declare void @llvm.riscv.xvse.nxv8i32.nxv8i32( define void @intrinsic_xvse_v_nxv8i32_nxv8i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vse.nxv8i32.nxv8i32( undef, * %0, iXLen %1) @@ -1256,7 +1256,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vse.mask.nxv8i32.nxv8i32( , *, , @@ -1265,12 +1265,12 @@ declare void @llvm.riscv.xvse.mask.nxv8i32.nxv8i32( define void @intrinsic_xvse_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vse.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1279,7 +1279,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8f32.nxv8f32( +declare void @llvm.riscv.th.vse.nxv8f32.nxv8f32( , *, iXLen); @@ -1287,12 +1287,12 @@ declare void @llvm.riscv.xvse.nxv8f32.nxv8f32( define void @intrinsic_xvse_v_nxv8f32_nxv8f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8f32.nxv8f32( + call void @llvm.riscv.th.vse.nxv8f32.nxv8f32( undef, * %0, iXLen %1) @@ -1300,7 +1300,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8f32.nxv8f32( +declare void @llvm.riscv.th.vse.mask.nxv8f32.nxv8f32( , *, , @@ -1309,12 +1309,12 @@ declare void @llvm.riscv.xvse.mask.nxv8f32.nxv8f32( define void @intrinsic_xvse_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8f32.nxv8f32( + call void @llvm.riscv.th.vse.mask.nxv8f32.nxv8f32( %0, * %1, %2, @@ -1323,7 +1323,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vse.nxv16i32.nxv16i32( , *, iXLen); @@ -1331,12 +1331,12 @@ declare void @llvm.riscv.xvse.nxv16i32.nxv16i32( define void @intrinsic_xvse_v_nxv16i32_nxv16i32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vse.nxv16i32.nxv16i32( undef, * %0, iXLen %1) @@ -1344,7 +1344,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vse.mask.nxv16i32.nxv16i32( , *, , @@ -1353,12 +1353,12 @@ declare void @llvm.riscv.xvse.mask.nxv16i32.nxv16i32( define void @intrinsic_xvse_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vse.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1367,7 +1367,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv16f32.nxv16f32( +declare void @llvm.riscv.th.vse.nxv16f32.nxv16f32( , *, iXLen); @@ -1375,12 +1375,12 @@ declare void @llvm.riscv.xvse.nxv16f32.nxv16f32( define void @intrinsic_xvse_v_nxv16f32_nxv16f32(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv16f32.nxv16f32( + call void @llvm.riscv.th.vse.nxv16f32.nxv16f32( undef, * %0, iXLen %1) @@ -1388,7 +1388,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv16f32.nxv16f32( +declare void @llvm.riscv.th.vse.mask.nxv16f32.nxv16f32( , *, , @@ -1397,12 +1397,12 @@ declare void @llvm.riscv.xvse.mask.nxv16f32.nxv16f32( define void @intrinsic_xvse_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv16f32.nxv16f32( + call void @llvm.riscv.th.vse.mask.nxv16f32.nxv16f32( %0, * %1, %2, @@ -1411,7 +1411,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv1i64.nxv1i64( +declare void @llvm.riscv.th.vse.nxv1i64.nxv1i64( , *, iXLen); @@ -1419,12 +1419,12 @@ declare void @llvm.riscv.xvse.nxv1i64.nxv1i64( define void @intrinsic_xvse_v_nxv1i64_nxv1i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv1i64.nxv1i64( + call void @llvm.riscv.th.vse.nxv1i64.nxv1i64( undef, * %0, iXLen %1) @@ -1432,7 +1432,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv1i64.nxv1i64( +declare void @llvm.riscv.th.vse.mask.nxv1i64.nxv1i64( , *, , @@ -1441,12 +1441,12 @@ declare void @llvm.riscv.xvse.mask.nxv1i64.nxv1i64( define void @intrinsic_xvse_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv1i64.nxv1i64( + call void @llvm.riscv.th.vse.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -1455,7 +1455,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv1f64.nxv1f64( +declare void @llvm.riscv.th.vse.nxv1f64.nxv1f64( , *, iXLen); @@ -1463,12 +1463,12 @@ declare void @llvm.riscv.xvse.nxv1f64.nxv1f64( define void @intrinsic_xvse_v_nxv1f64_nxv1f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv1f64.nxv1f64( + call void @llvm.riscv.th.vse.nxv1f64.nxv1f64( undef, * %0, iXLen %1) @@ -1476,7 +1476,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv1f64.nxv1f64( +declare void @llvm.riscv.th.vse.mask.nxv1f64.nxv1f64( , *, , @@ -1485,12 +1485,12 @@ declare void @llvm.riscv.xvse.mask.nxv1f64.nxv1f64( define void @intrinsic_xvse_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv1f64.nxv1f64( + call void @llvm.riscv.th.vse.mask.nxv1f64.nxv1f64( %0, * %1, %2, @@ -1499,7 +1499,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv2i64.nxv2i64( +declare void @llvm.riscv.th.vse.nxv2i64.nxv2i64( , *, iXLen); @@ -1507,12 +1507,12 @@ declare void @llvm.riscv.xvse.nxv2i64.nxv2i64( define void @intrinsic_xvse_v_nxv2i64_nxv2i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv2i64.nxv2i64( + call void @llvm.riscv.th.vse.nxv2i64.nxv2i64( undef, * %0, iXLen %1) @@ -1520,7 +1520,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv2i64.nxv2i64( +declare void @llvm.riscv.th.vse.mask.nxv2i64.nxv2i64( , *, , @@ -1529,12 +1529,12 @@ declare void @llvm.riscv.xvse.mask.nxv2i64.nxv2i64( define void @intrinsic_xvse_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv2i64.nxv2i64( + call void @llvm.riscv.th.vse.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -1543,7 +1543,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv2f64.nxv2f64( +declare void @llvm.riscv.th.vse.nxv2f64.nxv2f64( , *, iXLen); @@ -1551,12 +1551,12 @@ declare void @llvm.riscv.xvse.nxv2f64.nxv2f64( define void @intrinsic_xvse_v_nxv2f64_nxv2f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv2f64.nxv2f64( + call void @llvm.riscv.th.vse.nxv2f64.nxv2f64( undef, * %0, iXLen %1) @@ -1564,7 +1564,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv2f64.nxv2f64( +declare void @llvm.riscv.th.vse.mask.nxv2f64.nxv2f64( , *, , @@ -1573,12 +1573,12 @@ declare void @llvm.riscv.xvse.mask.nxv2f64.nxv2f64( define void @intrinsic_xvse_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv2f64.nxv2f64( + call void @llvm.riscv.th.vse.mask.nxv2f64.nxv2f64( %0, * %1, %2, @@ -1587,7 +1587,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv4i64.nxv4i64( +declare void @llvm.riscv.th.vse.nxv4i64.nxv4i64( , *, iXLen); @@ -1595,12 +1595,12 @@ declare void @llvm.riscv.xvse.nxv4i64.nxv4i64( define void @intrinsic_xvse_v_nxv4i64_nxv4i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv4i64.nxv4i64( + call void @llvm.riscv.th.vse.nxv4i64.nxv4i64( undef, * %0, iXLen %1) @@ -1608,7 +1608,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv4i64.nxv4i64( +declare void @llvm.riscv.th.vse.mask.nxv4i64.nxv4i64( , *, , @@ -1617,12 +1617,12 @@ declare void @llvm.riscv.xvse.mask.nxv4i64.nxv4i64( define void @intrinsic_xvse_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv4i64.nxv4i64( + call void @llvm.riscv.th.vse.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -1631,7 +1631,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv4f64.nxv4f64( +declare void @llvm.riscv.th.vse.nxv4f64.nxv4f64( , *, iXLen); @@ -1639,12 +1639,12 @@ declare void @llvm.riscv.xvse.nxv4f64.nxv4f64( define void @intrinsic_xvse_v_nxv4f64_nxv4f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv4f64.nxv4f64( + call void @llvm.riscv.th.vse.nxv4f64.nxv4f64( undef, * %0, iXLen %1) @@ -1652,7 +1652,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv4f64.nxv4f64( +declare void @llvm.riscv.th.vse.mask.nxv4f64.nxv4f64( , *, , @@ -1661,12 +1661,12 @@ declare void @llvm.riscv.xvse.mask.nxv4f64.nxv4f64( define void @intrinsic_xvse_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv4f64.nxv4f64( + call void @llvm.riscv.th.vse.mask.nxv4f64.nxv4f64( %0, * %1, %2, @@ -1675,7 +1675,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8i64.nxv8i64( +declare void @llvm.riscv.th.vse.nxv8i64.nxv8i64( , *, iXLen); @@ -1683,12 +1683,12 @@ declare void @llvm.riscv.xvse.nxv8i64.nxv8i64( define void @intrinsic_xvse_v_nxv8i64_nxv8i64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8i64.nxv8i64( + call void @llvm.riscv.th.vse.nxv8i64.nxv8i64( undef, * %0, iXLen %1) @@ -1696,7 +1696,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8i64.nxv8i64( +declare void @llvm.riscv.th.vse.mask.nxv8i64.nxv8i64( , *, , @@ -1705,12 +1705,12 @@ declare void @llvm.riscv.xvse.mask.nxv8i64.nxv8i64( define void @intrinsic_xvse_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8i64.nxv8i64( + call void @llvm.riscv.th.vse.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -1719,7 +1719,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.nxv8f64.nxv8f64( +declare void @llvm.riscv.th.vse.nxv8f64.nxv8f64( , *, iXLen); @@ -1727,12 +1727,12 @@ declare void @llvm.riscv.xvse.nxv8f64.nxv8f64( define void @intrinsic_xvse_v_nxv8f64_nxv8f64(* %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_xvse_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.nxv8f64.nxv8f64( + call void @llvm.riscv.th.vse.nxv8f64.nxv8f64( undef, * %0, iXLen %1) @@ -1740,7 +1740,7 @@ entry: ret void } -declare void @llvm.riscv.xvse.mask.nxv8f64.nxv8f64( +declare void @llvm.riscv.th.vse.mask.nxv8f64.nxv8f64( , *, , @@ -1749,12 +1749,12 @@ declare void @llvm.riscv.xvse.mask.nxv8f64.nxv8f64( define void @intrinsic_xvse_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_xvse_mask_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vse.v v8, (a0), v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvse.mask.nxv8f64.nxv8f64( + call void @llvm.riscv.th.vse.mask.nxv8f64.nxv8f64( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vsetvl.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vsetvl.ll index 75e64884607a8..713dc868ce538 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vsetvl.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vsetvl.ll @@ -1,6 +1,6 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s ; https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/v0.7.1/rvv_intrinsic_funcs/01_configuration-setting_and_utility_functions.md @@ -16,14 +16,14 @@ ; ----------------------------------- ; In intrinsic, ediv is always 0 for ASM name `d1` -declare iXLen @llvm.riscv.xvsetvl.iXLen (iXLen %avl, iXLen %sew, iXLen %lmul); -declare iXLen @llvm.riscv.xvsetvlmax.iXLen( iXLen %sew, iXLen %lmul); +declare iXLen @llvm.riscv.th.vsetvl.iXLen (iXLen %avl, iXLen %sew, iXLen %lmul); +declare iXLen @llvm.riscv.th.vsetvlmax.iXLen( iXLen %sew, iXLen %lmul); define iXLen @intrinsic_xvsetvl_e8m1(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e8m1 ; CHECK: vsetvli a0, a0, e8, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 0) ret iXLen %v } @@ -31,7 +31,7 @@ define iXLen @intrinsic_xvsetvl_e8m1(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e8m2(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e8m2 ; CHECK: vsetvli a0, a0, e8, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 1) ret iXLen %v } @@ -39,7 +39,7 @@ define iXLen @intrinsic_xvsetvl_e8m2(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e8m4(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e8m4 ; CHECK: vsetvli a0, a0, e8, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 2) ret iXLen %v } @@ -47,7 +47,7 @@ define iXLen @intrinsic_xvsetvl_e8m4(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e8m8(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e8m8 ; CHECK: vsetvli a0, a0, e8, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 0, iXLen 3) ret iXLen %v } @@ -55,7 +55,7 @@ define iXLen @intrinsic_xvsetvl_e8m8(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e16m1(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e16m1 ; CHECK: vsetvli a0, a0, e16, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 0) ret iXLen %v } @@ -63,7 +63,7 @@ define iXLen @intrinsic_xvsetvl_e16m1(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e16m2(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e16m2 ; CHECK: vsetvli a0, a0, e16, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 1) ret iXLen %v } @@ -71,7 +71,7 @@ define iXLen @intrinsic_xvsetvl_e16m2(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e16m4(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e16m4 ; CHECK: vsetvli a0, a0, e16, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 2) ret iXLen %v } @@ -79,7 +79,7 @@ define iXLen @intrinsic_xvsetvl_e16m4(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e16m8(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e16m8 ; CHECK: vsetvli a0, a0, e16, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 1, iXLen 3) ret iXLen %v } @@ -87,7 +87,7 @@ define iXLen @intrinsic_xvsetvl_e16m8(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e32m1(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e32m1 ; CHECK: vsetvli a0, a0, e32, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 0) ret iXLen %v } @@ -95,7 +95,7 @@ define iXLen @intrinsic_xvsetvl_e32m1(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e32m2(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e32m2 ; CHECK: vsetvli a0, a0, e32, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 1) ret iXLen %v } @@ -103,7 +103,7 @@ define iXLen @intrinsic_xvsetvl_e32m2(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e32m4(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e32m4 ; CHECK: vsetvli a0, a0, e32, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 2) ret iXLen %v } @@ -111,7 +111,7 @@ define iXLen @intrinsic_xvsetvl_e32m4(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e32m8(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e32m8 ; CHECK: vsetvli a0, a0, e32, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 2, iXLen 3) ret iXLen %v } @@ -119,7 +119,7 @@ define iXLen @intrinsic_xvsetvl_e32m8(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e64m1(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e64m1 ; CHECK: vsetvli a0, a0, e64, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 0) ret iXLen %v } @@ -127,7 +127,7 @@ define iXLen @intrinsic_xvsetvl_e64m1(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e64m2(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e64m2 ; CHECK: vsetvli a0, a0, e64, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 1) ret iXLen %v } @@ -135,7 +135,7 @@ define iXLen @intrinsic_xvsetvl_e64m2(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e64m4(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e64m4 ; CHECK: vsetvli a0, a0, e64, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 2) ret iXLen %v } @@ -143,6 +143,6 @@ define iXLen @intrinsic_xvsetvl_e64m4(iXLen %avl) { define iXLen @intrinsic_xvsetvl_e64m8(iXLen %avl) { ; CHECK-LABEL: intrinsic_xvsetvl_e64m8 ; CHECK: vsetvli a0, a0, e64, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvl.iXLen(iXLen %avl, iXLen 3, iXLen 3) ret iXLen %v } diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vsetvlmax.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vsetvlmax.ll index 4d2bbd3073e31..6962a9e26beeb 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vsetvlmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vsetvlmax.ll @@ -1,6 +1,6 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s ; https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/v0.7.1/rvv_intrinsic_funcs/01_configuration-setting_and_utility_functions.md @@ -16,15 +16,15 @@ ; ----------------------------------- ; In intrinsic, ediv is always 0 for ASM name `d1` -declare iXLen @llvm.riscv.xvsetvl.iXLen (iXLen %avl, iXLen %sew, iXLen %lmul); -declare iXLen @llvm.riscv.xvsetvlmax.iXLen( iXLen %sew, iXLen %lmul); +declare iXLen @llvm.riscv.th.vsetvl.iXLen (iXLen %avl, iXLen %sew, iXLen %lmul); +declare iXLen @llvm.riscv.th.vsetvlmax.iXLen( iXLen %sew, iXLen %lmul); define iXLen @intrinsic_xvsetvlmax_e8m1() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e8m1 ; CHECK: vsetvli a0, zero, e8, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 0, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 0, iXLen 0) ret iXLen %v } @@ -33,7 +33,7 @@ define iXLen @intrinsic_xvsetvlmax_e8m2() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e8m2 ; CHECK: vsetvli a0, zero, e8, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 0, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 0, iXLen 1) ret iXLen %v } @@ -42,7 +42,7 @@ define iXLen @intrinsic_xvsetvlmax_e8m4() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e8m4 ; CHECK: vsetvli a0, zero, e8, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 0, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 0, iXLen 2) ret iXLen %v } @@ -51,7 +51,7 @@ define iXLen @intrinsic_xvsetvlmax_e8m8() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e8m8 ; CHECK: vsetvli a0, zero, e8, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 0, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 0, iXLen 3) ret iXLen %v } @@ -60,7 +60,7 @@ define iXLen @intrinsic_xvsetvlmax_e16m1() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e16m1 ; CHECK: vsetvli a0, zero, e16, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 1, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 1, iXLen 0) ret iXLen %v } @@ -69,7 +69,7 @@ define iXLen @intrinsic_xvsetvlmax_e16m2() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e16m2 ; CHECK: vsetvli a0, zero, e16, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 1, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 1, iXLen 1) ret iXLen %v } @@ -78,7 +78,7 @@ define iXLen @intrinsic_xvsetvlmax_e16m4() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e16m4 ; CHECK: vsetvli a0, zero, e16, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 1, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 1, iXLen 2) ret iXLen %v } @@ -87,7 +87,7 @@ define iXLen @intrinsic_xvsetvlmax_e16m8() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e16m8 ; CHECK: vsetvli a0, zero, e16, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 1, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 1, iXLen 3) ret iXLen %v } @@ -96,7 +96,7 @@ define iXLen @intrinsic_xvsetvlmax_e32m1() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e32m1 ; CHECK: vsetvli a0, zero, e32, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 2, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 2, iXLen 0) ret iXLen %v } @@ -105,7 +105,7 @@ define iXLen @intrinsic_xvsetvlmax_e32m2() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e32m2 ; CHECK: vsetvli a0, zero, e32, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 2, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 2, iXLen 1) ret iXLen %v } @@ -114,7 +114,7 @@ define iXLen @intrinsic_xvsetvlmax_e32m4() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e32m4 ; CHECK: vsetvli a0, zero, e32, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 2, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 2, iXLen 2) ret iXLen %v } @@ -123,7 +123,7 @@ define iXLen @intrinsic_xvsetvlmax_e32m8() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e32m8 ; CHECK: vsetvli a0, zero, e32, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 2, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 2, iXLen 3) ret iXLen %v } @@ -132,7 +132,7 @@ define iXLen @intrinsic_xvsetvlmax_e64m1() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e64m1 ; CHECK: vsetvli a0, zero, e64, m1, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 3, iXLen 0) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 3, iXLen 0) ret iXLen %v } @@ -141,7 +141,7 @@ define iXLen @intrinsic_xvsetvlmax_e64m2() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e64m2 ; CHECK: vsetvli a0, zero, e64, m2, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 3, iXLen 1) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 3, iXLen 1) ret iXLen %v } @@ -150,7 +150,7 @@ define iXLen @intrinsic_xvsetvlmax_e64m4() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e64m4 ; CHECK: vsetvli a0, zero, e64, m4, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 3, iXLen 2) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 3, iXLen 2) ret iXLen %v } @@ -159,6 +159,6 @@ define iXLen @intrinsic_xvsetvlmax_e64m8() { entry: ; CHECK-LABEL: intrinsic_xvsetvlmax_e64m8 ; CHECK: vsetvli a0, zero, e64, m8, d1 - %v = call iXLen @llvm.riscv.xvsetvlmax.iXLen(iXLen 3, iXLen 3) + %v = call iXLen @llvm.riscv.th.vsetvlmax.iXLen(iXLen 3, iXLen 3) ret iXLen %v } diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vss.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vss.ll index 2e950813225f3..50e279a8fe7e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vss.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vss.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare void @llvm.riscv.xvssb.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vssb.nxv8i8.nxv8i8( , *, iXLen, @@ -12,12 +12,12 @@ declare void @llvm.riscv.xvssb.nxv8i8.nxv8i8( define void @intrinsic_xvssb_v_nxv8i8_nxv8i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssb_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vssb.nxv8i8.nxv8i8( undef, * %0, iXLen %1, @@ -26,7 +26,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.mask.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vssb.mask.nxv8i8.nxv8i8( , *, iXLen, @@ -36,12 +36,12 @@ declare void @llvm.riscv.xvssb.mask.nxv8i8.nxv8i8( define void @intrinsic_xvssb_mask_v_nxv8i8_nxv8i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssb_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.mask.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vssb.mask.nxv8i8.nxv8i8( %0, * %1, iXLen %2, @@ -51,7 +51,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vssb.nxv16i8.nxv16i8( , *, iXLen, @@ -60,12 +60,12 @@ declare void @llvm.riscv.xvssb.nxv16i8.nxv16i8( define void @intrinsic_xvssb_v_nxv16i8_nxv16i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssb_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vssb.nxv16i8.nxv16i8( undef, * %0, iXLen %1, @@ -74,7 +74,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.mask.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vssb.mask.nxv16i8.nxv16i8( , *, iXLen, @@ -84,12 +84,12 @@ declare void @llvm.riscv.xvssb.mask.nxv16i8.nxv16i8( define void @intrinsic_xvssb_mask_v_nxv16i8_nxv16i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssb_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.mask.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vssb.mask.nxv16i8.nxv16i8( %0, * %1, iXLen %2, @@ -99,7 +99,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vssb.nxv32i8.nxv32i8( , *, iXLen, @@ -108,12 +108,12 @@ declare void @llvm.riscv.xvssb.nxv32i8.nxv32i8( define void @intrinsic_xvssb_v_nxv32i8_nxv32i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssb_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vssb.nxv32i8.nxv32i8( undef, * %0, iXLen %1, @@ -122,7 +122,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.mask.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vssb.mask.nxv32i8.nxv32i8( , *, iXLen, @@ -132,12 +132,12 @@ declare void @llvm.riscv.xvssb.mask.nxv32i8.nxv32i8( define void @intrinsic_xvssb_mask_v_nxv32i8_nxv32i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssb_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.mask.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vssb.mask.nxv32i8.nxv32i8( %0, * %1, iXLen %2, @@ -147,7 +147,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vssb.nxv64i8.nxv64i8( , *, iXLen, @@ -156,12 +156,12 @@ declare void @llvm.riscv.xvssb.nxv64i8.nxv64i8( define void @intrinsic_xvssb_v_nxv64i8_nxv64i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssb_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vssb.nxv64i8.nxv64i8( undef, * %0, iXLen %1, @@ -170,7 +170,7 @@ entry: ret void } -declare void @llvm.riscv.xvssb.mask.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vssb.mask.nxv64i8.nxv64i8( , *, iXLen, @@ -180,12 +180,12 @@ declare void @llvm.riscv.xvssb.mask.nxv64i8.nxv64i8( define void @intrinsic_xvssb_mask_v_nxv64i8_nxv64i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssb_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vssb.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vssb.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssb.mask.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vssb.mask.nxv64i8.nxv64i8( %0, * %1, iXLen %2, @@ -195,7 +195,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vssh.nxv4i16.nxv4i16( , *, iXLen, @@ -204,12 +204,12 @@ declare void @llvm.riscv.xvssh.nxv4i16.nxv4i16( define void @intrinsic_xvssh_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssh_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vssh.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -218,7 +218,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.mask.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vssh.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -228,12 +228,12 @@ declare void @llvm.riscv.xvssh.mask.nxv4i16.nxv4i16( define void @intrinsic_xvssh_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssh_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.mask.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vssh.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -243,7 +243,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vssh.nxv8i16.nxv8i16( , *, iXLen, @@ -252,12 +252,12 @@ declare void @llvm.riscv.xvssh.nxv8i16.nxv8i16( define void @intrinsic_xvssh_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssh_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vssh.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -266,7 +266,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.mask.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vssh.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -276,12 +276,12 @@ declare void @llvm.riscv.xvssh.mask.nxv8i16.nxv8i16( define void @intrinsic_xvssh_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssh_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.mask.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vssh.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -291,7 +291,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vssh.nxv16i16.nxv16i16( , *, iXLen, @@ -300,12 +300,12 @@ declare void @llvm.riscv.xvssh.nxv16i16.nxv16i16( define void @intrinsic_xvssh_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssh_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vssh.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -314,7 +314,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.mask.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vssh.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -324,12 +324,12 @@ declare void @llvm.riscv.xvssh.mask.nxv16i16.nxv16i16( define void @intrinsic_xvssh_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssh_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.mask.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vssh.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -339,7 +339,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vssh.nxv32i16.nxv32i16( , *, iXLen, @@ -348,12 +348,12 @@ declare void @llvm.riscv.xvssh.nxv32i16.nxv32i16( define void @intrinsic_xvssh_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssh_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vssh.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -362,7 +362,7 @@ entry: ret void } -declare void @llvm.riscv.xvssh.mask.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vssh.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -372,12 +372,12 @@ declare void @llvm.riscv.xvssh.mask.nxv32i16.nxv32i16( define void @intrinsic_xvssh_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssh_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vssh.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vssh.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssh.mask.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vssh.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -387,7 +387,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vssw.nxv2i32.nxv2i32( , *, iXLen, @@ -396,12 +396,12 @@ declare void @llvm.riscv.xvssw.nxv2i32.nxv2i32( define void @intrinsic_xvssw_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssw_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vssw.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -410,7 +410,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.mask.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vssw.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -420,12 +420,12 @@ declare void @llvm.riscv.xvssw.mask.nxv2i32.nxv2i32( define void @intrinsic_xvssw_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssw_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.mask.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vssw.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -435,7 +435,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vssw.nxv4i32.nxv4i32( , *, iXLen, @@ -444,12 +444,12 @@ declare void @llvm.riscv.xvssw.nxv4i32.nxv4i32( define void @intrinsic_xvssw_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssw_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vssw.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -458,7 +458,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.mask.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vssw.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -468,12 +468,12 @@ declare void @llvm.riscv.xvssw.mask.nxv4i32.nxv4i32( define void @intrinsic_xvssw_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssw_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.mask.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vssw.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -483,7 +483,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vssw.nxv8i32.nxv8i32( , *, iXLen, @@ -492,12 +492,12 @@ declare void @llvm.riscv.xvssw.nxv8i32.nxv8i32( define void @intrinsic_xvssw_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssw_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vssw.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -506,7 +506,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.mask.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vssw.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -516,12 +516,12 @@ declare void @llvm.riscv.xvssw.mask.nxv8i32.nxv8i32( define void @intrinsic_xvssw_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssw_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.mask.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vssw.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -531,7 +531,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vssw.nxv16i32.nxv16i32( , *, iXLen, @@ -540,12 +540,12 @@ declare void @llvm.riscv.xvssw.nxv16i32.nxv16i32( define void @intrinsic_xvssw_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvssw_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vssw.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -554,7 +554,7 @@ entry: ret void } -declare void @llvm.riscv.xvssw.mask.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vssw.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -564,12 +564,12 @@ declare void @llvm.riscv.xvssw.mask.nxv16i32.nxv16i32( define void @intrinsic_xvssw_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvssw_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vssw.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vssw.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvssw.mask.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vssw.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -579,7 +579,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsse.nxv8i8.nxv8i8( , *, iXLen, @@ -588,12 +588,12 @@ declare void @llvm.riscv.xvsse.nxv8i8.nxv8i8( define void @intrinsic_xvsse_v_nxv8i8_nxv8i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsse.nxv8i8.nxv8i8( undef, * %0, iXLen %1, @@ -602,7 +602,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsse.mask.nxv8i8.nxv8i8( , *, iXLen, @@ -612,12 +612,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8i8.nxv8i8( define void @intrinsic_xvsse_mask_v_nxv8i8_nxv8i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsse.mask.nxv8i8.nxv8i8( %0, * %1, iXLen %2, @@ -627,7 +627,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsse.nxv16i8.nxv16i8( , *, iXLen, @@ -636,12 +636,12 @@ declare void @llvm.riscv.xvsse.nxv16i8.nxv16i8( define void @intrinsic_xvsse_v_nxv16i8_nxv16i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsse.nxv16i8.nxv16i8( undef, * %0, iXLen %1, @@ -650,7 +650,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsse.mask.nxv16i8.nxv16i8( , *, iXLen, @@ -660,12 +660,12 @@ declare void @llvm.riscv.xvsse.mask.nxv16i8.nxv16i8( define void @intrinsic_xvsse_mask_v_nxv16i8_nxv16i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsse.mask.nxv16i8.nxv16i8( %0, * %1, iXLen %2, @@ -675,7 +675,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsse.nxv32i8.nxv32i8( , *, iXLen, @@ -684,12 +684,12 @@ declare void @llvm.riscv.xvsse.nxv32i8.nxv32i8( define void @intrinsic_xvsse_v_nxv32i8_nxv32i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsse.nxv32i8.nxv32i8( undef, * %0, iXLen %1, @@ -698,7 +698,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsse.mask.nxv32i8.nxv32i8( , *, iXLen, @@ -708,12 +708,12 @@ declare void @llvm.riscv.xvsse.mask.nxv32i8.nxv32i8( define void @intrinsic_xvsse_mask_v_nxv32i8_nxv32i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsse.mask.nxv32i8.nxv32i8( %0, * %1, iXLen %2, @@ -723,7 +723,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsse.nxv64i8.nxv64i8( , *, iXLen, @@ -732,12 +732,12 @@ declare void @llvm.riscv.xvsse.nxv64i8.nxv64i8( define void @intrinsic_xvsse_v_nxv64i8_nxv64i8(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsse.nxv64i8.nxv64i8( undef, * %0, iXLen %1, @@ -746,7 +746,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsse.mask.nxv64i8.nxv64i8( , *, iXLen, @@ -756,12 +756,12 @@ declare void @llvm.riscv.xvsse.mask.nxv64i8.nxv64i8( define void @intrinsic_xvsse_mask_v_nxv64i8_nxv64i8( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e8, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e8, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsse.mask.nxv64i8.nxv64i8( %0, * %1, iXLen %2, @@ -771,7 +771,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsse.nxv4i16.nxv4i16( , *, iXLen, @@ -780,12 +780,12 @@ declare void @llvm.riscv.xvsse.nxv4i16.nxv4i16( define void @intrinsic_xvsse_v_nxv4i16_nxv4i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsse.nxv4i16.nxv4i16( undef, * %0, iXLen %1, @@ -794,7 +794,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsse.mask.nxv4i16.nxv4i16( , *, iXLen, @@ -804,12 +804,12 @@ declare void @llvm.riscv.xvsse.mask.nxv4i16.nxv4i16( define void @intrinsic_xvsse_mask_v_nxv4i16_nxv4i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsse.mask.nxv4i16.nxv4i16( %0, * %1, iXLen %2, @@ -819,7 +819,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv4f16.nxv4f16( +declare void @llvm.riscv.th.vsse.nxv4f16.nxv4f16( , *, iXLen, @@ -828,12 +828,12 @@ declare void @llvm.riscv.xvsse.nxv4f16.nxv4f16( define void @intrinsic_xvsse_v_nxv4f16_nxv4f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv4f16.nxv4f16( + call void @llvm.riscv.th.vsse.nxv4f16.nxv4f16( undef, * %0, iXLen %1, @@ -842,7 +842,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv4f16.nxv4f16( +declare void @llvm.riscv.th.vsse.mask.nxv4f16.nxv4f16( , *, iXLen, @@ -852,12 +852,12 @@ declare void @llvm.riscv.xvsse.mask.nxv4f16.nxv4f16( define void @intrinsic_xvsse_mask_v_nxv4f16_nxv4f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv4f16.nxv4f16( + call void @llvm.riscv.th.vsse.mask.nxv4f16.nxv4f16( %0, * %1, iXLen %2, @@ -867,7 +867,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsse.nxv8i16.nxv8i16( , *, iXLen, @@ -876,12 +876,12 @@ declare void @llvm.riscv.xvsse.nxv8i16.nxv8i16( define void @intrinsic_xvsse_v_nxv8i16_nxv8i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsse.nxv8i16.nxv8i16( undef, * %0, iXLen %1, @@ -890,7 +890,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsse.mask.nxv8i16.nxv8i16( , *, iXLen, @@ -900,12 +900,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8i16.nxv8i16( define void @intrinsic_xvsse_mask_v_nxv8i16_nxv8i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsse.mask.nxv8i16.nxv8i16( %0, * %1, iXLen %2, @@ -915,7 +915,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8f16.nxv8f16( +declare void @llvm.riscv.th.vsse.nxv8f16.nxv8f16( , *, iXLen, @@ -924,12 +924,12 @@ declare void @llvm.riscv.xvsse.nxv8f16.nxv8f16( define void @intrinsic_xvsse_v_nxv8f16_nxv8f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8f16.nxv8f16( + call void @llvm.riscv.th.vsse.nxv8f16.nxv8f16( undef, * %0, iXLen %1, @@ -938,7 +938,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8f16.nxv8f16( +declare void @llvm.riscv.th.vsse.mask.nxv8f16.nxv8f16( , *, iXLen, @@ -948,12 +948,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8f16.nxv8f16( define void @intrinsic_xvsse_mask_v_nxv8f16_nxv8f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8f16.nxv8f16( + call void @llvm.riscv.th.vsse.mask.nxv8f16.nxv8f16( %0, * %1, iXLen %2, @@ -963,7 +963,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsse.nxv16i16.nxv16i16( , *, iXLen, @@ -972,12 +972,12 @@ declare void @llvm.riscv.xvsse.nxv16i16.nxv16i16( define void @intrinsic_xvsse_v_nxv16i16_nxv16i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsse.nxv16i16.nxv16i16( undef, * %0, iXLen %1, @@ -986,7 +986,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsse.mask.nxv16i16.nxv16i16( , *, iXLen, @@ -996,12 +996,12 @@ declare void @llvm.riscv.xvsse.mask.nxv16i16.nxv16i16( define void @intrinsic_xvsse_mask_v_nxv16i16_nxv16i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsse.mask.nxv16i16.nxv16i16( %0, * %1, iXLen %2, @@ -1011,7 +1011,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv16f16.nxv16f16( +declare void @llvm.riscv.th.vsse.nxv16f16.nxv16f16( , *, iXLen, @@ -1020,12 +1020,12 @@ declare void @llvm.riscv.xvsse.nxv16f16.nxv16f16( define void @intrinsic_xvsse_v_nxv16f16_nxv16f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv16f16.nxv16f16( + call void @llvm.riscv.th.vsse.nxv16f16.nxv16f16( undef, * %0, iXLen %1, @@ -1034,7 +1034,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv16f16.nxv16f16( +declare void @llvm.riscv.th.vsse.mask.nxv16f16.nxv16f16( , *, iXLen, @@ -1044,12 +1044,12 @@ declare void @llvm.riscv.xvsse.mask.nxv16f16.nxv16f16( define void @intrinsic_xvsse_mask_v_nxv16f16_nxv16f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv16f16.nxv16f16( + call void @llvm.riscv.th.vsse.mask.nxv16f16.nxv16f16( %0, * %1, iXLen %2, @@ -1059,7 +1059,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsse.nxv32i16.nxv32i16( , *, iXLen, @@ -1068,12 +1068,12 @@ declare void @llvm.riscv.xvsse.nxv32i16.nxv32i16( define void @intrinsic_xvsse_v_nxv32i16_nxv32i16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsse.nxv32i16.nxv32i16( undef, * %0, iXLen %1, @@ -1082,7 +1082,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsse.mask.nxv32i16.nxv32i16( , *, iXLen, @@ -1092,12 +1092,12 @@ declare void @llvm.riscv.xvsse.mask.nxv32i16.nxv32i16( define void @intrinsic_xvsse_mask_v_nxv32i16_nxv32i16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsse.mask.nxv32i16.nxv32i16( %0, * %1, iXLen %2, @@ -1107,7 +1107,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv32f16.nxv32f16( +declare void @llvm.riscv.th.vsse.nxv32f16.nxv32f16( , *, iXLen, @@ -1116,12 +1116,12 @@ declare void @llvm.riscv.xvsse.nxv32f16.nxv32f16( define void @intrinsic_xvsse_v_nxv32f16_nxv32f16(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv32f16.nxv32f16( + call void @llvm.riscv.th.vsse.nxv32f16.nxv32f16( undef, * %0, iXLen %1, @@ -1130,7 +1130,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv32f16.nxv32f16( +declare void @llvm.riscv.th.vsse.mask.nxv32f16.nxv32f16( , *, iXLen, @@ -1140,12 +1140,12 @@ declare void @llvm.riscv.xvsse.mask.nxv32f16.nxv32f16( define void @intrinsic_xvsse_mask_v_nxv32f16_nxv32f16( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e16, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e16, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv32f16.nxv32f16( + call void @llvm.riscv.th.vsse.mask.nxv32f16.nxv32f16( %0, * %1, iXLen %2, @@ -1155,7 +1155,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsse.nxv2i32.nxv2i32( , *, iXLen, @@ -1164,12 +1164,12 @@ declare void @llvm.riscv.xvsse.nxv2i32.nxv2i32( define void @intrinsic_xvsse_v_nxv2i32_nxv2i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsse.nxv2i32.nxv2i32( undef, * %0, iXLen %1, @@ -1178,7 +1178,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsse.mask.nxv2i32.nxv2i32( , *, iXLen, @@ -1188,12 +1188,12 @@ declare void @llvm.riscv.xvsse.mask.nxv2i32.nxv2i32( define void @intrinsic_xvsse_mask_v_nxv2i32_nxv2i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsse.mask.nxv2i32.nxv2i32( %0, * %1, iXLen %2, @@ -1203,7 +1203,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv2f32.nxv2f32( +declare void @llvm.riscv.th.vsse.nxv2f32.nxv2f32( , *, iXLen, @@ -1212,12 +1212,12 @@ declare void @llvm.riscv.xvsse.nxv2f32.nxv2f32( define void @intrinsic_xvsse_v_nxv2f32_nxv2f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv2f32.nxv2f32( + call void @llvm.riscv.th.vsse.nxv2f32.nxv2f32( undef, * %0, iXLen %1, @@ -1226,7 +1226,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv2f32.nxv2f32( +declare void @llvm.riscv.th.vsse.mask.nxv2f32.nxv2f32( , *, iXLen, @@ -1236,12 +1236,12 @@ declare void @llvm.riscv.xvsse.mask.nxv2f32.nxv2f32( define void @intrinsic_xvsse_mask_v_nxv2f32_nxv2f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv2f32.nxv2f32( + call void @llvm.riscv.th.vsse.mask.nxv2f32.nxv2f32( %0, * %1, iXLen %2, @@ -1251,7 +1251,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsse.nxv4i32.nxv4i32( , *, iXLen, @@ -1260,12 +1260,12 @@ declare void @llvm.riscv.xvsse.nxv4i32.nxv4i32( define void @intrinsic_xvsse_v_nxv4i32_nxv4i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsse.nxv4i32.nxv4i32( undef, * %0, iXLen %1, @@ -1274,7 +1274,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsse.mask.nxv4i32.nxv4i32( , *, iXLen, @@ -1284,12 +1284,12 @@ declare void @llvm.riscv.xvsse.mask.nxv4i32.nxv4i32( define void @intrinsic_xvsse_mask_v_nxv4i32_nxv4i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsse.mask.nxv4i32.nxv4i32( %0, * %1, iXLen %2, @@ -1299,7 +1299,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv4f32.nxv4f32( +declare void @llvm.riscv.th.vsse.nxv4f32.nxv4f32( , *, iXLen, @@ -1308,12 +1308,12 @@ declare void @llvm.riscv.xvsse.nxv4f32.nxv4f32( define void @intrinsic_xvsse_v_nxv4f32_nxv4f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv4f32.nxv4f32( + call void @llvm.riscv.th.vsse.nxv4f32.nxv4f32( undef, * %0, iXLen %1, @@ -1322,7 +1322,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv4f32.nxv4f32( +declare void @llvm.riscv.th.vsse.mask.nxv4f32.nxv4f32( , *, iXLen, @@ -1332,12 +1332,12 @@ declare void @llvm.riscv.xvsse.mask.nxv4f32.nxv4f32( define void @intrinsic_xvsse_mask_v_nxv4f32_nxv4f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv4f32.nxv4f32( + call void @llvm.riscv.th.vsse.mask.nxv4f32.nxv4f32( %0, * %1, iXLen %2, @@ -1347,7 +1347,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsse.nxv8i32.nxv8i32( , *, iXLen, @@ -1356,12 +1356,12 @@ declare void @llvm.riscv.xvsse.nxv8i32.nxv8i32( define void @intrinsic_xvsse_v_nxv8i32_nxv8i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsse.nxv8i32.nxv8i32( undef, * %0, iXLen %1, @@ -1370,7 +1370,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsse.mask.nxv8i32.nxv8i32( , *, iXLen, @@ -1380,12 +1380,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8i32.nxv8i32( define void @intrinsic_xvsse_mask_v_nxv8i32_nxv8i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsse.mask.nxv8i32.nxv8i32( %0, * %1, iXLen %2, @@ -1395,7 +1395,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8f32.nxv8f32( +declare void @llvm.riscv.th.vsse.nxv8f32.nxv8f32( , *, iXLen, @@ -1404,12 +1404,12 @@ declare void @llvm.riscv.xvsse.nxv8f32.nxv8f32( define void @intrinsic_xvsse_v_nxv8f32_nxv8f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8f32.nxv8f32( + call void @llvm.riscv.th.vsse.nxv8f32.nxv8f32( undef, * %0, iXLen %1, @@ -1418,7 +1418,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8f32.nxv8f32( +declare void @llvm.riscv.th.vsse.mask.nxv8f32.nxv8f32( , *, iXLen, @@ -1428,12 +1428,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8f32.nxv8f32( define void @intrinsic_xvsse_mask_v_nxv8f32_nxv8f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8f32.nxv8f32( + call void @llvm.riscv.th.vsse.mask.nxv8f32.nxv8f32( %0, * %1, iXLen %2, @@ -1443,7 +1443,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsse.nxv16i32.nxv16i32( , *, iXLen, @@ -1452,12 +1452,12 @@ declare void @llvm.riscv.xvsse.nxv16i32.nxv16i32( define void @intrinsic_xvsse_v_nxv16i32_nxv16i32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsse.nxv16i32.nxv16i32( undef, * %0, iXLen %1, @@ -1466,7 +1466,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsse.mask.nxv16i32.nxv16i32( , *, iXLen, @@ -1476,12 +1476,12 @@ declare void @llvm.riscv.xvsse.mask.nxv16i32.nxv16i32( define void @intrinsic_xvsse_mask_v_nxv16i32_nxv16i32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsse.mask.nxv16i32.nxv16i32( %0, * %1, iXLen %2, @@ -1491,7 +1491,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv16f32.nxv16f32( +declare void @llvm.riscv.th.vsse.nxv16f32.nxv16f32( , *, iXLen, @@ -1500,12 +1500,12 @@ declare void @llvm.riscv.xvsse.nxv16f32.nxv16f32( define void @intrinsic_xvsse_v_nxv16f32_nxv16f32(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv16f32.nxv16f32( + call void @llvm.riscv.th.vsse.nxv16f32.nxv16f32( undef, * %0, iXLen %1, @@ -1514,7 +1514,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv16f32.nxv16f32( +declare void @llvm.riscv.th.vsse.mask.nxv16f32.nxv16f32( , *, iXLen, @@ -1524,12 +1524,12 @@ declare void @llvm.riscv.xvsse.mask.nxv16f32.nxv16f32( define void @intrinsic_xvsse_mask_v_nxv16f32_nxv16f32( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e32, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e32, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv16f32.nxv16f32( + call void @llvm.riscv.th.vsse.mask.nxv16f32.nxv16f32( %0, * %1, iXLen %2, @@ -1539,7 +1539,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv1i64.nxv1i64( +declare void @llvm.riscv.th.vsse.nxv1i64.nxv1i64( , *, iXLen, @@ -1548,12 +1548,12 @@ declare void @llvm.riscv.xvsse.nxv1i64.nxv1i64( define void @intrinsic_xvsse_v_nxv1i64_nxv1i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv1i64.nxv1i64( + call void @llvm.riscv.th.vsse.nxv1i64.nxv1i64( undef, * %0, iXLen %1, @@ -1562,7 +1562,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv1i64.nxv1i64( +declare void @llvm.riscv.th.vsse.mask.nxv1i64.nxv1i64( , *, iXLen, @@ -1572,12 +1572,12 @@ declare void @llvm.riscv.xvsse.mask.nxv1i64.nxv1i64( define void @intrinsic_xvsse_mask_v_nxv1i64_nxv1i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv1i64.nxv1i64( + call void @llvm.riscv.th.vsse.mask.nxv1i64.nxv1i64( %0, * %1, iXLen %2, @@ -1587,7 +1587,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv1f64.nxv1f64( +declare void @llvm.riscv.th.vsse.nxv1f64.nxv1f64( , *, iXLen, @@ -1596,12 +1596,12 @@ declare void @llvm.riscv.xvsse.nxv1f64.nxv1f64( define void @intrinsic_xvsse_v_nxv1f64_nxv1f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv1f64.nxv1f64( + call void @llvm.riscv.th.vsse.nxv1f64.nxv1f64( undef, * %0, iXLen %1, @@ -1610,7 +1610,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv1f64.nxv1f64( +declare void @llvm.riscv.th.vsse.mask.nxv1f64.nxv1f64( , *, iXLen, @@ -1620,12 +1620,12 @@ declare void @llvm.riscv.xvsse.mask.nxv1f64.nxv1f64( define void @intrinsic_xvsse_mask_v_nxv1f64_nxv1f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m1, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m1, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv1f64.nxv1f64( + call void @llvm.riscv.th.vsse.mask.nxv1f64.nxv1f64( %0, * %1, iXLen %2, @@ -1635,7 +1635,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv2i64.nxv2i64( +declare void @llvm.riscv.th.vsse.nxv2i64.nxv2i64( , *, iXLen, @@ -1644,12 +1644,12 @@ declare void @llvm.riscv.xvsse.nxv2i64.nxv2i64( define void @intrinsic_xvsse_v_nxv2i64_nxv2i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv2i64.nxv2i64( + call void @llvm.riscv.th.vsse.nxv2i64.nxv2i64( undef, * %0, iXLen %1, @@ -1658,7 +1658,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv2i64.nxv2i64( +declare void @llvm.riscv.th.vsse.mask.nxv2i64.nxv2i64( , *, iXLen, @@ -1668,12 +1668,12 @@ declare void @llvm.riscv.xvsse.mask.nxv2i64.nxv2i64( define void @intrinsic_xvsse_mask_v_nxv2i64_nxv2i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv2i64.nxv2i64( + call void @llvm.riscv.th.vsse.mask.nxv2i64.nxv2i64( %0, * %1, iXLen %2, @@ -1683,7 +1683,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv2f64.nxv2f64( +declare void @llvm.riscv.th.vsse.nxv2f64.nxv2f64( , *, iXLen, @@ -1692,12 +1692,12 @@ declare void @llvm.riscv.xvsse.nxv2f64.nxv2f64( define void @intrinsic_xvsse_v_nxv2f64_nxv2f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv2f64.nxv2f64( + call void @llvm.riscv.th.vsse.nxv2f64.nxv2f64( undef, * %0, iXLen %1, @@ -1706,7 +1706,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv2f64.nxv2f64( +declare void @llvm.riscv.th.vsse.mask.nxv2f64.nxv2f64( , *, iXLen, @@ -1716,12 +1716,12 @@ declare void @llvm.riscv.xvsse.mask.nxv2f64.nxv2f64( define void @intrinsic_xvsse_mask_v_nxv2f64_nxv2f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m2, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m2, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv2f64.nxv2f64( + call void @llvm.riscv.th.vsse.mask.nxv2f64.nxv2f64( %0, * %1, iXLen %2, @@ -1731,7 +1731,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv4i64.nxv4i64( +declare void @llvm.riscv.th.vsse.nxv4i64.nxv4i64( , *, iXLen, @@ -1740,12 +1740,12 @@ declare void @llvm.riscv.xvsse.nxv4i64.nxv4i64( define void @intrinsic_xvsse_v_nxv4i64_nxv4i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv4i64.nxv4i64( + call void @llvm.riscv.th.vsse.nxv4i64.nxv4i64( undef, * %0, iXLen %1, @@ -1754,7 +1754,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv4i64.nxv4i64( +declare void @llvm.riscv.th.vsse.mask.nxv4i64.nxv4i64( , *, iXLen, @@ -1764,12 +1764,12 @@ declare void @llvm.riscv.xvsse.mask.nxv4i64.nxv4i64( define void @intrinsic_xvsse_mask_v_nxv4i64_nxv4i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv4i64.nxv4i64( + call void @llvm.riscv.th.vsse.mask.nxv4i64.nxv4i64( %0, * %1, iXLen %2, @@ -1779,7 +1779,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv4f64.nxv4f64( +declare void @llvm.riscv.th.vsse.nxv4f64.nxv4f64( , *, iXLen, @@ -1788,12 +1788,12 @@ declare void @llvm.riscv.xvsse.nxv4f64.nxv4f64( define void @intrinsic_xvsse_v_nxv4f64_nxv4f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv4f64.nxv4f64( + call void @llvm.riscv.th.vsse.nxv4f64.nxv4f64( undef, * %0, iXLen %1, @@ -1802,7 +1802,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv4f64.nxv4f64( +declare void @llvm.riscv.th.vsse.mask.nxv4f64.nxv4f64( , *, iXLen, @@ -1812,12 +1812,12 @@ declare void @llvm.riscv.xvsse.mask.nxv4f64.nxv4f64( define void @intrinsic_xvsse_mask_v_nxv4f64_nxv4f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m4, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m4, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv4f64.nxv4f64( + call void @llvm.riscv.th.vsse.mask.nxv4f64.nxv4f64( %0, * %1, iXLen %2, @@ -1827,7 +1827,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8i64.nxv8i64( +declare void @llvm.riscv.th.vsse.nxv8i64.nxv8i64( , *, iXLen, @@ -1836,12 +1836,12 @@ declare void @llvm.riscv.xvsse.nxv8i64.nxv8i64( define void @intrinsic_xvsse_v_nxv8i64_nxv8i64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8i64.nxv8i64( + call void @llvm.riscv.th.vsse.nxv8i64.nxv8i64( undef, * %0, iXLen %1, @@ -1850,7 +1850,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8i64.nxv8i64( +declare void @llvm.riscv.th.vsse.mask.nxv8i64.nxv8i64( , *, iXLen, @@ -1860,12 +1860,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8i64.nxv8i64( define void @intrinsic_xvsse_mask_v_nxv8i64_nxv8i64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8i64.nxv8i64( + call void @llvm.riscv.th.vsse.mask.nxv8i64.nxv8i64( %0, * %1, iXLen %2, @@ -1875,7 +1875,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.nxv8f64.nxv8f64( +declare void @llvm.riscv.th.vsse.nxv8f64.nxv8f64( , *, iXLen, @@ -1884,12 +1884,12 @@ declare void @llvm.riscv.xvsse.nxv8f64.nxv8f64( define void @intrinsic_xvsse_v_nxv8f64_nxv8f64(* %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsse_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1 +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.nxv8f64.nxv8f64( + call void @llvm.riscv.th.vsse.nxv8f64.nxv8f64( undef, * %0, iXLen %1, @@ -1898,7 +1898,7 @@ entry: ret void } -declare void @llvm.riscv.xvsse.mask.nxv8f64.nxv8f64( +declare void @llvm.riscv.th.vsse.mask.nxv8f64.nxv8f64( , *, iXLen, @@ -1908,12 +1908,12 @@ declare void @llvm.riscv.xvsse.mask.nxv8f64.nxv8f64( define void @intrinsic_xvsse_mask_v_nxv8f64_nxv8f64( %0, * %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsse_mask_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a2, e64, m8, d1 -; CHECK-NEXT: vsse.v v8, (a0), a1, v0.t +; CHECK-NEXT: th.vsetvli zero, a2, e64, m8, d1 +; CHECK-NEXT: th.vsse.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsse.mask.nxv8f64.nxv8f64( + call void @llvm.riscv.th.vsse.mask.nxv8f64.nxv8f64( %0, * %1, iXLen %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vsx-64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vsx-64.ll index 39cd440a44a94..2e23ff3934031 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vsx-64.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vsx-64.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=riscv64 -mattr=+xtheadv -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector -verify-machineinstrs < %s | \ ; RUN: FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare void @llvm.riscv.xvsxe.nxv1i64.nxv1i64( +declare void @llvm.riscv.th.vsxe.nxv1i64.nxv1i64( , *, , @@ -10,12 +10,12 @@ declare void @llvm.riscv.xvsxe.nxv1i64.nxv1i64( define void @intrinsic_xvsxe_v_nxv1i64_nxv1i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv1i64.nxv1i64( + call void @llvm.riscv.th.vsxe.nxv1i64.nxv1i64( undef, * %0, %1, @@ -24,7 +24,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv1i64.nxv1i64( +declare void @llvm.riscv.th.vsxe.mask.nxv1i64.nxv1i64( , *, , @@ -34,12 +34,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv1i64.nxv1i64( define void @intrinsic_xvsxe_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv1i64_nxv1i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv1i64.nxv1i64( + call void @llvm.riscv.th.vsxe.mask.nxv1i64.nxv1i64( %0, * %1, %2, @@ -49,7 +49,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv1f64.nxv1f64( +declare void @llvm.riscv.th.vsxe.nxv1f64.nxv1f64( , *, , @@ -58,12 +58,12 @@ declare void @llvm.riscv.xvsxe.nxv1f64.nxv1f64( define void @intrinsic_xvsxe_v_nxv1f64_nxv1f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv1f64.nxv1f64( + call void @llvm.riscv.th.vsxe.nxv1f64.nxv1f64( undef, * %0, %1, @@ -72,7 +72,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv1f64.nxv1f64( +declare void @llvm.riscv.th.vsxe.mask.nxv1f64.nxv1f64( , *, , @@ -82,12 +82,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv1f64.nxv1f64( define void @intrinsic_xvsxe_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv1f64_nxv1f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv1f64.nxv1f64( + call void @llvm.riscv.th.vsxe.mask.nxv1f64.nxv1f64( %0, * %1, %2, @@ -97,7 +97,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv2i64.nxv2i64( +declare void @llvm.riscv.th.vsxe.nxv2i64.nxv2i64( , *, , @@ -106,12 +106,12 @@ declare void @llvm.riscv.xvsxe.nxv2i64.nxv2i64( define void @intrinsic_xvsxe_v_nxv2i64_nxv2i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv2i64.nxv2i64( + call void @llvm.riscv.th.vsxe.nxv2i64.nxv2i64( undef, * %0, %1, @@ -120,7 +120,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv2i64.nxv2i64( +declare void @llvm.riscv.th.vsxe.mask.nxv2i64.nxv2i64( , *, , @@ -130,12 +130,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv2i64.nxv2i64( define void @intrinsic_xvsxe_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv2i64_nxv2i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv2i64.nxv2i64( + call void @llvm.riscv.th.vsxe.mask.nxv2i64.nxv2i64( %0, * %1, %2, @@ -145,7 +145,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv2f64.nxv2f64( +declare void @llvm.riscv.th.vsxe.nxv2f64.nxv2f64( , *, , @@ -154,12 +154,12 @@ declare void @llvm.riscv.xvsxe.nxv2f64.nxv2f64( define void @intrinsic_xvsxe_v_nxv2f64_nxv2f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv2f64.nxv2f64( + call void @llvm.riscv.th.vsxe.nxv2f64.nxv2f64( undef, * %0, %1, @@ -168,7 +168,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv2f64.nxv2f64( +declare void @llvm.riscv.th.vsxe.mask.nxv2f64.nxv2f64( , *, , @@ -178,12 +178,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv2f64.nxv2f64( define void @intrinsic_xvsxe_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv2f64_nxv2f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv2f64.nxv2f64( + call void @llvm.riscv.th.vsxe.mask.nxv2f64.nxv2f64( %0, * %1, %2, @@ -193,7 +193,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv4i64.nxv4i64( +declare void @llvm.riscv.th.vsxe.nxv4i64.nxv4i64( , *, , @@ -202,12 +202,12 @@ declare void @llvm.riscv.xvsxe.nxv4i64.nxv4i64( define void @intrinsic_xvsxe_v_nxv4i64_nxv4i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv4i64.nxv4i64( + call void @llvm.riscv.th.vsxe.nxv4i64.nxv4i64( undef, * %0, %1, @@ -216,7 +216,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv4i64.nxv4i64( +declare void @llvm.riscv.th.vsxe.mask.nxv4i64.nxv4i64( , *, , @@ -226,12 +226,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv4i64.nxv4i64( define void @intrinsic_xvsxe_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv4i64_nxv4i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv4i64.nxv4i64( + call void @llvm.riscv.th.vsxe.mask.nxv4i64.nxv4i64( %0, * %1, %2, @@ -241,7 +241,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv4f64.nxv4f64( +declare void @llvm.riscv.th.vsxe.nxv4f64.nxv4f64( , *, , @@ -250,12 +250,12 @@ declare void @llvm.riscv.xvsxe.nxv4f64.nxv4f64( define void @intrinsic_xvsxe_v_nxv4f64_nxv4f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv4f64.nxv4f64( + call void @llvm.riscv.th.vsxe.nxv4f64.nxv4f64( undef, * %0, %1, @@ -264,7 +264,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv4f64.nxv4f64( +declare void @llvm.riscv.th.vsxe.mask.nxv4f64.nxv4f64( , *, , @@ -274,12 +274,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv4f64.nxv4f64( define void @intrinsic_xvsxe_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv4f64_nxv4f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv4f64.nxv4f64( + call void @llvm.riscv.th.vsxe.mask.nxv4f64.nxv4f64( %0, * %1, %2, @@ -289,7 +289,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8i64.nxv8i64( +declare void @llvm.riscv.th.vsxe.nxv8i64.nxv8i64( , *, , @@ -298,12 +298,12 @@ declare void @llvm.riscv.xvsxe.nxv8i64.nxv8i64( define void @intrinsic_xvsxe_v_nxv8i64_nxv8i64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8i64.nxv8i64( + call void @llvm.riscv.th.vsxe.nxv8i64.nxv8i64( undef, * %0, %1, @@ -312,7 +312,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8i64.nxv8i64( +declare void @llvm.riscv.th.vsxe.mask.nxv8i64.nxv8i64( , *, , @@ -322,12 +322,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8i64.nxv8i64( define void @intrinsic_xvsxe_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8i64_nxv8i64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8i64.nxv8i64( + call void @llvm.riscv.th.vsxe.mask.nxv8i64.nxv8i64( %0, * %1, %2, @@ -337,7 +337,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8f64.nxv8f64( +declare void @llvm.riscv.th.vsxe.nxv8f64.nxv8f64( , *, , @@ -346,12 +346,12 @@ declare void @llvm.riscv.xvsxe.nxv8f64.nxv8f64( define void @intrinsic_xvsxe_v_nxv8f64_nxv8f64(* %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8f64.nxv8f64( + call void @llvm.riscv.th.vsxe.nxv8f64.nxv8f64( undef, * %0, %1, @@ -360,7 +360,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8f64.nxv8f64( +declare void @llvm.riscv.th.vsxe.mask.nxv8f64.nxv8f64( , *, , @@ -370,12 +370,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8f64.nxv8f64( define void @intrinsic_xvsxe_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8f64_nxv8f64 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8f64.nxv8f64( + call void @llvm.riscv.th.vsxe.mask.nxv8f64.nxv8f64( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vsx.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vsx.ll index 85c231f6443ba..307716b10a1e2 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/vsx.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vsx.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare void @llvm.riscv.xvsxb.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsxb.nxv8i8.nxv8i8( , *, , @@ -12,12 +12,12 @@ declare void @llvm.riscv.xvsxb.nxv8i8.nxv8i8( define void @intrinsic_xvsxb_v_nxv8i8_nxv8i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsxb.nxv8i8.nxv8i8( undef, * %0, %1, @@ -26,7 +26,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.mask.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsxb.mask.nxv8i8.nxv8i8( , *, , @@ -36,12 +36,12 @@ declare void @llvm.riscv.xvsxb.mask.nxv8i8.nxv8i8( define void @intrinsic_xvsxb_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.mask.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsxb.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -51,7 +51,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsxb.nxv16i8.nxv16i8( , *, , @@ -60,12 +60,12 @@ declare void @llvm.riscv.xvsxb.nxv16i8.nxv16i8( define void @intrinsic_xvsxb_v_nxv16i8_nxv16i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsxb.nxv16i8.nxv16i8( undef, * %0, %1, @@ -74,7 +74,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.mask.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsxb.mask.nxv16i8.nxv16i8( , *, , @@ -84,12 +84,12 @@ declare void @llvm.riscv.xvsxb.mask.nxv16i8.nxv16i8( define void @intrinsic_xvsxb_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.mask.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsxb.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -99,7 +99,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsxb.nxv32i8.nxv32i8( , *, , @@ -108,12 +108,12 @@ declare void @llvm.riscv.xvsxb.nxv32i8.nxv32i8( define void @intrinsic_xvsxb_v_nxv32i8_nxv32i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsxb.nxv32i8.nxv32i8( undef, * %0, %1, @@ -122,7 +122,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.mask.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsxb.mask.nxv32i8.nxv32i8( , *, , @@ -132,12 +132,12 @@ declare void @llvm.riscv.xvsxb.mask.nxv32i8.nxv32i8( define void @intrinsic_xvsxb_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.mask.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsxb.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -147,7 +147,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsxb.nxv64i8.nxv64i8( , *, , @@ -156,12 +156,12 @@ declare void @llvm.riscv.xvsxb.nxv64i8.nxv64i8( define void @intrinsic_xvsxb_v_nxv64i8_nxv64i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsxb.nxv64i8.nxv64i8( undef, * %0, %1, @@ -170,7 +170,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxb.mask.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsxb.mask.nxv64i8.nxv64i8( , *, , @@ -180,12 +180,12 @@ declare void @llvm.riscv.xvsxb.mask.nxv64i8.nxv64i8( define void @intrinsic_xvsxb_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxb_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vsxb.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vsxb.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxb.mask.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsxb.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -195,7 +195,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsxh.nxv4i16.nxv4i16( , *, , @@ -204,12 +204,12 @@ declare void @llvm.riscv.xvsxh.nxv4i16.nxv4i16( define void @intrinsic_xvsxh_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsxh.nxv4i16.nxv4i16( undef, * %0, %1, @@ -218,7 +218,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.mask.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsxh.mask.nxv4i16.nxv4i16( , *, , @@ -228,12 +228,12 @@ declare void @llvm.riscv.xvsxh.mask.nxv4i16.nxv4i16( define void @intrinsic_xvsxh_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.mask.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsxh.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -243,7 +243,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsxh.nxv8i16.nxv8i16( , *, , @@ -252,12 +252,12 @@ declare void @llvm.riscv.xvsxh.nxv8i16.nxv8i16( define void @intrinsic_xvsxh_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsxh.nxv8i16.nxv8i16( undef, * %0, %1, @@ -266,7 +266,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.mask.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsxh.mask.nxv8i16.nxv8i16( , *, , @@ -276,12 +276,12 @@ declare void @llvm.riscv.xvsxh.mask.nxv8i16.nxv8i16( define void @intrinsic_xvsxh_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.mask.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsxh.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -291,7 +291,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsxh.nxv16i16.nxv16i16( , *, , @@ -300,12 +300,12 @@ declare void @llvm.riscv.xvsxh.nxv16i16.nxv16i16( define void @intrinsic_xvsxh_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsxh.nxv16i16.nxv16i16( undef, * %0, %1, @@ -314,7 +314,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.mask.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsxh.mask.nxv16i16.nxv16i16( , *, , @@ -324,12 +324,12 @@ declare void @llvm.riscv.xvsxh.mask.nxv16i16.nxv16i16( define void @intrinsic_xvsxh_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.mask.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsxh.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -339,7 +339,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsxh.nxv32i16.nxv32i16( , *, , @@ -348,12 +348,12 @@ declare void @llvm.riscv.xvsxh.nxv32i16.nxv32i16( define void @intrinsic_xvsxh_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsxh.nxv32i16.nxv32i16( undef, * %0, %1, @@ -362,7 +362,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxh.mask.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsxh.mask.nxv32i16.nxv32i16( , *, , @@ -372,12 +372,12 @@ declare void @llvm.riscv.xvsxh.mask.nxv32i16.nxv32i16( define void @intrinsic_xvsxh_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxh_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsxh.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsxh.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxh.mask.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsxh.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -387,7 +387,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsxw.nxv2i32.nxv2i32( , *, , @@ -396,12 +396,12 @@ declare void @llvm.riscv.xvsxw.nxv2i32.nxv2i32( define void @intrinsic_xvsxw_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsxw.nxv2i32.nxv2i32( undef, * %0, %1, @@ -410,7 +410,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.mask.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsxw.mask.nxv2i32.nxv2i32( , *, , @@ -420,12 +420,12 @@ declare void @llvm.riscv.xvsxw.mask.nxv2i32.nxv2i32( define void @intrinsic_xvsxw_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.mask.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsxw.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -435,7 +435,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsxw.nxv4i32.nxv4i32( , *, , @@ -444,12 +444,12 @@ declare void @llvm.riscv.xvsxw.nxv4i32.nxv4i32( define void @intrinsic_xvsxw_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsxw.nxv4i32.nxv4i32( undef, * %0, %1, @@ -458,7 +458,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.mask.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsxw.mask.nxv4i32.nxv4i32( , *, , @@ -468,12 +468,12 @@ declare void @llvm.riscv.xvsxw.mask.nxv4i32.nxv4i32( define void @intrinsic_xvsxw_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.mask.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsxw.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -483,7 +483,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsxw.nxv8i32.nxv8i32( , *, , @@ -492,12 +492,12 @@ declare void @llvm.riscv.xvsxw.nxv8i32.nxv8i32( define void @intrinsic_xvsxw_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsxw.nxv8i32.nxv8i32( undef, * %0, %1, @@ -506,7 +506,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.mask.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsxw.mask.nxv8i32.nxv8i32( , *, , @@ -516,12 +516,12 @@ declare void @llvm.riscv.xvsxw.mask.nxv8i32.nxv8i32( define void @intrinsic_xvsxw_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.mask.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsxw.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -531,7 +531,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsxw.nxv16i32.nxv16i32( , *, , @@ -540,12 +540,12 @@ declare void @llvm.riscv.xvsxw.nxv16i32.nxv16i32( define void @intrinsic_xvsxw_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsxw.nxv16i32.nxv16i32( undef, * %0, %1, @@ -554,7 +554,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxw.mask.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsxw.mask.nxv16i32.nxv16i32( , *, , @@ -564,12 +564,12 @@ declare void @llvm.riscv.xvsxw.mask.nxv16i32.nxv16i32( define void @intrinsic_xvsxw_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxw_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsxw.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsxw.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxw.mask.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsxw.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -579,7 +579,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsxe.nxv8i8.nxv8i8( , *, , @@ -588,12 +588,12 @@ declare void @llvm.riscv.xvsxe.nxv8i8.nxv8i8( define void @intrinsic_xvsxe_v_nxv8i8_nxv8i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsxe.nxv8i8.nxv8i8( undef, * %0, %1, @@ -602,7 +602,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8i8.nxv8i8( +declare void @llvm.riscv.th.vsxe.mask.nxv8i8.nxv8i8( , *, , @@ -612,12 +612,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8i8.nxv8i8( define void @intrinsic_xvsxe_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8i8_nxv8i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8i8.nxv8i8( + call void @llvm.riscv.th.vsxe.mask.nxv8i8.nxv8i8( %0, * %1, %2, @@ -627,7 +627,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsxe.nxv16i8.nxv16i8( , *, , @@ -636,12 +636,12 @@ declare void @llvm.riscv.xvsxe.nxv16i8.nxv16i8( define void @intrinsic_xvsxe_v_nxv16i8_nxv16i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsxe.nxv16i8.nxv16i8( undef, * %0, %1, @@ -650,7 +650,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv16i8.nxv16i8( +declare void @llvm.riscv.th.vsxe.mask.nxv16i8.nxv16i8( , *, , @@ -660,12 +660,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv16i8.nxv16i8( define void @intrinsic_xvsxe_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv16i8_nxv16i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv16i8.nxv16i8( + call void @llvm.riscv.th.vsxe.mask.nxv16i8.nxv16i8( %0, * %1, %2, @@ -675,7 +675,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsxe.nxv32i8.nxv32i8( , *, , @@ -684,12 +684,12 @@ declare void @llvm.riscv.xvsxe.nxv32i8.nxv32i8( define void @intrinsic_xvsxe_v_nxv32i8_nxv32i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsxe.nxv32i8.nxv32i8( undef, * %0, %1, @@ -698,7 +698,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv32i8.nxv32i8( +declare void @llvm.riscv.th.vsxe.mask.nxv32i8.nxv32i8( , *, , @@ -708,12 +708,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv32i8.nxv32i8( define void @intrinsic_xvsxe_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv32i8_nxv32i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv32i8.nxv32i8( + call void @llvm.riscv.th.vsxe.mask.nxv32i8.nxv32i8( %0, * %1, %2, @@ -723,7 +723,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsxe.nxv64i8.nxv64i8( , *, , @@ -732,12 +732,12 @@ declare void @llvm.riscv.xvsxe.nxv64i8.nxv64i8( define void @intrinsic_xvsxe_v_nxv64i8_nxv64i8(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsxe.nxv64i8.nxv64i8( undef, * %0, %1, @@ -746,7 +746,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv64i8.nxv64i8( +declare void @llvm.riscv.th.vsxe.mask.nxv64i8.nxv64i8( , *, , @@ -756,12 +756,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv64i8.nxv64i8( define void @intrinsic_xvsxe_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv64i8_nxv64i8 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv64i8.nxv64i8( + call void @llvm.riscv.th.vsxe.mask.nxv64i8.nxv64i8( %0, * %1, %2, @@ -771,7 +771,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsxe.nxv4i16.nxv4i16( , *, , @@ -780,12 +780,12 @@ declare void @llvm.riscv.xvsxe.nxv4i16.nxv4i16( define void @intrinsic_xvsxe_v_nxv4i16_nxv4i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsxe.nxv4i16.nxv4i16( undef, * %0, %1, @@ -794,7 +794,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv4i16.nxv4i16( +declare void @llvm.riscv.th.vsxe.mask.nxv4i16.nxv4i16( , *, , @@ -804,12 +804,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv4i16.nxv4i16( define void @intrinsic_xvsxe_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv4i16_nxv4i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv4i16.nxv4i16( + call void @llvm.riscv.th.vsxe.mask.nxv4i16.nxv4i16( %0, * %1, %2, @@ -819,7 +819,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv4f16.nxv4f16( +declare void @llvm.riscv.th.vsxe.nxv4f16.nxv4f16( , *, , @@ -828,12 +828,12 @@ declare void @llvm.riscv.xvsxe.nxv4f16.nxv4f16( define void @intrinsic_xvsxe_v_nxv4f16_nxv4f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv4f16.nxv4f16( + call void @llvm.riscv.th.vsxe.nxv4f16.nxv4f16( undef, * %0, %1, @@ -842,7 +842,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv4f16.nxv4f16( +declare void @llvm.riscv.th.vsxe.mask.nxv4f16.nxv4f16( , *, , @@ -852,12 +852,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv4f16.nxv4f16( define void @intrinsic_xvsxe_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv4f16_nxv4f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv4f16.nxv4f16( + call void @llvm.riscv.th.vsxe.mask.nxv4f16.nxv4f16( %0, * %1, %2, @@ -867,7 +867,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsxe.nxv8i16.nxv8i16( , *, , @@ -876,12 +876,12 @@ declare void @llvm.riscv.xvsxe.nxv8i16.nxv8i16( define void @intrinsic_xvsxe_v_nxv8i16_nxv8i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsxe.nxv8i16.nxv8i16( undef, * %0, %1, @@ -890,7 +890,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8i16.nxv8i16( +declare void @llvm.riscv.th.vsxe.mask.nxv8i16.nxv8i16( , *, , @@ -900,12 +900,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8i16.nxv8i16( define void @intrinsic_xvsxe_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8i16_nxv8i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8i16.nxv8i16( + call void @llvm.riscv.th.vsxe.mask.nxv8i16.nxv8i16( %0, * %1, %2, @@ -915,7 +915,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8f16.nxv8f16( +declare void @llvm.riscv.th.vsxe.nxv8f16.nxv8f16( , *, , @@ -924,12 +924,12 @@ declare void @llvm.riscv.xvsxe.nxv8f16.nxv8f16( define void @intrinsic_xvsxe_v_nxv8f16_nxv8f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8f16.nxv8f16( + call void @llvm.riscv.th.vsxe.nxv8f16.nxv8f16( undef, * %0, %1, @@ -938,7 +938,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8f16.nxv8f16( +declare void @llvm.riscv.th.vsxe.mask.nxv8f16.nxv8f16( , *, , @@ -948,12 +948,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8f16.nxv8f16( define void @intrinsic_xvsxe_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8f16_nxv8f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8f16.nxv8f16( + call void @llvm.riscv.th.vsxe.mask.nxv8f16.nxv8f16( %0, * %1, %2, @@ -963,7 +963,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsxe.nxv16i16.nxv16i16( , *, , @@ -972,12 +972,12 @@ declare void @llvm.riscv.xvsxe.nxv16i16.nxv16i16( define void @intrinsic_xvsxe_v_nxv16i16_nxv16i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsxe.nxv16i16.nxv16i16( undef, * %0, %1, @@ -986,7 +986,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv16i16.nxv16i16( +declare void @llvm.riscv.th.vsxe.mask.nxv16i16.nxv16i16( , *, , @@ -996,12 +996,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv16i16.nxv16i16( define void @intrinsic_xvsxe_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv16i16_nxv16i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv16i16.nxv16i16( + call void @llvm.riscv.th.vsxe.mask.nxv16i16.nxv16i16( %0, * %1, %2, @@ -1011,7 +1011,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv16f16.nxv16f16( +declare void @llvm.riscv.th.vsxe.nxv16f16.nxv16f16( , *, , @@ -1020,12 +1020,12 @@ declare void @llvm.riscv.xvsxe.nxv16f16.nxv16f16( define void @intrinsic_xvsxe_v_nxv16f16_nxv16f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv16f16.nxv16f16( + call void @llvm.riscv.th.vsxe.nxv16f16.nxv16f16( undef, * %0, %1, @@ -1034,7 +1034,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv16f16.nxv16f16( +declare void @llvm.riscv.th.vsxe.mask.nxv16f16.nxv16f16( , *, , @@ -1044,12 +1044,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv16f16.nxv16f16( define void @intrinsic_xvsxe_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv16f16_nxv16f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv16f16.nxv16f16( + call void @llvm.riscv.th.vsxe.mask.nxv16f16.nxv16f16( %0, * %1, %2, @@ -1059,7 +1059,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsxe.nxv32i16.nxv32i16( , *, , @@ -1068,12 +1068,12 @@ declare void @llvm.riscv.xvsxe.nxv32i16.nxv32i16( define void @intrinsic_xvsxe_v_nxv32i16_nxv32i16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsxe.nxv32i16.nxv32i16( undef, * %0, %1, @@ -1082,7 +1082,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv32i16.nxv32i16( +declare void @llvm.riscv.th.vsxe.mask.nxv32i16.nxv32i16( , *, , @@ -1092,12 +1092,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv32i16.nxv32i16( define void @intrinsic_xvsxe_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv32i16_nxv32i16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv32i16.nxv32i16( + call void @llvm.riscv.th.vsxe.mask.nxv32i16.nxv32i16( %0, * %1, %2, @@ -1107,7 +1107,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv32f16.nxv32f16( +declare void @llvm.riscv.th.vsxe.nxv32f16.nxv32f16( , *, , @@ -1116,12 +1116,12 @@ declare void @llvm.riscv.xvsxe.nxv32f16.nxv32f16( define void @intrinsic_xvsxe_v_nxv32f16_nxv32f16(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv32f16.nxv32f16( + call void @llvm.riscv.th.vsxe.nxv32f16.nxv32f16( undef, * %0, %1, @@ -1130,7 +1130,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv32f16.nxv32f16( +declare void @llvm.riscv.th.vsxe.mask.nxv32f16.nxv32f16( , *, , @@ -1140,12 +1140,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv32f16.nxv32f16( define void @intrinsic_xvsxe_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv32f16_nxv32f16 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv32f16.nxv32f16( + call void @llvm.riscv.th.vsxe.mask.nxv32f16.nxv32f16( %0, * %1, %2, @@ -1155,7 +1155,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsxe.nxv2i32.nxv2i32( , *, , @@ -1164,12 +1164,12 @@ declare void @llvm.riscv.xvsxe.nxv2i32.nxv2i32( define void @intrinsic_xvsxe_v_nxv2i32_nxv2i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsxe.nxv2i32.nxv2i32( undef, * %0, %1, @@ -1178,7 +1178,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv2i32.nxv2i32( +declare void @llvm.riscv.th.vsxe.mask.nxv2i32.nxv2i32( , *, , @@ -1188,12 +1188,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv2i32.nxv2i32( define void @intrinsic_xvsxe_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv2i32_nxv2i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv2i32.nxv2i32( + call void @llvm.riscv.th.vsxe.mask.nxv2i32.nxv2i32( %0, * %1, %2, @@ -1203,7 +1203,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv2f32.nxv2f32( +declare void @llvm.riscv.th.vsxe.nxv2f32.nxv2f32( , *, , @@ -1212,12 +1212,12 @@ declare void @llvm.riscv.xvsxe.nxv2f32.nxv2f32( define void @intrinsic_xvsxe_v_nxv2f32_nxv2f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv2f32.nxv2f32( + call void @llvm.riscv.th.vsxe.nxv2f32.nxv2f32( undef, * %0, %1, @@ -1226,7 +1226,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv2f32.nxv2f32( +declare void @llvm.riscv.th.vsxe.mask.nxv2f32.nxv2f32( , *, , @@ -1236,12 +1236,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv2f32.nxv2f32( define void @intrinsic_xvsxe_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv2f32_nxv2f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v9, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv2f32.nxv2f32( + call void @llvm.riscv.th.vsxe.mask.nxv2f32.nxv2f32( %0, * %1, %2, @@ -1251,7 +1251,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsxe.nxv4i32.nxv4i32( , *, , @@ -1260,12 +1260,12 @@ declare void @llvm.riscv.xvsxe.nxv4i32.nxv4i32( define void @intrinsic_xvsxe_v_nxv4i32_nxv4i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsxe.nxv4i32.nxv4i32( undef, * %0, %1, @@ -1274,7 +1274,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv4i32.nxv4i32( +declare void @llvm.riscv.th.vsxe.mask.nxv4i32.nxv4i32( , *, , @@ -1284,12 +1284,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv4i32.nxv4i32( define void @intrinsic_xvsxe_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv4i32_nxv4i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv4i32.nxv4i32( + call void @llvm.riscv.th.vsxe.mask.nxv4i32.nxv4i32( %0, * %1, %2, @@ -1299,7 +1299,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv4f32.nxv4f32( +declare void @llvm.riscv.th.vsxe.nxv4f32.nxv4f32( , *, , @@ -1308,12 +1308,12 @@ declare void @llvm.riscv.xvsxe.nxv4f32.nxv4f32( define void @intrinsic_xvsxe_v_nxv4f32_nxv4f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv4f32.nxv4f32( + call void @llvm.riscv.th.vsxe.nxv4f32.nxv4f32( undef, * %0, %1, @@ -1322,7 +1322,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv4f32.nxv4f32( +declare void @llvm.riscv.th.vsxe.mask.nxv4f32.nxv4f32( , *, , @@ -1332,12 +1332,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv4f32.nxv4f32( define void @intrinsic_xvsxe_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv4f32_nxv4f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v10, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv4f32.nxv4f32( + call void @llvm.riscv.th.vsxe.mask.nxv4f32.nxv4f32( %0, * %1, %2, @@ -1347,7 +1347,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsxe.nxv8i32.nxv8i32( , *, , @@ -1356,12 +1356,12 @@ declare void @llvm.riscv.xvsxe.nxv8i32.nxv8i32( define void @intrinsic_xvsxe_v_nxv8i32_nxv8i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsxe.nxv8i32.nxv8i32( undef, * %0, %1, @@ -1370,7 +1370,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8i32.nxv8i32( +declare void @llvm.riscv.th.vsxe.mask.nxv8i32.nxv8i32( , *, , @@ -1380,12 +1380,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8i32.nxv8i32( define void @intrinsic_xvsxe_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8i32_nxv8i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8i32.nxv8i32( + call void @llvm.riscv.th.vsxe.mask.nxv8i32.nxv8i32( %0, * %1, %2, @@ -1395,7 +1395,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv8f32.nxv8f32( +declare void @llvm.riscv.th.vsxe.nxv8f32.nxv8f32( , *, , @@ -1404,12 +1404,12 @@ declare void @llvm.riscv.xvsxe.nxv8f32.nxv8f32( define void @intrinsic_xvsxe_v_nxv8f32_nxv8f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv8f32.nxv8f32( + call void @llvm.riscv.th.vsxe.nxv8f32.nxv8f32( undef, * %0, %1, @@ -1418,7 +1418,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv8f32.nxv8f32( +declare void @llvm.riscv.th.vsxe.mask.nxv8f32.nxv8f32( , *, , @@ -1428,12 +1428,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv8f32.nxv8f32( define void @intrinsic_xvsxe_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv8f32_nxv8f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v12, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv8f32.nxv8f32( + call void @llvm.riscv.th.vsxe.mask.nxv8f32.nxv8f32( %0, * %1, %2, @@ -1443,7 +1443,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsxe.nxv16i32.nxv16i32( , *, , @@ -1452,12 +1452,12 @@ declare void @llvm.riscv.xvsxe.nxv16i32.nxv16i32( define void @intrinsic_xvsxe_v_nxv16i32_nxv16i32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsxe.nxv16i32.nxv16i32( undef, * %0, %1, @@ -1466,7 +1466,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv16i32.nxv16i32( +declare void @llvm.riscv.th.vsxe.mask.nxv16i32.nxv16i32( , *, , @@ -1476,12 +1476,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv16i32.nxv16i32( define void @intrinsic_xvsxe_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv16i32_nxv16i32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv16i32.nxv16i32( + call void @llvm.riscv.th.vsxe.mask.nxv16i32.nxv16i32( %0, * %1, %2, @@ -1491,7 +1491,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.nxv16f32.nxv16f32( +declare void @llvm.riscv.th.vsxe.nxv16f32.nxv16f32( , *, , @@ -1500,12 +1500,12 @@ declare void @llvm.riscv.xvsxe.nxv16f32.nxv16f32( define void @intrinsic_xvsxe_v_nxv16f32_nxv16f32(* %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v8 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v8 ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.nxv16f32.nxv16f32( + call void @llvm.riscv.th.vsxe.nxv16f32.nxv16f32( undef, * %0, %1, @@ -1514,7 +1514,7 @@ entry: ret void } -declare void @llvm.riscv.xvsxe.mask.nxv16f32.nxv16f32( +declare void @llvm.riscv.th.vsxe.mask.nxv16f32.nxv16f32( , *, , @@ -1524,12 +1524,12 @@ declare void @llvm.riscv.xvsxe.mask.nxv16f32.nxv16f32( define void @intrinsic_xvsxe_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_xvsxe_mask_v_nxv16f32_nxv16f32 ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, d1 -; CHECK-NEXT: vsxe.v v8, (a0), v16, v0.t +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vsxe.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: - call void @llvm.riscv.xvsxe.mask.nxv16f32.nxv16f32( + call void @llvm.riscv.th.vsxe.mask.nxv16f32.nxv16f32( %0, * %1, %2, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-16.ll b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-16.ll index fd63584e3c71f..2cb9a2a601916 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-16.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-16.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvadd.nxv4i16.nxv4i16( +declare @llvm.riscv.th.vadd.nxv4i16.nxv4i16( , , , @@ -14,31 +14,31 @@ define void @vadd_vint16m1( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv4i16.nxv4i16( + %vc = call @llvm.riscv.th.vadd.nxv4i16.nxv4i16( undef, %va, %vb, @@ -47,7 +47,7 @@ define void @vadd_vint16m1( *%pc, *%pa, @llvm.riscv.xvadd.nxv8i16.nxv8i16( +declare @llvm.riscv.th.vadd.nxv8i16.nxv8i16( , , , @@ -58,31 +58,31 @@ define void @vadd_vint16m2( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv8i16.nxv8i16( + %vc = call @llvm.riscv.th.vadd.nxv8i16.nxv8i16( undef, %va, %vb, @@ -91,7 +91,7 @@ define void @vadd_vint16m2( *%pc, *%pa, @llvm.riscv.xvadd.nxv16i16.nxv16i16( +declare @llvm.riscv.th.vadd.nxv16i16.nxv16i16( , , , @@ -102,31 +102,31 @@ define void @vadd_vint16m4( *%pc, *%pa, < ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a4, vl ; CHECK-NEXT: csrr a5, vtype -; CHECK-NEXT: vsetvli zero, zero, e16, m4, d1 -; CHECK-NEXT: vle.v v8, (a1) -; CHECK-NEXT: vsetvl zero, a4, a5 +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vle.v v8, (a1) +; CHECK-NEXT: th.vsetvl zero, a4, a5 ; CHECK-NEXT: csrr a1, vl ; CHECK-NEXT: csrr a4, vtype -; CHECK-NEXT: vsetvli zero, zero, e16, m4, d1 -; CHECK-NEXT: vle.v v12, (a2) -; CHECK-NEXT: vsetvl zero, a1, a4 +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vle.v v12, (a2) +; CHECK-NEXT: th.vsetvl zero, a1, a4 -; CHECK-NEXT: vsetvli zero, a3, e16, m4, d1 -; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: th.vsetvli zero, a3, e16, m4, d1 +; CHECK-NEXT: th.vadd.vv v8, v8, v12 ; CHECK-NEXT: csrr a1, vl ; CHECK-NEXT: csrr a2, vtype -; CHECK-NEXT: vsetvli zero, zero, e16, m4, d1 -; CHECK-NEXT: vse.v v8, (a0) -; CHECK-NEXT: vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vse.v v8, (a0) +; CHECK-NEXT: th.vsetvl zero, a1, a2 ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv16i16.nxv16i16( + %vc = call @llvm.riscv.th.vadd.nxv16i16.nxv16i16( undef, %va, %vb, @@ -135,7 +135,7 @@ define void @vadd_vint16m4( *%pc, *%pa, < ret void } -declare @llvm.riscv.xvadd.nxv32i16.nxv32i16( +declare @llvm.riscv.th.vadd.nxv32i16.nxv32i16( , , , @@ -146,31 +146,31 @@ define void @vadd_vint16m8( *%pc, *%pa, < ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a4, vl ; CHECK-NEXT: csrr a5, vtype -; CHECK-NEXT: vsetvli zero, zero, e16, m8, d1 -; CHECK-NEXT: vle.v v8, (a1) -; CHECK-NEXT: vsetvl zero, a4, a5 +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a1) +; CHECK-NEXT: th.vsetvl zero, a4, a5 ; CHECK-NEXT: csrr a1, vl ; CHECK-NEXT: csrr a4, vtype -; CHECK-NEXT: vsetvli zero, zero, e16, m8, d1 -; CHECK-NEXT: vle.v v16, (a2) -; CHECK-NEXT: vsetvl zero, a1, a4 +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vle.v v16, (a2) +; CHECK-NEXT: th.vsetvl zero, a1, a4 -; CHECK-NEXT: vsetvli zero, a3, e16, m8, d1 -; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: th.vsetvli zero, a3, e16, m8, d1 +; CHECK-NEXT: th.vadd.vv v8, v8, v16 ; CHECK-NEXT: csrr a1, vl ; CHECK-NEXT: csrr a2, vtype -; CHECK-NEXT: vsetvli zero, zero, e16, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) -; CHECK-NEXT: vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) +; CHECK-NEXT: th.vsetvl zero, a1, a2 ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv32i16.nxv32i16( + %vc = call @llvm.riscv.th.vadd.nxv32i16.nxv32i16( undef, %va, %vb, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-32.ll b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-32.ll index 956aab3c64399..c96bc4d21e652 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-32.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-32.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvadd.nxv2i32.nxv2i32( +declare @llvm.riscv.th.vadd.nxv2i32.nxv2i32( , , , @@ -14,31 +14,31 @@ define void @vadd_vint32m1( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv2i32.nxv2i32( + %vc = call @llvm.riscv.th.vadd.nxv2i32.nxv2i32( undef, %va, %vb, @@ -47,7 +47,7 @@ define void @vadd_vint32m1( *%pc, *%pa, @llvm.riscv.xvadd.nxv4i32.nxv4i32( +declare @llvm.riscv.th.vadd.nxv4i32.nxv4i32( , , , @@ -58,31 +58,31 @@ define void @vadd_vint32m2( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv4i32.nxv4i32( + %vc = call @llvm.riscv.th.vadd.nxv4i32.nxv4i32( undef, %va, %vb, @@ -91,7 +91,7 @@ define void @vadd_vint32m2( *%pc, *%pa, @llvm.riscv.xvadd.nxv8i32.nxv8i32( +declare @llvm.riscv.th.vadd.nxv8i32.nxv8i32( , , , @@ -102,31 +102,31 @@ define void @vadd_vint32m4( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv8i32.nxv8i32( + %vc = call @llvm.riscv.th.vadd.nxv8i32.nxv8i32( undef, %va, %vb, @@ -135,7 +135,7 @@ define void @vadd_vint32m4( *%pc, *%pa, @llvm.riscv.xvadd.nxv16i32.nxv16i32( +declare @llvm.riscv.th.vadd.nxv16i32.nxv16i32( , , , @@ -146,31 +146,31 @@ define void @vadd_vint32m8( *%pc, *%pa, < ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a4, vl ; CHECK-NEXT: csrr a5, vtype -; CHECK-NEXT: vsetvli zero, zero, e32, m8, d1 -; CHECK-NEXT: vle.v v8, (a1) -; CHECK-NEXT: vsetvl zero, a4, a5 +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vle.v v8, (a1) +; CHECK-NEXT: th.vsetvl zero, a4, a5 ; CHECK-NEXT: csrr a1, vl ; CHECK-NEXT: csrr a4, vtype -; CHECK-NEXT: vsetvli zero, zero, e32, m8, d1 -; CHECK-NEXT: vle.v v16, (a2) -; CHECK-NEXT: vsetvl zero, a1, a4 +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vle.v v16, (a2) +; CHECK-NEXT: th.vsetvl zero, a1, a4 -; CHECK-NEXT: vsetvli zero, a3, e32, m8, d1 -; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: th.vsetvli zero, a3, e32, m8, d1 +; CHECK-NEXT: th.vadd.vv v8, v8, v16 ; CHECK-NEXT: csrr a1, vl ; CHECK-NEXT: csrr a2, vtype -; CHECK-NEXT: vsetvli zero, zero, e32, m8, d1 -; CHECK-NEXT: vse.v v8, (a0) -; CHECK-NEXT: vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vse.v v8, (a0) +; CHECK-NEXT: th.vsetvl zero, a1, a2 ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv16i32.nxv16i32( + %vc = call @llvm.riscv.th.vadd.nxv16i32.nxv16i32( undef, %va, %vb, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-64.ll index 9619955c4e9c7..c8c8388c1b000 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-64.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-64.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvadd.nxv1i64.nxv1i64( +declare @llvm.riscv.th.vadd.nxv1i64.nxv1i64( , , , @@ -14,31 +14,31 @@ define void @vadd_vint64m1( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv1i64.nxv1i64( + %vc = call @llvm.riscv.th.vadd.nxv1i64.nxv1i64( undef, %va, %vb, @@ -47,7 +47,7 @@ define void @vadd_vint64m1( *%pc, *%pa, @llvm.riscv.xvadd.nxv2i64.nxv2i64( +declare @llvm.riscv.th.vadd.nxv2i64.nxv2i64( , , , @@ -58,31 +58,31 @@ define void @vadd_vint32m2( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv2i64.nxv2i64( + %vc = call @llvm.riscv.th.vadd.nxv2i64.nxv2i64( undef, %va, %vb, @@ -91,7 +91,7 @@ define void @vadd_vint32m2( *%pc, *%pa, @llvm.riscv.xvadd.nxv4i64.nxv4i64( +declare @llvm.riscv.th.vadd.nxv4i64.nxv4i64( , , , @@ -102,31 +102,31 @@ define void @vadd_vint32m4( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv4i64.nxv4i64( + %vc = call @llvm.riscv.th.vadd.nxv4i64.nxv4i64( undef, %va, %vb, @@ -135,7 +135,7 @@ define void @vadd_vint32m4( *%pc, *%pa, @llvm.riscv.xvadd.nxv8i64.nxv8i64( +declare @llvm.riscv.th.vadd.nxv8i64.nxv8i64( , , , @@ -146,31 +146,31 @@ define void @vadd_vint32m8( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv8i64.nxv8i64( + %vc = call @llvm.riscv.th.vadd.nxv8i64.nxv8i64( undef, %va, %vb, diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-8.ll b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-8.ll index aa4f2ed535ddb..fc29ba3a6463c 100644 --- a/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv0p71/whole-load-store-8.ll @@ -1,9 +1,9 @@ -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadv \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT -declare @llvm.riscv.xvadd.nxv8i8.nxv8i8( +declare @llvm.riscv.th.vadd.nxv8i8.nxv8i8( , , , @@ -14,31 +14,31 @@ define void @vadd_vint8m1( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv8i8.nxv8i8( + %vc = call @llvm.riscv.th.vadd.nxv8i8.nxv8i8( undef, %va, %vb, @@ -47,7 +47,7 @@ define void @vadd_vint8m1( *%pc, *%pa, @llvm.riscv.xvadd.nxv16i8.nxv16i8( +declare @llvm.riscv.th.vadd.nxv16i8.nxv16i8( , , , @@ -58,31 +58,31 @@ define void @vadd_vint8m2( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv16i8.nxv16i8( + %vc = call @llvm.riscv.th.vadd.nxv16i8.nxv16i8( undef, %va, %vb, @@ -91,7 +91,7 @@ define void @vadd_vint8m2( *%pc, *%pa, @llvm.riscv.xvadd.nxv32i8.nxv32i8( +declare @llvm.riscv.th.vadd.nxv32i8.nxv32i8( , , , @@ -102,31 +102,31 @@ define void @vadd_vint8m4( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv32i8.nxv32i8( + %vc = call @llvm.riscv.th.vadd.nxv32i8.nxv32i8( undef, %va, %vb, @@ -135,7 +135,7 @@ define void @vadd_vint8m4( *%pc, *%pa, @llvm.riscv.xvadd.nxv64i8.nxv64i8( +declare @llvm.riscv.th.vadd.nxv64i8.nxv64i8( , , , @@ -146,31 +146,31 @@ define void @vadd_vint8m8( *%pc, *%pa, , * %pa %vb = load , * %pb - ; TODO: support select `add` to `llvm.riscv.xvadd` + ; TODO: support select `add` to `llvm.riscv.th.vadd` ; %vc = add %va, %vb - %vc = call @llvm.riscv.xvadd.nxv64i8.nxv64i8( + %vc = call @llvm.riscv.th.vadd.nxv64i8.nxv64i8( undef, %va, %vb, diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f4543f004a1b9..fd2277b115132 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -291,15 +291,15 @@ .attribute arch, "rv32i_xcvmac" # CHECK: attribute 5, "rv32i2p1_xcvmac1p0" -.attribute arch, "rv32i_xtheadv" -# CHECK: attribute 5, "rv32i2p1_xtheadv0p7" +.attribute arch, "rv32i_xtheadvector" +# CHECK: attribute 5, "rv32i2p1_xtheadvector0p7" -.attribute arch, "rv32i_xtheadv_xtheadvamo_xtheadvediv_xtheadvlsseg" -# CHECK: attribute 5, "rv32i2p1_a2p1_xtheadv0p7_xtheadvamo0p7_xtheadvediv0p7_xtheadvlsseg0p7" +.attribute arch, "rv32i_xtheadvector_xtheadvamo_xtheadvediv_xtheadvlsseg" +# CHECK: attribute 5, "rv32i2p1_a2p1_xtheadvamo0p7_xtheadvector0p7_xtheadvediv0p7_xtheadvlsseg0p7" -.attribute arch, "rv32i_xtheadv" -# CHECK: attribute 5, "rv32i2p1_xtheadv0p7" +.attribute arch, "rv32i_xtheadvector" +# CHECK: attribute 5, "rv32i2p1_xtheadvector0p7" -.attribute arch, "rv64i_xtheadv_xtheadvamo_xtheadvediv_xtheadvlsseg" -# CHECK: attribute 5, "rv64i2p1_a2p1_xtheadv0p7_xtheadvamo0p7_xtheadvediv0p7_xtheadvlsseg0p7" +.attribute arch, "rv64i_xtheadvector_xtheadvamo_xtheadvediv_xtheadvlsseg" +# CHECK: attribute 5, "rv64i2p1_a2p1_xtheadvamo0p7_xtheadvector0p7_xtheadvediv0p7_xtheadvlsseg0p7" diff --git a/llvm/test/MC/RISCV/rvv0p71/add.s b/llvm/test/MC/RISCV/rvv0p71/add.s index 919639d027ea6..220f4f02c2b3b 100644 --- a/llvm/test/MC/RISCV/rvv0p71/add.s +++ b/llvm/test/MC/RISCV/rvv0p71/add.s @@ -1,309 +1,309 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vadd.vv v8, v4, v20, v0.t -# CHECK-INST: vadd.vv v8, v4, v20, v0.t +th.vadd.vv v8, v4, v20, v0.t +# CHECK-INST: th.vadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 00 -vadd.vv v8, v4, v20 -# CHECK-INST: vadd.vv v8, v4, v20 +th.vadd.vv v8, v4, v20 +# CHECK-INST: th.vadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 02 -vadd.vx v8, v4, a0, v0.t -# CHECK-INST: vadd.vx v8, v4, a0, v0.t +th.vadd.vx v8, v4, a0, v0.t +# CHECK-INST: th.vadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 00 -vadd.vx v8, v4, a0 -# CHECK-INST: vadd.vx v8, v4, a0 +th.vadd.vx v8, v4, a0 +# CHECK-INST: th.vadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 02 -vadd.vi v8, v4, 15, v0.t -# CHECK-INST: vadd.vi v8, v4, 15, v0.t +th.vadd.vi v8, v4, 15, v0.t +# CHECK-INST: th.vadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 00 -vadd.vi v8, v4, 15 -# CHECK-INST: vadd.vi v8, v4, 15 +th.vadd.vi v8, v4, 15 +# CHECK-INST: th.vadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 02 -vwaddu.vv v8, v4, v20, v0.t -# CHECK-INST: vwaddu.vv v8, v4, v20, v0.t +th.vwaddu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a c0 -vwaddu.vv v8, v4, v20 -# CHECK-INST: vwaddu.vv v8, v4, v20 +th.vwaddu.vv v8, v4, v20 +# CHECK-INST: th.vwaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a c2 -vwaddu.vx v8, v4, a0, v0.t -# CHECK-INST: vwaddu.vx v8, v4, a0, v0.t +th.vwaddu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 c0 -vwaddu.vx v8, v4, a0 -# CHECK-INST: vwaddu.vx v8, v4, a0 +th.vwaddu.vx v8, v4, a0 +# CHECK-INST: th.vwaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 c2 -vwadd.vv v8, v4, v20, v0.t -# CHECK-INST: vwadd.vv v8, v4, v20, v0.t +th.vwadd.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a c4 -vwadd.vv v8, v4, v20 -# CHECK-INST: vwadd.vv v8, v4, v20 +th.vwadd.vv v8, v4, v20 +# CHECK-INST: th.vwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a c6 -vwadd.vx v8, v4, a0, v0.t -# CHECK-INST: vwadd.vx v8, v4, a0, v0.t +th.vwadd.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 c4 -vwadd.vx v8, v4, a0 -# CHECK-INST: vwadd.vx v8, v4, a0 +th.vwadd.vx v8, v4, a0 +# CHECK-INST: th.vwadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 c6 -vwaddu.wv v8, v4, v20, v0.t -# CHECK-INST: vwaddu.wv v8, v4, v20, v0.t +th.vwaddu.wv v8, v4, v20, v0.t +# CHECK-INST: th.vwaddu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a d0 -vwaddu.wv v8, v4, v20 -# CHECK-INST: vwaddu.wv v8, v4, v20 +th.vwaddu.wv v8, v4, v20 +# CHECK-INST: th.vwaddu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a d2 -vwaddu.wx v8, v4, a0, v0.t -# CHECK-INST: vwaddu.wx v8, v4, a0, v0.t +th.vwaddu.wx v8, v4, a0, v0.t +# CHECK-INST: th.vwaddu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 d0 -vwaddu.wx v8, v4, a0 -# CHECK-INST: vwaddu.wx v8, v4, a0 +th.vwaddu.wx v8, v4, a0 +# CHECK-INST: th.vwaddu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 d2 -vwadd.wv v8, v4, v20, v0.t -# CHECK-INST: vwadd.wv v8, v4, v20, v0.t +th.vwadd.wv v8, v4, v20, v0.t +# CHECK-INST: th.vwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a d4 -vwadd.wv v8, v4, v20 -# CHECK-INST: vwadd.wv v8, v4, v20 +th.vwadd.wv v8, v4, v20 +# CHECK-INST: th.vwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a d6 -vwadd.wx v8, v4, a0, v0.t -# CHECK-INST: vwadd.wx v8, v4, a0, v0.t +th.vwadd.wx v8, v4, a0, v0.t +# CHECK-INST: th.vwadd.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 d4 -vwadd.wx v8, v4, a0 -# CHECK-INST: vwadd.wx v8, v4, a0 +th.vwadd.wx v8, v4, a0 +# CHECK-INST: th.vwadd.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 d6 -vadc.vvm v8, v4, v20, v0 -# CHECK-INST: vadc.vvm v8, v4, v20, v0 +th.vadc.vvm v8, v4, v20, v0 +# CHECK-INST: th.vadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 42 -vadc.vvm v4, v4, v20, v0 -# CHECK-INST: vadc.vvm v4, v4, v20, v0 +th.vadc.vvm v4, v4, v20, v0 +# CHECK-INST: th.vadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 02 4a 42 -vadc.vvm v8, v4, v8, v0 -# CHECK-INST: vadc.vvm v8, v4, v8, v0 +th.vadc.vvm v8, v4, v8, v0 +# CHECK-INST: th.vadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 44 42 -vadc.vxm v8, v4, a0, v0 -# CHECK-INST: vadc.vxm v8, v4, a0, v0 +th.vadc.vxm v8, v4, a0, v0 +# CHECK-INST: th.vadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 42 -vadc.vim v8, v4, 15, v0 -# CHECK-INST: vadc.vim v8, v4, 15, v0 +th.vadc.vim v8, v4, 15, v0 +# CHECK-INST: th.vadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 42 -vmadc.vvm v8, v4, v20, v0 -# CHECK-INST: vmadc.vvm v8, v4, v20, v0 +th.vmadc.vvm v8, v4, v20, v0 +# CHECK-INST: th.vmadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 46 -vmadc.vvm v4, v4, v20, v0 -# CHECK-INST: vmadc.vvm v4, v4, v20, v0 +th.vmadc.vvm v4, v4, v20, v0 +# CHECK-INST: th.vmadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 02 4a 46 -vmadc.vvm v8, v4, v8, v0 -# CHECK-INST: vmadc.vvm v8, v4, v8, v0 +th.vmadc.vvm v8, v4, v8, v0 +# CHECK-INST: th.vmadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 44 46 -vmadc.vxm v8, v4, a0, v0 -# CHECK-INST: vmadc.vxm v8, v4, a0, v0 +th.vmadc.vxm v8, v4, a0, v0 +# CHECK-INST: th.vmadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 46 -vmadc.vim v8, v4, 15, v0 -# CHECK-INST: vmadc.vim v8, v4, 15, v0 +th.vmadc.vim v8, v4, 15, v0 +# CHECK-INST: th.vmadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 46 -vsaddu.vv v8, v4, v20, v0.t -# CHECK-INST: vsaddu.vv v8, v4, v20, v0.t +th.vsaddu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 80 -vsaddu.vv v8, v4, v20 -# CHECK-INST: vsaddu.vv v8, v4, v20 +th.vsaddu.vv v8, v4, v20 +# CHECK-INST: th.vsaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 82 -vsaddu.vx v8, v4, a0, v0.t -# CHECK-INST: vsaddu.vx v8, v4, a0, v0.t +th.vsaddu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 80 -vsaddu.vx v8, v4, a0 -# CHECK-INST: vsaddu.vx v8, v4, a0 +th.vsaddu.vx v8, v4, a0 +# CHECK-INST: th.vsaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 82 -vsaddu.vi v8, v4, 15, v0.t -# CHECK-INST: vsaddu.vi v8, v4, 15, v0.t +th.vsaddu.vi v8, v4, 15, v0.t +# CHECK-INST: th.vsaddu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 80 -vsaddu.vi v8, v4, 15 -# CHECK-INST: vsaddu.vi v8, v4, 15 +th.vsaddu.vi v8, v4, 15 +# CHECK-INST: th.vsaddu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 82 -vsadd.vv v8, v4, v20, v0.t -# CHECK-INST: vsadd.vv v8, v4, v20, v0.t +th.vsadd.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 84 -vsadd.vv v8, v4, v20 -# CHECK-INST: vsadd.vv v8, v4, v20 +th.vsadd.vv v8, v4, v20 +# CHECK-INST: th.vsadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 86 -vsadd.vx v8, v4, a0, v0.t -# CHECK-INST: vsadd.vx v8, v4, a0, v0.t +th.vsadd.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 84 -vsadd.vx v8, v4, a0 -# CHECK-INST: vsadd.vx v8, v4, a0 +th.vsadd.vx v8, v4, a0 +# CHECK-INST: th.vsadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 86 -vsadd.vi v8, v4, 15, v0.t -# CHECK-INST: vsadd.vi v8, v4, 15, v0.t +th.vsadd.vi v8, v4, 15, v0.t +# CHECK-INST: th.vsadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 84 -vsadd.vi v8, v4, 15 -# CHECK-INST: vsadd.vi v8, v4, 15 +th.vsadd.vi v8, v4, 15 +# CHECK-INST: th.vsadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 86 -vaadd.vv v8, v4, v20, v0.t -# CHECK-INST: vaadd.vv v8, v4, v20, v0.t +th.vaadd.vv v8, v4, v20, v0.t +# CHECK-INST: th.vaadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 90 -vaadd.vv v8, v4, v20 -# CHECK-INST: vaadd.vv v8, v4, v20 +th.vaadd.vv v8, v4, v20 +# CHECK-INST: th.vaadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 92 -vaadd.vx v8, v4, a0, v0.t -# CHECK-INST: vaadd.vx v8, v4, a0, v0.t +th.vaadd.vx v8, v4, a0, v0.t +# CHECK-INST: th.vaadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 90 -vaadd.vx v8, v4, a0 -# CHECK-INST: vaadd.vx v8, v4, a0 +th.vaadd.vx v8, v4, a0 +# CHECK-INST: th.vaadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 92 -vaadd.vi v8, v4, 15, v0.t -# CHECK-INST: vaadd.vi v8, v4, 15, v0.t +th.vaadd.vi v8, v4, 15, v0.t +# CHECK-INST: th.vaadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x90] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 90 -vaadd.vi v8, v4, 15 -# CHECK-INST: vaadd.vi v8, v4, 15 +th.vaadd.vi v8, v4, 15 +# CHECK-INST: th.vaadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x92] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 92 diff --git a/llvm/test/MC/RISCV/rvv0p71/and.s b/llvm/test/MC/RISCV/rvv0p71/and.s index bf0f62b0a8092..7956c5d433eb2 100644 --- a/llvm/test/MC/RISCV/rvv0p71/and.s +++ b/llvm/test/MC/RISCV/rvv0p71/and.s @@ -1,45 +1,45 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vand.vv v8, v4, v20, v0.t -# CHECK-INST: vand.vv v8, v4, v20, v0.t +th.vand.vv v8, v4, v20, v0.t +# CHECK-INST: th.vand.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 24 -vand.vv v8, v4, v20 -# CHECK-INST: vand.vv v8, v4, v20 +th.vand.vv v8, v4, v20 +# CHECK-INST: th.vand.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 26 -vand.vx v8, v4, a0, v0.t -# CHECK-INST: vand.vx v8, v4, a0, v0.t +th.vand.vx v8, v4, a0, v0.t +# CHECK-INST: th.vand.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 24 -vand.vx v8, v4, a0 -# CHECK-INST: vand.vx v8, v4, a0 +th.vand.vx v8, v4, a0 +# CHECK-INST: th.vand.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 26 -vand.vi v8, v4, 15, v0.t -# CHECK-INST: vand.vi v8, v4, 15, v0.t +th.vand.vi v8, v4, 15, v0.t +# CHECK-INST: th.vand.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 24 -vand.vi v8, v4, 15 -# CHECK-INST: vand.vi v8, v4, 15 +th.vand.vi v8, v4, 15 +# CHECK-INST: th.vand.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 26 diff --git a/llvm/test/MC/RISCV/rvv0p71/clip.s b/llvm/test/MC/RISCV/rvv0p71/clip.s index fc1718d29242e..b0d2c6c164096 100644 --- a/llvm/test/MC/RISCV/rvv0p71/clip.s +++ b/llvm/test/MC/RISCV/rvv0p71/clip.s @@ -1,81 +1,81 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vnclipu.vv v8, v4, v20, v0.t -# CHECK-INST: vnclipu.vv v8, v4, v20, v0.t +th.vnclipu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vnclipu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a b8 -vnclipu.vv v8, v4, v20 -# CHECK-INST: vnclipu.vv v8, v4, v20 +th.vnclipu.vv v8, v4, v20 +# CHECK-INST: th.vnclipu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xba] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a ba -vnclipu.vx v8, v4, a0, v0.t -# CHECK-INST: vnclipu.vx v8, v4, a0, v0.t +th.vnclipu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vnclipu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 b8 -vnclipu.vx v8, v4, a0 -# CHECK-INST: vnclipu.vx v8, v4, a0 +th.vnclipu.vx v8, v4, a0 +# CHECK-INST: th.vnclipu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xba] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 ba -vnclipu.vi v8, v4, 31, v0.t -# CHECK-INST: vnclipu.vi v8, v4, 31, v0.t +th.vnclipu.vi v8, v4, 31, v0.t +# CHECK-INST: th.vnclipu.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f b8 -vnclipu.vi v8, v4, 31 -# CHECK-INST: vnclipu.vi v8, v4, 31 +th.vnclipu.vi v8, v4, 31 +# CHECK-INST: th.vnclipu.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xba] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f ba -vnclip.vv v8, v4, v20, v0.t -# CHECK-INST: vnclip.vv v8, v4, v20, v0.t +th.vnclip.vv v8, v4, v20, v0.t +# CHECK-INST: th.vnclip.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xbc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a bc -vnclip.vv v8, v4, v20 -# CHECK-INST: vnclip.vv v8, v4, v20 +th.vnclip.vv v8, v4, v20 +# CHECK-INST: th.vnclip.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xbe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a be -vnclip.vx v8, v4, a0, v0.t -# CHECK-INST: vnclip.vx v8, v4, a0, v0.t +th.vnclip.vx v8, v4, a0, v0.t +# CHECK-INST: th.vnclip.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xbc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 bc -vnclip.vx v8, v4, a0 -# CHECK-INST: vnclip.vx v8, v4, a0 +th.vnclip.vx v8, v4, a0 +# CHECK-INST: th.vnclip.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xbe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 be -vnclip.vi v8, v4, 31, v0.t -# CHECK-INST: vnclip.vi v8, v4, 31, v0.t +th.vnclip.vi v8, v4, 31, v0.t +# CHECK-INST: th.vnclip.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f bc -vnclip.vi v8, v4, 31 -# CHECK-INST: vnclip.vi v8, v4, 31 +th.vnclip.vi v8, v4, 31 +# CHECK-INST: th.vnclip.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f be diff --git a/llvm/test/MC/RISCV/rvv0p71/compare.s b/llvm/test/MC/RISCV/rvv0p71/compare.s index fa19840448cf5..7eb1026d49f1a 100644 --- a/llvm/test/MC/RISCV/rvv0p71/compare.s +++ b/llvm/test/MC/RISCV/rvv0p71/compare.s @@ -1,256 +1,256 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmslt.vv v0, v4, v20, v0.t -# CHECK-INST: vmslt.vv v0, v4, v20, v0.t +th.vmslt.vv v0, v4, v20, v0.t +# CHECK-INST: th.vmslt.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x00,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 00 4a 6c -vmseq.vv v8, v4, v20, v0.t -# CHECK-INST: vmseq.vv v8, v4, v20, v0.t +th.vmseq.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmseq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 60 -vmseq.vv v8, v4, v20 -# CHECK-INST: vmseq.vv v8, v4, v20 +th.vmseq.vv v8, v4, v20 +# CHECK-INST: th.vmseq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 62 -vmseq.vx v8, v4, a0, v0.t -# CHECK-INST: vmseq.vx v8, v4, a0, v0.t +th.vmseq.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmseq.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 60 -vmseq.vx v8, v4, a0 -# CHECK-INST: vmseq.vx v8, v4, a0 +th.vmseq.vx v8, v4, a0 +# CHECK-INST: th.vmseq.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 62 -vmseq.vi v8, v4, 15, v0.t -# CHECK-INST: vmseq.vi v8, v4, 15, v0.t +th.vmseq.vi v8, v4, 15, v0.t +# CHECK-INST: th.vmseq.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 60 -vmseq.vi v8, v4, 15 -# CHECK-INST: vmseq.vi v8, v4, 15 +th.vmseq.vi v8, v4, 15 +# CHECK-INST: th.vmseq.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 62 -vmsne.vv v8, v4, v20, v0.t -# CHECK-INST: vmsne.vv v8, v4, v20, v0.t +th.vmsne.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmsne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 64 -vmsne.vv v8, v4, v20 -# CHECK-INST: vmsne.vv v8, v4, v20 +th.vmsne.vv v8, v4, v20 +# CHECK-INST: th.vmsne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 66 -vmsne.vx v8, v4, a0, v0.t -# CHECK-INST: vmsne.vx v8, v4, a0, v0.t +th.vmsne.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmsne.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 64 -vmsne.vx v8, v4, a0 -# CHECK-INST: vmsne.vx v8, v4, a0 +th.vmsne.vx v8, v4, a0 +# CHECK-INST: th.vmsne.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 66 -vmsne.vi v8, v4, 15, v0.t -# CHECK-INST: vmsne.vi v8, v4, 15, v0.t +th.vmsne.vi v8, v4, 15, v0.t +# CHECK-INST: th.vmsne.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 64 -vmsne.vi v8, v4, 15 -# CHECK-INST: vmsne.vi v8, v4, 15 +th.vmsne.vi v8, v4, 15 +# CHECK-INST: th.vmsne.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 66 -vmsltu.vv v8, v4, v20, v0.t -# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t +th.vmsltu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 68 -vmsltu.vv v8, v4, v20 -# CHECK-INST: vmsltu.vv v8, v4, v20 +th.vmsltu.vv v8, v4, v20 +# CHECK-INST: th.vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 6a -vmsltu.vx v8, v4, a0, v0.t -# CHECK-INST: vmsltu.vx v8, v4, a0, v0.t +th.vmsltu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmsltu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 68 -vmsltu.vx v8, v4, a0 -# CHECK-INST: vmsltu.vx v8, v4, a0 +th.vmsltu.vx v8, v4, a0 +# CHECK-INST: th.vmsltu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 6a -vmslt.vv v8, v4, v20, v0.t -# CHECK-INST: vmslt.vv v8, v4, v20, v0.t +th.vmslt.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 6c -vmslt.vv v8, v4, v20 -# CHECK-INST: vmslt.vv v8, v4, v20 +th.vmslt.vv v8, v4, v20 +# CHECK-INST: th.vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 6e -vmslt.vx v8, v4, a0, v0.t -# CHECK-INST: vmslt.vx v8, v4, a0, v0.t +th.vmslt.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmslt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 6c -vmslt.vx v8, v4, a0 -# CHECK-INST: vmslt.vx v8, v4, a0 +th.vmslt.vx v8, v4, a0 +# CHECK-INST: th.vmslt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 6e -vmsleu.vv v8, v4, v20, v0.t -# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t +th.vmsleu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 70 -vmsleu.vv v8, v4, v20 -# CHECK-INST: vmsleu.vv v8, v4, v20 +th.vmsleu.vv v8, v4, v20 +# CHECK-INST: th.vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 72 -vmsleu.vx v8, v4, a0, v0.t -# CHECK-INST: vmsleu.vx v8, v4, a0, v0.t +th.vmsleu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmsleu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 70 -vmsleu.vx v8, v4, a0 -# CHECK-INST: vmsleu.vx v8, v4, a0 +th.vmsleu.vx v8, v4, a0 +# CHECK-INST: th.vmsleu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 72 -vmsleu.vi v8, v4, 15, v0.t -# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t +th.vmsleu.vi v8, v4, 15, v0.t +# CHECK-INST: th.vmsleu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 70 -vmsleu.vi v8, v4, 15 -# CHECK-INST: vmsleu.vi v8, v4, 15 +th.vmsleu.vi v8, v4, 15 +# CHECK-INST: th.vmsleu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 72 -vmsle.vv v8, v4, v20, v0.t -# CHECK-INST: vmsle.vv v8, v4, v20, v0.t +th.vmsle.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 74 -vmsle.vv v8, v4, v20 -# CHECK-INST: vmsle.vv v8, v4, v20 +th.vmsle.vv v8, v4, v20 +# CHECK-INST: th.vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 76 -vmsle.vx v8, v4, a0, v0.t -# CHECK-INST: vmsle.vx v8, v4, a0, v0.t +th.vmsle.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmsle.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 74 -vmsle.vx v8, v4, a0 -# CHECK-INST: vmsle.vx v8, v4, a0 +th.vmsle.vx v8, v4, a0 +# CHECK-INST: th.vmsle.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 76 -vmsle.vi v8, v4, 15, v0.t -# CHECK-INST: vmsle.vi v8, v4, 15, v0.t +th.vmsle.vi v8, v4, 15, v0.t +# CHECK-INST: th.vmsle.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 74 -vmsle.vi v8, v4, 15 -# CHECK-INST: vmsle.vi v8, v4, 15 +th.vmsle.vi v8, v4, 15 +# CHECK-INST: th.vmsle.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 76 -vmsgtu.vx v8, v4, a0, v0.t -# CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t +th.vmsgtu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmsgtu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 78 -vmsgtu.vx v8, v4, a0 -# CHECK-INST: vmsgtu.vx v8, v4, a0 +th.vmsgtu.vx v8, v4, a0 +# CHECK-INST: th.vmsgtu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 7a -vmsgtu.vi v8, v4, 15, v0.t -# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t +th.vmsgtu.vi v8, v4, 15, v0.t +# CHECK-INST: th.vmsgtu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 78 -vmsgtu.vi v8, v4, 15 -# CHECK-INST: vmsgtu.vi v8, v4, 15 +th.vmsgtu.vi v8, v4, 15 +# CHECK-INST: th.vmsgtu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 7a -vmsgt.vx v8, v4, a0, v0.t -# CHECK-INST: vmsgt.vx v8, v4, a0, v0.t +th.vmsgt.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmsgt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 7c -vmsgt.vx v8, v4, a0 -# CHECK-INST: vmsgt.vx v8, v4, a0 +th.vmsgt.vx v8, v4, a0 +# CHECK-INST: th.vmsgt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 7e -vmsgt.vi v8, v4, 15, v0.t -# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t +th.vmsgt.vi v8, v4, 15, v0.t +# CHECK-INST: th.vmsgt.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 7c -vmsgt.vi v8, v4, 15 -# CHECK-INST: vmsgt.vi v8, v4, 15 +th.vmsgt.vi v8, v4, 15 +# CHECK-INST: th.vmsgt.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 7e diff --git a/llvm/test/MC/RISCV/rvv0p71/convert.s b/llvm/test/MC/RISCV/rvv0p71/convert.s index a3b573bfca2d5..af5ee9ec1f936 100644 --- a/llvm/test/MC/RISCV/rvv0p71/convert.s +++ b/llvm/test/MC/RISCV/rvv0p71/convert.s @@ -1,186 +1,186 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfcvt.xu.f.v v8, v4, v0.t -# CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t +th.vfcvt.xu.f.v v8, v4, v0.t +# CHECK-INST: th.vfcvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x40,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 40 88 -vfcvt.xu.f.v v8, v4 -# CHECK-INST: vfcvt.xu.f.v v8, v4 +th.vfcvt.xu.f.v v8, v4 +# CHECK-INST: th.vfcvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x40,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 40 8a -vfcvt.x.f.v v8, v4, v0.t -# CHECK-INST: vfcvt.x.f.v v8, v4, v0.t +th.vfcvt.x.f.v v8, v4, v0.t +# CHECK-INST: th.vfcvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x40,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 40 88 -vfcvt.x.f.v v8, v4 -# CHECK-INST: vfcvt.x.f.v v8, v4 +th.vfcvt.x.f.v v8, v4 +# CHECK-INST: th.vfcvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x40,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 40 8a -vfcvt.f.xu.v v8, v4, v0.t -# CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t +th.vfcvt.f.xu.v v8, v4, v0.t +# CHECK-INST: th.vfcvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x41,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 41 88 -vfcvt.f.xu.v v8, v4 -# CHECK-INST: vfcvt.f.xu.v v8, v4 +th.vfcvt.f.xu.v v8, v4 +# CHECK-INST: th.vfcvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x41,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 41 8a -vfcvt.f.x.v v8, v4, v0.t -# CHECK-INST: vfcvt.f.x.v v8, v4, v0.t +th.vfcvt.f.x.v v8, v4, v0.t +# CHECK-INST: th.vfcvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x41,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 41 88 -vfcvt.f.x.v v8, v4 -# CHECK-INST: vfcvt.f.x.v v8, v4 +th.vfcvt.f.x.v v8, v4 +# CHECK-INST: th.vfcvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x41,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 41 8a -vfwcvt.xu.f.v v8, v4, v0.t -# CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t +th.vfwcvt.xu.f.v v8, v4, v0.t +# CHECK-INST: th.vfwcvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x44,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 44 88 -vfwcvt.xu.f.v v8, v4 -# CHECK-INST: vfwcvt.xu.f.v v8, v4 +th.vfwcvt.xu.f.v v8, v4 +# CHECK-INST: th.vfwcvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x44,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 44 8a -vfwcvt.x.f.v v8, v4, v0.t -# CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t +th.vfwcvt.x.f.v v8, v4, v0.t +# CHECK-INST: th.vfwcvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x44,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 44 88 -vfwcvt.x.f.v v8, v4 -# CHECK-INST: vfwcvt.x.f.v v8, v4 +th.vfwcvt.x.f.v v8, v4 +# CHECK-INST: th.vfwcvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x44,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 44 8a -vfwcvt.f.xu.v v8, v4, v0.t -# CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t +th.vfwcvt.f.xu.v v8, v4, v0.t +# CHECK-INST: th.vfwcvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 45 88 -vfwcvt.f.xu.v v8, v4 -# CHECK-INST: vfwcvt.f.xu.v v8, v4 +th.vfwcvt.f.xu.v v8, v4 +# CHECK-INST: th.vfwcvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 45 8a -vfwcvt.f.x.v v8, v4, v0.t -# CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t +th.vfwcvt.f.x.v v8, v4, v0.t +# CHECK-INST: th.vfwcvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 45 88 -vfwcvt.f.x.v v8, v4 -# CHECK-INST: vfwcvt.f.x.v v8, v4 +th.vfwcvt.f.x.v v8, v4 +# CHECK-INST: th.vfwcvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 45 8a -vfwcvt.f.f.v v8, v4, v0.t -# CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t +th.vfwcvt.f.f.v v8, v4, v0.t +# CHECK-INST: th.vfwcvt.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x46,0x88] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 46 88 -vfwcvt.f.f.v v8, v4 -# CHECK-INST: vfwcvt.f.f.v v8, v4 +th.vfwcvt.f.f.v v8, v4 +# CHECK-INST: th.vfwcvt.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x46,0x8a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 46 8a -vfncvt.xu.f.v v8, v4, v0.t -# CHECK-INST: vfncvt.xu.f.v v8, v4, v0.t +th.vfncvt.xu.f.v v8, v4, v0.t +# CHECK-INST: th.vfncvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x48,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 48 88 -vfncvt.xu.f.v v4, v4, v0.t -# CHECK-INST: vfncvt.xu.f.v v4, v4, v0.t +th.vfncvt.xu.f.v v4, v4, v0.t +# CHECK-INST: th.vfncvt.xu.f.v v4, v4, v0.t # CHECK-ENCODING: [0x57,0x12,0x48,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 12 48 88 -vfncvt.xu.f.v v8, v4 -# CHECK-INST: vfncvt.xu.f.v v8, v4 +th.vfncvt.xu.f.v v8, v4 +# CHECK-INST: th.vfncvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 48 8a -vfncvt.x.f.v v8, v4, v0.t -# CHECK-INST: vfncvt.x.f.v v8, v4, v0.t +th.vfncvt.x.f.v v8, v4, v0.t +# CHECK-INST: th.vfncvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x48,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 48 88 -vfncvt.x.f.v v8, v4 -# CHECK-INST: vfncvt.x.f.v v8, v4 +th.vfncvt.x.f.v v8, v4 +# CHECK-INST: th.vfncvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x48,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 48 8a -vfncvt.f.xu.v v8, v4, v0.t -# CHECK-INST: vfncvt.f.xu.v v8, v4, v0.t +th.vfncvt.f.xu.v v8, v4, v0.t +# CHECK-INST: th.vfncvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x49,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 49 88 -vfncvt.f.xu.v v8, v4 -# CHECK-INST: vfncvt.f.xu.v v8, v4 +th.vfncvt.f.xu.v v8, v4 +# CHECK-INST: th.vfncvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x49,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 49 8a -vfncvt.f.x.v v8, v4, v0.t -# CHECK-INST: vfncvt.f.x.v v8, v4, v0.t +th.vfncvt.f.x.v v8, v4, v0.t +# CHECK-INST: th.vfncvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x49,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 49 88 -vfncvt.f.x.v v8, v4 -# CHECK-INST: vfncvt.f.x.v v8, v4 +th.vfncvt.f.x.v v8, v4 +# CHECK-INST: th.vfncvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x49,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 94 49 8a -vfncvt.f.f.v v8, v4, v0.t -# CHECK-INST: vfncvt.f.f.v v8, v4, v0.t +th.vfncvt.f.f.v v8, v4, v0.t +# CHECK-INST: th.vfncvt.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 88 -vfncvt.f.f.v v8, v4 -# CHECK-INST: vfncvt.f.f.v v8, v4 +th.vfncvt.f.f.v v8, v4 +# CHECK-INST: th.vfncvt.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 8a diff --git a/llvm/test/MC/RISCV/rvv0p71/div.s b/llvm/test/MC/RISCV/rvv0p71/div.s index 5ad8e27a65bcb..d8ea62af6a83c 100644 --- a/llvm/test/MC/RISCV/rvv0p71/div.s +++ b/llvm/test/MC/RISCV/rvv0p71/div.s @@ -1,105 +1,105 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vdivu.vv v8, v4, v20, v0.t -# CHECK-INST: vdivu.vv v8, v4, v20, v0.t +th.vdivu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vdivu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 80 -vdivu.vv v8, v4, v20 -# CHECK-INST: vdivu.vv v8, v4, v20 +th.vdivu.vv v8, v4, v20 +# CHECK-INST: th.vdivu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 82 -vdivu.vx v8, v4, a0, v0.t -# CHECK-INST: vdivu.vx v8, v4, a0, v0.t +th.vdivu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vdivu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 80 -vdivu.vx v8, v4, a0 -# CHECK-INST: vdivu.vx v8, v4, a0 +th.vdivu.vx v8, v4, a0 +# CHECK-INST: th.vdivu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 82 -vdiv.vv v8, v4, v20, v0.t -# CHECK-INST: vdiv.vv v8, v4, v20, v0.t +th.vdiv.vv v8, v4, v20, v0.t +# CHECK-INST: th.vdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 84 -vdiv.vv v8, v4, v20 -# CHECK-INST: vdiv.vv v8, v4, v20 +th.vdiv.vv v8, v4, v20 +# CHECK-INST: th.vdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 86 -vdiv.vx v8, v4, a0, v0.t -# CHECK-INST: vdiv.vx v8, v4, a0, v0.t +th.vdiv.vx v8, v4, a0, v0.t +# CHECK-INST: th.vdiv.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 84 -vdiv.vx v8, v4, a0 -# CHECK-INST: vdiv.vx v8, v4, a0 +th.vdiv.vx v8, v4, a0 +# CHECK-INST: th.vdiv.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 86 -vremu.vv v8, v4, v20, v0.t -# CHECK-INST: vremu.vv v8, v4, v20, v0.t +th.vremu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vremu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 88 -vremu.vv v8, v4, v20 -# CHECK-INST: vremu.vv v8, v4, v20 +th.vremu.vv v8, v4, v20 +# CHECK-INST: th.vremu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 8a -vremu.vx v8, v4, a0, v0.t -# CHECK-INST: vremu.vx v8, v4, a0, v0.t +th.vremu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vremu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 88 -vremu.vx v8, v4, a0 -# CHECK-INST: vremu.vx v8, v4, a0 +th.vremu.vx v8, v4, a0 +# CHECK-INST: th.vremu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 8a -vrem.vv v8, v4, v20, v0.t -# CHECK-INST: vrem.vv v8, v4, v20, v0.t +th.vrem.vv v8, v4, v20, v0.t +# CHECK-INST: th.vrem.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 8c -vrem.vv v8, v4, v20 -# CHECK-INST: vrem.vv v8, v4, v20 +th.vrem.vv v8, v4, v20 +# CHECK-INST: th.vrem.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 8e -vrem.vx v8, v4, a0, v0.t -# CHECK-INST: vrem.vx v8, v4, a0, v0.t +th.vrem.vx v8, v4, a0, v0.t +# CHECK-INST: th.vrem.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 8c -vrem.vx v8, v4, a0 -# CHECK-INST: vrem.vx v8, v4, a0 +th.vrem.vx v8, v4, a0 +# CHECK-INST: th.vrem.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 8e diff --git a/llvm/test/MC/RISCV/rvv0p71/fadd.s b/llvm/test/MC/RISCV/rvv0p71/fadd.s index 46181865fd908..45a1bc479cabb 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fadd.s +++ b/llvm/test/MC/RISCV/rvv0p71/fadd.s @@ -1,84 +1,84 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfadd.vv v8, v4, v20, v0.t -# CHECK-INST: vfadd.vv v8, v4, v20, v0.t +th.vfadd.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 00 -vfadd.vv v8, v4, v20 -# CHECK-INST: vfadd.vv v8, v4, v20 +th.vfadd.vv v8, v4, v20 +# CHECK-INST: th.vfadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 02 -vfadd.vf v8, v4, fa0, v0.t -# CHECK-INST: vfadd.vf v8, v4, fa0, v0.t +th.vfadd.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfadd.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x00] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 00 -vfadd.vf v8, v4, fa0 -# CHECK-INST: vfadd.vf v8, v4, fa0 +th.vfadd.vf v8, v4, fa0 +# CHECK-INST: th.vfadd.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x02] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 02 -vfwadd.vv v8, v4, v20, v0.t -# CHECK-INST: vfwadd.vv v8, v4, v20, v0.t +th.vfwadd.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a c0 -vfwadd.vv v8, v4, v20 -# CHECK-INST: vfwadd.vv v8, v4, v20 +th.vfwadd.vv v8, v4, v20 +# CHECK-INST: th.vfwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a c2 -vfwadd.vf v8, v4, fa0, v0.t -# CHECK-INST: vfwadd.vf v8, v4, fa0, v0.t +th.vfwadd.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfwadd.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xc0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 c0 -vfwadd.vf v8, v4, fa0 -# CHECK-INST: vfwadd.vf v8, v4, fa0 +th.vfwadd.vf v8, v4, fa0 +# CHECK-INST: th.vfwadd.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xc2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 c2 -vfwadd.wv v8, v4, v20, v0.t -# CHECK-INST: vfwadd.wv v8, v4, v20, v0.t +th.vfwadd.wv v8, v4, v20, v0.t +# CHECK-INST: th.vfwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xd0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a d0 -vfwadd.wv v8, v4, v20 -# CHECK-INST: vfwadd.wv v8, v4, v20 +th.vfwadd.wv v8, v4, v20 +# CHECK-INST: th.vfwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xd2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a d2 -vfwadd.wf v8, v4, fa0, v0.t -# CHECK-INST: vfwadd.wf v8, v4, fa0, v0.t +th.vfwadd.wf v8, v4, fa0, v0.t +# CHECK-INST: th.vfwadd.wf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xd0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 d0 -vfwadd.wf v8, v4, fa0 -# CHECK-INST: vfwadd.wf v8, v4, fa0 +th.vfwadd.wf v8, v4, fa0 +# CHECK-INST: th.vfwadd.wf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xd2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 d2 diff --git a/llvm/test/MC/RISCV/rvv0p71/fcompare.s b/llvm/test/MC/RISCV/rvv0p71/fcompare.s index c93f5d9e92662..c91a1c12b97f5 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fcompare.s +++ b/llvm/test/MC/RISCV/rvv0p71/fcompare.s @@ -1,162 +1,162 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmfeq.vv v8, v4, v20, v0.t -# CHECK-INST: vmfeq.vv v8, v4, v20, v0.t +th.vmfeq.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmfeq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 60 -vmfeq.vv v8, v4, v20 -# CHECK-INST: vmfeq.vv v8, v4, v20 +th.vmfeq.vv v8, v4, v20 +# CHECK-INST: th.vmfeq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 62 -vmfeq.vf v8, v4, fa0, v0.t -# CHECK-INST: vmfeq.vf v8, v4, fa0, v0.t +th.vmfeq.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmfeq.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x60] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 60 -vmfeq.vf v8, v4, fa0 -# CHECK-INST: vmfeq.vf v8, v4, fa0 +th.vmfeq.vf v8, v4, fa0 +# CHECK-INST: th.vmfeq.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x62] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 62 -vmfne.vv v8, v4, v20, v0.t -# CHECK-INST: vmfne.vv v8, v4, v20, v0.t +th.vmfne.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmfne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 70 -vmfne.vv v8, v4, v20 -# CHECK-INST: vmfne.vv v8, v4, v20 +th.vmfne.vv v8, v4, v20 +# CHECK-INST: th.vmfne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 72 -vmfne.vf v8, v4, fa0, v0.t -# CHECK-INST: vmfne.vf v8, v4, fa0, v0.t +th.vmfne.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmfne.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x70] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 70 -vmfne.vf v8, v4, fa0 -# CHECK-INST: vmfne.vf v8, v4, fa0 +th.vmfne.vf v8, v4, fa0 +# CHECK-INST: th.vmfne.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x72] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 72 -vmflt.vv v8, v4, v20, v0.t -# CHECK-INST: vmflt.vv v8, v4, v20, v0.t +th.vmflt.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmflt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 6c -vmflt.vv v8, v4, v20 -# CHECK-INST: vmflt.vv v8, v4, v20 +th.vmflt.vv v8, v4, v20 +# CHECK-INST: th.vmflt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 6e -vmflt.vf v8, v4, fa0, v0.t -# CHECK-INST: vmflt.vf v8, v4, fa0, v0.t +th.vmflt.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmflt.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 6c -vmflt.vf v8, v4, fa0 -# CHECK-INST: vmflt.vf v8, v4, fa0 +th.vmflt.vf v8, v4, fa0 +# CHECK-INST: th.vmflt.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 6e -vmfle.vv v8, v4, v20, v0.t -# CHECK-INST: vmfle.vv v8, v4, v20, v0.t +th.vmfle.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmfle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x64] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 64 -vmfle.vv v8, v4, v20 -# CHECK-INST: vmfle.vv v8, v4, v20 +th.vmfle.vv v8, v4, v20 +# CHECK-INST: th.vmfle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 66 -vmfle.vf v8, v4, fa0, v0.t -# CHECK-INST: vmfle.vf v8, v4, fa0, v0.t +th.vmfle.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmfle.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 64 -vmfle.vf v8, v4, fa0 -# CHECK-INST: vmfle.vf v8, v4, fa0 +th.vmfle.vf v8, v4, fa0 +# CHECK-INST: th.vmfle.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 66 -vmfgt.vf v8, v4, fa0, v0.t -# CHECK-INST: vmfgt.vf v8, v4, fa0, v0.t +th.vmfgt.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmfgt.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x74] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 74 -vmfgt.vf v8, v4, fa0 -# CHECK-INST: vmfgt.vf v8, v4, fa0 +th.vmfgt.vf v8, v4, fa0 +# CHECK-INST: th.vmfgt.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x76] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 76 -vmfge.vf v8, v4, fa0, v0.t -# CHECK-INST: vmfge.vf v8, v4, fa0, v0.t +th.vmfge.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmfge.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x7c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 7c -vmfge.vf v8, v4, fa0 -# CHECK-INST: vmfge.vf v8, v4, fa0 +th.vmfge.vf v8, v4, fa0 +# CHECK-INST: th.vmfge.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x7e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 7e -vmford.vv v8, v4, v20, v0.t -# CHECK-INST: vmford.vv v8, v4, v20, v0.t +th.vmford.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmford.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 68 -vmford.vv v8, v4, v20 -# CHECK-INST: vmford.vv v8, v4, v20 +th.vmford.vv v8, v4, v20 +# CHECK-INST: th.vmford.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 6a -vmford.vf v8, v4, fa0, v0.t -# CHECK-INST: vmford.vf v8, v4, fa0, v0.t +th.vmford.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vmford.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 68 -vmford.vf v8, v4, fa0 -# CHECK-INST: vmford.vf v8, v4, fa0 +th.vmford.vf v8, v4, fa0 +# CHECK-INST: th.vmford.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 6a -vmfeq.vv v0, v4, v20, v0.t -# CHECK-INST: vmfeq.vv v0, v4, v20, v0.t +th.vmfeq.vv v0, v4, v20, v0.t +# CHECK-INST: th.vmfeq.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x10,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 10 4a 60 diff --git a/llvm/test/MC/RISCV/rvv0p71/fdiv.s b/llvm/test/MC/RISCV/rvv0p71/fdiv.s index add4e1413d181..2062a0355b985 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fdiv.s +++ b/llvm/test/MC/RISCV/rvv0p71/fdiv.s @@ -1,48 +1,48 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfdiv.vv v8, v4, v20, v0.t -# CHECK-INST: vfdiv.vv v8, v4, v20, v0.t +th.vfdiv.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 80 -vfdiv.vv v8, v4, v20 -# CHECK-INST: vfdiv.vv v8, v4, v20 +th.vfdiv.vv v8, v4, v20 +# CHECK-INST: th.vfdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 82 -vfdiv.vf v8, v4, fa0, v0.t -# CHECK-INST: vfdiv.vf v8, v4, fa0, v0.t +th.vfdiv.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfdiv.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 80 -vfdiv.vf v8, v4, fa0 -# CHECK-INST: vfdiv.vf v8, v4, fa0 +th.vfdiv.vf v8, v4, fa0 +# CHECK-INST: th.vfdiv.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 82 -vfrdiv.vf v8, v4, fa0, v0.t -# CHECK-INST: vfrdiv.vf v8, v4, fa0, v0.t +th.vfrdiv.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfrdiv.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 84 -vfrdiv.vf v8, v4, fa0 -# CHECK-INST: vfrdiv.vf v8, v4, fa0 +th.vfrdiv.vf v8, v4, fa0 +# CHECK-INST: th.vfrdiv.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 86 diff --git a/llvm/test/MC/RISCV/rvv0p71/fmacc.s b/llvm/test/MC/RISCV/rvv0p71/fmacc.s index b674658f1f2d8..f13115ba240c2 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fmacc.s +++ b/llvm/test/MC/RISCV/rvv0p71/fmacc.s @@ -1,300 +1,300 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vfmacc.vv v8, v20, v4, v0.t +th.vfmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a b0 -vfmacc.vv v8, v20, v4 -# CHECK-INST: vfmacc.vv v8, v20, v4 +th.vfmacc.vv v8, v20, v4 +# CHECK-INST: th.vfmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xb2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a b2 -vfmacc.vf v8, fa0, v4, v0.t -# CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t +th.vfmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 b0 -vfmacc.vf v8, fa0, v4 -# CHECK-INST: vfmacc.vf v8, fa0, v4 +th.vfmacc.vf v8, fa0, v4 +# CHECK-INST: th.vfmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xb2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 b2 -vfnmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t +th.vfnmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfnmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a b4 -vfnmacc.vv v8, v20, v4 -# CHECK-INST: vfnmacc.vv v8, v20, v4 +th.vfnmacc.vv v8, v20, v4 +# CHECK-INST: th.vfnmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a b6 -vfnmacc.vf v8, fa0, v4, v0.t -# CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t +th.vfnmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfnmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 b4 -vfnmacc.vf v8, fa0, v4 -# CHECK-INST: vfnmacc.vf v8, fa0, v4 +th.vfnmacc.vf v8, fa0, v4 +# CHECK-INST: th.vfnmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 b6 -vfmsac.vv v8, v20, v4, v0.t -# CHECK-INST: vfmsac.vv v8, v20, v4, v0.t +th.vfmsac.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a b8 -vfmsac.vv v8, v20, v4 -# CHECK-INST: vfmsac.vv v8, v20, v4 +th.vfmsac.vv v8, v20, v4 +# CHECK-INST: th.vfmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xba] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a ba -vfmsac.vf v8, fa0, v4, v0.t -# CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t +th.vfmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 b8 -vfmsac.vf v8, fa0, v4 -# CHECK-INST: vfmsac.vf v8, fa0, v4 +th.vfmsac.vf v8, fa0, v4 +# CHECK-INST: th.vfmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xba] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 ba -vfnmsac.vv v8, v20, v4, v0.t -# CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t +th.vfnmsac.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a bc -vfnmsac.vv v8, v20, v4 -# CHECK-INST: vfnmsac.vv v8, v20, v4 +th.vfnmsac.vv v8, v20, v4 +# CHECK-INST: th.vfnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a be -vfnmsac.vf v8, fa0, v4, v0.t -# CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t +th.vfnmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfnmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 bc -vfnmsac.vf v8, fa0, v4 -# CHECK-INST: vfnmsac.vf v8, fa0, v4 +th.vfnmsac.vf v8, fa0, v4 +# CHECK-INST: th.vfnmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 be -vfmadd.vv v8, v20, v4, v0.t -# CHECK-INST: vfmadd.vv v8, v20, v4, v0.t +th.vfmadd.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a a0 -vfmadd.vv v8, v20, v4 -# CHECK-INST: vfmadd.vv v8, v20, v4 +th.vfmadd.vv v8, v20, v4 +# CHECK-INST: th.vfmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xa2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a a2 -vfmadd.vf v8, fa0, v4, v0.t -# CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t +th.vfmadd.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfmadd.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 a0 -vfmadd.vf v8, fa0, v4 -# CHECK-INST: vfmadd.vf v8, fa0, v4 +th.vfmadd.vf v8, fa0, v4 +# CHECK-INST: th.vfmadd.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xa2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 a2 -vfnmadd.vv v8, v20, v4, v0.t -# CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t +th.vfnmadd.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfnmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a a4 -vfnmadd.vv v8, v20, v4 -# CHECK-INST: vfnmadd.vv v8, v20, v4 +th.vfnmadd.vv v8, v20, v4 +# CHECK-INST: th.vfnmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a a6 -vfnmadd.vf v8, fa0, v4, v0.t -# CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t +th.vfnmadd.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfnmadd.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 a4 -vfnmadd.vf v8, fa0, v4 -# CHECK-INST: vfnmadd.vf v8, fa0, v4 +th.vfnmadd.vf v8, fa0, v4 +# CHECK-INST: th.vfnmadd.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 a6 -vfmsub.vv v8, v20, v4, v0.t -# CHECK-INST: vfmsub.vv v8, v20, v4, v0.t +th.vfmsub.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a a8 -vfmsub.vv v8, v20, v4 -# CHECK-INST: vfmsub.vv v8, v20, v4 +th.vfmsub.vv v8, v20, v4 +# CHECK-INST: th.vfmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xaa] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a aa -vfmsub.vf v8, fa0, v4, v0.t -# CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t +th.vfmsub.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfmsub.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 a8 -vfmsub.vf v8, fa0, v4 -# CHECK-INST: vfmsub.vf v8, fa0, v4 +th.vfmsub.vf v8, fa0, v4 +# CHECK-INST: th.vfmsub.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xaa] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 aa -vfnmsub.vv v8, v20, v4, v0.t -# CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t +th.vfnmsub.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a ac -vfnmsub.vv v8, v20, v4 -# CHECK-INST: vfnmsub.vv v8, v20, v4 +th.vfnmsub.vv v8, v20, v4 +# CHECK-INST: th.vfnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a ae -vfnmsub.vf v8, fa0, v4, v0.t -# CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t +th.vfnmsub.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfnmsub.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 ac -vfnmsub.vf v8, fa0, v4 -# CHECK-INST: vfnmsub.vf v8, fa0, v4 +th.vfnmsub.vf v8, fa0, v4 +# CHECK-INST: th.vfnmsub.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 ae -vfwmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t +th.vfwmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a f0 -vfwmacc.vv v8, v20, v4 -# CHECK-INST: vfwmacc.vv v8, v20, v4 +th.vfwmacc.vv v8, v20, v4 +# CHECK-INST: th.vfwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xf2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a f2 -vfwmacc.vf v8, fa0, v4, v0.t -# CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t +th.vfwmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfwmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 f0 -vfwmacc.vf v8, fa0, v4 -# CHECK-INST: vfwmacc.vf v8, fa0, v4 +th.vfwmacc.vf v8, fa0, v4 +# CHECK-INST: th.vfwmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xf2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 f2 -vfwnmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t +th.vfwnmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfwnmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a f4 -vfwnmacc.vv v8, v20, v4 -# CHECK-INST: vfwnmacc.vv v8, v20, v4 +th.vfwnmacc.vv v8, v20, v4 +# CHECK-INST: th.vfwnmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xf6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a f6 -vfwnmacc.vf v8, fa0, v4, v0.t -# CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t +th.vfwnmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfwnmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 f4 -vfwnmacc.vf v8, fa0, v4 -# CHECK-INST: vfwnmacc.vf v8, fa0, v4 +th.vfwnmacc.vf v8, fa0, v4 +# CHECK-INST: th.vfwnmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xf6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 f6 -vfwmsac.vv v8, v20, v4, v0.t -# CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t +th.vfwmsac.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfwmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a f8 -vfwmsac.vv v8, v20, v4 -# CHECK-INST: vfwmsac.vv v8, v20, v4 +th.vfwmsac.vv v8, v20, v4 +# CHECK-INST: th.vfwmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xfa] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a fa -vfwmsac.vf v8, fa0, v4, v0.t -# CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t +th.vfwmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfwmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 f8 -vfwmsac.vf v8, fa0, v4 -# CHECK-INST: vfwmsac.vf v8, fa0, v4 +th.vfwmsac.vf v8, fa0, v4 +# CHECK-INST: th.vfwmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xfa] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 fa -vfwnmsac.vv v8, v20, v4, v0.t -# CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t +th.vfwnmsac.vv v8, v20, v4, v0.t +# CHECK-INST: th.vfwnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xfc] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a fc -vfwnmsac.vv v8, v20, v4 -# CHECK-INST: vfwnmsac.vv v8, v20, v4 +th.vfwnmsac.vv v8, v20, v4 +# CHECK-INST: th.vfwnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xfe] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a fe -vfwnmsac.vf v8, fa0, v4, v0.t -# CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t +th.vfwnmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: th.vfwnmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xfc] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 fc -vfwnmsac.vf v8, fa0, v4 -# CHECK-INST: vfwnmsac.vf v8, fa0, v4 +th.vfwnmsac.vf v8, fa0, v4 +# CHECK-INST: th.vfwnmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xfe] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 fe diff --git a/llvm/test/MC/RISCV/rvv0p71/fminmax.s b/llvm/test/MC/RISCV/rvv0p71/fminmax.s index ea14e11c395ef..6feb8fb361bca 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fminmax.s +++ b/llvm/test/MC/RISCV/rvv0p71/fminmax.s @@ -1,60 +1,60 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfmin.vv v8, v4, v20, v0.t -# CHECK-INST: vfmin.vv v8, v4, v20, v0.t +th.vfmin.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 10 -vfmin.vv v8, v4, v20 -# CHECK-INST: vfmin.vv v8, v4, v20 +th.vfmin.vv v8, v4, v20 +# CHECK-INST: th.vfmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 12 -vfmin.vf v8, v4, fa0, v0.t -# CHECK-INST: vfmin.vf v8, v4, fa0, v0.t +th.vfmin.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfmin.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x10] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 10 -vfmin.vf v8, v4, fa0 -# CHECK-INST: vfmin.vf v8, v4, fa0 +th.vfmin.vf v8, v4, fa0 +# CHECK-INST: th.vfmin.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x12] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 12 -vfmax.vv v8, v4, v20, v0.t -# CHECK-INST: vfmax.vv v8, v4, v20, v0.t +th.vfmax.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 18 -vfmax.vv v8, v4, v20 -# CHECK-INST: vfmax.vv v8, v4, v20 +th.vfmax.vv v8, v4, v20 +# CHECK-INST: th.vfmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 1a -vfmax.vf v8, v4, fa0, v0.t -# CHECK-INST: vfmax.vf v8, v4, fa0, v0.t +th.vfmax.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfmax.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x18] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 18 -vfmax.vf v8, v4, fa0 -# CHECK-INST: vfmax.vf v8, v4, fa0 +th.vfmax.vf v8, v4, fa0 +# CHECK-INST: th.vfmax.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x1a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 1a diff --git a/llvm/test/MC/RISCV/rvv0p71/fmul.s b/llvm/test/MC/RISCV/rvv0p71/fmul.s index b492e2dd8b427..0909cdc047b6a 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fmul.s +++ b/llvm/test/MC/RISCV/rvv0p71/fmul.s @@ -1,60 +1,60 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfmul.vv v8, v4, v20, v0.t -# CHECK-INST: vfmul.vv v8, v4, v20, v0.t +th.vfmul.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 90 -vfmul.vv v8, v4, v20 -# CHECK-INST: vfmul.vv v8, v4, v20 +th.vfmul.vv v8, v4, v20 +# CHECK-INST: th.vfmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 92 -vfmul.vf v8, v4, fa0, v0.t -# CHECK-INST: vfmul.vf v8, v4, fa0, v0.t +th.vfmul.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfmul.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 90 -vfmul.vf v8, v4, fa0 -# CHECK-INST: vfmul.vf v8, v4, fa0 +th.vfmul.vf v8, v4, fa0 +# CHECK-INST: th.vfmul.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 92 -vfwmul.vv v8, v4, v20, v0.t -# CHECK-INST: vfwmul.vv v8, v4, v20, v0.t +th.vfwmul.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xe0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a e0 -vfwmul.vv v8, v4, v20 -# CHECK-INST: vfwmul.vv v8, v4, v20 +th.vfwmul.vv v8, v4, v20 +# CHECK-INST: th.vfwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xe2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a e2 -vfwmul.vf v8, v4, fa0, v0.t -# CHECK-INST: vfwmul.vf v8, v4, fa0, v0.t +th.vfwmul.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfwmul.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xe0] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 e0 -vfwmul.vf v8, v4, fa0 -# CHECK-INST: vfwmul.vf v8, v4, fa0 +th.vfwmul.vf v8, v4, fa0 +# CHECK-INST: th.vfwmul.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xe2] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 e2 diff --git a/llvm/test/MC/RISCV/rvv0p71/fmv.s b/llvm/test/MC/RISCV/rvv0p71/fmv.s index 33abaf6bffcf5..dd30247b96810 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fmv.s +++ b/llvm/test/MC/RISCV/rvv0p71/fmv.s @@ -1,30 +1,30 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfmv.v.f v8, fa0 -# CHECK-INST: vfmv.v.f v8, fa0 +th.vfmv.v.f v8, fa0 +# CHECK-INST: th.vfmv.v.f v8, fa0 # CHECK-ENCODING: [0x57,0x54,0x05,0x5e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 05 5e -vfmv.f.s fa0, v4 -# CHECK-INST: vfmv.f.s fa0, v4 +th.vfmv.f.s fa0, v4 +# CHECK-INST: th.vfmv.f.s fa0, v4 # CHECK-ENCODING: [0x57,0x15,0x40,0x32] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 15 40 32 -vfmv.s.f v8, fa0 -# CHECK-INST: vfmv.s.f v8, fa0 +th.vfmv.s.f v8, fa0 +# CHECK-INST: th.vfmv.s.f v8, fa0 # CHECK-ENCODING: [0x57,0x54,0x05,0x36] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 05 36 diff --git a/llvm/test/MC/RISCV/rvv0p71/fothers.s b/llvm/test/MC/RISCV/rvv0p71/fothers.s index b8cc07a2eced6..c8ea8a6d173c6 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fothers.s +++ b/llvm/test/MC/RISCV/rvv0p71/fothers.s @@ -1,40 +1,40 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f --riscv-no-aliases \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: --mattr=+f | llvm-objdump -d --mattr=+xtheadv --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: --mattr=+f | llvm-objdump -d --mattr=+xtheadvector --mattr=+f -M no-aliases - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfsqrt.v v8, v4, v0.t -# CHECK-INST: vfsqrt.v v8, v4, v0.t +th.vfsqrt.v v8, v4, v0.t +# CHECK-INST: th.vfsqrt.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x40,0x8c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 40 8c -vfsqrt.v v8, v4 -# CHECK-INST: vfsqrt.v v8, v4 +th.vfsqrt.v v8, v4 +# CHECK-INST: th.vfsqrt.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x40,0x8e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 40 8e -vfclass.v v8, v4, v0.t -# CHECK-INST: vfclass.v v8, v4, v0.t +th.vfclass.v v8, v4, v0.t +# CHECK-INST: th.vfclass.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x48,0x8c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 48 8c -vfclass.v v8, v4 -# CHECK-INST: vfclass.v v8, v4 +th.vfclass.v v8, v4 +# CHECK-INST: th.vfclass.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x8e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 48 8e -vfmerge.vfm v8, v4, fa0, v0 -# CHECK-INST: vfmerge.vfm v8, v4, fa0, v0 +th.vfmerge.vfm v8, v4, fa0, v0 +# CHECK-INST: th.vfmerge.vfm v8, v4, fa0, v0 # CHECK-ENCODING: [0x57,0x54,0x45,0x5c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 5c diff --git a/llvm/test/MC/RISCV/rvv0p71/freduction.s b/llvm/test/MC/RISCV/rvv0p71/freduction.s index a200a0e690268..39db3c113b10a 100644 --- a/llvm/test/MC/RISCV/rvv0p71/freduction.s +++ b/llvm/test/MC/RISCV/rvv0p71/freduction.s @@ -1,90 +1,90 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f --riscv-no-aliases \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f \ # RUN: -M no-aliases - | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfredosum.vs v8, v4, v20, v0.t -# CHECK-INST: vfredosum.vs v8, v4, v20, v0.t +th.vfredosum.vs v8, v4, v20, v0.t +# CHECK-INST: th.vfredosum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 0c -vfredosum.vs v8, v4, v20 -# CHECK-INST: vfredosum.vs v8, v4, v20 +th.vfredosum.vs v8, v4, v20 +# CHECK-INST: th.vfredosum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x0e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 0e -vfredsum.vs v8, v4, v20, v0.t -# CHECK-INST: vfredsum.vs v8, v4, v20, v0.t +th.vfredsum.vs v8, v4, v20, v0.t +# CHECK-INST: th.vfredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x04] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 04 -vfredsum.vs v8, v4, v20 -# CHECK-INST: vfredsum.vs v8, v4, v20 +th.vfredsum.vs v8, v4, v20 +# CHECK-INST: th.vfredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x06] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 06 -vfredmax.vs v8, v4, v20, v0.t -# CHECK-INST: vfredmax.vs v8, v4, v20, v0.t +th.vfredmax.vs v8, v4, v20, v0.t +# CHECK-INST: th.vfredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 1c -vfredmax.vs v8, v4, v20 -# CHECK-INST: vfredmax.vs v8, v4, v20 +th.vfredmax.vs v8, v4, v20 +# CHECK-INST: th.vfredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 1e -vfredmin.vs v8, v4, v20, v0.t -# CHECK-INST: vfredmin.vs v8, v4, v20, v0.t +th.vfredmin.vs v8, v4, v20, v0.t +# CHECK-INST: th.vfredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 14 -vfredmin.vs v8, v4, v20 -# CHECK-INST: vfredmin.vs v8, v4, v20 +th.vfredmin.vs v8, v4, v20 +# CHECK-INST: th.vfredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 16 -vfwredosum.vs v8, v4, v20, v0.t -# CHECK-INST: vfwredosum.vs v8, v4, v20, v0.t +th.vfwredosum.vs v8, v4, v20, v0.t +# CHECK-INST: th.vfwredosum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xcc] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a cc -vfwredosum.vs v8, v4, v20 -# CHECK-INST: vfwredosum.vs v8, v4, v20 +th.vfwredosum.vs v8, v4, v20 +# CHECK-INST: th.vfwredosum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xce] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a ce -vfwredsum.vs v8, v4, v20, v0.t -# CHECK-INST: vfwredsum.vs v8, v4, v20, v0.t +th.vfwredsum.vs v8, v4, v20, v0.t +# CHECK-INST: th.vfwredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a c4 -vfwredsum.vs v8, v4, v20 -# CHECK-INST: vfwredsum.vs v8, v4, v20 +th.vfwredsum.vs v8, v4, v20 +# CHECK-INST: th.vfwredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a c6 -vfredosum.vs v0, v4, v20, v0.t -# CHECK-INST: vfredosum.vs v0, v4, v20, v0.t +th.vfredosum.vs v0, v4, v20, v0.t +# CHECK-INST: th.vfredosum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x10,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 10 4a 0c diff --git a/llvm/test/MC/RISCV/rvv0p71/fsub.s b/llvm/test/MC/RISCV/rvv0p71/fsub.s index b5816e542057b..5cc69d9a5d844 100644 --- a/llvm/test/MC/RISCV/rvv0p71/fsub.s +++ b/llvm/test/MC/RISCV/rvv0p71/fsub.s @@ -1,96 +1,96 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfsub.vv v8, v4, v20, v0.t -# CHECK-INST: vfsub.vv v8, v4, v20, v0.t +th.vfsub.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 08 -vfsub.vv v8, v4, v20 -# CHECK-INST: vfsub.vv v8, v4, v20 +th.vfsub.vv v8, v4, v20 +# CHECK-INST: th.vfsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 0a -vfsub.vf v8, v4, fa0, v0.t -# CHECK-INST: vfsub.vf v8, v4, fa0, v0.t +th.vfsub.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x08] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 08 -vfsub.vf v8, v4, fa0 -# CHECK-INST: vfsub.vf v8, v4, fa0 +th.vfsub.vf v8, v4, fa0 +# CHECK-INST: th.vfsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x0a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 0a -vfrsub.vf v8, v4, fa0, v0.t -# CHECK-INST: vfrsub.vf v8, v4, fa0, v0.t +th.vfrsub.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfrsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 9c -vfrsub.vf v8, v4, fa0 -# CHECK-INST: vfrsub.vf v8, v4, fa0 +th.vfrsub.vf v8, v4, fa0 +# CHECK-INST: th.vfrsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 9e -vfwsub.vv v8, v4, v20, v0.t -# CHECK-INST: vfwsub.vv v8, v4, v20, v0.t +th.vfwsub.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a c8 -vfwsub.vv v8, v4, v20 -# CHECK-INST: vfwsub.vv v8, v4, v20 +th.vfwsub.vv v8, v4, v20 +# CHECK-INST: th.vfwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xca] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a ca -vfwsub.vf v8, v4, fa0, v0.t -# CHECK-INST: vfwsub.vf v8, v4, fa0, v0.t +th.vfwsub.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfwsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xc8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 c8 -vfwsub.vf v8, v4, fa0 -# CHECK-INST: vfwsub.vf v8, v4, fa0 +th.vfwsub.vf v8, v4, fa0 +# CHECK-INST: th.vfwsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xca] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 ca -vfwsub.wv v8, v4, v20, v0.t -# CHECK-INST: vfwsub.wv v8, v4, v20, v0.t +th.vfwsub.wv v8, v4, v20, v0.t +# CHECK-INST: th.vfwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xd8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a d8 -vfwsub.wv v8, v4, v20 -# CHECK-INST: vfwsub.wv v8, v4, v20 +th.vfwsub.wv v8, v4, v20 +# CHECK-INST: th.vfwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xda] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a da -vfwsub.wf v8, v4, fa0, v0.t -# CHECK-INST: vfwsub.wf v8, v4, fa0, v0.t +th.vfwsub.wf v8, v4, fa0, v0.t +# CHECK-INST: th.vfwsub.wf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xd8] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 d8 -vfwsub.wf v8, v4, fa0 -# CHECK-INST: vfwsub.wf v8, v4, fa0 +th.vfwsub.wf v8, v4, fa0 +# CHECK-INST: th.vfwsub.wf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xda] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 da diff --git a/llvm/test/MC/RISCV/rvv0p71/invalid.s b/llvm/test/MC/RISCV/rvv0p71/invalid.s index e275a595b2f3b..573a3cfe37d1b 100644 --- a/llvm/test/MC/RISCV/rvv0p71/invalid.s +++ b/llvm/test/MC/RISCV/rvv0p71/invalid.s @@ -1,14 +1,14 @@ -# RUN: not llvm-mc -triple=riscv64 --mattr=+xtheadv %s 2>&1 \ +# RUN: not llvm-mc -triple=riscv64 --mattr=+xtheadvector %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -vmsge.vx v2, v4, a0, v0.t, v0 +th.vmsge.vx v2, v4, a0, v0.t, v0 # CHECK-ERROR: invalid operand for instruction -vmsgeu.vx v2, v4, a0, v0.t, v0 +th.vmsgeu.vx v2, v4, a0, v0.t, v0 # CHECK-ERROR: invalid operand for instruction -vmsge.vx v2, v4, a0, v0.t, v2 +th.vmsge.vx v2, v4, a0, v0.t, v2 # CHECK-ERROR: The temporary vector register cannot be the same as the destination register. -vmsgeu.vx v2, v4, a0, v0.t, v2 +th.vmsgeu.vx v2, v4, a0, v0.t, v2 # CHECK-ERROR: The temporary vector register cannot be the same as the destination register. diff --git a/llvm/test/MC/RISCV/rvv0p71/load.s b/llvm/test/MC/RISCV/rvv0p71/load.s index 025745218fa9d..3832152ffa8e2 100644 --- a/llvm/test/MC/RISCV/rvv0p71/load.s +++ b/llvm/test/MC/RISCV/rvv0p71/load.s @@ -1,345 +1,345 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv -M no-aliases - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector -M no-aliases - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vlb.v v8, (a0), v0.t -# CHECK-INST: vlb.v v8, (a0), v0.t +th.vlb.v v8, (a0), v0.t +# CHECK-INST: th.vlb.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x10] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 10 -vlb.v v8, (a0) -# CHECK-INST: vlb.v v8, (a0) +th.vlb.v v8, (a0) +# CHECK-INST: th.vlb.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x12] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 12 -vlh.v v8, (a0), v0.t -# CHECK-INST: vlh.v v8, (a0), v0.t +th.vlh.v v8, (a0), v0.t +# CHECK-INST: th.vlh.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x10] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 10 -vlh.v v8, (a0) -# CHECK-INST: vlh.v v8, (a0) +th.vlh.v v8, (a0) +# CHECK-INST: th.vlh.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x12] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 12 -vlw.v v8, (a0), v0.t -# CHECK-INST: vlw.v v8, (a0), v0.t +th.vlw.v v8, (a0), v0.t +# CHECK-INST: th.vlw.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x10] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 10 -vlw.v v8, (a0) -# CHECK-INST: vlw.v v8, (a0) +th.vlw.v v8, (a0) +# CHECK-INST: th.vlw.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x12] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 12 -vlbu.v v8, (a0), v0.t -# CHECK-INST: vlbu.v v8, (a0), v0.t +th.vlbu.v v8, (a0), v0.t +# CHECK-INST: th.vlbu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 00 -vlbu.v v8, (a0) -# CHECK-INST: vlbu.v v8, (a0) +th.vlbu.v v8, (a0) +# CHECK-INST: th.vlbu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 02 -vlhu.v v8, (a0), v0.t -# CHECK-INST: vlhu.v v8, (a0), v0.t +th.vlhu.v v8, (a0), v0.t +# CHECK-INST: th.vlhu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 00 -vlhu.v v8, (a0) -# CHECK-INST: vlhu.v v8, (a0) +th.vlhu.v v8, (a0) +# CHECK-INST: th.vlhu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 02 -vlwu.v v8, (a0), v0.t -# CHECK-INST: vlwu.v v8, (a0), v0.t +th.vlwu.v v8, (a0), v0.t +# CHECK-INST: th.vlwu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 00 -vlwu.v v8, (a0) -# CHECK-INST: vlwu.v v8, (a0) +th.vlwu.v v8, (a0) +# CHECK-INST: th.vlwu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 02 -vle.v v8, (a0), v0.t -# CHECK-INST: vle.v v8, (a0), v0.t +th.vle.v v8, (a0), v0.t +# CHECK-INST: th.vle.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 00 -vle.v v8, (a0) -# CHECK-INST: vle.v v8, (a0) +th.vle.v v8, (a0) +# CHECK-INST: th.vle.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 02 -vlsb.v v8, (a0), a1, v0.t -# CHECK-INST: vlsb.v v8, (a0), a1, v0.t +th.vlsb.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsb.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x18] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 18 -vlsb.v v8, (a0), a1 -# CHECK-INST: vlsb.v v8, (a0), a1 +th.vlsb.v v8, (a0), a1 +# CHECK-INST: th.vlsb.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x1a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 1a -vlsh.v v8, (a0), a1, v0.t -# CHECK-INST: vlsh.v v8, (a0), a1, v0.t +th.vlsh.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsh.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x18] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 18 -vlsh.v v8, (a0), a1 -# CHECK-INST: vlsh.v v8, (a0), a1 +th.vlsh.v v8, (a0), a1 +# CHECK-INST: th.vlsh.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x1a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 1a -vlsw.v v8, (a0), a1, v0.t -# CHECK-INST: vlsw.v v8, (a0), a1, v0.t +th.vlsw.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsw.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x18] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 18 -vlsw.v v8, (a0), a1 -# CHECK-INST: vlsw.v v8, (a0), a1 +th.vlsw.v v8, (a0), a1 +# CHECK-INST: th.vlsw.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x1a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 1a -vlsbu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t +th.vlsbu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsbu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 08 -vlsbu.v v8, (a0), a1 -# CHECK-INST: vlsbu.v v8, (a0), a1 +th.vlsbu.v v8, (a0), a1 +# CHECK-INST: th.vlsbu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 0a -vlshu.v v8, (a0), a1, v0.t -# CHECK-INST: vlshu.v v8, (a0), a1, v0.t +th.vlshu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlshu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 08 -vlshu.v v8, (a0), a1 -# CHECK-INST: vlshu.v v8, (a0), a1 +th.vlshu.v v8, (a0), a1 +# CHECK-INST: th.vlshu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 0a -vlswu.v v8, (a0), a1, v0.t -# CHECK-INST: vlswu.v v8, (a0), a1, v0.t +th.vlswu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlswu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 08 -vlswu.v v8, (a0), a1 -# CHECK-INST: vlswu.v v8, (a0), a1 +th.vlswu.v v8, (a0), a1 +# CHECK-INST: th.vlswu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 0a -vlse.v v8, (a0), a1, v0.t -# CHECK-INST: vlse.v v8, (a0), a1, v0.t +th.vlse.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlse.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 08 -vlse.v v8, (a0), a1 -# CHECK-INST: vlse.v v8, (a0), a1 +th.vlse.v v8, (a0), a1 +# CHECK-INST: th.vlse.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 0a -vlxb.v v8, (a0), v4, v0.t -# CHECK-INST: vlxb.v v8, (a0), v4, v0.t +th.vlxb.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxb.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 1c -vlxb.v v8, (a0), v4 -# CHECK-INST: vlxb.v v8, (a0), v4 +th.vlxb.v v8, (a0), v4 +# CHECK-INST: th.vlxb.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 1e -vlxh.v v8, (a0), v4, v0.t -# CHECK-INST: vlxh.v v8, (a0), v4, v0.t +th.vlxh.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxh.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 1c -vlxh.v v8, (a0), v4 -# CHECK-INST: vlxh.v v8, (a0), v4 +th.vlxh.v v8, (a0), v4 +# CHECK-INST: th.vlxh.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 1e -vlxw.v v8, (a0), v4, v0.t -# CHECK-INST: vlxw.v v8, (a0), v4, v0.t +th.vlxw.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxw.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 1c -vlxw.v v8, (a0), v4 -# CHECK-INST: vlxw.v v8, (a0), v4 +th.vlxw.v v8, (a0), v4 +# CHECK-INST: th.vlxw.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 1e -vlxbu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t +th.vlxbu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxbu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 0c -vlxbu.v v8, (a0), v4 -# CHECK-INST: vlxbu.v v8, (a0), v4 +th.vlxbu.v v8, (a0), v4 +# CHECK-INST: th.vlxbu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 0e -vlxhu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t +th.vlxhu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxhu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 0c -vlxhu.v v8, (a0), v4 -# CHECK-INST: vlxhu.v v8, (a0), v4 +th.vlxhu.v v8, (a0), v4 +# CHECK-INST: th.vlxhu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 0e -vlxwu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t +th.vlxwu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxwu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 0c -vlxwu.v v8, (a0), v4 -# CHECK-INST: vlxwu.v v8, (a0), v4 +th.vlxwu.v v8, (a0), v4 +# CHECK-INST: th.vlxwu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 0e -vlxe.v v8, (a0), v4, v0.t -# CHECK-INST: vlxe.v v8, (a0), v4, v0.t +th.vlxe.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxe.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 0c -vlxe.v v8, (a0), v4 -# CHECK-INST: vlxe.v v8, (a0), v4 +th.vlxe.v v8, (a0), v4 +# CHECK-INST: th.vlxe.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 0e -vlbff.v v8, (a0) -# CHECK-INST: vlbff.v v8, (a0) +th.vlbff.v v8, (a0) +# CHECK-INST: th.vlbff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x13] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 13 -vlbff.v v8, (a0), v0.t -# CHECK-INST: vlbff.v v8, (a0), v0.t +th.vlbff.v v8, (a0), v0.t +# CHECK-INST: th.vlbff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x11] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 11 -vlhff.v v8, (a0) -# CHECK-INST: vlhff.v v8, (a0) +th.vlhff.v v8, (a0) +# CHECK-INST: th.vlhff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x13] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 13 -vlhff.v v8, (a0), v0.t -# CHECK-INST: vlhff.v v8, (a0), v0.t +th.vlhff.v v8, (a0), v0.t +# CHECK-INST: th.vlhff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x11] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 11 -vlwff.v v8, (a0) -# CHECK-INST: vlwff.v v8, (a0) +th.vlwff.v v8, (a0) +# CHECK-INST: th.vlwff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x13] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 13 -vlwff.v v8, (a0), v0.t -# CHECK-INST: vlwff.v v8, (a0), v0.t +th.vlwff.v v8, (a0), v0.t +# CHECK-INST: th.vlwff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x11] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 11 -vlbuff.v v8, (a0) -# CHECK-INST: vlbuff.v v8, (a0) +th.vlbuff.v v8, (a0) +# CHECK-INST: th.vlbuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x03] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 03 -vlbuff.v v8, (a0), v0.t -# CHECK-INST: vlbuff.v v8, (a0), v0.t +th.vlbuff.v v8, (a0), v0.t +# CHECK-INST: th.vlbuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x01] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 01 -vlhuff.v v8, (a0) -# CHECK-INST: vlhuff.v v8, (a0) +th.vlhuff.v v8, (a0) +# CHECK-INST: th.vlhuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x03] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 03 -vlhuff.v v8, (a0), v0.t -# CHECK-INST: vlhuff.v v8, (a0), v0.t +th.vlhuff.v v8, (a0), v0.t +# CHECK-INST: th.vlhuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x01] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 01 -vlwuff.v v8, (a0) -# CHECK-INST: vlwuff.v v8, (a0) +th.vlwuff.v v8, (a0) +# CHECK-INST: th.vlwuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x03] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 03 -vlwuff.v v8, (a0), v0.t -# CHECK-INST: vlwuff.v v8, (a0), v0.t +th.vlwuff.v v8, (a0), v0.t +# CHECK-INST: th.vlwuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x01] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 01 -vleff.v v8, (a0) -# CHECK-INST: vleff.v v8, (a0) +th.vleff.v v8, (a0) +# CHECK-INST: th.vleff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x03] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 03 -vleff.v v8, (a0), v0.t -# CHECK-INST: vleff.v v8, (a0), v0.t +th.vleff.v v8, (a0), v0.t +# CHECK-INST: th.vleff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x01] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 01 diff --git a/llvm/test/MC/RISCV/rvv0p71/macc.s b/llvm/test/MC/RISCV/rvv0p71/macc.s index e59bda3278bb3..5a73f07cee232 100644 --- a/llvm/test/MC/RISCV/rvv0p71/macc.s +++ b/llvm/test/MC/RISCV/rvv0p71/macc.s @@ -1,273 +1,273 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vmacc.vv v8, v20, v4, v0.t +th.vmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a b4 -vmacc.vv v8, v20, v4 -# CHECK-INST: vmacc.vv v8, v20, v4 +th.vmacc.vv v8, v20, v4 +# CHECK-INST: th.vmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a b6 -vmacc.vx v8, a0, v4, v0.t -# CHECK-INST: vmacc.vx v8, a0, v4, v0.t +th.vmacc.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 b4 -vmacc.vx v8, a0, v4 -# CHECK-INST: vmacc.vx v8, a0, v4 +th.vmacc.vx v8, a0, v4 +# CHECK-INST: th.vmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 b6 -vnmsac.vv v8, v20, v4, v0.t -# CHECK-INST: vnmsac.vv v8, v20, v4, v0.t +th.vnmsac.vv v8, v20, v4, v0.t +# CHECK-INST: th.vnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a bc -vnmsac.vv v8, v20, v4 -# CHECK-INST: vnmsac.vv v8, v20, v4 +th.vnmsac.vv v8, v20, v4 +# CHECK-INST: th.vnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a be -vnmsac.vx v8, a0, v4, v0.t -# CHECK-INST: vnmsac.vx v8, a0, v4, v0.t +th.vnmsac.vx v8, a0, v4, v0.t +# CHECK-INST: th.vnmsac.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 bc -vnmsac.vx v8, a0, v4 -# CHECK-INST: vnmsac.vx v8, a0, v4 +th.vnmsac.vx v8, a0, v4 +# CHECK-INST: th.vnmsac.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 be -vmadd.vv v8, v20, v4, v0.t -# CHECK-INST: vmadd.vv v8, v20, v4, v0.t +th.vmadd.vv v8, v20, v4, v0.t +# CHECK-INST: th.vmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a a4 -vmadd.vv v8, v20, v4 -# CHECK-INST: vmadd.vv v8, v20, v4 +th.vmadd.vv v8, v20, v4 +# CHECK-INST: th.vmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a a6 -vmadd.vx v8, a0, v4, v0.t -# CHECK-INST: vmadd.vx v8, a0, v4, v0.t +th.vmadd.vx v8, a0, v4, v0.t +# CHECK-INST: th.vmadd.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 a4 -vmadd.vx v8, a0, v4 -# CHECK-INST: vmadd.vx v8, a0, v4 +th.vmadd.vx v8, a0, v4 +# CHECK-INST: th.vmadd.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 a6 -vnmsub.vv v8, v20, v4, v0.t -# CHECK-INST: vnmsub.vv v8, v20, v4, v0.t +th.vnmsub.vv v8, v20, v4, v0.t +# CHECK-INST: th.vnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ac -vnmsub.vv v8, v20, v4 -# CHECK-INST: vnmsub.vv v8, v20, v4 +th.vnmsub.vv v8, v20, v4 +# CHECK-INST: th.vnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ae -vnmsub.vx v8, a0, v4, v0.t -# CHECK-INST: vnmsub.vx v8, a0, v4, v0.t +th.vnmsub.vx v8, a0, v4, v0.t +# CHECK-INST: th.vnmsub.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ac -vnmsub.vx v8, a0, v4 -# CHECK-INST: vnmsub.vx v8, a0, v4 +th.vnmsub.vx v8, a0, v4 +# CHECK-INST: th.vnmsub.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ae -vwmaccu.vv v8, v20, v4, v0.t -# CHECK-INST: vwmaccu.vv v8, v20, v4, v0.t +th.vwmaccu.vv v8, v20, v4, v0.t +# CHECK-INST: th.vwmaccu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a f0 -vwmaccu.vv v8, v20, v4 -# CHECK-INST: vwmaccu.vv v8, v20, v4 +th.vwmaccu.vv v8, v20, v4 +# CHECK-INST: th.vwmaccu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a f2 -vwmaccu.vx v8, a0, v4, v0.t -# CHECK-INST: vwmaccu.vx v8, a0, v4, v0.t +th.vwmaccu.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwmaccu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 f0 -vwmaccu.vx v8, a0, v4 -# CHECK-INST: vwmaccu.vx v8, a0, v4 +th.vwmaccu.vx v8, a0, v4 +# CHECK-INST: th.vwmaccu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 f2 -vwmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vwmacc.vv v8, v20, v4, v0.t +th.vwmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a f4 -vwmacc.vv v8, v20, v4 -# CHECK-INST: vwmacc.vv v8, v20, v4 +th.vwmacc.vv v8, v20, v4 +# CHECK-INST: th.vwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a f6 -vwmacc.vx v8, a0, v4, v0.t -# CHECK-INST: vwmacc.vx v8, a0, v4, v0.t +th.vwmacc.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 f4 -vwmacc.vx v8, a0, v4 -# CHECK-INST: vwmacc.vx v8, a0, v4 +th.vwmacc.vx v8, a0, v4 +# CHECK-INST: th.vwmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 f6 -vwmaccsu.vv v8, v20, v4, v0.t -# CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t +th.vwmaccsu.vv v8, v20, v4, v0.t +# CHECK-INST: th.vwmaccsu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a f8 -vwmaccsu.vv v8, v20, v4 -# CHECK-INST: vwmaccsu.vv v8, v20, v4 +th.vwmaccsu.vv v8, v20, v4 +# CHECK-INST: th.vwmaccsu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xfa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a fa -vwmaccsu.vx v8, a0, v4, v0.t -# CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t +th.vwmaccsu.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwmaccsu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 f8 -vwmaccsu.vx v8, a0, v4 -# CHECK-INST: vwmaccsu.vx v8, a0, v4 +th.vwmaccsu.vx v8, a0, v4 +# CHECK-INST: th.vwmaccsu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 fa -vwmaccus.vx v8, a0, v4, v0.t -# CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t +th.vwmaccus.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwmaccus.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xfc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 fc -vwmaccus.vx v8, a0, v4 -# CHECK-INST: vwmaccus.vx v8, a0, v4 +th.vwmaccus.vx v8, a0, v4 +# CHECK-INST: th.vwmaccus.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 fe -vwsmaccu.vv v8, v20, v4, v0.t -# CHECK-INST: vwsmaccu.vv v8, v20, v4, v0.t +th.vwsmaccu.vv v8, v20, v4, v0.t +# CHECK-INST: th.vwsmaccu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xf0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a f0 -vwsmaccu.vv v8, v20, v4 -# CHECK-INST: vwsmaccu.vv v8, v20, v4 +th.vwsmaccu.vv v8, v20, v4 +# CHECK-INST: th.vwsmaccu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x04,0x4a,0xf2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a f2 -vwsmaccu.vx v8, a0, v4, v0.t -# CHECK-INST: vwsmaccu.vx v8, a0, v4, v0.t +th.vwsmaccu.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwsmaccu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xf0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 f0 -vwsmaccu.vx v8, a0, v4 -# CHECK-INST: vwsmaccu.vx v8, a0, v4 +th.vwsmaccu.vx v8, a0, v4 +# CHECK-INST: th.vwsmaccu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x44,0x45,0xf2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 f2 -vwsmacc.vv v8, v20, v4, v0.t -# CHECK-INST: vwsmacc.vv v8, v20, v4, v0.t +th.vwsmacc.vv v8, v20, v4, v0.t +# CHECK-INST: th.vwsmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xf4] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a f4 -vwsmacc.vv v8, v20, v4 -# CHECK-INST: vwsmacc.vv v8, v20, v4 +th.vwsmacc.vv v8, v20, v4 +# CHECK-INST: th.vwsmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x04,0x4a,0xf6] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a f6 -vwsmacc.vx v8, a0, v4, v0.t -# CHECK-INST: vwsmacc.vx v8, a0, v4, v0.t +th.vwsmacc.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwsmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xf4] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 f4 -vwsmacc.vx v8, a0, v4 -# CHECK-INST: vwsmacc.vx v8, a0, v4 +th.vwsmacc.vx v8, a0, v4 +# CHECK-INST: th.vwsmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x44,0x45,0xf6] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 f6 -vwsmaccsu.vv v8, v20, v4, v0.t -# CHECK-INST: vwsmaccsu.vv v8, v20, v4, v0.t +th.vwsmaccsu.vv v8, v20, v4, v0.t +# CHECK-INST: th.vwsmaccsu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xf8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a f8 -vwsmaccsu.vv v8, v20, v4 -# CHECK-INST: vwsmaccsu.vv v8, v20, v4 +th.vwsmaccsu.vv v8, v20, v4 +# CHECK-INST: th.vwsmaccsu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x04,0x4a,0xfa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a fa -vwsmaccsu.vx v8, a0, v4, v0.t -# CHECK-INST: vwsmaccsu.vx v8, a0, v4, v0.t +th.vwsmaccsu.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwsmaccsu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xf8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 f8 -vwsmaccsu.vx v8, a0, v4 -# CHECK-INST: vwsmaccsu.vx v8, a0, v4 +th.vwsmaccsu.vx v8, a0, v4 +# CHECK-INST: th.vwsmaccsu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x44,0x45,0xfa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 fa -vwsmaccus.vx v8, a0, v4, v0.t -# CHECK-INST: vwsmaccus.vx v8, a0, v4, v0.t +th.vwsmaccus.vx v8, a0, v4, v0.t +# CHECK-INST: th.vwsmaccus.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xfc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 fc -vwsmaccus.vx v8, a0, v4 -# CHECK-INST: vwsmaccus.vx v8, a0, v4 +th.vwsmaccus.vx v8, a0, v4 +# CHECK-INST: th.vwsmaccus.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x44,0x45,0xfe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 fe \ No newline at end of file diff --git a/llvm/test/MC/RISCV/rvv0p71/mask.s b/llvm/test/MC/RISCV/rvv0p71/mask.s index dfb8bc9c1e0ce..5a74807d46ef3 100644 --- a/llvm/test/MC/RISCV/rvv0p71/mask.s +++ b/llvm/test/MC/RISCV/rvv0p71/mask.s @@ -1,141 +1,141 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmand.mm v8, v4, v20 -# CHECK-INST: vmand.mm v8, v4, v20 +th.vmand.mm v8, v4, v20 +# CHECK-INST: th.vmand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 66 -vmnand.mm v8, v4, v20 -# CHECK-INST: vmnand.mm v8, v4, v20 +th.vmnand.mm v8, v4, v20 +# CHECK-INST: th.vmnand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 76 -vmandnot.mm v8, v4, v20 -# CHECK-INST: vmandnot.mm v8, v4, v20 +th.vmandnot.mm v8, v4, v20 +# CHECK-INST: th.vmandnot.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 62 -vmxor.mm v8, v4, v20 -# CHECK-INST: vmxor.mm v8, v4, v20 +th.vmxor.mm v8, v4, v20 +# CHECK-INST: th.vmxor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 6e -vmor.mm v8, v4, v20 -# CHECK-INST: vmor.mm v8, v4, v20 +th.vmor.mm v8, v4, v20 +# CHECK-INST: th.vmor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 6a -vmnor.mm v8, v4, v20 -# CHECK-INST: vmnor.mm v8, v4, v20 +th.vmnor.mm v8, v4, v20 +# CHECK-INST: th.vmnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 7a -vmornot.mm v8, v4, v20 -# CHECK-INST: vmornot.mm v8, v4, v20 +th.vmornot.mm v8, v4, v20 +# CHECK-INST: th.vmornot.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 72 -vmxnor.mm v8, v4, v20 -# CHECK-INST: vmxnor.mm v8, v4, v20 +th.vmxnor.mm v8, v4, v20 +# CHECK-INST: th.vmxnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 7e -vmpopc.m a2, v4, v0.t -# CHECK-INST: vmpopc.m a2, v4, v0.t +th.vmpopc.m a2, v4, v0.t +# CHECK-INST: th.vmpopc.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0x26,0x40,0x50] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 26 40 50 -vmpopc.m a2, v4 -# CHECK-INST: vmpopc.m a2, v4 +th.vmpopc.m a2, v4 +# CHECK-INST: th.vmpopc.m a2, v4 # CHECK-ENCODING: [0x57,0x26,0x40,0x52] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 26 40 52 -vmfirst.m a2, v4, v0.t -# CHECK-INST: vmfirst.m a2, v4, v0.t +th.vmfirst.m a2, v4, v0.t +# CHECK-INST: th.vmfirst.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0x26,0x40,0x54] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 26 40 54 -vmfirst.m a2, v4 -# CHECK-INST: vmfirst.m a2, v4 +th.vmfirst.m a2, v4 +# CHECK-INST: th.vmfirst.m a2, v4 # CHECK-ENCODING: [0x57,0x26,0x40,0x56] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 26 40 56 -vmsbf.m v8, v4, v0.t -# CHECK-INST: vmsbf.m v8, v4, v0.t +th.vmsbf.m v8, v4, v0.t +# CHECK-INST: th.vmsbf.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x40,0x58] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 a4 40 58 -vmsbf.m v8, v4 -# CHECK-INST: vmsbf.m v8, v4 +th.vmsbf.m v8, v4 +# CHECK-INST: th.vmsbf.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x40,0x5a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 a4 40 5a -vmsif.m v8, v4, v0.t -# CHECK-INST: vmsif.m v8, v4, v0.t +th.vmsif.m v8, v4, v0.t +# CHECK-INST: th.vmsif.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x58] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 a4 41 58 -vmsif.m v8, v4 -# CHECK-INST: vmsif.m v8, v4 +th.vmsif.m v8, v4 +# CHECK-INST: th.vmsif.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x5a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 a4 41 5a -vmsof.m v8, v4, v0.t -# CHECK-INST: vmsof.m v8, v4, v0.t +th.vmsof.m v8, v4, v0.t +# CHECK-INST: th.vmsof.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x58] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 41 58 -vmsof.m v8, v4 -# CHECK-INST: vmsof.m v8, v4 +th.vmsof.m v8, v4 +# CHECK-INST: th.vmsof.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x5a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 41 5a -viota.m v8, v4, v0.t -# CHECK-INST: viota.m v8, v4, v0.t +th.viota.m v8, v4, v0.t +# CHECK-INST: th.viota.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x48,0x58] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 48 58 -viota.m v8, v4 -# CHECK-INST: viota.m v8, v4 +th.viota.m v8, v4 +# CHECK-INST: th.viota.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x48,0x5a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 48 5a -vid.v v8, v0.t -# CHECK-INST: vid.v v8, v0.t +th.vid.v v8, v0.t +# CHECK-INST: th.vid.v v8, v0.t # CHECK-ENCODING: [0x57,0xa4,0x08,0x58] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 a4 08 58 -vid.v v8 -# CHECK-INST: vid.v v8 +th.vid.v v8 +# CHECK-INST: th.vid.v v8 # CHECK-ENCODING: [0x57,0xa4,0x08,0x5a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 a4 08 5a diff --git a/llvm/test/MC/RISCV/rvv0p71/minmax.s b/llvm/test/MC/RISCV/rvv0p71/minmax.s index 4c608f71ae5e5..a406cd16ccfe0 100644 --- a/llvm/test/MC/RISCV/rvv0p71/minmax.s +++ b/llvm/test/MC/RISCV/rvv0p71/minmax.s @@ -1,105 +1,105 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vminu.vv v8, v4, v20, v0.t -# CHECK-INST: vminu.vv v8, v4, v20, v0.t +th.vminu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vminu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 10 -vminu.vv v8, v4, v20 -# CHECK-INST: vminu.vv v8, v4, v20 +th.vminu.vv v8, v4, v20 +# CHECK-INST: th.vminu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 12 -vminu.vx v8, v4, a0, v0.t -# CHECK-INST: vminu.vx v8, v4, a0, v0.t +th.vminu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vminu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 10 -vminu.vx v8, v4, a0 -# CHECK-INST: vminu.vx v8, v4, a0 +th.vminu.vx v8, v4, a0 +# CHECK-INST: th.vminu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 12 -vmin.vv v8, v4, v20, v0.t -# CHECK-INST: vmin.vv v8, v4, v20, v0.t +th.vmin.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 14 -vmin.vv v8, v4, v20 -# CHECK-INST: vmin.vv v8, v4, v20 +th.vmin.vv v8, v4, v20 +# CHECK-INST: th.vmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 16 -vmin.vx v8, v4, a0, v0.t -# CHECK-INST: vmin.vx v8, v4, a0, v0.t +th.vmin.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmin.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 14 -vmin.vx v8, v4, a0 -# CHECK-INST: vmin.vx v8, v4, a0 +th.vmin.vx v8, v4, a0 +# CHECK-INST: th.vmin.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 16 -vmaxu.vv v8, v4, v20, v0.t -# CHECK-INST: vmaxu.vv v8, v4, v20, v0.t +th.vmaxu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmaxu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 18 -vmaxu.vv v8, v4, v20 -# CHECK-INST: vmaxu.vv v8, v4, v20 +th.vmaxu.vv v8, v4, v20 +# CHECK-INST: th.vmaxu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 1a -vmaxu.vx v8, v4, a0, v0.t -# CHECK-INST: vmaxu.vx v8, v4, a0, v0.t +th.vmaxu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmaxu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 18 -vmaxu.vx v8, v4, a0 -# CHECK-INST: vmaxu.vx v8, v4, a0 +th.vmaxu.vx v8, v4, a0 +# CHECK-INST: th.vmaxu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 1a -vmax.vv v8, v4, v20, v0.t -# CHECK-INST: vmax.vv v8, v4, v20, v0.t +th.vmax.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 1c -vmax.vv v8, v4, v20 -# CHECK-INST: vmax.vv v8, v4, v20 +th.vmax.vv v8, v4, v20 +# CHECK-INST: th.vmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 1e -vmax.vx v8, v4, a0, v0.t -# CHECK-INST: vmax.vx v8, v4, a0, v0.t +th.vmax.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmax.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 1c -vmax.vx v8, v4, a0 -# CHECK-INST: vmax.vx v8, v4, a0 +th.vmax.vx v8, v4, a0 +# CHECK-INST: th.vmax.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 1e diff --git a/llvm/test/MC/RISCV/rvv0p71/mul.s b/llvm/test/MC/RISCV/rvv0p71/mul.s index c217b2054447b..fecb361dcc533 100644 --- a/llvm/test/MC/RISCV/rvv0p71/mul.s +++ b/llvm/test/MC/RISCV/rvv0p71/mul.s @@ -1,201 +1,201 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmul.vv v8, v4, v20, v0.t -# CHECK-INST: vmul.vv v8, v4, v20, v0.t +th.vmul.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 94 -vmul.vv v8, v4, v20 -# CHECK-INST: vmul.vv v8, v4, v20 +th.vmul.vv v8, v4, v20 +# CHECK-INST: th.vmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 96 -vmul.vx v8, v4, a0, v0.t -# CHECK-INST: vmul.vx v8, v4, a0, v0.t +th.vmul.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 94 -vmul.vx v8, v4, a0 -# CHECK-INST: vmul.vx v8, v4, a0 +th.vmul.vx v8, v4, a0 +# CHECK-INST: th.vmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 96 -vmulh.vv v8, v4, v20, v0.t -# CHECK-INST: vmulh.vv v8, v4, v20, v0.t +th.vmulh.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmulh.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 9c -vmulh.vv v8, v4, v20 -# CHECK-INST: vmulh.vv v8, v4, v20 +th.vmulh.vv v8, v4, v20 +# CHECK-INST: th.vmulh.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 9e -vmulh.vx v8, v4, a0, v0.t -# CHECK-INST: vmulh.vx v8, v4, a0, v0.t +th.vmulh.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmulh.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 9c -vmulh.vx v8, v4, a0 -# CHECK-INST: vmulh.vx v8, v4, a0 +th.vmulh.vx v8, v4, a0 +# CHECK-INST: th.vmulh.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 9e -vmulhu.vv v8, v4, v20, v0.t -# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t +th.vmulhu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmulhu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 90 -vmulhu.vv v8, v4, v20 -# CHECK-INST: vmulhu.vv v8, v4, v20 +th.vmulhu.vv v8, v4, v20 +# CHECK-INST: th.vmulhu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 92 -vmulhu.vx v8, v4, a0, v0.t -# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t +th.vmulhu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmulhu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 90 -vmulhu.vx v8, v4, a0 -# CHECK-INST: vmulhu.vx v8, v4, a0 +th.vmulhu.vx v8, v4, a0 +# CHECK-INST: th.vmulhu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 92 -vmulhsu.vv v8, v4, v20, v0.t -# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t +th.vmulhsu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vmulhsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 98 -vmulhsu.vv v8, v4, v20 -# CHECK-INST: vmulhsu.vv v8, v4, v20 +th.vmulhsu.vv v8, v4, v20 +# CHECK-INST: th.vmulhsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 9a -vmulhsu.vx v8, v4, a0, v0.t -# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t +th.vmulhsu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vmulhsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 98 -vmulhsu.vx v8, v4, a0 -# CHECK-INST: vmulhsu.vx v8, v4, a0 +th.vmulhsu.vx v8, v4, a0 +# CHECK-INST: th.vmulhsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 9a -vwmul.vv v8, v4, v20, v0.t -# CHECK-INST: vwmul.vv v8, v4, v20, v0.t +th.vwmul.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xec] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ec -vwmul.vv v8, v4, v20 -# CHECK-INST: vwmul.vv v8, v4, v20 +th.vwmul.vv v8, v4, v20 +# CHECK-INST: th.vwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xee] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ee -vwmul.vx v8, v4, a0, v0.t -# CHECK-INST: vwmul.vx v8, v4, a0, v0.t +th.vwmul.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ec -vwmul.vx v8, v4, a0 -# CHECK-INST: vwmul.vx v8, v4, a0 +th.vwmul.vx v8, v4, a0 +# CHECK-INST: th.vwmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ee -vwmulu.vv v8, v4, v20, v0.t -# CHECK-INST: vwmulu.vv v8, v4, v20, v0.t +th.vwmulu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwmulu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a e0 -vwmulu.vv v8, v4, v20 -# CHECK-INST: vwmulu.vv v8, v4, v20 +th.vwmulu.vv v8, v4, v20 +# CHECK-INST: th.vwmulu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a e2 -vwmulu.vx v8, v4, a0, v0.t -# CHECK-INST: vwmulu.vx v8, v4, a0, v0.t +th.vwmulu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwmulu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 e0 -vwmulu.vx v8, v4, a0 -# CHECK-INST: vwmulu.vx v8, v4, a0 +th.vwmulu.vx v8, v4, a0 +# CHECK-INST: th.vwmulu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 e2 -vwmulsu.vv v8, v4, v20, v0.t -# CHECK-INST: vwmulsu.vv v8, v4, v20, v0.t +th.vwmulsu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwmulsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a e8 -vwmulsu.vv v8, v4, v20 -# CHECK-INST: vwmulsu.vv v8, v4, v20 +th.vwmulsu.vv v8, v4, v20 +# CHECK-INST: th.vwmulsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xea] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ea -vwmulsu.vx v8, v4, a0, v0.t -# CHECK-INST: vwmulsu.vx v8, v4, a0, v0.t +th.vwmulsu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwmulsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 e8 -vwmulsu.vx v8, v4, a0 -# CHECK-INST: vwmulsu.vx v8, v4, a0 +th.vwmulsu.vx v8, v4, a0 +# CHECK-INST: th.vwmulsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xea] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ea -vsmul.vv v8, v4, v20, v0.t -# CHECK-INST: vsmul.vv v8, v4, v20, v0.t +th.vsmul.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 9c -vsmul.vv v8, v4, v20 -# CHECK-INST: vsmul.vv v8, v4, v20 +th.vsmul.vv v8, v4, v20 +# CHECK-INST: th.vsmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 9e -vsmul.vx v8, v4, a0, v0.t -# CHECK-INST: vsmul.vx v8, v4, a0, v0.t +th.vsmul.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 9c -vsmul.vx v8, v4, a0 -# CHECK-INST: vsmul.vx v8, v4, a0 +th.vsmul.vx v8, v4, a0 +# CHECK-INST: th.vsmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 9e diff --git a/llvm/test/MC/RISCV/rvv0p71/mv.s b/llvm/test/MC/RISCV/rvv0p71/mv.s index 7ab1ca284724b..17e0f4cb6325d 100644 --- a/llvm/test/MC/RISCV/rvv0p71/mv.s +++ b/llvm/test/MC/RISCV/rvv0p71/mv.s @@ -1,39 +1,39 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmv.v.v v8, v20 -# CHECK-INST: vmv.v.v v8, v20 +th.vmv.v.v v8, v20 +# CHECK-INST: th.vmv.v.v v8, v20 # CHECK-ENCODING: [0x57,0x04,0x0a,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 0a 5e -vmv.v.x v8, a0 -# CHECK-INST: vmv.v.x v8, a0 +th.vmv.v.x v8, a0 +# CHECK-INST: th.vmv.v.x v8, a0 # CHECK-ENCODING: [0x57,0x44,0x05,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 05 5e -vmv.v.i v8, 15 -# CHECK-INST: vmv.v.i v8, 15 +th.vmv.v.i v8, 15 +# CHECK-INST: th.vmv.v.i v8, 15 # CHECK-ENCODING: [0x57,0xb4,0x07,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 07 5e -vext.x.v a2, v4, a0 -# CHECK-INST: vext.x.v a2, v4, a0 +th.vext.x.v a2, v4, a0 +# CHECK-INST: th.vext.x.v a2, v4, a0 # CHECK-ENCODING: [0x57,0x26,0x45,0x32] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 26 45 32 -vmv.s.x v8, a0 -# CHECK-INST: vmv.s.x v8, a0 +th.vmv.s.x v8, a0 +# CHECK-INST: th.vmv.s.x v8, a0 # CHECK-ENCODING: [0x57,0x64,0x05,0x36] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 05 36 diff --git a/llvm/test/MC/RISCV/rvv0p71/or.s b/llvm/test/MC/RISCV/rvv0p71/or.s index 2133f5b3aeba6..17221cfe813de 100644 --- a/llvm/test/MC/RISCV/rvv0p71/or.s +++ b/llvm/test/MC/RISCV/rvv0p71/or.s @@ -1,45 +1,45 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vor.vv v8, v4, v20, v0.t -# CHECK-INST: vor.vv v8, v4, v20, v0.t +th.vor.vv v8, v4, v20, v0.t +# CHECK-INST: th.vor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 28 -vor.vv v8, v4, v20 -# CHECK-INST: vor.vv v8, v4, v20 +th.vor.vv v8, v4, v20 +# CHECK-INST: th.vor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 2a -vor.vx v8, v4, a0, v0.t -# CHECK-INST: vor.vx v8, v4, a0, v0.t +th.vor.vx v8, v4, a0, v0.t +# CHECK-INST: th.vor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 28 -vor.vx v8, v4, a0 -# CHECK-INST: vor.vx v8, v4, a0 +th.vor.vx v8, v4, a0 +# CHECK-INST: th.vor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 2a -vor.vi v8, v4, 15, v0.t -# CHECK-INST: vor.vi v8, v4, 15, v0.t +th.vor.vi v8, v4, 15, v0.t +# CHECK-INST: th.vor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 28 -vor.vi v8, v4, 15 -# CHECK-INST: vor.vi v8, v4, 15 +th.vor.vi v8, v4, 15 +# CHECK-INST: th.vor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 2a diff --git a/llvm/test/MC/RISCV/rvv0p71/others.s b/llvm/test/MC/RISCV/rvv0p71/others.s index dd878b44b63a4..3ceeb7930a0ca 100644 --- a/llvm/test/MC/RISCV/rvv0p71/others.s +++ b/llvm/test/MC/RISCV/rvv0p71/others.s @@ -1,141 +1,141 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv -M no-aliases - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector -M no-aliases - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vmerge.vvm v8, v4, v20, v0 -# CHECK-INST: vmerge.vvm v8, v4, v20, v0 +th.vmerge.vvm v8, v4, v20, v0 +# CHECK-INST: th.vmerge.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 5c -vmerge.vxm v8, v4, a0, v0 -# CHECK-INST: vmerge.vxm v8, v4, a0, v0 +th.vmerge.vxm v8, v4, a0, v0 +# CHECK-INST: th.vmerge.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 5c -vmerge.vim v8, v4, 15, v0 -# CHECK-INST: vmerge.vim v8, v4, 15, v0 +th.vmerge.vim v8, v4, 15, v0 +# CHECK-INST: th.vmerge.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 5c -vslideup.vx v8, v4, a0, v0.t -# CHECK-INST: vslideup.vx v8, v4, a0, v0.t +th.vslideup.vx v8, v4, a0, v0.t +# CHECK-INST: th.vslideup.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 38 -vslideup.vx v8, v4, a0 -# CHECK-INST: vslideup.vx v8, v4, a0 +th.vslideup.vx v8, v4, a0 +# CHECK-INST: th.vslideup.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 3a -vslideup.vi v8, v4, 31, v0.t -# CHECK-INST: vslideup.vi v8, v4, 31, v0.t +th.vslideup.vi v8, v4, 31, v0.t +# CHECK-INST: th.vslideup.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 38 -vslideup.vi v8, v4, 31 -# CHECK-INST: vslideup.vi v8, v4, 31 +th.vslideup.vi v8, v4, 31 +# CHECK-INST: th.vslideup.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 3a -vslidedown.vx v8, v4, a0, v0.t -# CHECK-INST: vslidedown.vx v8, v4, a0, v0.t +th.vslidedown.vx v8, v4, a0, v0.t +# CHECK-INST: th.vslidedown.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 3c -vslidedown.vx v8, v4, a0 -# CHECK-INST: vslidedown.vx v8, v4, a0 +th.vslidedown.vx v8, v4, a0 +# CHECK-INST: th.vslidedown.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 3e -vslidedown.vi v8, v4, 31, v0.t -# CHECK-INST: vslidedown.vi v8, v4, 31, v0.t +th.vslidedown.vi v8, v4, 31, v0.t +# CHECK-INST: th.vslidedown.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 3c -vslidedown.vi v8, v4, 31 -# CHECK-INST: vslidedown.vi v8, v4, 31 +th.vslidedown.vi v8, v4, 31 +# CHECK-INST: th.vslidedown.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 3e -vslide1up.vx v8, v4, a0, v0.t -# CHECK-INST: vslide1up.vx v8, v4, a0, v0.t +th.vslide1up.vx v8, v4, a0, v0.t +# CHECK-INST: th.vslide1up.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 38 -vslide1up.vx v8, v4, a0 -# CHECK-INST: vslide1up.vx v8, v4, a0 +th.vslide1up.vx v8, v4, a0 +# CHECK-INST: th.vslide1up.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 3a -vslide1down.vx v8, v4, a0, v0.t -# CHECK-INST: vslide1down.vx v8, v4, a0, v0.t +th.vslide1down.vx v8, v4, a0, v0.t +# CHECK-INST: th.vslide1down.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 3c -vslide1down.vx v8, v4, a0 -# CHECK-INST: vslide1down.vx v8, v4, a0 +th.vslide1down.vx v8, v4, a0 +# CHECK-INST: th.vslide1down.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 3e -vrgather.vv v8, v4, v20, v0.t -# CHECK-INST: vrgather.vv v8, v4, v20, v0.t +th.vrgather.vv v8, v4, v20, v0.t +# CHECK-INST: th.vrgather.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 30 -vrgather.vv v8, v4, v20 -# CHECK-INST: vrgather.vv v8, v4, v20 +th.vrgather.vv v8, v4, v20 +# CHECK-INST: th.vrgather.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 32 -vrgather.vx v8, v4, a0, v0.t -# CHECK-INST: vrgather.vx v8, v4, a0, v0.t +th.vrgather.vx v8, v4, a0, v0.t +# CHECK-INST: th.vrgather.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 30 -vrgather.vx v8, v4, a0 -# CHECK-INST: vrgather.vx v8, v4, a0 +th.vrgather.vx v8, v4, a0 +# CHECK-INST: th.vrgather.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 32 -vrgather.vi v8, v4, 31, v0.t -# CHECK-INST: vrgather.vi v8, v4, 31, v0.t +th.vrgather.vi v8, v4, 31, v0.t +# CHECK-INST: th.vrgather.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 30 -vrgather.vi v8, v4, 31 -# CHECK-INST: vrgather.vi v8, v4, 31 +th.vrgather.vi v8, v4, 31 +# CHECK-INST: th.vrgather.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 32 -vcompress.vm v8, v4, v20 -# CHECK-INST: vcompress.vm v8, v4, v20 +th.vcompress.vm v8, v4, v20 +# CHECK-INST: th.vcompress.vm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 5e diff --git a/llvm/test/MC/RISCV/rvv0p71/reduction.s b/llvm/test/MC/RISCV/rvv0p71/reduction.s index 258372a731fad..2580de7827a5c 100644 --- a/llvm/test/MC/RISCV/rvv0p71/reduction.s +++ b/llvm/test/MC/RISCV/rvv0p71/reduction.s @@ -1,135 +1,135 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vredsum.vs v8, v4, v20, v0.t -# CHECK-INST: vredsum.vs v8, v4, v20, v0.t +th.vredsum.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 00 -vredsum.vs v8, v4, v20 -# CHECK-INST: vredsum.vs v8, v4, v20 +th.vredsum.vs v8, v4, v20 +# CHECK-INST: th.vredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 02 -vredmaxu.vs v8, v4, v20, v0.t -# CHECK-INST: vredmaxu.vs v8, v4, v20, v0.t +th.vredmaxu.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredmaxu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 18 -vredmaxu.vs v8, v4, v20 -# CHECK-INST: vredmaxu.vs v8, v4, v20 +th.vredmaxu.vs v8, v4, v20 +# CHECK-INST: th.vredmaxu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 1a -vredmax.vs v8, v4, v20, v0.t -# CHECK-INST: vredmax.vs v8, v4, v20, v0.t +th.vredmax.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 1c -vredmax.vs v8, v4, v20 -# CHECK-INST: vredmax.vs v8, v4, v20 +th.vredmax.vs v8, v4, v20 +# CHECK-INST: th.vredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 1e -vredminu.vs v8, v4, v20, v0.t -# CHECK-INST: vredminu.vs v8, v4, v20, v0.t +th.vredminu.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredminu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 10 -vredminu.vs v8, v4, v20 -# CHECK-INST: vredminu.vs v8, v4, v20 +th.vredminu.vs v8, v4, v20 +# CHECK-INST: th.vredminu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 12 -vredmin.vs v8, v4, v20, v0.t -# CHECK-INST: vredmin.vs v8, v4, v20, v0.t +th.vredmin.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 14 -vredmin.vs v8, v4, v20 -# CHECK-INST: vredmin.vs v8, v4, v20 +th.vredmin.vs v8, v4, v20 +# CHECK-INST: th.vredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 16 -vredand.vs v8, v4, v20, v0.t -# CHECK-INST: vredand.vs v8, v4, v20, v0.t +th.vredand.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredand.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 04 -vredand.vs v8, v4, v20 -# CHECK-INST: vredand.vs v8, v4, v20 +th.vredand.vs v8, v4, v20 +# CHECK-INST: th.vredand.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 06 -vredor.vs v8, v4, v20, v0.t -# CHECK-INST: vredor.vs v8, v4, v20, v0.t +th.vredor.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 08 -vredor.vs v8, v4, v20 -# CHECK-INST: vredor.vs v8, v4, v20 +th.vredor.vs v8, v4, v20 +# CHECK-INST: th.vredor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 0a -vredxor.vs v8, v4, v20, v0.t -# CHECK-INST: vredxor.vs v8, v4, v20, v0.t +th.vredxor.vs v8, v4, v20, v0.t +# CHECK-INST: th.vredxor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 0c -vredxor.vs v8, v4, v20 -# CHECK-INST: vredxor.vs v8, v4, v20 +th.vredxor.vs v8, v4, v20 +# CHECK-INST: th.vredxor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a 0e -vwredsumu.vs v8, v4, v20, v0.t -# CHECK-INST: vwredsumu.vs v8, v4, v20, v0.t +th.vwredsumu.vs v8, v4, v20, v0.t +# CHECK-INST: th.vwredsumu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a c0 -vwredsumu.vs v8, v4, v20 -# CHECK-INST: vwredsumu.vs v8, v4, v20 +th.vwredsumu.vs v8, v4, v20 +# CHECK-INST: th.vwredsumu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a c2 -vwredsum.vs v8, v4, v20, v0.t -# CHECK-INST: vwredsum.vs v8, v4, v20, v0.t +th.vwredsum.vs v8, v4, v20, v0.t +# CHECK-INST: th.vwredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a c4 -vwredsum.vs v8, v4, v20 -# CHECK-INST: vwredsum.vs v8, v4, v20 +th.vwredsum.vs v8, v4, v20 +# CHECK-INST: th.vwredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a c6 -vredsum.vs v0, v4, v20, v0.t -# CHECK-INST: vredsum.vs v0, v4, v20, v0.t +th.vredsum.vs v0, v4, v20, v0.t +# CHECK-INST: th.vredsum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x20,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 20 4a 00 diff --git a/llvm/test/MC/RISCV/rvv0p71/shift.s b/llvm/test/MC/RISCV/rvv0p71/shift.s index 6287c768b42bd..d4f0aff3bd60a 100644 --- a/llvm/test/MC/RISCV/rvv0p71/shift.s +++ b/llvm/test/MC/RISCV/rvv0p71/shift.s @@ -1,267 +1,267 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vsll.vv v8, v4, v20, v0.t -# CHECK-INST: vsll.vv v8, v4, v20, v0.t +th.vsll.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsll.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 94 -vsll.vv v8, v4, v20 -# CHECK-INST: vsll.vv v8, v4, v20 +th.vsll.vv v8, v4, v20 +# CHECK-INST: th.vsll.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 96 -vsll.vx v8, v4, a0, v0.t -# CHECK-INST: vsll.vx v8, v4, a0, v0.t +th.vsll.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsll.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 94 -vsll.vx v8, v4, a0 -# CHECK-INST: vsll.vx v8, v4, a0 +th.vsll.vx v8, v4, a0 +# CHECK-INST: th.vsll.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 96 -vsll.vi v8, v4, 31, v0.t -# CHECK-INST: vsll.vi v8, v4, 31, v0.t +th.vsll.vi v8, v4, 31, v0.t +# CHECK-INST: th.vsll.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 94 -vsll.vi v8, v4, 31 -# CHECK-INST: vsll.vi v8, v4, 31 +th.vsll.vi v8, v4, 31 +# CHECK-INST: th.vsll.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f 96 -vsrl.vv v8, v4, v20, v0.t -# CHECK-INST: vsrl.vv v8, v4, v20, v0.t +th.vsrl.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a a0 -vsrl.vv v8, v4, v20 -# CHECK-INST: vsrl.vv v8, v4, v20 +th.vsrl.vv v8, v4, v20 +# CHECK-INST: th.vsrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a a2 -vsrl.vx v8, v4, a0, v0.t -# CHECK-INST: vsrl.vx v8, v4, a0, v0.t +th.vsrl.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 a0 -vsrl.vx v8, v4, a0 -# CHECK-INST: vsrl.vx v8, v4, a0 +th.vsrl.vx v8, v4, a0 +# CHECK-INST: th.vsrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 a2 -vsrl.vi v8, v4, 31, v0.t -# CHECK-INST: vsrl.vi v8, v4, 31, v0.t +th.vsrl.vi v8, v4, 31, v0.t +# CHECK-INST: th.vsrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f a0 -vsrl.vi v8, v4, 31 -# CHECK-INST: vsrl.vi v8, v4, 31 +th.vsrl.vi v8, v4, 31 +# CHECK-INST: th.vsrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f a2 -vsra.vv v8, v4, v20, v0.t -# CHECK-INST: vsra.vv v8, v4, v20, v0.t +th.vsra.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a a4 -vsra.vv v8, v4, v20 -# CHECK-INST: vsra.vv v8, v4, v20 +th.vsra.vv v8, v4, v20 +# CHECK-INST: th.vsra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a a6 -vsra.vx v8, v4, a0, v0.t -# CHECK-INST: vsra.vx v8, v4, a0, v0.t +th.vsra.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 a4 -vsra.vx v8, v4, a0 -# CHECK-INST: vsra.vx v8, v4, a0 +th.vsra.vx v8, v4, a0 +# CHECK-INST: th.vsra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 a6 -vsra.vi v8, v4, 31, v0.t -# CHECK-INST: vsra.vi v8, v4, 31, v0.t +th.vsra.vi v8, v4, 31, v0.t +# CHECK-INST: th.vsra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f a4 -vsra.vi v8, v4, 31 -# CHECK-INST: vsra.vi v8, v4, 31 +th.vsra.vi v8, v4, 31 +# CHECK-INST: th.vsra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f a6 -vnsrl.vv v8, v4, v20, v0.t -# CHECK-INST: vnsrl.vv v8, v4, v20, v0.t +th.vnsrl.vv v8, v4, v20, v0.t +# CHECK-INST: th.vnsrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a b0 -vnsrl.vv v4, v4, v20, v0.t -# CHECK-INST: vnsrl.vv v4, v4, v20, v0.t +th.vnsrl.vv v4, v4, v20, v0.t +# CHECK-INST: th.vnsrl.vv v4, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x02,0x4a,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 02 4a b0 -vnsrl.vv v8, v4, v20 -# CHECK-INST: vnsrl.vv v8, v4, v20 +th.vnsrl.vv v8, v4, v20 +# CHECK-INST: th.vnsrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a b2 -vnsrl.vx v8, v4, a0, v0.t -# CHECK-INST: vnsrl.vx v8, v4, a0, v0.t +th.vnsrl.vx v8, v4, a0, v0.t +# CHECK-INST: th.vnsrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 b0 -vnsrl.vx v8, v4, a0 -# CHECK-INST: vnsrl.vx v8, v4, a0 +th.vnsrl.vx v8, v4, a0 +# CHECK-INST: th.vnsrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 b2 -vnsrl.vi v8, v4, 31, v0.t -# CHECK-INST: vnsrl.vi v8, v4, 31, v0.t +th.vnsrl.vi v8, v4, 31, v0.t +# CHECK-INST: th.vnsrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f b0 -vnsrl.vi v8, v4, 31 -# CHECK-INST: vnsrl.vi v8, v4, 31 +th.vnsrl.vi v8, v4, 31 +# CHECK-INST: th.vnsrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f b2 -vnsra.vv v8, v4, v20, v0.t -# CHECK-INST: vnsra.vv v8, v4, v20, v0.t +th.vnsra.vv v8, v4, v20, v0.t +# CHECK-INST: th.vnsra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb4] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a b4 -vnsra.vv v8, v4, v20 -# CHECK-INST: vnsra.vv v8, v4, v20 +th.vnsra.vv v8, v4, v20 +# CHECK-INST: th.vnsra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb6] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a b6 -vnsra.vx v8, v4, a0, v0.t -# CHECK-INST: vnsra.vx v8, v4, a0, v0.t +th.vnsra.vx v8, v4, a0, v0.t +# CHECK-INST: th.vnsra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb4] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 b4 -vnsra.vx v8, v4, a0 -# CHECK-INST: vnsra.vx v8, v4, a0 +th.vnsra.vx v8, v4, a0 +# CHECK-INST: th.vnsra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb6] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 b6 -vnsra.vi v8, v4, 31, v0.t -# CHECK-INST: vnsra.vi v8, v4, 31, v0.t +th.vnsra.vi v8, v4, 31, v0.t +# CHECK-INST: th.vnsra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f b4 -vnsra.vi v8, v4, 31 -# CHECK-INST: vnsra.vi v8, v4, 31 +th.vnsra.vi v8, v4, 31 +# CHECK-INST: th.vnsra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f b6 -vssrl.vv v8, v4, v20, v0.t -# CHECK-INST: vssrl.vv v8, v4, v20, v0.t +th.vssrl.vv v8, v4, v20, v0.t +# CHECK-INST: th.vssrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a a8 -vssrl.vv v8, v4, v20 -# CHECK-INST: vssrl.vv v8, v4, v20 +th.vssrl.vv v8, v4, v20 +# CHECK-INST: th.vssrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a aa -vssrl.vx v8, v4, a0, v0.t -# CHECK-INST: vssrl.vx v8, v4, a0, v0.t +th.vssrl.vx v8, v4, a0, v0.t +# CHECK-INST: th.vssrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 a8 -vssrl.vx v8, v4, a0 -# CHECK-INST: vssrl.vx v8, v4, a0 +th.vssrl.vx v8, v4, a0 +# CHECK-INST: th.vssrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 aa -vssrl.vi v8, v4, 31, v0.t -# CHECK-INST: vssrl.vi v8, v4, 31, v0.t +th.vssrl.vi v8, v4, 31, v0.t +# CHECK-INST: th.vssrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f a8 -vssrl.vi v8, v4, 31 -# CHECK-INST: vssrl.vi v8, v4, 31 +th.vssrl.vi v8, v4, 31 +# CHECK-INST: th.vssrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f aa -vssra.vv v8, v4, v20, v0.t -# CHECK-INST: vssra.vv v8, v4, v20, v0.t +th.vssra.vv v8, v4, v20, v0.t +# CHECK-INST: th.vssra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a ac -vssra.vv v8, v4, v20 -# CHECK-INST: vssra.vv v8, v4, v20 +th.vssra.vv v8, v4, v20 +# CHECK-INST: th.vssra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a ae -vssra.vx v8, v4, a0, v0.t -# CHECK-INST: vssra.vx v8, v4, a0, v0.t +th.vssra.vx v8, v4, a0, v0.t +# CHECK-INST: th.vssra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 ac -vssra.vx v8, v4, a0 -# CHECK-INST: vssra.vx v8, v4, a0 +th.vssra.vx v8, v4, a0 +# CHECK-INST: th.vssra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 ae -vssra.vi v8, v4, 31, v0.t -# CHECK-INST: vssra.vi v8, v4, 31, v0.t +th.vssra.vi v8, v4, 31, v0.t +# CHECK-INST: th.vssra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f ac -vssra.vi v8, v4, 31 -# CHECK-INST: vssra.vi v8, v4, 31 +th.vssra.vi v8, v4, 31 +# CHECK-INST: th.vssra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 4f ae diff --git a/llvm/test/MC/RISCV/rvv0p71/sign-injection.s b/llvm/test/MC/RISCV/rvv0p71/sign-injection.s index 55b98099005c7..43a970115f080 100644 --- a/llvm/test/MC/RISCV/rvv0p71/sign-injection.s +++ b/llvm/test/MC/RISCV/rvv0p71/sign-injection.s @@ -1,84 +1,84 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+xtheadv --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector --mattr=+f - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vfsgnj.vv v8, v4, v20, v0.t -# CHECK-INST: vfsgnj.vv v8, v4, v20, v0.t +th.vfsgnj.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfsgnj.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x20] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 20 -vfsgnj.vv v8, v4, v20 -# CHECK-INST: vfsgnj.vv v8, v4, v20 +th.vfsgnj.vv v8, v4, v20 +# CHECK-INST: th.vfsgnj.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x22] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 22 -vfsgnj.vf v8, v4, fa0, v0.t -# CHECK-INST: vfsgnj.vf v8, v4, fa0, v0.t +th.vfsgnj.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfsgnj.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x20] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 20 -vfsgnj.vf v8, v4, fa0 -# CHECK-INST: vfsgnj.vf v8, v4, fa0 +th.vfsgnj.vf v8, v4, fa0 +# CHECK-INST: th.vfsgnj.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 22 -vfsgnjn.vv v8, v4, v20, v0.t -# CHECK-INST: vfsgnjn.vv v8, v4, v20, v0.t +th.vfsgnjn.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfsgnjn.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 24 -vfsgnjn.vv v8, v4, v20 -# CHECK-INST: vfsgnjn.vv v8, v4, v20 +th.vfsgnjn.vv v8, v4, v20 +# CHECK-INST: th.vfsgnjn.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 26 -vfsgnjn.vf v8, v4, fa0, v0.t -# CHECK-INST: vfsgnjn.vf v8, v4, fa0, v0.t +th.vfsgnjn.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfsgnjn.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 24 -vfsgnjn.vf v8, v4, fa0 -# CHECK-INST: vfsgnjn.vf v8, v4, fa0 +th.vfsgnjn.vf v8, v4, fa0 +# CHECK-INST: th.vfsgnjn.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 26 -vfsgnjx.vv v8, v4, v20, v0.t -# CHECK-INST: vfsgnjx.vv v8, v4, v20, v0.t +th.vfsgnjx.vv v8, v4, v20, v0.t +# CHECK-INST: th.vfsgnjx.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 28 -vfsgnjx.vv v8, v4, v20 -# CHECK-INST: vfsgnjx.vv v8, v4, v20 +th.vfsgnjx.vv v8, v4, v20 +# CHECK-INST: th.vfsgnjx.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 14 4a 2a -vfsgnjx.vf v8, v4, fa0, v0.t -# CHECK-INST: vfsgnjx.vf v8, v4, fa0, v0.t +th.vfsgnjx.vf v8, v4, fa0, v0.t +# CHECK-INST: th.vfsgnjx.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 28 -vfsgnjx.vf v8, v4, fa0 -# CHECK-INST: vfsgnjx.vf v8, v4, fa0 +th.vfsgnjx.vf v8, v4, fa0 +# CHECK-INST: th.vfsgnjx.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'F' (Single-Precision Floating-Point), 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 54 45 2a diff --git a/llvm/test/MC/RISCV/rvv0p71/store.s b/llvm/test/MC/RISCV/rvv0p71/store.s index f8572eabf1363..0945c46ed1ae9 100644 --- a/llvm/test/MC/RISCV/rvv0p71/store.s +++ b/llvm/test/MC/RISCV/rvv0p71/store.s @@ -1,201 +1,201 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv -M no-aliases - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector -M no-aliases - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vsb.v v8, (a0), v0.t -# CHECK-INST: vsb.v v8, (a0), v0.t +th.vsb.v v8, (a0), v0.t +# CHECK-INST: th.vsb.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 00 -vsb.v v8, (a0) -# CHECK-INST: vsb.v v8, (a0) +th.vsb.v v8, (a0) +# CHECK-INST: th.vsb.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 02 -vsh.v v8, (a0), v0.t -# CHECK-INST: vsh.v v8, (a0), v0.t +th.vsh.v v8, (a0), v0.t +# CHECK-INST: th.vsh.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 00 -vsh.v v8, (a0) -# CHECK-INST: vsh.v v8, (a0) +th.vsh.v v8, (a0) +# CHECK-INST: th.vsh.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 02 -vsw.v v8, (a0), v0.t -# CHECK-INST: vsw.v v8, (a0), v0.t +th.vsw.v v8, (a0), v0.t +# CHECK-INST: th.vsw.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 00 -vsw.v v8, (a0) -# CHECK-INST: vsw.v v8, (a0) +th.vsw.v v8, (a0) +# CHECK-INST: th.vsw.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 02 -vse.v v8, (a0), v0.t -# CHECK-INST: vse.v v8, (a0), v0.t +th.vse.v v8, (a0), v0.t +# CHECK-INST: th.vse.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0x00] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 00 -vse.v v8, (a0) -# CHECK-INST: vse.v v8, (a0) +th.vse.v v8, (a0) +# CHECK-INST: th.vse.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0x02] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 02 -vssb.v v8, (a0), a1 -# CHECK-INST: vssb.v v8, (a0), a1 +th.vssb.v v8, (a0), a1 +# CHECK-INST: th.vssb.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 0a -vssb.v v8, (a0), a1, v0.t -# CHECK-INST: vssb.v v8, (a0), a1, v0.t +th.vssb.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssb.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 08 -vssh.v v8, (a0), a1 -# CHECK-INST: vssh.v v8, (a0), a1 +th.vssh.v v8, (a0), a1 +# CHECK-INST: th.vssh.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 0a -vssh.v v8, (a0), a1, v0.t -# CHECK-INST: vssh.v v8, (a0), a1, v0.t +th.vssh.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssh.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 08 -vssw.v v8, (a0), a1 -# CHECK-INST: vssw.v v8, (a0), a1 +th.vssw.v v8, (a0), a1 +# CHECK-INST: th.vssw.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 0a -vssw.v v8, (a0), a1, v0.t -# CHECK-INST: vssw.v v8, (a0), a1, v0.t +th.vssw.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssw.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 08 -vsse.v v8, (a0), a1 -# CHECK-INST: vsse.v v8, (a0), a1 +th.vsse.v v8, (a0), a1 +# CHECK-INST: th.vsse.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0x0a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 0a -vsse.v v8, (a0), a1, v0.t -# CHECK-INST: vsse.v v8, (a0), a1, v0.t +th.vsse.v v8, (a0), a1, v0.t +# CHECK-INST: th.vsse.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0x08] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 08 -vsxb.v v8, (a0), v4 -# CHECK-INST: vsxb.v v8, (a0), v4 +th.vsxb.v v8, (a0), v4 +# CHECK-INST: th.vsxb.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 0e -vsxb.v v8, (a0), v4, v0.t -# CHECK-INST: vsxb.v v8, (a0), v4, v0.t +th.vsxb.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxb.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 0c -vsxh.v v8, (a0), v4 -# CHECK-INST: vsxh.v v8, (a0), v4 +th.vsxh.v v8, (a0), v4 +# CHECK-INST: th.vsxh.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 0e -vsxh.v v8, (a0), v4, v0.t -# CHECK-INST: vsxh.v v8, (a0), v4, v0.t +th.vsxh.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxh.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 0c -vsxw.v v8, (a0), v4 -# CHECK-INST: vsxw.v v8, (a0), v4 +th.vsxw.v v8, (a0), v4 +# CHECK-INST: th.vsxw.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 0e -vsxw.v v8, (a0), v4, v0.t -# CHECK-INST: vsxw.v v8, (a0), v4, v0.t +th.vsxw.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxw.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 0c -vsxe.v v8, (a0), v4 -# CHECK-INST: vsxe.v v8, (a0), v4 +th.vsxe.v v8, (a0), v4 +# CHECK-INST: th.vsxe.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0x0e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 0e -vsxe.v v8, (a0), v4, v0.t -# CHECK-INST: vsxe.v v8, (a0), v4, v0.t +th.vsxe.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxe.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0x0c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 0c -vsuxb.v v8, (a0), v4 -# CHECK-INST: vsuxb.v v8, (a0), v4 +th.vsuxb.v v8, (a0), v4 +# CHECK-INST: th.vsuxb.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 1e -vsuxb.v v8, (a0), v4, v0.t -# CHECK-INST: vsuxb.v v8, (a0), v4, v0.t +th.vsuxb.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsuxb.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 1c -vsuxh.v v8, (a0), v4 -# CHECK-INST: vsuxh.v v8, (a0), v4 +th.vsuxh.v v8, (a0), v4 +# CHECK-INST: th.vsuxh.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 1e -vsuxh.v v8, (a0), v4, v0.t -# CHECK-INST: vsuxh.v v8, (a0), v4, v0.t +th.vsuxh.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsuxh.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 1c -vsuxw.v v8, (a0), v4 -# CHECK-INST: vsuxw.v v8, (a0), v4 +th.vsuxw.v v8, (a0), v4 +# CHECK-INST: th.vsuxw.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 1e -vsuxw.v v8, (a0), v4, v0.t -# CHECK-INST: vsuxw.v v8, (a0), v4, v0.t +th.vsuxw.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsuxw.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 1c -vsuxe.v v8, (a0), v4 -# CHECK-INST: vsuxe.v v8, (a0), v4 +th.vsuxe.v v8, (a0), v4 +# CHECK-INST: th.vsuxe.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0x1e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 1e -vsuxe.v v8, (a0), v4, v0.t -# CHECK-INST: vsuxe.v v8, (a0), v4, v0.t +th.vsuxe.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsuxe.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0x1c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 1c diff --git a/llvm/test/MC/RISCV/rvv0p71/sub.s b/llvm/test/MC/RISCV/rvv0p71/sub.s index 2d42080105047..fb5de4391e2f5 100644 --- a/llvm/test/MC/RISCV/rvv0p71/sub.s +++ b/llvm/test/MC/RISCV/rvv0p71/sub.s @@ -1,273 +1,273 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vsub.vv v8, v4, v20, v0.t -# CHECK-INST: vsub.vv v8, v4, v20, v0.t +th.vsub.vv v8, v4, v20, v0.t +# CHECK-INST: th.vsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 08 -vsub.vv v8, v4, v20 -# CHECK-INST: vsub.vv v8, v4, v20 +th.vsub.vv v8, v4, v20 +# CHECK-INST: th.vsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 0a -vsub.vx v8, v4, a0, v0.t -# CHECK-INST: vsub.vx v8, v4, a0, v0.t +th.vsub.vx v8, v4, a0, v0.t +# CHECK-INST: th.vsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 08 -vsub.vx v8, v4, a0 -# CHECK-INST: vsub.vx v8, v4, a0 +th.vsub.vx v8, v4, a0 +# CHECK-INST: th.vsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 0a -vrsub.vx v8, v4, a0, v0.t -# CHECK-INST: vrsub.vx v8, v4, a0, v0.t +th.vrsub.vx v8, v4, a0, v0.t +# CHECK-INST: th.vrsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 0c -vrsub.vx v8, v4, a0 -# CHECK-INST: vrsub.vx v8, v4, a0 +th.vrsub.vx v8, v4, a0 +# CHECK-INST: th.vrsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 0e -vrsub.vi v8, v4, 15, v0.t -# CHECK-INST: vrsub.vi v8, v4, 15, v0.t +th.vrsub.vi v8, v4, 15, v0.t +# CHECK-INST: th.vrsub.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 0c -vrsub.vi v8, v4, 15 -# CHECK-INST: vrsub.vi v8, v4, 15 +th.vrsub.vi v8, v4, 15 +# CHECK-INST: th.vrsub.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 0e -vwsubu.vv v8, v4, v20, v0.t -# CHECK-INST: vwsubu.vv v8, v4, v20, v0.t +th.vwsubu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwsubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a c8 -vwsubu.vv v8, v4, v20 -# CHECK-INST: vwsubu.vv v8, v4, v20 +th.vwsubu.vv v8, v4, v20 +# CHECK-INST: th.vwsubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xca] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ca -vwsubu.vx v8, v4, a0, v0.t -# CHECK-INST: vwsubu.vx v8, v4, a0, v0.t +th.vwsubu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwsubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 c8 -vwsubu.vx v8, v4, a0 -# CHECK-INST: vwsubu.vx v8, v4, a0 +th.vwsubu.vx v8, v4, a0 +# CHECK-INST: th.vwsubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xca] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ca -vwsub.vv v8, v4, v20, v0.t -# CHECK-INST: vwsub.vv v8, v4, v20, v0.t +th.vwsub.vv v8, v4, v20, v0.t +# CHECK-INST: th.vwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xcc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a cc -vwsub.vv v8, v4, v20 -# CHECK-INST: vwsub.vv v8, v4, v20 +th.vwsub.vv v8, v4, v20 +# CHECK-INST: th.vwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xce] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a ce -vwsub.vx v8, v4, a0, v0.t -# CHECK-INST: vwsub.vx v8, v4, a0, v0.t +th.vwsub.vx v8, v4, a0, v0.t +# CHECK-INST: th.vwsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 cc -vwsub.vx v8, v4, a0 -# CHECK-INST: vwsub.vx v8, v4, a0 +th.vwsub.vx v8, v4, a0 +# CHECK-INST: th.vwsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 ce -vwsubu.wv v8, v4, v20, v0.t -# CHECK-INST: vwsubu.wv v8, v4, v20, v0.t +th.vwsubu.wv v8, v4, v20, v0.t +# CHECK-INST: th.vwsubu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a d8 -vwsubu.wv v8, v4, v20 -# CHECK-INST: vwsubu.wv v8, v4, v20 +th.vwsubu.wv v8, v4, v20 +# CHECK-INST: th.vwsubu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xda] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a da -vwsubu.wx v8, v4, a0, v0.t -# CHECK-INST: vwsubu.wx v8, v4, a0, v0.t +th.vwsubu.wx v8, v4, a0, v0.t +# CHECK-INST: th.vwsubu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 d8 -vwsubu.wx v8, v4, a0 -# CHECK-INST: vwsubu.wx v8, v4, a0 +th.vwsubu.wx v8, v4, a0 +# CHECK-INST: th.vwsubu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xda] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 da -vwsub.wv v8, v4, v20, v0.t -# CHECK-INST: vwsub.wv v8, v4, v20, v0.t +th.vwsub.wv v8, v4, v20, v0.t +# CHECK-INST: th.vwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xdc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a dc -vwsub.wv v8, v4, v20 -# CHECK-INST: vwsub.wv v8, v4, v20 +th.vwsub.wv v8, v4, v20 +# CHECK-INST: th.vwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xde] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 24 4a de -vwsub.wx v8, v4, a0, v0.t -# CHECK-INST: vwsub.wx v8, v4, a0, v0.t +th.vwsub.wx v8, v4, a0, v0.t +# CHECK-INST: th.vwsub.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xdc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 dc -vwsub.wx v8, v4, a0 -# CHECK-INST: vwsub.wx v8, v4, a0 +th.vwsub.wx v8, v4, a0 +# CHECK-INST: th.vwsub.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xde] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 64 45 de -vsbc.vvm v8, v4, v20, v0 -# CHECK-INST: vsbc.vvm v8, v4, v20, v0 +th.vsbc.vvm v8, v4, v20, v0 +# CHECK-INST: th.vsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 4a -vsbc.vvm v4, v4, v20, v0 -# CHECK-INST: vsbc.vvm v4, v4, v20, v0 +th.vsbc.vvm v4, v4, v20, v0 +# CHECK-INST: th.vsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 02 4a 4a -vsbc.vvm v8, v4, v8, v0 -# CHECK-INST: vsbc.vvm v8, v4, v8, v0 +th.vsbc.vvm v8, v4, v8, v0 +# CHECK-INST: th.vsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 44 4a -vsbc.vxm v8, v4, a0, v0 -# CHECK-INST: vsbc.vxm v8, v4, a0, v0 +th.vsbc.vxm v8, v4, a0, v0 +# CHECK-INST: th.vsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 4a -vmsbc.vvm v8, v4, v20, v0 -# CHECK-INST: vmsbc.vvm v8, v4, v20, v0 +th.vmsbc.vvm v8, v4, v20, v0 +# CHECK-INST: th.vmsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 4e -vmsbc.vvm v4, v4, v20, v0 -# CHECK-INST: vmsbc.vvm v4, v4, v20, v0 +th.vmsbc.vvm v4, v4, v20, v0 +# CHECK-INST: th.vmsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 02 4a 4e -vmsbc.vvm v8, v4, v8, v0 -# CHECK-INST: vmsbc.vvm v8, v4, v8, v0 +th.vmsbc.vvm v8, v4, v8, v0 +# CHECK-INST: th.vmsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 44 4e -vmsbc.vxm v8, v4, a0, v0 -# CHECK-INST: vmsbc.vxm v8, v4, a0, v0 +th.vmsbc.vxm v8, v4, a0, v0 +# CHECK-INST: th.vmsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 4e -vssubu.vv v8, v4, v20, v0.t -# CHECK-INST: vssubu.vv v8, v4, v20, v0.t +th.vssubu.vv v8, v4, v20, v0.t +# CHECK-INST: th.vssubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 88 -vssubu.vv v8, v4, v20 -# CHECK-INST: vssubu.vv v8, v4, v20 +th.vssubu.vv v8, v4, v20 +# CHECK-INST: th.vssubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 8a -vssubu.vx v8, v4, a0, v0.t -# CHECK-INST: vssubu.vx v8, v4, a0, v0.t +th.vssubu.vx v8, v4, a0, v0.t +# CHECK-INST: th.vssubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 88 -vssubu.vx v8, v4, a0 -# CHECK-INST: vssubu.vx v8, v4, a0 +th.vssubu.vx v8, v4, a0 +# CHECK-INST: th.vssubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 8a -vssub.vv v8, v4, v20, v0.t -# CHECK-INST: vssub.vv v8, v4, v20, v0.t +th.vssub.vv v8, v4, v20, v0.t +# CHECK-INST: th.vssub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 8c -vssub.vv v8, v4, v20 -# CHECK-INST: vssub.vv v8, v4, v20 +th.vssub.vv v8, v4, v20 +# CHECK-INST: th.vssub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 8e -vssub.vx v8, v4, a0, v0.t -# CHECK-INST: vssub.vx v8, v4, a0, v0.t +th.vssub.vx v8, v4, a0, v0.t +# CHECK-INST: th.vssub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 8c -vssub.vx v8, v4, a0 -# CHECK-INST: vssub.vx v8, v4, a0 +th.vssub.vx v8, v4, a0 +# CHECK-INST: th.vssub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 8e -vasub.vv v8, v4, v20, v0.t -# CHECK-INST: vasub.vv v8, v4, v20, v0.t +th.vasub.vv v8, v4, v20, v0.t +# CHECK-INST: th.vasub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 98 -vasub.vv v8, v4, v20 -# CHECK-INST: vasub.vv v8, v4, v20 +th.vasub.vv v8, v4, v20 +# CHECK-INST: th.vasub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 9a -vasub.vx v8, v4, a0, v0.t -# CHECK-INST: vasub.vx v8, v4, a0, v0.t +th.vasub.vx v8, v4, a0, v0.t +# CHECK-INST: th.vasub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 98 -vasub.vx v8, v4, a0 -# CHECK-INST: vasub.vx v8, v4, a0 +th.vasub.vx v8, v4, a0 +# CHECK-INST: th.vasub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 9a diff --git a/llvm/test/MC/RISCV/rvv0p71/vector-insns.s b/llvm/test/MC/RISCV/rvv0p71/vector-insns.s index c265756cf4d0b..2eafff623e795 100644 --- a/llvm/test/MC/RISCV/rvv0p71/vector-insns.s +++ b/llvm/test/MC/RISCV/rvv0p71/vector-insns.s @@ -2,6837 +2,6837 @@ # Golden value for this test: https://github.com/riscvarchive/riscv-binutils-gdb/blob/1aeeeab05f3c39e2bfc6e99384490d4c7f484ba0/gas/testsuite/gas/riscv/vector-insns.d # Generated using the script: https://gist.github.com/imkiva/05facf1a51ff8abfeeeea8fa7bc307ad#file-rvvtestgen-java -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+f,+a,+xtheadv,+xtheadvlsseg,+xtheadvamo %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+f,+a,+xtheadvector,+xtheadvlsseg,+xtheadvamo %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -vsetvl a0, a1, a2 -# CHECK-INST: vsetvl a0, a1, a2 +th.vsetvl a0, a1, a2 +# CHECK-INST: th.vsetvl a0, a1, a2 # CHECK-ENCODING: [0x57,0xf5,0xc5,0x80] -vsetvli a0, a1, 0 -# CHECK-INST: vsetvli a0, a1, e8, m1, d1 +th.vsetvli a0, a1, 0 +# CHECK-INST: th.vsetvli a0, a1, e8, m1, d1 # CHECK-ENCODING: [0x57,0xf5,0x05,0x00] -vsetvli a0, a1, 0x7ff -# CHECK-INST: vsetvli a0, a1, 2047 +th.vsetvli a0, a1, 0x7ff +# CHECK-INST: th.vsetvli a0, a1, 2047 # CHECK-ENCODING: [0x57,0xf5,0xf5,0x7f] -vsetvli a0, a1, e16,m2,d4 -# CHECK-INST: vsetvli a0, a1, e16, m2, d4 +th.vsetvli a0, a1, e16,m2,d4 +# CHECK-INST: th.vsetvli a0, a1, e16, m2, d4 # CHECK-ENCODING: [0x57,0xf5,0x55,0x04] -vlb.v v4, (a0) -# CHECK-INST: vlb.v v4, (a0) +th.vlb.v v4, (a0) +# CHECK-INST: th.vlb.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x12] -vlb.v v4, 0(a0) -# CHECK-INST: vlb.v v4, (a0) +th.vlb.v v4, 0(a0) +# CHECK-INST: th.vlb.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x12] -vlb.v v4, (a0), v0.t -# CHECK-INST: vlb.v v4, (a0), v0.t +th.vlb.v v4, (a0), v0.t +# CHECK-INST: th.vlb.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x10] -vlh.v v4, (a0) -# CHECK-INST: vlh.v v4, (a0) +th.vlh.v v4, (a0) +# CHECK-INST: th.vlh.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x12] -vlh.v v4, 0(a0) -# CHECK-INST: vlh.v v4, (a0) +th.vlh.v v4, 0(a0) +# CHECK-INST: th.vlh.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x12] -vlh.v v4, (a0), v0.t -# CHECK-INST: vlh.v v4, (a0), v0.t +th.vlh.v v4, (a0), v0.t +# CHECK-INST: th.vlh.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x10] -vlw.v v4, (a0) -# CHECK-INST: vlw.v v4, (a0) +th.vlw.v v4, (a0) +# CHECK-INST: th.vlw.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x12] -vlw.v v4, 0(a0) -# CHECK-INST: vlw.v v4, (a0) +th.vlw.v v4, 0(a0) +# CHECK-INST: th.vlw.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x12] -vlw.v v4, (a0), v0.t -# CHECK-INST: vlw.v v4, (a0), v0.t +th.vlw.v v4, (a0), v0.t +# CHECK-INST: th.vlw.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x10] -vlbu.v v4, (a0) -# CHECK-INST: vlbu.v v4, (a0) +th.vlbu.v v4, (a0) +# CHECK-INST: th.vlbu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x02] -vlbu.v v4, 0(a0) -# CHECK-INST: vlbu.v v4, (a0) +th.vlbu.v v4, 0(a0) +# CHECK-INST: th.vlbu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x02] -vlbu.v v4, (a0), v0.t -# CHECK-INST: vlbu.v v4, (a0), v0.t +th.vlbu.v v4, (a0), v0.t +# CHECK-INST: th.vlbu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x00] -vlhu.v v4, (a0) -# CHECK-INST: vlhu.v v4, (a0) +th.vlhu.v v4, (a0) +# CHECK-INST: th.vlhu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x02] -vlhu.v v4, 0(a0) -# CHECK-INST: vlhu.v v4, (a0) +th.vlhu.v v4, 0(a0) +# CHECK-INST: th.vlhu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x02] -vlhu.v v4, (a0), v0.t -# CHECK-INST: vlhu.v v4, (a0), v0.t +th.vlhu.v v4, (a0), v0.t +# CHECK-INST: th.vlhu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x00] -vlwu.v v4, (a0) -# CHECK-INST: vlwu.v v4, (a0) +th.vlwu.v v4, (a0) +# CHECK-INST: th.vlwu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x02] -vlwu.v v4, 0(a0) -# CHECK-INST: vlwu.v v4, (a0) +th.vlwu.v v4, 0(a0) +# CHECK-INST: th.vlwu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x02] -vlwu.v v4, (a0), v0.t -# CHECK-INST: vlwu.v v4, (a0), v0.t +th.vlwu.v v4, (a0), v0.t +# CHECK-INST: th.vlwu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x00] -vle.v v4, (a0) -# CHECK-INST: vle.v v4, (a0) +th.vle.v v4, (a0) +# CHECK-INST: th.vle.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x02] -vle.v v4, 0(a0) -# CHECK-INST: vle.v v4, (a0) +th.vle.v v4, 0(a0) +# CHECK-INST: th.vle.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x02] -vle.v v4, (a0), v0.t -# CHECK-INST: vle.v v4, (a0), v0.t +th.vle.v v4, (a0), v0.t +# CHECK-INST: th.vle.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x00] -vsb.v v4, (a0) -# CHECK-INST: vsb.v v4, (a0) +th.vsb.v v4, (a0) +# CHECK-INST: th.vsb.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x02] -vsb.v v4, 0(a0) -# CHECK-INST: vsb.v v4, (a0) +th.vsb.v v4, 0(a0) +# CHECK-INST: th.vsb.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x02] -vsb.v v4, (a0), v0.t -# CHECK-INST: vsb.v v4, (a0), v0.t +th.vsb.v v4, (a0), v0.t +# CHECK-INST: th.vsb.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0x00] -vsh.v v4, (a0) -# CHECK-INST: vsh.v v4, (a0) +th.vsh.v v4, (a0) +# CHECK-INST: th.vsh.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x02] -vsh.v v4, 0(a0) -# CHECK-INST: vsh.v v4, (a0) +th.vsh.v v4, 0(a0) +# CHECK-INST: th.vsh.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x02] -vsh.v v4, (a0), v0.t -# CHECK-INST: vsh.v v4, (a0), v0.t +th.vsh.v v4, (a0), v0.t +# CHECK-INST: th.vsh.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0x00] -vsw.v v4, (a0) -# CHECK-INST: vsw.v v4, (a0) +th.vsw.v v4, (a0) +# CHECK-INST: th.vsw.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x02] -vsw.v v4, 0(a0) -# CHECK-INST: vsw.v v4, (a0) +th.vsw.v v4, 0(a0) +# CHECK-INST: th.vsw.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x02] -vsw.v v4, (a0), v0.t -# CHECK-INST: vsw.v v4, (a0), v0.t +th.vsw.v v4, (a0), v0.t +# CHECK-INST: th.vsw.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0x00] -vse.v v4, (a0) -# CHECK-INST: vse.v v4, (a0) +th.vse.v v4, (a0) +# CHECK-INST: th.vse.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x02] -vse.v v4, 0(a0) -# CHECK-INST: vse.v v4, (a0) +th.vse.v v4, 0(a0) +# CHECK-INST: th.vse.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x02] -vse.v v4, (a0), v0.t -# CHECK-INST: vse.v v4, (a0), v0.t +th.vse.v v4, (a0), v0.t +# CHECK-INST: th.vse.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0x00] -vlsb.v v4, (a0), a1 -# CHECK-INST: vlsb.v v4, (a0), a1 +th.vlsb.v v4, (a0), a1 +# CHECK-INST: th.vlsb.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x1a] -vlsb.v v4, 0(a0), a1 -# CHECK-INST: vlsb.v v4, (a0), a1 +th.vlsb.v v4, 0(a0), a1 +# CHECK-INST: th.vlsb.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x1a] -vlsb.v v4, (a0), a1, v0.t -# CHECK-INST: vlsb.v v4, (a0), a1, v0.t +th.vlsb.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsb.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x18] -vlsh.v v4, (a0), a1 -# CHECK-INST: vlsh.v v4, (a0), a1 +th.vlsh.v v4, (a0), a1 +# CHECK-INST: th.vlsh.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x1a] -vlsh.v v4, 0(a0), a1 -# CHECK-INST: vlsh.v v4, (a0), a1 +th.vlsh.v v4, 0(a0), a1 +# CHECK-INST: th.vlsh.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x1a] -vlsh.v v4, (a0), a1, v0.t -# CHECK-INST: vlsh.v v4, (a0), a1, v0.t +th.vlsh.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsh.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x18] -vlsw.v v4, (a0), a1 -# CHECK-INST: vlsw.v v4, (a0), a1 +th.vlsw.v v4, (a0), a1 +# CHECK-INST: th.vlsw.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x1a] -vlsw.v v4, 0(a0), a1 -# CHECK-INST: vlsw.v v4, (a0), a1 +th.vlsw.v v4, 0(a0), a1 +# CHECK-INST: th.vlsw.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x1a] -vlsw.v v4, (a0), a1, v0.t -# CHECK-INST: vlsw.v v4, (a0), a1, v0.t +th.vlsw.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsw.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x18] -vlsbu.v v4, (a0), a1 -# CHECK-INST: vlsbu.v v4, (a0), a1 +th.vlsbu.v v4, (a0), a1 +# CHECK-INST: th.vlsbu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x0a] -vlsbu.v v4, 0(a0), a1 -# CHECK-INST: vlsbu.v v4, (a0), a1 +th.vlsbu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsbu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x0a] -vlsbu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsbu.v v4, (a0), a1, v0.t +th.vlsbu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsbu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x08] -vlshu.v v4, (a0), a1 -# CHECK-INST: vlshu.v v4, (a0), a1 +th.vlshu.v v4, (a0), a1 +# CHECK-INST: th.vlshu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x0a] -vlshu.v v4, 0(a0), a1 -# CHECK-INST: vlshu.v v4, (a0), a1 +th.vlshu.v v4, 0(a0), a1 +# CHECK-INST: th.vlshu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x0a] -vlshu.v v4, (a0), a1, v0.t -# CHECK-INST: vlshu.v v4, (a0), a1, v0.t +th.vlshu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlshu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x08] -vlswu.v v4, (a0), a1 -# CHECK-INST: vlswu.v v4, (a0), a1 +th.vlswu.v v4, (a0), a1 +# CHECK-INST: th.vlswu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x0a] -vlswu.v v4, 0(a0), a1 -# CHECK-INST: vlswu.v v4, (a0), a1 +th.vlswu.v v4, 0(a0), a1 +# CHECK-INST: th.vlswu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x0a] -vlswu.v v4, (a0), a1, v0.t -# CHECK-INST: vlswu.v v4, (a0), a1, v0.t +th.vlswu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlswu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x08] -vlse.v v4, (a0), a1 -# CHECK-INST: vlse.v v4, (a0), a1 +th.vlse.v v4, (a0), a1 +# CHECK-INST: th.vlse.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x0a] -vlse.v v4, 0(a0), a1 -# CHECK-INST: vlse.v v4, (a0), a1 +th.vlse.v v4, 0(a0), a1 +# CHECK-INST: th.vlse.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x0a] -vlse.v v4, (a0), a1, v0.t -# CHECK-INST: vlse.v v4, (a0), a1, v0.t +th.vlse.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlse.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0x08] -vssb.v v4, (a0), a1 -# CHECK-INST: vssb.v v4, (a0), a1 +th.vssb.v v4, (a0), a1 +# CHECK-INST: th.vssb.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x0a] -vssb.v v4, 0(a0), a1 -# CHECK-INST: vssb.v v4, (a0), a1 +th.vssb.v v4, 0(a0), a1 +# CHECK-INST: th.vssb.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x0a] -vssb.v v4, (a0), a1, v0.t -# CHECK-INST: vssb.v v4, (a0), a1, v0.t +th.vssb.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssb.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0x08] -vssh.v v4, (a0), a1 -# CHECK-INST: vssh.v v4, (a0), a1 +th.vssh.v v4, (a0), a1 +# CHECK-INST: th.vssh.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x0a] -vssh.v v4, 0(a0), a1 -# CHECK-INST: vssh.v v4, (a0), a1 +th.vssh.v v4, 0(a0), a1 +# CHECK-INST: th.vssh.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x0a] -vssh.v v4, (a0), a1, v0.t -# CHECK-INST: vssh.v v4, (a0), a1, v0.t +th.vssh.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssh.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0x08] -vssw.v v4, (a0), a1 -# CHECK-INST: vssw.v v4, (a0), a1 +th.vssw.v v4, (a0), a1 +# CHECK-INST: th.vssw.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x0a] -vssw.v v4, 0(a0), a1 -# CHECK-INST: vssw.v v4, (a0), a1 +th.vssw.v v4, 0(a0), a1 +# CHECK-INST: th.vssw.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x0a] -vssw.v v4, (a0), a1, v0.t -# CHECK-INST: vssw.v v4, (a0), a1, v0.t +th.vssw.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssw.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0x08] -vsse.v v4, (a0), a1 -# CHECK-INST: vsse.v v4, (a0), a1 +th.vsse.v v4, (a0), a1 +# CHECK-INST: th.vsse.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x0a] -vsse.v v4, 0(a0), a1 -# CHECK-INST: vsse.v v4, (a0), a1 +th.vsse.v v4, 0(a0), a1 +# CHECK-INST: th.vsse.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x0a] -vsse.v v4, (a0), a1, v0.t -# CHECK-INST: vsse.v v4, (a0), a1, v0.t +th.vsse.v v4, (a0), a1, v0.t +# CHECK-INST: th.vsse.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0x08] -vlxb.v v4, (a0), v12 -# CHECK-INST: vlxb.v v4, (a0), v12 +th.vlxb.v v4, (a0), v12 +# CHECK-INST: th.vlxb.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x1e] -vlxb.v v4, 0(a0), v12 -# CHECK-INST: vlxb.v v4, (a0), v12 +th.vlxb.v v4, 0(a0), v12 +# CHECK-INST: th.vlxb.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x1e] -vlxb.v v4, (a0), v12, v0.t -# CHECK-INST: vlxb.v v4, (a0), v12, v0.t +th.vlxb.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxb.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x1c] -vlxh.v v4, (a0), v12 -# CHECK-INST: vlxh.v v4, (a0), v12 +th.vlxh.v v4, (a0), v12 +# CHECK-INST: th.vlxh.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x1e] -vlxh.v v4, 0(a0), v12 -# CHECK-INST: vlxh.v v4, (a0), v12 +th.vlxh.v v4, 0(a0), v12 +# CHECK-INST: th.vlxh.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x1e] -vlxh.v v4, (a0), v12, v0.t -# CHECK-INST: vlxh.v v4, (a0), v12, v0.t +th.vlxh.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxh.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x1c] -vlxw.v v4, (a0), v12 -# CHECK-INST: vlxw.v v4, (a0), v12 +th.vlxw.v v4, (a0), v12 +# CHECK-INST: th.vlxw.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x1e] -vlxw.v v4, 0(a0), v12 -# CHECK-INST: vlxw.v v4, (a0), v12 +th.vlxw.v v4, 0(a0), v12 +# CHECK-INST: th.vlxw.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x1e] -vlxw.v v4, (a0), v12, v0.t -# CHECK-INST: vlxw.v v4, (a0), v12, v0.t +th.vlxw.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxw.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x1c] -vlxbu.v v4, (a0), v12 -# CHECK-INST: vlxbu.v v4, (a0), v12 +th.vlxbu.v v4, (a0), v12 +# CHECK-INST: th.vlxbu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x0e] -vlxbu.v v4, 0(a0), v12 -# CHECK-INST: vlxbu.v v4, (a0), v12 +th.vlxbu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxbu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x0e] -vlxbu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxbu.v v4, (a0), v12, v0.t +th.vlxbu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxbu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x0c] -vlxhu.v v4, (a0), v12 -# CHECK-INST: vlxhu.v v4, (a0), v12 +th.vlxhu.v v4, (a0), v12 +# CHECK-INST: th.vlxhu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x0e] -vlxhu.v v4, 0(a0), v12 -# CHECK-INST: vlxhu.v v4, (a0), v12 +th.vlxhu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxhu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x0e] -vlxhu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxhu.v v4, (a0), v12, v0.t +th.vlxhu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxhu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x0c] -vlxwu.v v4, (a0), v12 -# CHECK-INST: vlxwu.v v4, (a0), v12 +th.vlxwu.v v4, (a0), v12 +# CHECK-INST: th.vlxwu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x0e] -vlxwu.v v4, 0(a0), v12 -# CHECK-INST: vlxwu.v v4, (a0), v12 +th.vlxwu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxwu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x0e] -vlxwu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxwu.v v4, (a0), v12, v0.t +th.vlxwu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxwu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x0c] -vlxe.v v4, (a0), v12 -# CHECK-INST: vlxe.v v4, (a0), v12 +th.vlxe.v v4, (a0), v12 +# CHECK-INST: th.vlxe.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x0e] -vlxe.v v4, 0(a0), v12 -# CHECK-INST: vlxe.v v4, (a0), v12 +th.vlxe.v v4, 0(a0), v12 +# CHECK-INST: th.vlxe.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x0e] -vlxe.v v4, (a0), v12, v0.t -# CHECK-INST: vlxe.v v4, (a0), v12, v0.t +th.vlxe.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxe.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0x0c] -vsxb.v v4, (a0), v12 -# CHECK-INST: vsxb.v v4, (a0), v12 +th.vsxb.v v4, (a0), v12 +# CHECK-INST: th.vsxb.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x0e] -vsxb.v v4, 0(a0), v12 -# CHECK-INST: vsxb.v v4, (a0), v12 +th.vsxb.v v4, 0(a0), v12 +# CHECK-INST: th.vsxb.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x0e] -vsxb.v v4, (a0), v12, v0.t -# CHECK-INST: vsxb.v v4, (a0), v12, v0.t +th.vsxb.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxb.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0x0c] -vsxh.v v4, (a0), v12 -# CHECK-INST: vsxh.v v4, (a0), v12 +th.vsxh.v v4, (a0), v12 +# CHECK-INST: th.vsxh.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x0e] -vsxh.v v4, 0(a0), v12 -# CHECK-INST: vsxh.v v4, (a0), v12 +th.vsxh.v v4, 0(a0), v12 +# CHECK-INST: th.vsxh.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x0e] -vsxh.v v4, (a0), v12, v0.t -# CHECK-INST: vsxh.v v4, (a0), v12, v0.t +th.vsxh.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxh.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0x0c] -vsxw.v v4, (a0), v12 -# CHECK-INST: vsxw.v v4, (a0), v12 +th.vsxw.v v4, (a0), v12 +# CHECK-INST: th.vsxw.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x0e] -vsxw.v v4, 0(a0), v12 -# CHECK-INST: vsxw.v v4, (a0), v12 +th.vsxw.v v4, 0(a0), v12 +# CHECK-INST: th.vsxw.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x0e] -vsxw.v v4, (a0), v12, v0.t -# CHECK-INST: vsxw.v v4, (a0), v12, v0.t +th.vsxw.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxw.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0x0c] -vsxe.v v4, (a0), v12 -# CHECK-INST: vsxe.v v4, (a0), v12 +th.vsxe.v v4, (a0), v12 +# CHECK-INST: th.vsxe.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x0e] -vsxe.v v4, 0(a0), v12 -# CHECK-INST: vsxe.v v4, (a0), v12 +th.vsxe.v v4, 0(a0), v12 +# CHECK-INST: th.vsxe.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x0e] -vsxe.v v4, (a0), v12, v0.t -# CHECK-INST: vsxe.v v4, (a0), v12, v0.t +th.vsxe.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxe.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0x0c] -vsuxb.v v4, (a0), v12 -# CHECK-INST: vsuxb.v v4, (a0), v12 +th.vsuxb.v v4, (a0), v12 +# CHECK-INST: th.vsuxb.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x1e] -vsuxb.v v4, 0(a0), v12 -# CHECK-INST: vsuxb.v v4, (a0), v12 +th.vsuxb.v v4, 0(a0), v12 +# CHECK-INST: th.vsuxb.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x1e] -vsuxb.v v4, (a0), v12, v0.t -# CHECK-INST: vsuxb.v v4, (a0), v12, v0.t +th.vsuxb.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsuxb.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0x1c] -vsuxh.v v4, (a0), v12 -# CHECK-INST: vsuxh.v v4, (a0), v12 +th.vsuxh.v v4, (a0), v12 +# CHECK-INST: th.vsuxh.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x1e] -vsuxh.v v4, 0(a0), v12 -# CHECK-INST: vsuxh.v v4, (a0), v12 +th.vsuxh.v v4, 0(a0), v12 +# CHECK-INST: th.vsuxh.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x1e] -vsuxh.v v4, (a0), v12, v0.t -# CHECK-INST: vsuxh.v v4, (a0), v12, v0.t +th.vsuxh.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsuxh.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0x1c] -vsuxw.v v4, (a0), v12 -# CHECK-INST: vsuxw.v v4, (a0), v12 +th.vsuxw.v v4, (a0), v12 +# CHECK-INST: th.vsuxw.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x1e] -vsuxw.v v4, 0(a0), v12 -# CHECK-INST: vsuxw.v v4, (a0), v12 +th.vsuxw.v v4, 0(a0), v12 +# CHECK-INST: th.vsuxw.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x1e] -vsuxw.v v4, (a0), v12, v0.t -# CHECK-INST: vsuxw.v v4, (a0), v12, v0.t +th.vsuxw.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsuxw.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0x1c] -vsuxe.v v4, (a0), v12 -# CHECK-INST: vsuxe.v v4, (a0), v12 +th.vsuxe.v v4, (a0), v12 +# CHECK-INST: th.vsuxe.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x1e] -vsuxe.v v4, 0(a0), v12 -# CHECK-INST: vsuxe.v v4, (a0), v12 +th.vsuxe.v v4, 0(a0), v12 +# CHECK-INST: th.vsuxe.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x1e] -vsuxe.v v4, (a0), v12, v0.t -# CHECK-INST: vsuxe.v v4, (a0), v12, v0.t +th.vsuxe.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsuxe.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0x1c] -vlbff.v v4, (a0) -# CHECK-INST: vlbff.v v4, (a0) +th.vlbff.v v4, (a0) +# CHECK-INST: th.vlbff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x13] -vlbff.v v4, 0(a0) -# CHECK-INST: vlbff.v v4, (a0) +th.vlbff.v v4, 0(a0) +# CHECK-INST: th.vlbff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x13] -vlbff.v v4, (a0), v0.t -# CHECK-INST: vlbff.v v4, (a0), v0.t +th.vlbff.v v4, (a0), v0.t +# CHECK-INST: th.vlbff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x11] -vlhff.v v4, (a0) -# CHECK-INST: vlhff.v v4, (a0) +th.vlhff.v v4, (a0) +# CHECK-INST: th.vlhff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x13] -vlhff.v v4, 0(a0) -# CHECK-INST: vlhff.v v4, (a0) +th.vlhff.v v4, 0(a0) +# CHECK-INST: th.vlhff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x13] -vlhff.v v4, (a0), v0.t -# CHECK-INST: vlhff.v v4, (a0), v0.t +th.vlhff.v v4, (a0), v0.t +# CHECK-INST: th.vlhff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x11] -vlwff.v v4, (a0) -# CHECK-INST: vlwff.v v4, (a0) +th.vlwff.v v4, (a0) +# CHECK-INST: th.vlwff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x13] -vlwff.v v4, 0(a0) -# CHECK-INST: vlwff.v v4, (a0) +th.vlwff.v v4, 0(a0) +# CHECK-INST: th.vlwff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x13] -vlwff.v v4, (a0), v0.t -# CHECK-INST: vlwff.v v4, (a0), v0.t +th.vlwff.v v4, (a0), v0.t +# CHECK-INST: th.vlwff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x11] -vlbuff.v v4, (a0) -# CHECK-INST: vlbuff.v v4, (a0) +th.vlbuff.v v4, (a0) +# CHECK-INST: th.vlbuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x03] -vlbuff.v v4, 0(a0) -# CHECK-INST: vlbuff.v v4, (a0) +th.vlbuff.v v4, 0(a0) +# CHECK-INST: th.vlbuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x03] -vlbuff.v v4, (a0), v0.t -# CHECK-INST: vlbuff.v v4, (a0), v0.t +th.vlbuff.v v4, (a0), v0.t +# CHECK-INST: th.vlbuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x01] -vlhuff.v v4, (a0) -# CHECK-INST: vlhuff.v v4, (a0) +th.vlhuff.v v4, (a0) +# CHECK-INST: th.vlhuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x03] -vlhuff.v v4, 0(a0) -# CHECK-INST: vlhuff.v v4, (a0) +th.vlhuff.v v4, 0(a0) +# CHECK-INST: th.vlhuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x03] -vlhuff.v v4, (a0), v0.t -# CHECK-INST: vlhuff.v v4, (a0), v0.t +th.vlhuff.v v4, (a0), v0.t +# CHECK-INST: th.vlhuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x01] -vlwuff.v v4, (a0) -# CHECK-INST: vlwuff.v v4, (a0) +th.vlwuff.v v4, (a0) +# CHECK-INST: th.vlwuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x03] -vlwuff.v v4, 0(a0) -# CHECK-INST: vlwuff.v v4, (a0) +th.vlwuff.v v4, 0(a0) +# CHECK-INST: th.vlwuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x03] -vlwuff.v v4, (a0), v0.t -# CHECK-INST: vlwuff.v v4, (a0), v0.t +th.vlwuff.v v4, (a0), v0.t +# CHECK-INST: th.vlwuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x01] -vleff.v v4, (a0) -# CHECK-INST: vleff.v v4, (a0) +th.vleff.v v4, (a0) +# CHECK-INST: th.vleff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x03] -vleff.v v4, 0(a0) -# CHECK-INST: vleff.v v4, (a0) +th.vleff.v v4, 0(a0) +# CHECK-INST: th.vleff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x03] -vleff.v v4, (a0), v0.t -# CHECK-INST: vleff.v v4, (a0), v0.t +th.vleff.v v4, (a0), v0.t +# CHECK-INST: th.vleff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x01] -vlseg2b.v v4, (a0) -# CHECK-INST: vlseg2b.v v4, (a0) +th.vlseg2b.v v4, (a0) +# CHECK-INST: th.vlseg2b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x32] -vlseg2b.v v4, 0(a0) -# CHECK-INST: vlseg2b.v v4, (a0) +th.vlseg2b.v v4, 0(a0) +# CHECK-INST: th.vlseg2b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x32] -vlseg2b.v v4, (a0), v0.t -# CHECK-INST: vlseg2b.v v4, (a0), v0.t +th.vlseg2b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x30] -vlseg2h.v v4, (a0) -# CHECK-INST: vlseg2h.v v4, (a0) +th.vlseg2h.v v4, (a0) +# CHECK-INST: th.vlseg2h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x32] -vlseg2h.v v4, 0(a0) -# CHECK-INST: vlseg2h.v v4, (a0) +th.vlseg2h.v v4, 0(a0) +# CHECK-INST: th.vlseg2h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x32] -vlseg2h.v v4, (a0), v0.t -# CHECK-INST: vlseg2h.v v4, (a0), v0.t +th.vlseg2h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x30] -vlseg2w.v v4, (a0) -# CHECK-INST: vlseg2w.v v4, (a0) +th.vlseg2w.v v4, (a0) +# CHECK-INST: th.vlseg2w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x32] -vlseg2w.v v4, 0(a0) -# CHECK-INST: vlseg2w.v v4, (a0) +th.vlseg2w.v v4, 0(a0) +# CHECK-INST: th.vlseg2w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x32] -vlseg2w.v v4, (a0), v0.t -# CHECK-INST: vlseg2w.v v4, (a0), v0.t +th.vlseg2w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x30] -vlseg2bu.v v4, (a0) -# CHECK-INST: vlseg2bu.v v4, (a0) +th.vlseg2bu.v v4, (a0) +# CHECK-INST: th.vlseg2bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x22] -vlseg2bu.v v4, 0(a0) -# CHECK-INST: vlseg2bu.v v4, (a0) +th.vlseg2bu.v v4, 0(a0) +# CHECK-INST: th.vlseg2bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x22] -vlseg2bu.v v4, (a0), v0.t -# CHECK-INST: vlseg2bu.v v4, (a0), v0.t +th.vlseg2bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x20] -vlseg2hu.v v4, (a0) -# CHECK-INST: vlseg2hu.v v4, (a0) +th.vlseg2hu.v v4, (a0) +# CHECK-INST: th.vlseg2hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x22] -vlseg2hu.v v4, 0(a0) -# CHECK-INST: vlseg2hu.v v4, (a0) +th.vlseg2hu.v v4, 0(a0) +# CHECK-INST: th.vlseg2hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x22] -vlseg2hu.v v4, (a0), v0.t -# CHECK-INST: vlseg2hu.v v4, (a0), v0.t +th.vlseg2hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x20] -vlseg2wu.v v4, (a0) -# CHECK-INST: vlseg2wu.v v4, (a0) +th.vlseg2wu.v v4, (a0) +# CHECK-INST: th.vlseg2wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x22] -vlseg2wu.v v4, 0(a0) -# CHECK-INST: vlseg2wu.v v4, (a0) +th.vlseg2wu.v v4, 0(a0) +# CHECK-INST: th.vlseg2wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x22] -vlseg2wu.v v4, (a0), v0.t -# CHECK-INST: vlseg2wu.v v4, (a0), v0.t +th.vlseg2wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x20] -vlseg2e.v v4, (a0) -# CHECK-INST: vlseg2e.v v4, (a0) +th.vlseg2e.v v4, (a0) +# CHECK-INST: th.vlseg2e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x22] -vlseg2e.v v4, 0(a0) -# CHECK-INST: vlseg2e.v v4, (a0) +th.vlseg2e.v v4, 0(a0) +# CHECK-INST: th.vlseg2e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x22] -vlseg2e.v v4, (a0), v0.t -# CHECK-INST: vlseg2e.v v4, (a0), v0.t +th.vlseg2e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x20] -vsseg2b.v v4, (a0) -# CHECK-INST: vsseg2b.v v4, (a0) +th.vsseg2b.v v4, (a0) +# CHECK-INST: th.vsseg2b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x22] -vsseg2b.v v4, 0(a0) -# CHECK-INST: vsseg2b.v v4, (a0) +th.vsseg2b.v v4, 0(a0) +# CHECK-INST: th.vsseg2b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x22] -vsseg2b.v v4, (a0), v0.t -# CHECK-INST: vsseg2b.v v4, (a0), v0.t +th.vsseg2b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg2b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0x20] -vsseg2h.v v4, (a0) -# CHECK-INST: vsseg2h.v v4, (a0) +th.vsseg2h.v v4, (a0) +# CHECK-INST: th.vsseg2h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x22] -vsseg2h.v v4, 0(a0) -# CHECK-INST: vsseg2h.v v4, (a0) +th.vsseg2h.v v4, 0(a0) +# CHECK-INST: th.vsseg2h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x22] -vsseg2h.v v4, (a0), v0.t -# CHECK-INST: vsseg2h.v v4, (a0), v0.t +th.vsseg2h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg2h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0x20] -vsseg2w.v v4, (a0) -# CHECK-INST: vsseg2w.v v4, (a0) +th.vsseg2w.v v4, (a0) +# CHECK-INST: th.vsseg2w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x22] -vsseg2w.v v4, 0(a0) -# CHECK-INST: vsseg2w.v v4, (a0) +th.vsseg2w.v v4, 0(a0) +# CHECK-INST: th.vsseg2w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x22] -vsseg2w.v v4, (a0), v0.t -# CHECK-INST: vsseg2w.v v4, (a0), v0.t +th.vsseg2w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg2w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0x20] -vsseg2e.v v4, (a0) -# CHECK-INST: vsseg2e.v v4, (a0) +th.vsseg2e.v v4, (a0) +# CHECK-INST: th.vsseg2e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x22] -vsseg2e.v v4, 0(a0) -# CHECK-INST: vsseg2e.v v4, (a0) +th.vsseg2e.v v4, 0(a0) +# CHECK-INST: th.vsseg2e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x22] -vsseg2e.v v4, (a0), v0.t -# CHECK-INST: vsseg2e.v v4, (a0), v0.t +th.vsseg2e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg2e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0x20] -vlseg3b.v v4, (a0) -# CHECK-INST: vlseg3b.v v4, (a0) +th.vlseg3b.v v4, (a0) +# CHECK-INST: th.vlseg3b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x52] -vlseg3b.v v4, 0(a0) -# CHECK-INST: vlseg3b.v v4, (a0) +th.vlseg3b.v v4, 0(a0) +# CHECK-INST: th.vlseg3b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x52] -vlseg3b.v v4, (a0), v0.t -# CHECK-INST: vlseg3b.v v4, (a0), v0.t +th.vlseg3b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x50] -vlseg3h.v v4, (a0) -# CHECK-INST: vlseg3h.v v4, (a0) +th.vlseg3h.v v4, (a0) +# CHECK-INST: th.vlseg3h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x52] -vlseg3h.v v4, 0(a0) -# CHECK-INST: vlseg3h.v v4, (a0) +th.vlseg3h.v v4, 0(a0) +# CHECK-INST: th.vlseg3h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x52] -vlseg3h.v v4, (a0), v0.t -# CHECK-INST: vlseg3h.v v4, (a0), v0.t +th.vlseg3h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x50] -vlseg3w.v v4, (a0) -# CHECK-INST: vlseg3w.v v4, (a0) +th.vlseg3w.v v4, (a0) +# CHECK-INST: th.vlseg3w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x52] -vlseg3w.v v4, 0(a0) -# CHECK-INST: vlseg3w.v v4, (a0) +th.vlseg3w.v v4, 0(a0) +# CHECK-INST: th.vlseg3w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x52] -vlseg3w.v v4, (a0), v0.t -# CHECK-INST: vlseg3w.v v4, (a0), v0.t +th.vlseg3w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x50] -vlseg3bu.v v4, (a0) -# CHECK-INST: vlseg3bu.v v4, (a0) +th.vlseg3bu.v v4, (a0) +# CHECK-INST: th.vlseg3bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x42] -vlseg3bu.v v4, 0(a0) -# CHECK-INST: vlseg3bu.v v4, (a0) +th.vlseg3bu.v v4, 0(a0) +# CHECK-INST: th.vlseg3bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x42] -vlseg3bu.v v4, (a0), v0.t -# CHECK-INST: vlseg3bu.v v4, (a0), v0.t +th.vlseg3bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x40] -vlseg3hu.v v4, (a0) -# CHECK-INST: vlseg3hu.v v4, (a0) +th.vlseg3hu.v v4, (a0) +# CHECK-INST: th.vlseg3hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x42] -vlseg3hu.v v4, 0(a0) -# CHECK-INST: vlseg3hu.v v4, (a0) +th.vlseg3hu.v v4, 0(a0) +# CHECK-INST: th.vlseg3hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x42] -vlseg3hu.v v4, (a0), v0.t -# CHECK-INST: vlseg3hu.v v4, (a0), v0.t +th.vlseg3hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x40] -vlseg3wu.v v4, (a0) -# CHECK-INST: vlseg3wu.v v4, (a0) +th.vlseg3wu.v v4, (a0) +# CHECK-INST: th.vlseg3wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x42] -vlseg3wu.v v4, 0(a0) -# CHECK-INST: vlseg3wu.v v4, (a0) +th.vlseg3wu.v v4, 0(a0) +# CHECK-INST: th.vlseg3wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x42] -vlseg3wu.v v4, (a0), v0.t -# CHECK-INST: vlseg3wu.v v4, (a0), v0.t +th.vlseg3wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x40] -vlseg3e.v v4, (a0) -# CHECK-INST: vlseg3e.v v4, (a0) +th.vlseg3e.v v4, (a0) +# CHECK-INST: th.vlseg3e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x42] -vlseg3e.v v4, 0(a0) -# CHECK-INST: vlseg3e.v v4, (a0) +th.vlseg3e.v v4, 0(a0) +# CHECK-INST: th.vlseg3e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x42] -vlseg3e.v v4, (a0), v0.t -# CHECK-INST: vlseg3e.v v4, (a0), v0.t +th.vlseg3e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x40] -vsseg3b.v v4, (a0) -# CHECK-INST: vsseg3b.v v4, (a0) +th.vsseg3b.v v4, (a0) +# CHECK-INST: th.vsseg3b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x42] -vsseg3b.v v4, 0(a0) -# CHECK-INST: vsseg3b.v v4, (a0) +th.vsseg3b.v v4, 0(a0) +# CHECK-INST: th.vsseg3b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x42] -vsseg3b.v v4, (a0), v0.t -# CHECK-INST: vsseg3b.v v4, (a0), v0.t +th.vsseg3b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg3b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0x40] -vsseg3h.v v4, (a0) -# CHECK-INST: vsseg3h.v v4, (a0) +th.vsseg3h.v v4, (a0) +# CHECK-INST: th.vsseg3h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x42] -vsseg3h.v v4, 0(a0) -# CHECK-INST: vsseg3h.v v4, (a0) +th.vsseg3h.v v4, 0(a0) +# CHECK-INST: th.vsseg3h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x42] -vsseg3h.v v4, (a0), v0.t -# CHECK-INST: vsseg3h.v v4, (a0), v0.t +th.vsseg3h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg3h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0x40] -vsseg3w.v v4, (a0) -# CHECK-INST: vsseg3w.v v4, (a0) +th.vsseg3w.v v4, (a0) +# CHECK-INST: th.vsseg3w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x42] -vsseg3w.v v4, 0(a0) -# CHECK-INST: vsseg3w.v v4, (a0) +th.vsseg3w.v v4, 0(a0) +# CHECK-INST: th.vsseg3w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x42] -vsseg3w.v v4, (a0), v0.t -# CHECK-INST: vsseg3w.v v4, (a0), v0.t +th.vsseg3w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg3w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0x40] -vsseg3e.v v4, (a0) -# CHECK-INST: vsseg3e.v v4, (a0) +th.vsseg3e.v v4, (a0) +# CHECK-INST: th.vsseg3e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x42] -vsseg3e.v v4, 0(a0) -# CHECK-INST: vsseg3e.v v4, (a0) +th.vsseg3e.v v4, 0(a0) +# CHECK-INST: th.vsseg3e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x42] -vsseg3e.v v4, (a0), v0.t -# CHECK-INST: vsseg3e.v v4, (a0), v0.t +th.vsseg3e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg3e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0x40] -vlseg4b.v v4, (a0) -# CHECK-INST: vlseg4b.v v4, (a0) +th.vlseg4b.v v4, (a0) +# CHECK-INST: th.vlseg4b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x72] -vlseg4b.v v4, 0(a0) -# CHECK-INST: vlseg4b.v v4, (a0) +th.vlseg4b.v v4, 0(a0) +# CHECK-INST: th.vlseg4b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x72] -vlseg4b.v v4, (a0), v0.t -# CHECK-INST: vlseg4b.v v4, (a0), v0.t +th.vlseg4b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x70] -vlseg4h.v v4, (a0) -# CHECK-INST: vlseg4h.v v4, (a0) +th.vlseg4h.v v4, (a0) +# CHECK-INST: th.vlseg4h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x72] -vlseg4h.v v4, 0(a0) -# CHECK-INST: vlseg4h.v v4, (a0) +th.vlseg4h.v v4, 0(a0) +# CHECK-INST: th.vlseg4h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x72] -vlseg4h.v v4, (a0), v0.t -# CHECK-INST: vlseg4h.v v4, (a0), v0.t +th.vlseg4h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x70] -vlseg4w.v v4, (a0) -# CHECK-INST: vlseg4w.v v4, (a0) +th.vlseg4w.v v4, (a0) +# CHECK-INST: th.vlseg4w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x72] -vlseg4w.v v4, 0(a0) -# CHECK-INST: vlseg4w.v v4, (a0) +th.vlseg4w.v v4, 0(a0) +# CHECK-INST: th.vlseg4w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x72] -vlseg4w.v v4, (a0), v0.t -# CHECK-INST: vlseg4w.v v4, (a0), v0.t +th.vlseg4w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x70] -vlseg4bu.v v4, (a0) -# CHECK-INST: vlseg4bu.v v4, (a0) +th.vlseg4bu.v v4, (a0) +# CHECK-INST: th.vlseg4bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x62] -vlseg4bu.v v4, 0(a0) -# CHECK-INST: vlseg4bu.v v4, (a0) +th.vlseg4bu.v v4, 0(a0) +# CHECK-INST: th.vlseg4bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x62] -vlseg4bu.v v4, (a0), v0.t -# CHECK-INST: vlseg4bu.v v4, (a0), v0.t +th.vlseg4bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x60] -vlseg4hu.v v4, (a0) -# CHECK-INST: vlseg4hu.v v4, (a0) +th.vlseg4hu.v v4, (a0) +# CHECK-INST: th.vlseg4hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x62] -vlseg4hu.v v4, 0(a0) -# CHECK-INST: vlseg4hu.v v4, (a0) +th.vlseg4hu.v v4, 0(a0) +# CHECK-INST: th.vlseg4hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x62] -vlseg4hu.v v4, (a0), v0.t -# CHECK-INST: vlseg4hu.v v4, (a0), v0.t +th.vlseg4hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x60] -vlseg4wu.v v4, (a0) -# CHECK-INST: vlseg4wu.v v4, (a0) +th.vlseg4wu.v v4, (a0) +# CHECK-INST: th.vlseg4wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x62] -vlseg4wu.v v4, 0(a0) -# CHECK-INST: vlseg4wu.v v4, (a0) +th.vlseg4wu.v v4, 0(a0) +# CHECK-INST: th.vlseg4wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x62] -vlseg4wu.v v4, (a0), v0.t -# CHECK-INST: vlseg4wu.v v4, (a0), v0.t +th.vlseg4wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x60] -vlseg4e.v v4, (a0) -# CHECK-INST: vlseg4e.v v4, (a0) +th.vlseg4e.v v4, (a0) +# CHECK-INST: th.vlseg4e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x62] -vlseg4e.v v4, 0(a0) -# CHECK-INST: vlseg4e.v v4, (a0) +th.vlseg4e.v v4, 0(a0) +# CHECK-INST: th.vlseg4e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x62] -vlseg4e.v v4, (a0), v0.t -# CHECK-INST: vlseg4e.v v4, (a0), v0.t +th.vlseg4e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x60] -vsseg4b.v v4, (a0) -# CHECK-INST: vsseg4b.v v4, (a0) +th.vsseg4b.v v4, (a0) +# CHECK-INST: th.vsseg4b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x62] -vsseg4b.v v4, 0(a0) -# CHECK-INST: vsseg4b.v v4, (a0) +th.vsseg4b.v v4, 0(a0) +# CHECK-INST: th.vsseg4b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x62] -vsseg4b.v v4, (a0), v0.t -# CHECK-INST: vsseg4b.v v4, (a0), v0.t +th.vsseg4b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg4b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0x60] -vsseg4h.v v4, (a0) -# CHECK-INST: vsseg4h.v v4, (a0) +th.vsseg4h.v v4, (a0) +# CHECK-INST: th.vsseg4h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x62] -vsseg4h.v v4, 0(a0) -# CHECK-INST: vsseg4h.v v4, (a0) +th.vsseg4h.v v4, 0(a0) +# CHECK-INST: th.vsseg4h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x62] -vsseg4h.v v4, (a0), v0.t -# CHECK-INST: vsseg4h.v v4, (a0), v0.t +th.vsseg4h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg4h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0x60] -vsseg4w.v v4, (a0) -# CHECK-INST: vsseg4w.v v4, (a0) +th.vsseg4w.v v4, (a0) +# CHECK-INST: th.vsseg4w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x62] -vsseg4w.v v4, 0(a0) -# CHECK-INST: vsseg4w.v v4, (a0) +th.vsseg4w.v v4, 0(a0) +# CHECK-INST: th.vsseg4w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x62] -vsseg4w.v v4, (a0), v0.t -# CHECK-INST: vsseg4w.v v4, (a0), v0.t +th.vsseg4w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg4w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0x60] -vsseg4e.v v4, (a0) -# CHECK-INST: vsseg4e.v v4, (a0) +th.vsseg4e.v v4, (a0) +# CHECK-INST: th.vsseg4e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x62] -vsseg4e.v v4, 0(a0) -# CHECK-INST: vsseg4e.v v4, (a0) +th.vsseg4e.v v4, 0(a0) +# CHECK-INST: th.vsseg4e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x62] -vsseg4e.v v4, (a0), v0.t -# CHECK-INST: vsseg4e.v v4, (a0), v0.t +th.vsseg4e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg4e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0x60] -vlseg5b.v v4, (a0) -# CHECK-INST: vlseg5b.v v4, (a0) +th.vlseg5b.v v4, (a0) +# CHECK-INST: th.vlseg5b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x92] -vlseg5b.v v4, 0(a0) -# CHECK-INST: vlseg5b.v v4, (a0) +th.vlseg5b.v v4, 0(a0) +# CHECK-INST: th.vlseg5b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x92] -vlseg5b.v v4, (a0), v0.t -# CHECK-INST: vlseg5b.v v4, (a0), v0.t +th.vlseg5b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x90] -vlseg5h.v v4, (a0) -# CHECK-INST: vlseg5h.v v4, (a0) +th.vlseg5h.v v4, (a0) +# CHECK-INST: th.vlseg5h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x92] -vlseg5h.v v4, 0(a0) -# CHECK-INST: vlseg5h.v v4, (a0) +th.vlseg5h.v v4, 0(a0) +# CHECK-INST: th.vlseg5h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x92] -vlseg5h.v v4, (a0), v0.t -# CHECK-INST: vlseg5h.v v4, (a0), v0.t +th.vlseg5h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x90] -vlseg5w.v v4, (a0) -# CHECK-INST: vlseg5w.v v4, (a0) +th.vlseg5w.v v4, (a0) +# CHECK-INST: th.vlseg5w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x92] -vlseg5w.v v4, 0(a0) -# CHECK-INST: vlseg5w.v v4, (a0) +th.vlseg5w.v v4, 0(a0) +# CHECK-INST: th.vlseg5w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x92] -vlseg5w.v v4, (a0), v0.t -# CHECK-INST: vlseg5w.v v4, (a0), v0.t +th.vlseg5w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x90] -vlseg5bu.v v4, (a0) -# CHECK-INST: vlseg5bu.v v4, (a0) +th.vlseg5bu.v v4, (a0) +# CHECK-INST: th.vlseg5bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x82] -vlseg5bu.v v4, 0(a0) -# CHECK-INST: vlseg5bu.v v4, (a0) +th.vlseg5bu.v v4, 0(a0) +# CHECK-INST: th.vlseg5bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x82] -vlseg5bu.v v4, (a0), v0.t -# CHECK-INST: vlseg5bu.v v4, (a0), v0.t +th.vlseg5bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x80] -vlseg5hu.v v4, (a0) -# CHECK-INST: vlseg5hu.v v4, (a0) +th.vlseg5hu.v v4, (a0) +# CHECK-INST: th.vlseg5hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x82] -vlseg5hu.v v4, 0(a0) -# CHECK-INST: vlseg5hu.v v4, (a0) +th.vlseg5hu.v v4, 0(a0) +# CHECK-INST: th.vlseg5hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x82] -vlseg5hu.v v4, (a0), v0.t -# CHECK-INST: vlseg5hu.v v4, (a0), v0.t +th.vlseg5hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x80] -vlseg5wu.v v4, (a0) -# CHECK-INST: vlseg5wu.v v4, (a0) +th.vlseg5wu.v v4, (a0) +# CHECK-INST: th.vlseg5wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x82] -vlseg5wu.v v4, 0(a0) -# CHECK-INST: vlseg5wu.v v4, (a0) +th.vlseg5wu.v v4, 0(a0) +# CHECK-INST: th.vlseg5wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x82] -vlseg5wu.v v4, (a0), v0.t -# CHECK-INST: vlseg5wu.v v4, (a0), v0.t +th.vlseg5wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x80] -vlseg5e.v v4, (a0) -# CHECK-INST: vlseg5e.v v4, (a0) +th.vlseg5e.v v4, (a0) +# CHECK-INST: th.vlseg5e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x82] -vlseg5e.v v4, 0(a0) -# CHECK-INST: vlseg5e.v v4, (a0) +th.vlseg5e.v v4, 0(a0) +# CHECK-INST: th.vlseg5e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x82] -vlseg5e.v v4, (a0), v0.t -# CHECK-INST: vlseg5e.v v4, (a0), v0.t +th.vlseg5e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x80] -vsseg5b.v v4, (a0) -# CHECK-INST: vsseg5b.v v4, (a0) +th.vsseg5b.v v4, (a0) +# CHECK-INST: th.vsseg5b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x82] -vsseg5b.v v4, 0(a0) -# CHECK-INST: vsseg5b.v v4, (a0) +th.vsseg5b.v v4, 0(a0) +# CHECK-INST: th.vsseg5b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0x82] -vsseg5b.v v4, (a0), v0.t -# CHECK-INST: vsseg5b.v v4, (a0), v0.t +th.vsseg5b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg5b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0x80] -vsseg5h.v v4, (a0) -# CHECK-INST: vsseg5h.v v4, (a0) +th.vsseg5h.v v4, (a0) +# CHECK-INST: th.vsseg5h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x82] -vsseg5h.v v4, 0(a0) -# CHECK-INST: vsseg5h.v v4, (a0) +th.vsseg5h.v v4, 0(a0) +# CHECK-INST: th.vsseg5h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0x82] -vsseg5h.v v4, (a0), v0.t -# CHECK-INST: vsseg5h.v v4, (a0), v0.t +th.vsseg5h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg5h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0x80] -vsseg5w.v v4, (a0) -# CHECK-INST: vsseg5w.v v4, (a0) +th.vsseg5w.v v4, (a0) +# CHECK-INST: th.vsseg5w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x82] -vsseg5w.v v4, 0(a0) -# CHECK-INST: vsseg5w.v v4, (a0) +th.vsseg5w.v v4, 0(a0) +# CHECK-INST: th.vsseg5w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0x82] -vsseg5w.v v4, (a0), v0.t -# CHECK-INST: vsseg5w.v v4, (a0), v0.t +th.vsseg5w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg5w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0x80] -vsseg5e.v v4, (a0) -# CHECK-INST: vsseg5e.v v4, (a0) +th.vsseg5e.v v4, (a0) +# CHECK-INST: th.vsseg5e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x82] -vsseg5e.v v4, 0(a0) -# CHECK-INST: vsseg5e.v v4, (a0) +th.vsseg5e.v v4, 0(a0) +# CHECK-INST: th.vsseg5e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0x82] -vsseg5e.v v4, (a0), v0.t -# CHECK-INST: vsseg5e.v v4, (a0), v0.t +th.vsseg5e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg5e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0x80] -vlseg6b.v v4, (a0) -# CHECK-INST: vlseg6b.v v4, (a0) +th.vlseg6b.v v4, (a0) +# CHECK-INST: th.vlseg6b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xb2] -vlseg6b.v v4, 0(a0) -# CHECK-INST: vlseg6b.v v4, (a0) +th.vlseg6b.v v4, 0(a0) +# CHECK-INST: th.vlseg6b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xb2] -vlseg6b.v v4, (a0), v0.t -# CHECK-INST: vlseg6b.v v4, (a0), v0.t +th.vlseg6b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xb0] -vlseg6h.v v4, (a0) -# CHECK-INST: vlseg6h.v v4, (a0) +th.vlseg6h.v v4, (a0) +# CHECK-INST: th.vlseg6h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xb2] -vlseg6h.v v4, 0(a0) -# CHECK-INST: vlseg6h.v v4, (a0) +th.vlseg6h.v v4, 0(a0) +# CHECK-INST: th.vlseg6h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xb2] -vlseg6h.v v4, (a0), v0.t -# CHECK-INST: vlseg6h.v v4, (a0), v0.t +th.vlseg6h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xb0] -vlseg6w.v v4, (a0) -# CHECK-INST: vlseg6w.v v4, (a0) +th.vlseg6w.v v4, (a0) +# CHECK-INST: th.vlseg6w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xb2] -vlseg6w.v v4, 0(a0) -# CHECK-INST: vlseg6w.v v4, (a0) +th.vlseg6w.v v4, 0(a0) +# CHECK-INST: th.vlseg6w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xb2] -vlseg6w.v v4, (a0), v0.t -# CHECK-INST: vlseg6w.v v4, (a0), v0.t +th.vlseg6w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xb0] -vlseg6bu.v v4, (a0) -# CHECK-INST: vlseg6bu.v v4, (a0) +th.vlseg6bu.v v4, (a0) +# CHECK-INST: th.vlseg6bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xa2] -vlseg6bu.v v4, 0(a0) -# CHECK-INST: vlseg6bu.v v4, (a0) +th.vlseg6bu.v v4, 0(a0) +# CHECK-INST: th.vlseg6bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xa2] -vlseg6bu.v v4, (a0), v0.t -# CHECK-INST: vlseg6bu.v v4, (a0), v0.t +th.vlseg6bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xa0] -vlseg6hu.v v4, (a0) -# CHECK-INST: vlseg6hu.v v4, (a0) +th.vlseg6hu.v v4, (a0) +# CHECK-INST: th.vlseg6hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xa2] -vlseg6hu.v v4, 0(a0) -# CHECK-INST: vlseg6hu.v v4, (a0) +th.vlseg6hu.v v4, 0(a0) +# CHECK-INST: th.vlseg6hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xa2] -vlseg6hu.v v4, (a0), v0.t -# CHECK-INST: vlseg6hu.v v4, (a0), v0.t +th.vlseg6hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xa0] -vlseg6wu.v v4, (a0) -# CHECK-INST: vlseg6wu.v v4, (a0) +th.vlseg6wu.v v4, (a0) +# CHECK-INST: th.vlseg6wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xa2] -vlseg6wu.v v4, 0(a0) -# CHECK-INST: vlseg6wu.v v4, (a0) +th.vlseg6wu.v v4, 0(a0) +# CHECK-INST: th.vlseg6wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xa2] -vlseg6wu.v v4, (a0), v0.t -# CHECK-INST: vlseg6wu.v v4, (a0), v0.t +th.vlseg6wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xa0] -vlseg6e.v v4, (a0) -# CHECK-INST: vlseg6e.v v4, (a0) +th.vlseg6e.v v4, (a0) +# CHECK-INST: th.vlseg6e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xa2] -vlseg6e.v v4, 0(a0) -# CHECK-INST: vlseg6e.v v4, (a0) +th.vlseg6e.v v4, 0(a0) +# CHECK-INST: th.vlseg6e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xa2] -vlseg6e.v v4, (a0), v0.t -# CHECK-INST: vlseg6e.v v4, (a0), v0.t +th.vlseg6e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0xa0] -vsseg6b.v v4, (a0) -# CHECK-INST: vsseg6b.v v4, (a0) +th.vsseg6b.v v4, (a0) +# CHECK-INST: th.vsseg6b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0xa2] -vsseg6b.v v4, 0(a0) -# CHECK-INST: vsseg6b.v v4, (a0) +th.vsseg6b.v v4, 0(a0) +# CHECK-INST: th.vsseg6b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0xa2] -vsseg6b.v v4, (a0), v0.t -# CHECK-INST: vsseg6b.v v4, (a0), v0.t +th.vsseg6b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg6b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0xa0] -vsseg6h.v v4, (a0) -# CHECK-INST: vsseg6h.v v4, (a0) +th.vsseg6h.v v4, (a0) +# CHECK-INST: th.vsseg6h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0xa2] -vsseg6h.v v4, 0(a0) -# CHECK-INST: vsseg6h.v v4, (a0) +th.vsseg6h.v v4, 0(a0) +# CHECK-INST: th.vsseg6h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0xa2] -vsseg6h.v v4, (a0), v0.t -# CHECK-INST: vsseg6h.v v4, (a0), v0.t +th.vsseg6h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg6h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0xa0] -vsseg6w.v v4, (a0) -# CHECK-INST: vsseg6w.v v4, (a0) +th.vsseg6w.v v4, (a0) +# CHECK-INST: th.vsseg6w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0xa2] -vsseg6w.v v4, 0(a0) -# CHECK-INST: vsseg6w.v v4, (a0) +th.vsseg6w.v v4, 0(a0) +# CHECK-INST: th.vsseg6w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0xa2] -vsseg6w.v v4, (a0), v0.t -# CHECK-INST: vsseg6w.v v4, (a0), v0.t +th.vsseg6w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg6w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0xa0] -vsseg6e.v v4, (a0) -# CHECK-INST: vsseg6e.v v4, (a0) +th.vsseg6e.v v4, (a0) +# CHECK-INST: th.vsseg6e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0xa2] -vsseg6e.v v4, 0(a0) -# CHECK-INST: vsseg6e.v v4, (a0) +th.vsseg6e.v v4, 0(a0) +# CHECK-INST: th.vsseg6e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0xa2] -vsseg6e.v v4, (a0), v0.t -# CHECK-INST: vsseg6e.v v4, (a0), v0.t +th.vsseg6e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg6e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0xa0] -vlseg7b.v v4, (a0) -# CHECK-INST: vlseg7b.v v4, (a0) +th.vlseg7b.v v4, (a0) +# CHECK-INST: th.vlseg7b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xd2] -vlseg7b.v v4, 0(a0) -# CHECK-INST: vlseg7b.v v4, (a0) +th.vlseg7b.v v4, 0(a0) +# CHECK-INST: th.vlseg7b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xd2] -vlseg7b.v v4, (a0), v0.t -# CHECK-INST: vlseg7b.v v4, (a0), v0.t +th.vlseg7b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xd0] -vlseg7h.v v4, (a0) -# CHECK-INST: vlseg7h.v v4, (a0) +th.vlseg7h.v v4, (a0) +# CHECK-INST: th.vlseg7h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xd2] -vlseg7h.v v4, 0(a0) -# CHECK-INST: vlseg7h.v v4, (a0) +th.vlseg7h.v v4, 0(a0) +# CHECK-INST: th.vlseg7h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xd2] -vlseg7h.v v4, (a0), v0.t -# CHECK-INST: vlseg7h.v v4, (a0), v0.t +th.vlseg7h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xd0] -vlseg7w.v v4, (a0) -# CHECK-INST: vlseg7w.v v4, (a0) +th.vlseg7w.v v4, (a0) +# CHECK-INST: th.vlseg7w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xd2] -vlseg7w.v v4, 0(a0) -# CHECK-INST: vlseg7w.v v4, (a0) +th.vlseg7w.v v4, 0(a0) +# CHECK-INST: th.vlseg7w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xd2] -vlseg7w.v v4, (a0), v0.t -# CHECK-INST: vlseg7w.v v4, (a0), v0.t +th.vlseg7w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xd0] -vlseg7bu.v v4, (a0) -# CHECK-INST: vlseg7bu.v v4, (a0) +th.vlseg7bu.v v4, (a0) +# CHECK-INST: th.vlseg7bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xc2] -vlseg7bu.v v4, 0(a0) -# CHECK-INST: vlseg7bu.v v4, (a0) +th.vlseg7bu.v v4, 0(a0) +# CHECK-INST: th.vlseg7bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xc2] -vlseg7bu.v v4, (a0), v0.t -# CHECK-INST: vlseg7bu.v v4, (a0), v0.t +th.vlseg7bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xc0] -vlseg7hu.v v4, (a0) -# CHECK-INST: vlseg7hu.v v4, (a0) +th.vlseg7hu.v v4, (a0) +# CHECK-INST: th.vlseg7hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xc2] -vlseg7hu.v v4, 0(a0) -# CHECK-INST: vlseg7hu.v v4, (a0) +th.vlseg7hu.v v4, 0(a0) +# CHECK-INST: th.vlseg7hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xc2] -vlseg7hu.v v4, (a0), v0.t -# CHECK-INST: vlseg7hu.v v4, (a0), v0.t +th.vlseg7hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xc0] -vlseg7wu.v v4, (a0) -# CHECK-INST: vlseg7wu.v v4, (a0) +th.vlseg7wu.v v4, (a0) +# CHECK-INST: th.vlseg7wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xc2] -vlseg7wu.v v4, 0(a0) -# CHECK-INST: vlseg7wu.v v4, (a0) +th.vlseg7wu.v v4, 0(a0) +# CHECK-INST: th.vlseg7wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xc2] -vlseg7wu.v v4, (a0), v0.t -# CHECK-INST: vlseg7wu.v v4, (a0), v0.t +th.vlseg7wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xc0] -vlseg7e.v v4, (a0) -# CHECK-INST: vlseg7e.v v4, (a0) +th.vlseg7e.v v4, (a0) +# CHECK-INST: th.vlseg7e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xc2] -vlseg7e.v v4, 0(a0) -# CHECK-INST: vlseg7e.v v4, (a0) +th.vlseg7e.v v4, 0(a0) +# CHECK-INST: th.vlseg7e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xc2] -vlseg7e.v v4, (a0), v0.t -# CHECK-INST: vlseg7e.v v4, (a0), v0.t +th.vlseg7e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0xc0] -vsseg7b.v v4, (a0) -# CHECK-INST: vsseg7b.v v4, (a0) +th.vsseg7b.v v4, (a0) +# CHECK-INST: th.vsseg7b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0xc2] -vsseg7b.v v4, 0(a0) -# CHECK-INST: vsseg7b.v v4, (a0) +th.vsseg7b.v v4, 0(a0) +# CHECK-INST: th.vsseg7b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0xc2] -vsseg7b.v v4, (a0), v0.t -# CHECK-INST: vsseg7b.v v4, (a0), v0.t +th.vsseg7b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg7b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0xc0] -vsseg7h.v v4, (a0) -# CHECK-INST: vsseg7h.v v4, (a0) +th.vsseg7h.v v4, (a0) +# CHECK-INST: th.vsseg7h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0xc2] -vsseg7h.v v4, 0(a0) -# CHECK-INST: vsseg7h.v v4, (a0) +th.vsseg7h.v v4, 0(a0) +# CHECK-INST: th.vsseg7h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0xc2] -vsseg7h.v v4, (a0), v0.t -# CHECK-INST: vsseg7h.v v4, (a0), v0.t +th.vsseg7h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg7h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0xc0] -vsseg7w.v v4, (a0) -# CHECK-INST: vsseg7w.v v4, (a0) +th.vsseg7w.v v4, (a0) +# CHECK-INST: th.vsseg7w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0xc2] -vsseg7w.v v4, 0(a0) -# CHECK-INST: vsseg7w.v v4, (a0) +th.vsseg7w.v v4, 0(a0) +# CHECK-INST: th.vsseg7w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0xc2] -vsseg7w.v v4, (a0), v0.t -# CHECK-INST: vsseg7w.v v4, (a0), v0.t +th.vsseg7w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg7w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0xc0] -vsseg7e.v v4, (a0) -# CHECK-INST: vsseg7e.v v4, (a0) +th.vsseg7e.v v4, (a0) +# CHECK-INST: th.vsseg7e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0xc2] -vsseg7e.v v4, 0(a0) -# CHECK-INST: vsseg7e.v v4, (a0) +th.vsseg7e.v v4, 0(a0) +# CHECK-INST: th.vsseg7e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0xc2] -vsseg7e.v v4, (a0), v0.t -# CHECK-INST: vsseg7e.v v4, (a0), v0.t +th.vsseg7e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg7e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0xc0] -vlseg8b.v v4, (a0) -# CHECK-INST: vlseg8b.v v4, (a0) +th.vlseg8b.v v4, (a0) +# CHECK-INST: th.vlseg8b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xf2] -vlseg8b.v v4, 0(a0) -# CHECK-INST: vlseg8b.v v4, (a0) +th.vlseg8b.v v4, 0(a0) +# CHECK-INST: th.vlseg8b.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xf2] -vlseg8b.v v4, (a0), v0.t -# CHECK-INST: vlseg8b.v v4, (a0), v0.t +th.vlseg8b.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8b.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xf0] -vlseg8h.v v4, (a0) -# CHECK-INST: vlseg8h.v v4, (a0) +th.vlseg8h.v v4, (a0) +# CHECK-INST: th.vlseg8h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xf2] -vlseg8h.v v4, 0(a0) -# CHECK-INST: vlseg8h.v v4, (a0) +th.vlseg8h.v v4, 0(a0) +# CHECK-INST: th.vlseg8h.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xf2] -vlseg8h.v v4, (a0), v0.t -# CHECK-INST: vlseg8h.v v4, (a0), v0.t +th.vlseg8h.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8h.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xf0] -vlseg8w.v v4, (a0) -# CHECK-INST: vlseg8w.v v4, (a0) +th.vlseg8w.v v4, (a0) +# CHECK-INST: th.vlseg8w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xf2] -vlseg8w.v v4, 0(a0) -# CHECK-INST: vlseg8w.v v4, (a0) +th.vlseg8w.v v4, 0(a0) +# CHECK-INST: th.vlseg8w.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xf2] -vlseg8w.v v4, (a0), v0.t -# CHECK-INST: vlseg8w.v v4, (a0), v0.t +th.vlseg8w.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8w.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xf0] -vlseg8bu.v v4, (a0) -# CHECK-INST: vlseg8bu.v v4, (a0) +th.vlseg8bu.v v4, (a0) +# CHECK-INST: th.vlseg8bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xe2] -vlseg8bu.v v4, 0(a0) -# CHECK-INST: vlseg8bu.v v4, (a0) +th.vlseg8bu.v v4, 0(a0) +# CHECK-INST: th.vlseg8bu.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xe2] -vlseg8bu.v v4, (a0), v0.t -# CHECK-INST: vlseg8bu.v v4, (a0), v0.t +th.vlseg8bu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8bu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xe0] -vlseg8hu.v v4, (a0) -# CHECK-INST: vlseg8hu.v v4, (a0) +th.vlseg8hu.v v4, (a0) +# CHECK-INST: th.vlseg8hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xe2] -vlseg8hu.v v4, 0(a0) -# CHECK-INST: vlseg8hu.v v4, (a0) +th.vlseg8hu.v v4, 0(a0) +# CHECK-INST: th.vlseg8hu.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xe2] -vlseg8hu.v v4, (a0), v0.t -# CHECK-INST: vlseg8hu.v v4, (a0), v0.t +th.vlseg8hu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8hu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xe0] -vlseg8wu.v v4, (a0) -# CHECK-INST: vlseg8wu.v v4, (a0) +th.vlseg8wu.v v4, (a0) +# CHECK-INST: th.vlseg8wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xe2] -vlseg8wu.v v4, 0(a0) -# CHECK-INST: vlseg8wu.v v4, (a0) +th.vlseg8wu.v v4, 0(a0) +# CHECK-INST: th.vlseg8wu.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xe2] -vlseg8wu.v v4, (a0), v0.t -# CHECK-INST: vlseg8wu.v v4, (a0), v0.t +th.vlseg8wu.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8wu.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xe0] -vlseg8e.v v4, (a0) -# CHECK-INST: vlseg8e.v v4, (a0) +th.vlseg8e.v v4, (a0) +# CHECK-INST: th.vlseg8e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xe2] -vlseg8e.v v4, 0(a0) -# CHECK-INST: vlseg8e.v v4, (a0) +th.vlseg8e.v v4, 0(a0) +# CHECK-INST: th.vlseg8e.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xe2] -vlseg8e.v v4, (a0), v0.t -# CHECK-INST: vlseg8e.v v4, (a0), v0.t +th.vlseg8e.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8e.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0xe0] -vsseg8b.v v4, (a0) -# CHECK-INST: vsseg8b.v v4, (a0) +th.vsseg8b.v v4, (a0) +# CHECK-INST: th.vsseg8b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0xe2] -vsseg8b.v v4, 0(a0) -# CHECK-INST: vsseg8b.v v4, (a0) +th.vsseg8b.v v4, 0(a0) +# CHECK-INST: th.vsseg8b.v v4, (a0) # CHECK-ENCODING: [0x27,0x02,0x05,0xe2] -vsseg8b.v v4, (a0), v0.t -# CHECK-INST: vsseg8b.v v4, (a0), v0.t +th.vsseg8b.v v4, (a0), v0.t +# CHECK-INST: th.vsseg8b.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x02,0x05,0xe0] -vsseg8h.v v4, (a0) -# CHECK-INST: vsseg8h.v v4, (a0) +th.vsseg8h.v v4, (a0) +# CHECK-INST: th.vsseg8h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0xe2] -vsseg8h.v v4, 0(a0) -# CHECK-INST: vsseg8h.v v4, (a0) +th.vsseg8h.v v4, 0(a0) +# CHECK-INST: th.vsseg8h.v v4, (a0) # CHECK-ENCODING: [0x27,0x52,0x05,0xe2] -vsseg8h.v v4, (a0), v0.t -# CHECK-INST: vsseg8h.v v4, (a0), v0.t +th.vsseg8h.v v4, (a0), v0.t +# CHECK-INST: th.vsseg8h.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x52,0x05,0xe0] -vsseg8w.v v4, (a0) -# CHECK-INST: vsseg8w.v v4, (a0) +th.vsseg8w.v v4, (a0) +# CHECK-INST: th.vsseg8w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0xe2] -vsseg8w.v v4, 0(a0) -# CHECK-INST: vsseg8w.v v4, (a0) +th.vsseg8w.v v4, 0(a0) +# CHECK-INST: th.vsseg8w.v v4, (a0) # CHECK-ENCODING: [0x27,0x62,0x05,0xe2] -vsseg8w.v v4, (a0), v0.t -# CHECK-INST: vsseg8w.v v4, (a0), v0.t +th.vsseg8w.v v4, (a0), v0.t +# CHECK-INST: th.vsseg8w.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x62,0x05,0xe0] -vsseg8e.v v4, (a0) -# CHECK-INST: vsseg8e.v v4, (a0) +th.vsseg8e.v v4, (a0) +# CHECK-INST: th.vsseg8e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0xe2] -vsseg8e.v v4, 0(a0) -# CHECK-INST: vsseg8e.v v4, (a0) +th.vsseg8e.v v4, 0(a0) +# CHECK-INST: th.vsseg8e.v v4, (a0) # CHECK-ENCODING: [0x27,0x72,0x05,0xe2] -vsseg8e.v v4, (a0), v0.t -# CHECK-INST: vsseg8e.v v4, (a0), v0.t +th.vsseg8e.v v4, (a0), v0.t +# CHECK-INST: th.vsseg8e.v v4, (a0), v0.t # CHECK-ENCODING: [0x27,0x72,0x05,0xe0] -vlsseg2b.v v4, (a0), a1 -# CHECK-INST: vlsseg2b.v v4, (a0), a1 +th.vlsseg2b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x3a] -vlsseg2b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2b.v v4, (a0), a1 +th.vlsseg2b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x3a] -vlsseg2b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2b.v v4, (a0), a1, v0.t +th.vlsseg2b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x38] -vlsseg2h.v v4, (a0), a1 -# CHECK-INST: vlsseg2h.v v4, (a0), a1 +th.vlsseg2h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x3a] -vlsseg2h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2h.v v4, (a0), a1 +th.vlsseg2h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x3a] -vlsseg2h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2h.v v4, (a0), a1, v0.t +th.vlsseg2h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x38] -vlsseg2w.v v4, (a0), a1 -# CHECK-INST: vlsseg2w.v v4, (a0), a1 +th.vlsseg2w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x3a] -vlsseg2w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2w.v v4, (a0), a1 +th.vlsseg2w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x3a] -vlsseg2w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2w.v v4, (a0), a1, v0.t +th.vlsseg2w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x38] -vlsseg2bu.v v4, (a0), a1 -# CHECK-INST: vlsseg2bu.v v4, (a0), a1 +th.vlsseg2bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x2a] -vlsseg2bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2bu.v v4, (a0), a1 +th.vlsseg2bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x2a] -vlsseg2bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2bu.v v4, (a0), a1, v0.t +th.vlsseg2bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x28] -vlsseg2hu.v v4, (a0), a1 -# CHECK-INST: vlsseg2hu.v v4, (a0), a1 +th.vlsseg2hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x2a] -vlsseg2hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2hu.v v4, (a0), a1 +th.vlsseg2hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x2a] -vlsseg2hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2hu.v v4, (a0), a1, v0.t +th.vlsseg2hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x28] -vlsseg2wu.v v4, (a0), a1 -# CHECK-INST: vlsseg2wu.v v4, (a0), a1 +th.vlsseg2wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x2a] -vlsseg2wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2wu.v v4, (a0), a1 +th.vlsseg2wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x2a] -vlsseg2wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2wu.v v4, (a0), a1, v0.t +th.vlsseg2wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x28] -vlsseg2e.v v4, (a0), a1 -# CHECK-INST: vlsseg2e.v v4, (a0), a1 +th.vlsseg2e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg2e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x2a] -vlsseg2e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg2e.v v4, (a0), a1 +th.vlsseg2e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg2e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x2a] -vlsseg2e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg2e.v v4, (a0), a1, v0.t +th.vlsseg2e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0x28] -vssseg2b.v v4, (a0), a1 -# CHECK-INST: vssseg2b.v v4, (a0), a1 +th.vssseg2b.v v4, (a0), a1 +# CHECK-INST: th.vssseg2b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x2a] -vssseg2b.v v4, 0(a0), a1 -# CHECK-INST: vssseg2b.v v4, (a0), a1 +th.vssseg2b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg2b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x2a] -vssseg2b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg2b.v v4, (a0), a1, v0.t +th.vssseg2b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg2b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0x28] -vssseg2h.v v4, (a0), a1 -# CHECK-INST: vssseg2h.v v4, (a0), a1 +th.vssseg2h.v v4, (a0), a1 +# CHECK-INST: th.vssseg2h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x2a] -vssseg2h.v v4, 0(a0), a1 -# CHECK-INST: vssseg2h.v v4, (a0), a1 +th.vssseg2h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg2h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x2a] -vssseg2h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg2h.v v4, (a0), a1, v0.t +th.vssseg2h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg2h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0x28] -vssseg2w.v v4, (a0), a1 -# CHECK-INST: vssseg2w.v v4, (a0), a1 +th.vssseg2w.v v4, (a0), a1 +# CHECK-INST: th.vssseg2w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x2a] -vssseg2w.v v4, 0(a0), a1 -# CHECK-INST: vssseg2w.v v4, (a0), a1 +th.vssseg2w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg2w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x2a] -vssseg2w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg2w.v v4, (a0), a1, v0.t +th.vssseg2w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg2w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0x28] -vssseg2e.v v4, (a0), a1 -# CHECK-INST: vssseg2e.v v4, (a0), a1 +th.vssseg2e.v v4, (a0), a1 +# CHECK-INST: th.vssseg2e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x2a] -vssseg2e.v v4, 0(a0), a1 -# CHECK-INST: vssseg2e.v v4, (a0), a1 +th.vssseg2e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg2e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x2a] -vssseg2e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg2e.v v4, (a0), a1, v0.t +th.vssseg2e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg2e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0x28] -vlsseg3b.v v4, (a0), a1 -# CHECK-INST: vlsseg3b.v v4, (a0), a1 +th.vlsseg3b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x5a] -vlsseg3b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3b.v v4, (a0), a1 +th.vlsseg3b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x5a] -vlsseg3b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3b.v v4, (a0), a1, v0.t +th.vlsseg3b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x58] -vlsseg3h.v v4, (a0), a1 -# CHECK-INST: vlsseg3h.v v4, (a0), a1 +th.vlsseg3h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x5a] -vlsseg3h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3h.v v4, (a0), a1 +th.vlsseg3h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x5a] -vlsseg3h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3h.v v4, (a0), a1, v0.t +th.vlsseg3h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x58] -vlsseg3w.v v4, (a0), a1 -# CHECK-INST: vlsseg3w.v v4, (a0), a1 +th.vlsseg3w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x5a] -vlsseg3w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3w.v v4, (a0), a1 +th.vlsseg3w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x5a] -vlsseg3w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3w.v v4, (a0), a1, v0.t +th.vlsseg3w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x58] -vlsseg3bu.v v4, (a0), a1 -# CHECK-INST: vlsseg3bu.v v4, (a0), a1 +th.vlsseg3bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x4a] -vlsseg3bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3bu.v v4, (a0), a1 +th.vlsseg3bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x4a] -vlsseg3bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3bu.v v4, (a0), a1, v0.t +th.vlsseg3bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x48] -vlsseg3hu.v v4, (a0), a1 -# CHECK-INST: vlsseg3hu.v v4, (a0), a1 +th.vlsseg3hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x4a] -vlsseg3hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3hu.v v4, (a0), a1 +th.vlsseg3hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x4a] -vlsseg3hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3hu.v v4, (a0), a1, v0.t +th.vlsseg3hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x48] -vlsseg3wu.v v4, (a0), a1 -# CHECK-INST: vlsseg3wu.v v4, (a0), a1 +th.vlsseg3wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x4a] -vlsseg3wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3wu.v v4, (a0), a1 +th.vlsseg3wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x4a] -vlsseg3wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3wu.v v4, (a0), a1, v0.t +th.vlsseg3wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x48] -vlsseg3e.v v4, (a0), a1 -# CHECK-INST: vlsseg3e.v v4, (a0), a1 +th.vlsseg3e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg3e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x4a] -vlsseg3e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg3e.v v4, (a0), a1 +th.vlsseg3e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg3e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x4a] -vlsseg3e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg3e.v v4, (a0), a1, v0.t +th.vlsseg3e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0x48] -vssseg3b.v v4, (a0), a1 -# CHECK-INST: vssseg3b.v v4, (a0), a1 +th.vssseg3b.v v4, (a0), a1 +# CHECK-INST: th.vssseg3b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x4a] -vssseg3b.v v4, 0(a0), a1 -# CHECK-INST: vssseg3b.v v4, (a0), a1 +th.vssseg3b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg3b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x4a] -vssseg3b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg3b.v v4, (a0), a1, v0.t +th.vssseg3b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg3b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0x48] -vssseg3h.v v4, (a0), a1 -# CHECK-INST: vssseg3h.v v4, (a0), a1 +th.vssseg3h.v v4, (a0), a1 +# CHECK-INST: th.vssseg3h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x4a] -vssseg3h.v v4, 0(a0), a1 -# CHECK-INST: vssseg3h.v v4, (a0), a1 +th.vssseg3h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg3h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x4a] -vssseg3h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg3h.v v4, (a0), a1, v0.t +th.vssseg3h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg3h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0x48] -vssseg3w.v v4, (a0), a1 -# CHECK-INST: vssseg3w.v v4, (a0), a1 +th.vssseg3w.v v4, (a0), a1 +# CHECK-INST: th.vssseg3w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x4a] -vssseg3w.v v4, 0(a0), a1 -# CHECK-INST: vssseg3w.v v4, (a0), a1 +th.vssseg3w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg3w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x4a] -vssseg3w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg3w.v v4, (a0), a1, v0.t +th.vssseg3w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg3w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0x48] -vssseg3e.v v4, (a0), a1 -# CHECK-INST: vssseg3e.v v4, (a0), a1 +th.vssseg3e.v v4, (a0), a1 +# CHECK-INST: th.vssseg3e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x4a] -vssseg3e.v v4, 0(a0), a1 -# CHECK-INST: vssseg3e.v v4, (a0), a1 +th.vssseg3e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg3e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x4a] -vssseg3e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg3e.v v4, (a0), a1, v0.t +th.vssseg3e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg3e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0x48] -vlsseg4b.v v4, (a0), a1 -# CHECK-INST: vlsseg4b.v v4, (a0), a1 +th.vlsseg4b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x7a] -vlsseg4b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4b.v v4, (a0), a1 +th.vlsseg4b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x7a] -vlsseg4b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4b.v v4, (a0), a1, v0.t +th.vlsseg4b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x78] -vlsseg4h.v v4, (a0), a1 -# CHECK-INST: vlsseg4h.v v4, (a0), a1 +th.vlsseg4h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x7a] -vlsseg4h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4h.v v4, (a0), a1 +th.vlsseg4h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x7a] -vlsseg4h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4h.v v4, (a0), a1, v0.t +th.vlsseg4h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x78] -vlsseg4w.v v4, (a0), a1 -# CHECK-INST: vlsseg4w.v v4, (a0), a1 +th.vlsseg4w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x7a] -vlsseg4w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4w.v v4, (a0), a1 +th.vlsseg4w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x7a] -vlsseg4w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4w.v v4, (a0), a1, v0.t +th.vlsseg4w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x78] -vlsseg4bu.v v4, (a0), a1 -# CHECK-INST: vlsseg4bu.v v4, (a0), a1 +th.vlsseg4bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x6a] -vlsseg4bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4bu.v v4, (a0), a1 +th.vlsseg4bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x6a] -vlsseg4bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4bu.v v4, (a0), a1, v0.t +th.vlsseg4bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x68] -vlsseg4hu.v v4, (a0), a1 -# CHECK-INST: vlsseg4hu.v v4, (a0), a1 +th.vlsseg4hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x6a] -vlsseg4hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4hu.v v4, (a0), a1 +th.vlsseg4hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x6a] -vlsseg4hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4hu.v v4, (a0), a1, v0.t +th.vlsseg4hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x68] -vlsseg4wu.v v4, (a0), a1 -# CHECK-INST: vlsseg4wu.v v4, (a0), a1 +th.vlsseg4wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x6a] -vlsseg4wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4wu.v v4, (a0), a1 +th.vlsseg4wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x6a] -vlsseg4wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4wu.v v4, (a0), a1, v0.t +th.vlsseg4wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x68] -vlsseg4e.v v4, (a0), a1 -# CHECK-INST: vlsseg4e.v v4, (a0), a1 +th.vlsseg4e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg4e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x6a] -vlsseg4e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg4e.v v4, (a0), a1 +th.vlsseg4e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg4e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x6a] -vlsseg4e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg4e.v v4, (a0), a1, v0.t +th.vlsseg4e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0x68] -vssseg4b.v v4, (a0), a1 -# CHECK-INST: vssseg4b.v v4, (a0), a1 +th.vssseg4b.v v4, (a0), a1 +# CHECK-INST: th.vssseg4b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x6a] -vssseg4b.v v4, 0(a0), a1 -# CHECK-INST: vssseg4b.v v4, (a0), a1 +th.vssseg4b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg4b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x6a] -vssseg4b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg4b.v v4, (a0), a1, v0.t +th.vssseg4b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg4b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0x68] -vssseg4h.v v4, (a0), a1 -# CHECK-INST: vssseg4h.v v4, (a0), a1 +th.vssseg4h.v v4, (a0), a1 +# CHECK-INST: th.vssseg4h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x6a] -vssseg4h.v v4, 0(a0), a1 -# CHECK-INST: vssseg4h.v v4, (a0), a1 +th.vssseg4h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg4h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x6a] -vssseg4h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg4h.v v4, (a0), a1, v0.t +th.vssseg4h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg4h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0x68] -vssseg4w.v v4, (a0), a1 -# CHECK-INST: vssseg4w.v v4, (a0), a1 +th.vssseg4w.v v4, (a0), a1 +# CHECK-INST: th.vssseg4w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x6a] -vssseg4w.v v4, 0(a0), a1 -# CHECK-INST: vssseg4w.v v4, (a0), a1 +th.vssseg4w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg4w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x6a] -vssseg4w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg4w.v v4, (a0), a1, v0.t +th.vssseg4w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg4w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0x68] -vssseg4e.v v4, (a0), a1 -# CHECK-INST: vssseg4e.v v4, (a0), a1 +th.vssseg4e.v v4, (a0), a1 +# CHECK-INST: th.vssseg4e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x6a] -vssseg4e.v v4, 0(a0), a1 -# CHECK-INST: vssseg4e.v v4, (a0), a1 +th.vssseg4e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg4e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x6a] -vssseg4e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg4e.v v4, (a0), a1, v0.t +th.vssseg4e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg4e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0x68] -vlsseg5b.v v4, (a0), a1 -# CHECK-INST: vlsseg5b.v v4, (a0), a1 +th.vlsseg5b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x9a] -vlsseg5b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5b.v v4, (a0), a1 +th.vlsseg5b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x9a] -vlsseg5b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5b.v v4, (a0), a1, v0.t +th.vlsseg5b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x98] -vlsseg5h.v v4, (a0), a1 -# CHECK-INST: vlsseg5h.v v4, (a0), a1 +th.vlsseg5h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x9a] -vlsseg5h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5h.v v4, (a0), a1 +th.vlsseg5h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x9a] -vlsseg5h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5h.v v4, (a0), a1, v0.t +th.vlsseg5h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x98] -vlsseg5w.v v4, (a0), a1 -# CHECK-INST: vlsseg5w.v v4, (a0), a1 +th.vlsseg5w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x9a] -vlsseg5w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5w.v v4, (a0), a1 +th.vlsseg5w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x9a] -vlsseg5w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5w.v v4, (a0), a1, v0.t +th.vlsseg5w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x98] -vlsseg5bu.v v4, (a0), a1 -# CHECK-INST: vlsseg5bu.v v4, (a0), a1 +th.vlsseg5bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x8a] -vlsseg5bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5bu.v v4, (a0), a1 +th.vlsseg5bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0x8a] -vlsseg5bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5bu.v v4, (a0), a1, v0.t +th.vlsseg5bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0x88] -vlsseg5hu.v v4, (a0), a1 -# CHECK-INST: vlsseg5hu.v v4, (a0), a1 +th.vlsseg5hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x8a] -vlsseg5hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5hu.v v4, (a0), a1 +th.vlsseg5hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0x8a] -vlsseg5hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5hu.v v4, (a0), a1, v0.t +th.vlsseg5hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0x88] -vlsseg5wu.v v4, (a0), a1 -# CHECK-INST: vlsseg5wu.v v4, (a0), a1 +th.vlsseg5wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x8a] -vlsseg5wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5wu.v v4, (a0), a1 +th.vlsseg5wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0x8a] -vlsseg5wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5wu.v v4, (a0), a1, v0.t +th.vlsseg5wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0x88] -vlsseg5e.v v4, (a0), a1 -# CHECK-INST: vlsseg5e.v v4, (a0), a1 +th.vlsseg5e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg5e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x8a] -vlsseg5e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg5e.v v4, (a0), a1 +th.vlsseg5e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg5e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0x8a] -vlsseg5e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg5e.v v4, (a0), a1, v0.t +th.vlsseg5e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0x88] -vssseg5b.v v4, (a0), a1 -# CHECK-INST: vssseg5b.v v4, (a0), a1 +th.vssseg5b.v v4, (a0), a1 +# CHECK-INST: th.vssseg5b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x8a] -vssseg5b.v v4, 0(a0), a1 -# CHECK-INST: vssseg5b.v v4, (a0), a1 +th.vssseg5b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg5b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0x8a] -vssseg5b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg5b.v v4, (a0), a1, v0.t +th.vssseg5b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg5b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0x88] -vssseg5h.v v4, (a0), a1 -# CHECK-INST: vssseg5h.v v4, (a0), a1 +th.vssseg5h.v v4, (a0), a1 +# CHECK-INST: th.vssseg5h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x8a] -vssseg5h.v v4, 0(a0), a1 -# CHECK-INST: vssseg5h.v v4, (a0), a1 +th.vssseg5h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg5h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0x8a] -vssseg5h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg5h.v v4, (a0), a1, v0.t +th.vssseg5h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg5h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0x88] -vssseg5w.v v4, (a0), a1 -# CHECK-INST: vssseg5w.v v4, (a0), a1 +th.vssseg5w.v v4, (a0), a1 +# CHECK-INST: th.vssseg5w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x8a] -vssseg5w.v v4, 0(a0), a1 -# CHECK-INST: vssseg5w.v v4, (a0), a1 +th.vssseg5w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg5w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0x8a] -vssseg5w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg5w.v v4, (a0), a1, v0.t +th.vssseg5w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg5w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0x88] -vssseg5e.v v4, (a0), a1 -# CHECK-INST: vssseg5e.v v4, (a0), a1 +th.vssseg5e.v v4, (a0), a1 +# CHECK-INST: th.vssseg5e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x8a] -vssseg5e.v v4, 0(a0), a1 -# CHECK-INST: vssseg5e.v v4, (a0), a1 +th.vssseg5e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg5e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0x8a] -vssseg5e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg5e.v v4, (a0), a1, v0.t +th.vssseg5e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg5e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0x88] -vlsseg6b.v v4, (a0), a1 -# CHECK-INST: vlsseg6b.v v4, (a0), a1 +th.vlsseg6b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xba] -vlsseg6b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6b.v v4, (a0), a1 +th.vlsseg6b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xba] -vlsseg6b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6b.v v4, (a0), a1, v0.t +th.vlsseg6b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0xb8] -vlsseg6h.v v4, (a0), a1 -# CHECK-INST: vlsseg6h.v v4, (a0), a1 +th.vlsseg6h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xba] -vlsseg6h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6h.v v4, (a0), a1 +th.vlsseg6h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xba] -vlsseg6h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6h.v v4, (a0), a1, v0.t +th.vlsseg6h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0xb8] -vlsseg6w.v v4, (a0), a1 -# CHECK-INST: vlsseg6w.v v4, (a0), a1 +th.vlsseg6w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xba] -vlsseg6w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6w.v v4, (a0), a1 +th.vlsseg6w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xba] -vlsseg6w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6w.v v4, (a0), a1, v0.t +th.vlsseg6w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0xb8] -vlsseg6bu.v v4, (a0), a1 -# CHECK-INST: vlsseg6bu.v v4, (a0), a1 +th.vlsseg6bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xaa] -vlsseg6bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6bu.v v4, (a0), a1 +th.vlsseg6bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xaa] -vlsseg6bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6bu.v v4, (a0), a1, v0.t +th.vlsseg6bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0xa8] -vlsseg6hu.v v4, (a0), a1 -# CHECK-INST: vlsseg6hu.v v4, (a0), a1 +th.vlsseg6hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xaa] -vlsseg6hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6hu.v v4, (a0), a1 +th.vlsseg6hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xaa] -vlsseg6hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6hu.v v4, (a0), a1, v0.t +th.vlsseg6hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0xa8] -vlsseg6wu.v v4, (a0), a1 -# CHECK-INST: vlsseg6wu.v v4, (a0), a1 +th.vlsseg6wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xaa] -vlsseg6wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6wu.v v4, (a0), a1 +th.vlsseg6wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xaa] -vlsseg6wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6wu.v v4, (a0), a1, v0.t +th.vlsseg6wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0xa8] -vlsseg6e.v v4, (a0), a1 -# CHECK-INST: vlsseg6e.v v4, (a0), a1 +th.vlsseg6e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg6e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0xaa] -vlsseg6e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg6e.v v4, (a0), a1 +th.vlsseg6e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg6e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0xaa] -vlsseg6e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg6e.v v4, (a0), a1, v0.t +th.vlsseg6e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0xa8] -vssseg6b.v v4, (a0), a1 -# CHECK-INST: vssseg6b.v v4, (a0), a1 +th.vssseg6b.v v4, (a0), a1 +# CHECK-INST: th.vssseg6b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0xaa] -vssseg6b.v v4, 0(a0), a1 -# CHECK-INST: vssseg6b.v v4, (a0), a1 +th.vssseg6b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg6b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0xaa] -vssseg6b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg6b.v v4, (a0), a1, v0.t +th.vssseg6b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg6b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0xa8] -vssseg6h.v v4, (a0), a1 -# CHECK-INST: vssseg6h.v v4, (a0), a1 +th.vssseg6h.v v4, (a0), a1 +# CHECK-INST: th.vssseg6h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0xaa] -vssseg6h.v v4, 0(a0), a1 -# CHECK-INST: vssseg6h.v v4, (a0), a1 +th.vssseg6h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg6h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0xaa] -vssseg6h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg6h.v v4, (a0), a1, v0.t +th.vssseg6h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg6h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0xa8] -vssseg6w.v v4, (a0), a1 -# CHECK-INST: vssseg6w.v v4, (a0), a1 +th.vssseg6w.v v4, (a0), a1 +# CHECK-INST: th.vssseg6w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0xaa] -vssseg6w.v v4, 0(a0), a1 -# CHECK-INST: vssseg6w.v v4, (a0), a1 +th.vssseg6w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg6w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0xaa] -vssseg6w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg6w.v v4, (a0), a1, v0.t +th.vssseg6w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg6w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0xa8] -vssseg6e.v v4, (a0), a1 -# CHECK-INST: vssseg6e.v v4, (a0), a1 +th.vssseg6e.v v4, (a0), a1 +# CHECK-INST: th.vssseg6e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0xaa] -vssseg6e.v v4, 0(a0), a1 -# CHECK-INST: vssseg6e.v v4, (a0), a1 +th.vssseg6e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg6e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0xaa] -vssseg6e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg6e.v v4, (a0), a1, v0.t +th.vssseg6e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg6e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0xa8] -vlsseg7b.v v4, (a0), a1 -# CHECK-INST: vlsseg7b.v v4, (a0), a1 +th.vlsseg7b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xda] -vlsseg7b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7b.v v4, (a0), a1 +th.vlsseg7b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xda] -vlsseg7b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7b.v v4, (a0), a1, v0.t +th.vlsseg7b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0xd8] -vlsseg7h.v v4, (a0), a1 -# CHECK-INST: vlsseg7h.v v4, (a0), a1 +th.vlsseg7h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xda] -vlsseg7h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7h.v v4, (a0), a1 +th.vlsseg7h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xda] -vlsseg7h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7h.v v4, (a0), a1, v0.t +th.vlsseg7h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0xd8] -vlsseg7w.v v4, (a0), a1 -# CHECK-INST: vlsseg7w.v v4, (a0), a1 +th.vlsseg7w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xda] -vlsseg7w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7w.v v4, (a0), a1 +th.vlsseg7w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xda] -vlsseg7w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7w.v v4, (a0), a1, v0.t +th.vlsseg7w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0xd8] -vlsseg7bu.v v4, (a0), a1 -# CHECK-INST: vlsseg7bu.v v4, (a0), a1 +th.vlsseg7bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xca] -vlsseg7bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7bu.v v4, (a0), a1 +th.vlsseg7bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xca] -vlsseg7bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7bu.v v4, (a0), a1, v0.t +th.vlsseg7bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0xc8] -vlsseg7hu.v v4, (a0), a1 -# CHECK-INST: vlsseg7hu.v v4, (a0), a1 +th.vlsseg7hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xca] -vlsseg7hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7hu.v v4, (a0), a1 +th.vlsseg7hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xca] -vlsseg7hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7hu.v v4, (a0), a1, v0.t +th.vlsseg7hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0xc8] -vlsseg7wu.v v4, (a0), a1 -# CHECK-INST: vlsseg7wu.v v4, (a0), a1 +th.vlsseg7wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xca] -vlsseg7wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7wu.v v4, (a0), a1 +th.vlsseg7wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xca] -vlsseg7wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7wu.v v4, (a0), a1, v0.t +th.vlsseg7wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0xc8] -vlsseg7e.v v4, (a0), a1 -# CHECK-INST: vlsseg7e.v v4, (a0), a1 +th.vlsseg7e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg7e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0xca] -vlsseg7e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg7e.v v4, (a0), a1 +th.vlsseg7e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg7e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0xca] -vlsseg7e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg7e.v v4, (a0), a1, v0.t +th.vlsseg7e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0xc8] -vssseg7b.v v4, (a0), a1 -# CHECK-INST: vssseg7b.v v4, (a0), a1 +th.vssseg7b.v v4, (a0), a1 +# CHECK-INST: th.vssseg7b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0xca] -vssseg7b.v v4, 0(a0), a1 -# CHECK-INST: vssseg7b.v v4, (a0), a1 +th.vssseg7b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg7b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0xca] -vssseg7b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg7b.v v4, (a0), a1, v0.t +th.vssseg7b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg7b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0xc8] -vssseg7h.v v4, (a0), a1 -# CHECK-INST: vssseg7h.v v4, (a0), a1 +th.vssseg7h.v v4, (a0), a1 +# CHECK-INST: th.vssseg7h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0xca] -vssseg7h.v v4, 0(a0), a1 -# CHECK-INST: vssseg7h.v v4, (a0), a1 +th.vssseg7h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg7h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0xca] -vssseg7h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg7h.v v4, (a0), a1, v0.t +th.vssseg7h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg7h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0xc8] -vssseg7w.v v4, (a0), a1 -# CHECK-INST: vssseg7w.v v4, (a0), a1 +th.vssseg7w.v v4, (a0), a1 +# CHECK-INST: th.vssseg7w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0xca] -vssseg7w.v v4, 0(a0), a1 -# CHECK-INST: vssseg7w.v v4, (a0), a1 +th.vssseg7w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg7w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0xca] -vssseg7w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg7w.v v4, (a0), a1, v0.t +th.vssseg7w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg7w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0xc8] -vssseg7e.v v4, (a0), a1 -# CHECK-INST: vssseg7e.v v4, (a0), a1 +th.vssseg7e.v v4, (a0), a1 +# CHECK-INST: th.vssseg7e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0xca] -vssseg7e.v v4, 0(a0), a1 -# CHECK-INST: vssseg7e.v v4, (a0), a1 +th.vssseg7e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg7e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0xca] -vssseg7e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg7e.v v4, (a0), a1, v0.t +th.vssseg7e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg7e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0xc8] -vlsseg8b.v v4, (a0), a1 -# CHECK-INST: vlsseg8b.v v4, (a0), a1 +th.vlsseg8b.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xfa] -vlsseg8b.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8b.v v4, (a0), a1 +th.vlsseg8b.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8b.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xfa] -vlsseg8b.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8b.v v4, (a0), a1, v0.t +th.vlsseg8b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0xf8] -vlsseg8h.v v4, (a0), a1 -# CHECK-INST: vlsseg8h.v v4, (a0), a1 +th.vlsseg8h.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xfa] -vlsseg8h.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8h.v v4, (a0), a1 +th.vlsseg8h.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8h.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xfa] -vlsseg8h.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8h.v v4, (a0), a1, v0.t +th.vlsseg8h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0xf8] -vlsseg8w.v v4, (a0), a1 -# CHECK-INST: vlsseg8w.v v4, (a0), a1 +th.vlsseg8w.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xfa] -vlsseg8w.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8w.v v4, (a0), a1 +th.vlsseg8w.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8w.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xfa] -vlsseg8w.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8w.v v4, (a0), a1, v0.t +th.vlsseg8w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0xf8] -vlsseg8bu.v v4, (a0), a1 -# CHECK-INST: vlsseg8bu.v v4, (a0), a1 +th.vlsseg8bu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xea] -vlsseg8bu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8bu.v v4, (a0), a1 +th.vlsseg8bu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8bu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x02,0xb5,0xea] -vlsseg8bu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8bu.v v4, (a0), a1, v0.t +th.vlsseg8bu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8bu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x02,0xb5,0xe8] -vlsseg8hu.v v4, (a0), a1 -# CHECK-INST: vlsseg8hu.v v4, (a0), a1 +th.vlsseg8hu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xea] -vlsseg8hu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8hu.v v4, (a0), a1 +th.vlsseg8hu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8hu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x52,0xb5,0xea] -vlsseg8hu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8hu.v v4, (a0), a1, v0.t +th.vlsseg8hu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8hu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x52,0xb5,0xe8] -vlsseg8wu.v v4, (a0), a1 -# CHECK-INST: vlsseg8wu.v v4, (a0), a1 +th.vlsseg8wu.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xea] -vlsseg8wu.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8wu.v v4, (a0), a1 +th.vlsseg8wu.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8wu.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x62,0xb5,0xea] -vlsseg8wu.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8wu.v v4, (a0), a1, v0.t +th.vlsseg8wu.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8wu.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x62,0xb5,0xe8] -vlsseg8e.v v4, (a0), a1 -# CHECK-INST: vlsseg8e.v v4, (a0), a1 +th.vlsseg8e.v v4, (a0), a1 +# CHECK-INST: th.vlsseg8e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0xea] -vlsseg8e.v v4, 0(a0), a1 -# CHECK-INST: vlsseg8e.v v4, (a0), a1 +th.vlsseg8e.v v4, 0(a0), a1 +# CHECK-INST: th.vlsseg8e.v v4, (a0), a1 # CHECK-ENCODING: [0x07,0x72,0xb5,0xea] -vlsseg8e.v v4, (a0), a1, v0.t -# CHECK-INST: vlsseg8e.v v4, (a0), a1, v0.t +th.vlsseg8e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x72,0xb5,0xe8] -vssseg8b.v v4, (a0), a1 -# CHECK-INST: vssseg8b.v v4, (a0), a1 +th.vssseg8b.v v4, (a0), a1 +# CHECK-INST: th.vssseg8b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0xea] -vssseg8b.v v4, 0(a0), a1 -# CHECK-INST: vssseg8b.v v4, (a0), a1 +th.vssseg8b.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg8b.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x02,0xb5,0xea] -vssseg8b.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg8b.v v4, (a0), a1, v0.t +th.vssseg8b.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg8b.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x02,0xb5,0xe8] -vssseg8h.v v4, (a0), a1 -# CHECK-INST: vssseg8h.v v4, (a0), a1 +th.vssseg8h.v v4, (a0), a1 +# CHECK-INST: th.vssseg8h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0xea] -vssseg8h.v v4, 0(a0), a1 -# CHECK-INST: vssseg8h.v v4, (a0), a1 +th.vssseg8h.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg8h.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x52,0xb5,0xea] -vssseg8h.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg8h.v v4, (a0), a1, v0.t +th.vssseg8h.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg8h.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x52,0xb5,0xe8] -vssseg8w.v v4, (a0), a1 -# CHECK-INST: vssseg8w.v v4, (a0), a1 +th.vssseg8w.v v4, (a0), a1 +# CHECK-INST: th.vssseg8w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0xea] -vssseg8w.v v4, 0(a0), a1 -# CHECK-INST: vssseg8w.v v4, (a0), a1 +th.vssseg8w.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg8w.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x62,0xb5,0xea] -vssseg8w.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg8w.v v4, (a0), a1, v0.t +th.vssseg8w.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg8w.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x62,0xb5,0xe8] -vssseg8e.v v4, (a0), a1 -# CHECK-INST: vssseg8e.v v4, (a0), a1 +th.vssseg8e.v v4, (a0), a1 +# CHECK-INST: th.vssseg8e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0xea] -vssseg8e.v v4, 0(a0), a1 -# CHECK-INST: vssseg8e.v v4, (a0), a1 +th.vssseg8e.v v4, 0(a0), a1 +# CHECK-INST: th.vssseg8e.v v4, (a0), a1 # CHECK-ENCODING: [0x27,0x72,0xb5,0xea] -vssseg8e.v v4, (a0), a1, v0.t -# CHECK-INST: vssseg8e.v v4, (a0), a1, v0.t +th.vssseg8e.v v4, (a0), a1, v0.t +# CHECK-INST: th.vssseg8e.v v4, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x72,0xb5,0xe8] -vlxseg2b.v v4, (a0), v12 -# CHECK-INST: vlxseg2b.v v4, (a0), v12 +th.vlxseg2b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x3e] -vlxseg2b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2b.v v4, (a0), v12 +th.vlxseg2b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x3e] -vlxseg2b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2b.v v4, (a0), v12, v0.t +th.vlxseg2b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x3c] -vlxseg2h.v v4, (a0), v12 -# CHECK-INST: vlxseg2h.v v4, (a0), v12 +th.vlxseg2h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x3e] -vlxseg2h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2h.v v4, (a0), v12 +th.vlxseg2h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x3e] -vlxseg2h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2h.v v4, (a0), v12, v0.t +th.vlxseg2h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x3c] -vlxseg2w.v v4, (a0), v12 -# CHECK-INST: vlxseg2w.v v4, (a0), v12 +th.vlxseg2w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x3e] -vlxseg2w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2w.v v4, (a0), v12 +th.vlxseg2w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x3e] -vlxseg2w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2w.v v4, (a0), v12, v0.t +th.vlxseg2w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x3c] -vlxseg2bu.v v4, (a0), v12 -# CHECK-INST: vlxseg2bu.v v4, (a0), v12 +th.vlxseg2bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x2e] -vlxseg2bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2bu.v v4, (a0), v12 +th.vlxseg2bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x2e] -vlxseg2bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2bu.v v4, (a0), v12, v0.t +th.vlxseg2bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x2c] -vlxseg2hu.v v4, (a0), v12 -# CHECK-INST: vlxseg2hu.v v4, (a0), v12 +th.vlxseg2hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x2e] -vlxseg2hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2hu.v v4, (a0), v12 +th.vlxseg2hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x2e] -vlxseg2hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2hu.v v4, (a0), v12, v0.t +th.vlxseg2hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x2c] -vlxseg2wu.v v4, (a0), v12 -# CHECK-INST: vlxseg2wu.v v4, (a0), v12 +th.vlxseg2wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x2e] -vlxseg2wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2wu.v v4, (a0), v12 +th.vlxseg2wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x2e] -vlxseg2wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2wu.v v4, (a0), v12, v0.t +th.vlxseg2wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x2c] -vlxseg2e.v v4, (a0), v12 -# CHECK-INST: vlxseg2e.v v4, (a0), v12 +th.vlxseg2e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg2e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x2e] -vlxseg2e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg2e.v v4, (a0), v12 +th.vlxseg2e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg2e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x2e] -vlxseg2e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg2e.v v4, (a0), v12, v0.t +th.vlxseg2e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg2e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0x2c] -vsxseg2b.v v4, (a0), v12 -# CHECK-INST: vsxseg2b.v v4, (a0), v12 +th.vsxseg2b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg2b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x2e] -vsxseg2b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg2b.v v4, (a0), v12 +th.vsxseg2b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg2b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x2e] -vsxseg2b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg2b.v v4, (a0), v12, v0.t +th.vsxseg2b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg2b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0x2c] -vsxseg2h.v v4, (a0), v12 -# CHECK-INST: vsxseg2h.v v4, (a0), v12 +th.vsxseg2h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg2h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x2e] -vsxseg2h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg2h.v v4, (a0), v12 +th.vsxseg2h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg2h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x2e] -vsxseg2h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg2h.v v4, (a0), v12, v0.t +th.vsxseg2h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg2h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0x2c] -vsxseg2w.v v4, (a0), v12 -# CHECK-INST: vsxseg2w.v v4, (a0), v12 +th.vsxseg2w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg2w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x2e] -vsxseg2w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg2w.v v4, (a0), v12 +th.vsxseg2w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg2w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x2e] -vsxseg2w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg2w.v v4, (a0), v12, v0.t +th.vsxseg2w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg2w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0x2c] -vsxseg2e.v v4, (a0), v12 -# CHECK-INST: vsxseg2e.v v4, (a0), v12 +th.vsxseg2e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg2e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x2e] -vsxseg2e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg2e.v v4, (a0), v12 +th.vsxseg2e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg2e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x2e] -vsxseg2e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg2e.v v4, (a0), v12, v0.t +th.vsxseg2e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg2e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0x2c] -vlxseg3b.v v4, (a0), v12 -# CHECK-INST: vlxseg3b.v v4, (a0), v12 +th.vlxseg3b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x5e] -vlxseg3b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3b.v v4, (a0), v12 +th.vlxseg3b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x5e] -vlxseg3b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3b.v v4, (a0), v12, v0.t +th.vlxseg3b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x5c] -vlxseg3h.v v4, (a0), v12 -# CHECK-INST: vlxseg3h.v v4, (a0), v12 +th.vlxseg3h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x5e] -vlxseg3h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3h.v v4, (a0), v12 +th.vlxseg3h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x5e] -vlxseg3h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3h.v v4, (a0), v12, v0.t +th.vlxseg3h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x5c] -vlxseg3w.v v4, (a0), v12 -# CHECK-INST: vlxseg3w.v v4, (a0), v12 +th.vlxseg3w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x5e] -vlxseg3w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3w.v v4, (a0), v12 +th.vlxseg3w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x5e] -vlxseg3w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3w.v v4, (a0), v12, v0.t +th.vlxseg3w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x5c] -vlxseg3bu.v v4, (a0), v12 -# CHECK-INST: vlxseg3bu.v v4, (a0), v12 +th.vlxseg3bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x4e] -vlxseg3bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3bu.v v4, (a0), v12 +th.vlxseg3bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x4e] -vlxseg3bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3bu.v v4, (a0), v12, v0.t +th.vlxseg3bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x4c] -vlxseg3hu.v v4, (a0), v12 -# CHECK-INST: vlxseg3hu.v v4, (a0), v12 +th.vlxseg3hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x4e] -vlxseg3hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3hu.v v4, (a0), v12 +th.vlxseg3hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x4e] -vlxseg3hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3hu.v v4, (a0), v12, v0.t +th.vlxseg3hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x4c] -vlxseg3wu.v v4, (a0), v12 -# CHECK-INST: vlxseg3wu.v v4, (a0), v12 +th.vlxseg3wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x4e] -vlxseg3wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3wu.v v4, (a0), v12 +th.vlxseg3wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x4e] -vlxseg3wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3wu.v v4, (a0), v12, v0.t +th.vlxseg3wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x4c] -vlxseg3e.v v4, (a0), v12 -# CHECK-INST: vlxseg3e.v v4, (a0), v12 +th.vlxseg3e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg3e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x4e] -vlxseg3e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg3e.v v4, (a0), v12 +th.vlxseg3e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg3e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x4e] -vlxseg3e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg3e.v v4, (a0), v12, v0.t +th.vlxseg3e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg3e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0x4c] -vsxseg3b.v v4, (a0), v12 -# CHECK-INST: vsxseg3b.v v4, (a0), v12 +th.vsxseg3b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg3b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x4e] -vsxseg3b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg3b.v v4, (a0), v12 +th.vsxseg3b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg3b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x4e] -vsxseg3b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg3b.v v4, (a0), v12, v0.t +th.vsxseg3b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg3b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0x4c] -vsxseg3h.v v4, (a0), v12 -# CHECK-INST: vsxseg3h.v v4, (a0), v12 +th.vsxseg3h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg3h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x4e] -vsxseg3h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg3h.v v4, (a0), v12 +th.vsxseg3h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg3h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x4e] -vsxseg3h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg3h.v v4, (a0), v12, v0.t +th.vsxseg3h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg3h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0x4c] -vsxseg3w.v v4, (a0), v12 -# CHECK-INST: vsxseg3w.v v4, (a0), v12 +th.vsxseg3w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg3w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x4e] -vsxseg3w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg3w.v v4, (a0), v12 +th.vsxseg3w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg3w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x4e] -vsxseg3w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg3w.v v4, (a0), v12, v0.t +th.vsxseg3w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg3w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0x4c] -vsxseg3e.v v4, (a0), v12 -# CHECK-INST: vsxseg3e.v v4, (a0), v12 +th.vsxseg3e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg3e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x4e] -vsxseg3e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg3e.v v4, (a0), v12 +th.vsxseg3e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg3e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x4e] -vsxseg3e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg3e.v v4, (a0), v12, v0.t +th.vsxseg3e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg3e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0x4c] -vlxseg4b.v v4, (a0), v12 -# CHECK-INST: vlxseg4b.v v4, (a0), v12 +th.vlxseg4b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x7e] -vlxseg4b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4b.v v4, (a0), v12 +th.vlxseg4b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x7e] -vlxseg4b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4b.v v4, (a0), v12, v0.t +th.vlxseg4b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x7c] -vlxseg4h.v v4, (a0), v12 -# CHECK-INST: vlxseg4h.v v4, (a0), v12 +th.vlxseg4h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x7e] -vlxseg4h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4h.v v4, (a0), v12 +th.vlxseg4h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x7e] -vlxseg4h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4h.v v4, (a0), v12, v0.t +th.vlxseg4h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x7c] -vlxseg4w.v v4, (a0), v12 -# CHECK-INST: vlxseg4w.v v4, (a0), v12 +th.vlxseg4w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x7e] -vlxseg4w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4w.v v4, (a0), v12 +th.vlxseg4w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x7e] -vlxseg4w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4w.v v4, (a0), v12, v0.t +th.vlxseg4w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x7c] -vlxseg4bu.v v4, (a0), v12 -# CHECK-INST: vlxseg4bu.v v4, (a0), v12 +th.vlxseg4bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x6e] -vlxseg4bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4bu.v v4, (a0), v12 +th.vlxseg4bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x6e] -vlxseg4bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4bu.v v4, (a0), v12, v0.t +th.vlxseg4bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x6c] -vlxseg4hu.v v4, (a0), v12 -# CHECK-INST: vlxseg4hu.v v4, (a0), v12 +th.vlxseg4hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x6e] -vlxseg4hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4hu.v v4, (a0), v12 +th.vlxseg4hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x6e] -vlxseg4hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4hu.v v4, (a0), v12, v0.t +th.vlxseg4hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x6c] -vlxseg4wu.v v4, (a0), v12 -# CHECK-INST: vlxseg4wu.v v4, (a0), v12 +th.vlxseg4wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x6e] -vlxseg4wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4wu.v v4, (a0), v12 +th.vlxseg4wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x6e] -vlxseg4wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4wu.v v4, (a0), v12, v0.t +th.vlxseg4wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x6c] -vlxseg4e.v v4, (a0), v12 -# CHECK-INST: vlxseg4e.v v4, (a0), v12 +th.vlxseg4e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg4e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x6e] -vlxseg4e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg4e.v v4, (a0), v12 +th.vlxseg4e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg4e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x6e] -vlxseg4e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg4e.v v4, (a0), v12, v0.t +th.vlxseg4e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg4e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0x6c] -vsxseg4b.v v4, (a0), v12 -# CHECK-INST: vsxseg4b.v v4, (a0), v12 +th.vsxseg4b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg4b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x6e] -vsxseg4b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg4b.v v4, (a0), v12 +th.vsxseg4b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg4b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x6e] -vsxseg4b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg4b.v v4, (a0), v12, v0.t +th.vsxseg4b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg4b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0x6c] -vsxseg4h.v v4, (a0), v12 -# CHECK-INST: vsxseg4h.v v4, (a0), v12 +th.vsxseg4h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg4h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x6e] -vsxseg4h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg4h.v v4, (a0), v12 +th.vsxseg4h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg4h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x6e] -vsxseg4h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg4h.v v4, (a0), v12, v0.t +th.vsxseg4h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg4h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0x6c] -vsxseg4w.v v4, (a0), v12 -# CHECK-INST: vsxseg4w.v v4, (a0), v12 +th.vsxseg4w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg4w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x6e] -vsxseg4w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg4w.v v4, (a0), v12 +th.vsxseg4w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg4w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x6e] -vsxseg4w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg4w.v v4, (a0), v12, v0.t +th.vsxseg4w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg4w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0x6c] -vsxseg4e.v v4, (a0), v12 -# CHECK-INST: vsxseg4e.v v4, (a0), v12 +th.vsxseg4e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg4e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x6e] -vsxseg4e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg4e.v v4, (a0), v12 +th.vsxseg4e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg4e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x6e] -vsxseg4e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg4e.v v4, (a0), v12, v0.t +th.vsxseg4e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg4e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0x6c] -vlxseg5b.v v4, (a0), v12 -# CHECK-INST: vlxseg5b.v v4, (a0), v12 +th.vlxseg5b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x9e] -vlxseg5b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5b.v v4, (a0), v12 +th.vlxseg5b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x9e] -vlxseg5b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5b.v v4, (a0), v12, v0.t +th.vlxseg5b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x9c] -vlxseg5h.v v4, (a0), v12 -# CHECK-INST: vlxseg5h.v v4, (a0), v12 +th.vlxseg5h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x9e] -vlxseg5h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5h.v v4, (a0), v12 +th.vlxseg5h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x9e] -vlxseg5h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5h.v v4, (a0), v12, v0.t +th.vlxseg5h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x9c] -vlxseg5w.v v4, (a0), v12 -# CHECK-INST: vlxseg5w.v v4, (a0), v12 +th.vlxseg5w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x9e] -vlxseg5w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5w.v v4, (a0), v12 +th.vlxseg5w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x9e] -vlxseg5w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5w.v v4, (a0), v12, v0.t +th.vlxseg5w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x9c] -vlxseg5bu.v v4, (a0), v12 -# CHECK-INST: vlxseg5bu.v v4, (a0), v12 +th.vlxseg5bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x8e] -vlxseg5bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5bu.v v4, (a0), v12 +th.vlxseg5bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0x8e] -vlxseg5bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5bu.v v4, (a0), v12, v0.t +th.vlxseg5bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0x8c] -vlxseg5hu.v v4, (a0), v12 -# CHECK-INST: vlxseg5hu.v v4, (a0), v12 +th.vlxseg5hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x8e] -vlxseg5hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5hu.v v4, (a0), v12 +th.vlxseg5hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0x8e] -vlxseg5hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5hu.v v4, (a0), v12, v0.t +th.vlxseg5hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0x8c] -vlxseg5wu.v v4, (a0), v12 -# CHECK-INST: vlxseg5wu.v v4, (a0), v12 +th.vlxseg5wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x8e] -vlxseg5wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5wu.v v4, (a0), v12 +th.vlxseg5wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0x8e] -vlxseg5wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5wu.v v4, (a0), v12, v0.t +th.vlxseg5wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0x8c] -vlxseg5e.v v4, (a0), v12 -# CHECK-INST: vlxseg5e.v v4, (a0), v12 +th.vlxseg5e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg5e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x8e] -vlxseg5e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg5e.v v4, (a0), v12 +th.vlxseg5e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg5e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0x8e] -vlxseg5e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg5e.v v4, (a0), v12, v0.t +th.vlxseg5e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg5e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0x8c] -vsxseg5b.v v4, (a0), v12 -# CHECK-INST: vsxseg5b.v v4, (a0), v12 +th.vsxseg5b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg5b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x8e] -vsxseg5b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg5b.v v4, (a0), v12 +th.vsxseg5b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg5b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0x8e] -vsxseg5b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg5b.v v4, (a0), v12, v0.t +th.vsxseg5b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg5b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0x8c] -vsxseg5h.v v4, (a0), v12 -# CHECK-INST: vsxseg5h.v v4, (a0), v12 +th.vsxseg5h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg5h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x8e] -vsxseg5h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg5h.v v4, (a0), v12 +th.vsxseg5h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg5h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0x8e] -vsxseg5h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg5h.v v4, (a0), v12, v0.t +th.vsxseg5h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg5h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0x8c] -vsxseg5w.v v4, (a0), v12 -# CHECK-INST: vsxseg5w.v v4, (a0), v12 +th.vsxseg5w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg5w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x8e] -vsxseg5w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg5w.v v4, (a0), v12 +th.vsxseg5w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg5w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0x8e] -vsxseg5w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg5w.v v4, (a0), v12, v0.t +th.vsxseg5w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg5w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0x8c] -vsxseg5e.v v4, (a0), v12 -# CHECK-INST: vsxseg5e.v v4, (a0), v12 +th.vsxseg5e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg5e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x8e] -vsxseg5e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg5e.v v4, (a0), v12 +th.vsxseg5e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg5e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0x8e] -vsxseg5e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg5e.v v4, (a0), v12, v0.t +th.vsxseg5e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg5e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0x8c] -vlxseg6b.v v4, (a0), v12 -# CHECK-INST: vlxseg6b.v v4, (a0), v12 +th.vlxseg6b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xbe] -vlxseg6b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6b.v v4, (a0), v12 +th.vlxseg6b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xbe] -vlxseg6b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6b.v v4, (a0), v12, v0.t +th.vlxseg6b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0xbc] -vlxseg6h.v v4, (a0), v12 -# CHECK-INST: vlxseg6h.v v4, (a0), v12 +th.vlxseg6h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xbe] -vlxseg6h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6h.v v4, (a0), v12 +th.vlxseg6h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xbe] -vlxseg6h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6h.v v4, (a0), v12, v0.t +th.vlxseg6h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0xbc] -vlxseg6w.v v4, (a0), v12 -# CHECK-INST: vlxseg6w.v v4, (a0), v12 +th.vlxseg6w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xbe] -vlxseg6w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6w.v v4, (a0), v12 +th.vlxseg6w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xbe] -vlxseg6w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6w.v v4, (a0), v12, v0.t +th.vlxseg6w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0xbc] -vlxseg6bu.v v4, (a0), v12 -# CHECK-INST: vlxseg6bu.v v4, (a0), v12 +th.vlxseg6bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xae] -vlxseg6bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6bu.v v4, (a0), v12 +th.vlxseg6bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xae] -vlxseg6bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6bu.v v4, (a0), v12, v0.t +th.vlxseg6bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0xac] -vlxseg6hu.v v4, (a0), v12 -# CHECK-INST: vlxseg6hu.v v4, (a0), v12 +th.vlxseg6hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xae] -vlxseg6hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6hu.v v4, (a0), v12 +th.vlxseg6hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xae] -vlxseg6hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6hu.v v4, (a0), v12, v0.t +th.vlxseg6hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0xac] -vlxseg6wu.v v4, (a0), v12 -# CHECK-INST: vlxseg6wu.v v4, (a0), v12 +th.vlxseg6wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xae] -vlxseg6wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6wu.v v4, (a0), v12 +th.vlxseg6wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xae] -vlxseg6wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6wu.v v4, (a0), v12, v0.t +th.vlxseg6wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0xac] -vlxseg6e.v v4, (a0), v12 -# CHECK-INST: vlxseg6e.v v4, (a0), v12 +th.vlxseg6e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg6e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0xae] -vlxseg6e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg6e.v v4, (a0), v12 +th.vlxseg6e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg6e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0xae] -vlxseg6e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg6e.v v4, (a0), v12, v0.t +th.vlxseg6e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg6e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0xac] -vsxseg6b.v v4, (a0), v12 -# CHECK-INST: vsxseg6b.v v4, (a0), v12 +th.vsxseg6b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg6b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0xae] -vsxseg6b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg6b.v v4, (a0), v12 +th.vsxseg6b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg6b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0xae] -vsxseg6b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg6b.v v4, (a0), v12, v0.t +th.vsxseg6b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg6b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0xac] -vsxseg6h.v v4, (a0), v12 -# CHECK-INST: vsxseg6h.v v4, (a0), v12 +th.vsxseg6h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg6h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0xae] -vsxseg6h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg6h.v v4, (a0), v12 +th.vsxseg6h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg6h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0xae] -vsxseg6h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg6h.v v4, (a0), v12, v0.t +th.vsxseg6h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg6h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0xac] -vsxseg6w.v v4, (a0), v12 -# CHECK-INST: vsxseg6w.v v4, (a0), v12 +th.vsxseg6w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg6w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0xae] -vsxseg6w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg6w.v v4, (a0), v12 +th.vsxseg6w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg6w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0xae] -vsxseg6w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg6w.v v4, (a0), v12, v0.t +th.vsxseg6w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg6w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0xac] -vsxseg6e.v v4, (a0), v12 -# CHECK-INST: vsxseg6e.v v4, (a0), v12 +th.vsxseg6e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg6e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0xae] -vsxseg6e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg6e.v v4, (a0), v12 +th.vsxseg6e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg6e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0xae] -vsxseg6e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg6e.v v4, (a0), v12, v0.t +th.vsxseg6e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg6e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0xac] -vlxseg7b.v v4, (a0), v12 -# CHECK-INST: vlxseg7b.v v4, (a0), v12 +th.vlxseg7b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xde] -vlxseg7b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7b.v v4, (a0), v12 +th.vlxseg7b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xde] -vlxseg7b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7b.v v4, (a0), v12, v0.t +th.vlxseg7b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0xdc] -vlxseg7h.v v4, (a0), v12 -# CHECK-INST: vlxseg7h.v v4, (a0), v12 +th.vlxseg7h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xde] -vlxseg7h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7h.v v4, (a0), v12 +th.vlxseg7h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xde] -vlxseg7h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7h.v v4, (a0), v12, v0.t +th.vlxseg7h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0xdc] -vlxseg7w.v v4, (a0), v12 -# CHECK-INST: vlxseg7w.v v4, (a0), v12 +th.vlxseg7w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xde] -vlxseg7w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7w.v v4, (a0), v12 +th.vlxseg7w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xde] -vlxseg7w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7w.v v4, (a0), v12, v0.t +th.vlxseg7w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0xdc] -vlxseg7bu.v v4, (a0), v12 -# CHECK-INST: vlxseg7bu.v v4, (a0), v12 +th.vlxseg7bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xce] -vlxseg7bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7bu.v v4, (a0), v12 +th.vlxseg7bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xce] -vlxseg7bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7bu.v v4, (a0), v12, v0.t +th.vlxseg7bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0xcc] -vlxseg7hu.v v4, (a0), v12 -# CHECK-INST: vlxseg7hu.v v4, (a0), v12 +th.vlxseg7hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xce] -vlxseg7hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7hu.v v4, (a0), v12 +th.vlxseg7hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xce] -vlxseg7hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7hu.v v4, (a0), v12, v0.t +th.vlxseg7hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0xcc] -vlxseg7wu.v v4, (a0), v12 -# CHECK-INST: vlxseg7wu.v v4, (a0), v12 +th.vlxseg7wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xce] -vlxseg7wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7wu.v v4, (a0), v12 +th.vlxseg7wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xce] -vlxseg7wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7wu.v v4, (a0), v12, v0.t +th.vlxseg7wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0xcc] -vlxseg7e.v v4, (a0), v12 -# CHECK-INST: vlxseg7e.v v4, (a0), v12 +th.vlxseg7e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg7e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0xce] -vlxseg7e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg7e.v v4, (a0), v12 +th.vlxseg7e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg7e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0xce] -vlxseg7e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg7e.v v4, (a0), v12, v0.t +th.vlxseg7e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg7e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0xcc] -vsxseg7b.v v4, (a0), v12 -# CHECK-INST: vsxseg7b.v v4, (a0), v12 +th.vsxseg7b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg7b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0xce] -vsxseg7b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg7b.v v4, (a0), v12 +th.vsxseg7b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg7b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0xce] -vsxseg7b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg7b.v v4, (a0), v12, v0.t +th.vsxseg7b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg7b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0xcc] -vsxseg7h.v v4, (a0), v12 -# CHECK-INST: vsxseg7h.v v4, (a0), v12 +th.vsxseg7h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg7h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0xce] -vsxseg7h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg7h.v v4, (a0), v12 +th.vsxseg7h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg7h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0xce] -vsxseg7h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg7h.v v4, (a0), v12, v0.t +th.vsxseg7h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg7h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0xcc] -vsxseg7w.v v4, (a0), v12 -# CHECK-INST: vsxseg7w.v v4, (a0), v12 +th.vsxseg7w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg7w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0xce] -vsxseg7w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg7w.v v4, (a0), v12 +th.vsxseg7w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg7w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0xce] -vsxseg7w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg7w.v v4, (a0), v12, v0.t +th.vsxseg7w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg7w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0xcc] -vsxseg7e.v v4, (a0), v12 -# CHECK-INST: vsxseg7e.v v4, (a0), v12 +th.vsxseg7e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg7e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0xce] -vsxseg7e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg7e.v v4, (a0), v12 +th.vsxseg7e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg7e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0xce] -vsxseg7e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg7e.v v4, (a0), v12, v0.t +th.vsxseg7e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg7e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0xcc] -vlxseg8b.v v4, (a0), v12 -# CHECK-INST: vlxseg8b.v v4, (a0), v12 +th.vlxseg8b.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xfe] -vlxseg8b.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8b.v v4, (a0), v12 +th.vlxseg8b.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8b.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xfe] -vlxseg8b.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8b.v v4, (a0), v12, v0.t +th.vlxseg8b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0xfc] -vlxseg8h.v v4, (a0), v12 -# CHECK-INST: vlxseg8h.v v4, (a0), v12 +th.vlxseg8h.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xfe] -vlxseg8h.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8h.v v4, (a0), v12 +th.vlxseg8h.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8h.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xfe] -vlxseg8h.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8h.v v4, (a0), v12, v0.t +th.vlxseg8h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0xfc] -vlxseg8w.v v4, (a0), v12 -# CHECK-INST: vlxseg8w.v v4, (a0), v12 +th.vlxseg8w.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xfe] -vlxseg8w.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8w.v v4, (a0), v12 +th.vlxseg8w.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8w.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xfe] -vlxseg8w.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8w.v v4, (a0), v12, v0.t +th.vlxseg8w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0xfc] -vlxseg8bu.v v4, (a0), v12 -# CHECK-INST: vlxseg8bu.v v4, (a0), v12 +th.vlxseg8bu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xee] -vlxseg8bu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8bu.v v4, (a0), v12 +th.vlxseg8bu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8bu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x02,0xc5,0xee] -vlxseg8bu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8bu.v v4, (a0), v12, v0.t +th.vlxseg8bu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8bu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x02,0xc5,0xec] -vlxseg8hu.v v4, (a0), v12 -# CHECK-INST: vlxseg8hu.v v4, (a0), v12 +th.vlxseg8hu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xee] -vlxseg8hu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8hu.v v4, (a0), v12 +th.vlxseg8hu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8hu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x52,0xc5,0xee] -vlxseg8hu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8hu.v v4, (a0), v12, v0.t +th.vlxseg8hu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8hu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x52,0xc5,0xec] -vlxseg8wu.v v4, (a0), v12 -# CHECK-INST: vlxseg8wu.v v4, (a0), v12 +th.vlxseg8wu.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xee] -vlxseg8wu.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8wu.v v4, (a0), v12 +th.vlxseg8wu.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8wu.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x62,0xc5,0xee] -vlxseg8wu.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8wu.v v4, (a0), v12, v0.t +th.vlxseg8wu.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8wu.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x62,0xc5,0xec] -vlxseg8e.v v4, (a0), v12 -# CHECK-INST: vlxseg8e.v v4, (a0), v12 +th.vlxseg8e.v v4, (a0), v12 +# CHECK-INST: th.vlxseg8e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0xee] -vlxseg8e.v v4, 0(a0), v12 -# CHECK-INST: vlxseg8e.v v4, (a0), v12 +th.vlxseg8e.v v4, 0(a0), v12 +# CHECK-INST: th.vlxseg8e.v v4, (a0), v12 # CHECK-ENCODING: [0x07,0x72,0xc5,0xee] -vlxseg8e.v v4, (a0), v12, v0.t -# CHECK-INST: vlxseg8e.v v4, (a0), v12, v0.t +th.vlxseg8e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vlxseg8e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x07,0x72,0xc5,0xec] -vsxseg8b.v v4, (a0), v12 -# CHECK-INST: vsxseg8b.v v4, (a0), v12 +th.vsxseg8b.v v4, (a0), v12 +# CHECK-INST: th.vsxseg8b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0xee] -vsxseg8b.v v4, 0(a0), v12 -# CHECK-INST: vsxseg8b.v v4, (a0), v12 +th.vsxseg8b.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg8b.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x02,0xc5,0xee] -vsxseg8b.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg8b.v v4, (a0), v12, v0.t +th.vsxseg8b.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg8b.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x02,0xc5,0xec] -vsxseg8h.v v4, (a0), v12 -# CHECK-INST: vsxseg8h.v v4, (a0), v12 +th.vsxseg8h.v v4, (a0), v12 +# CHECK-INST: th.vsxseg8h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0xee] -vsxseg8h.v v4, 0(a0), v12 -# CHECK-INST: vsxseg8h.v v4, (a0), v12 +th.vsxseg8h.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg8h.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x52,0xc5,0xee] -vsxseg8h.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg8h.v v4, (a0), v12, v0.t +th.vsxseg8h.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg8h.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x52,0xc5,0xec] -vsxseg8w.v v4, (a0), v12 -# CHECK-INST: vsxseg8w.v v4, (a0), v12 +th.vsxseg8w.v v4, (a0), v12 +# CHECK-INST: th.vsxseg8w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0xee] -vsxseg8w.v v4, 0(a0), v12 -# CHECK-INST: vsxseg8w.v v4, (a0), v12 +th.vsxseg8w.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg8w.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x62,0xc5,0xee] -vsxseg8w.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg8w.v v4, (a0), v12, v0.t +th.vsxseg8w.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg8w.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x62,0xc5,0xec] -vsxseg8e.v v4, (a0), v12 -# CHECK-INST: vsxseg8e.v v4, (a0), v12 +th.vsxseg8e.v v4, (a0), v12 +# CHECK-INST: th.vsxseg8e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0xee] -vsxseg8e.v v4, 0(a0), v12 -# CHECK-INST: vsxseg8e.v v4, (a0), v12 +th.vsxseg8e.v v4, 0(a0), v12 +# CHECK-INST: th.vsxseg8e.v v4, (a0), v12 # CHECK-ENCODING: [0x27,0x72,0xc5,0xee] -vsxseg8e.v v4, (a0), v12, v0.t -# CHECK-INST: vsxseg8e.v v4, (a0), v12, v0.t +th.vsxseg8e.v v4, (a0), v12, v0.t +# CHECK-INST: th.vsxseg8e.v v4, (a0), v12, v0.t # CHECK-ENCODING: [0x27,0x72,0xc5,0xec] -vlseg2bff.v v4, (a0) -# CHECK-INST: vlseg2bff.v v4, (a0) +th.vlseg2bff.v v4, (a0) +# CHECK-INST: th.vlseg2bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x33] -vlseg2bff.v v4, 0(a0) -# CHECK-INST: vlseg2bff.v v4, (a0) +th.vlseg2bff.v v4, 0(a0) +# CHECK-INST: th.vlseg2bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x33] -vlseg2bff.v v4, (a0), v0.t -# CHECK-INST: vlseg2bff.v v4, (a0), v0.t +th.vlseg2bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x31] -vlseg2hff.v v4, (a0) -# CHECK-INST: vlseg2hff.v v4, (a0) +th.vlseg2hff.v v4, (a0) +# CHECK-INST: th.vlseg2hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x33] -vlseg2hff.v v4, 0(a0) -# CHECK-INST: vlseg2hff.v v4, (a0) +th.vlseg2hff.v v4, 0(a0) +# CHECK-INST: th.vlseg2hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x33] -vlseg2hff.v v4, (a0), v0.t -# CHECK-INST: vlseg2hff.v v4, (a0), v0.t +th.vlseg2hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x31] -vlseg2wff.v v4, (a0) -# CHECK-INST: vlseg2wff.v v4, (a0) +th.vlseg2wff.v v4, (a0) +# CHECK-INST: th.vlseg2wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x33] -vlseg2wff.v v4, 0(a0) -# CHECK-INST: vlseg2wff.v v4, (a0) +th.vlseg2wff.v v4, 0(a0) +# CHECK-INST: th.vlseg2wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x33] -vlseg2wff.v v4, (a0), v0.t -# CHECK-INST: vlseg2wff.v v4, (a0), v0.t +th.vlseg2wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x31] -vlseg2buff.v v4, (a0) -# CHECK-INST: vlseg2buff.v v4, (a0) +th.vlseg2buff.v v4, (a0) +# CHECK-INST: th.vlseg2buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x23] -vlseg2buff.v v4, 0(a0) -# CHECK-INST: vlseg2buff.v v4, (a0) +th.vlseg2buff.v v4, 0(a0) +# CHECK-INST: th.vlseg2buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x23] -vlseg2buff.v v4, (a0), v0.t -# CHECK-INST: vlseg2buff.v v4, (a0), v0.t +th.vlseg2buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x21] -vlseg2huff.v v4, (a0) -# CHECK-INST: vlseg2huff.v v4, (a0) +th.vlseg2huff.v v4, (a0) +# CHECK-INST: th.vlseg2huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x23] -vlseg2huff.v v4, 0(a0) -# CHECK-INST: vlseg2huff.v v4, (a0) +th.vlseg2huff.v v4, 0(a0) +# CHECK-INST: th.vlseg2huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x23] -vlseg2huff.v v4, (a0), v0.t -# CHECK-INST: vlseg2huff.v v4, (a0), v0.t +th.vlseg2huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x21] -vlseg2wuff.v v4, (a0) -# CHECK-INST: vlseg2wuff.v v4, (a0) +th.vlseg2wuff.v v4, (a0) +# CHECK-INST: th.vlseg2wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x23] -vlseg2wuff.v v4, 0(a0) -# CHECK-INST: vlseg2wuff.v v4, (a0) +th.vlseg2wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg2wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x23] -vlseg2wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg2wuff.v v4, (a0), v0.t +th.vlseg2wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x21] -vlseg2eff.v v4, (a0) -# CHECK-INST: vlseg2eff.v v4, (a0) +th.vlseg2eff.v v4, (a0) +# CHECK-INST: th.vlseg2eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x23] -vlseg2eff.v v4, 0(a0) -# CHECK-INST: vlseg2eff.v v4, (a0) +th.vlseg2eff.v v4, 0(a0) +# CHECK-INST: th.vlseg2eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x23] -vlseg2eff.v v4, (a0), v0.t -# CHECK-INST: vlseg2eff.v v4, (a0), v0.t +th.vlseg2eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg2eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x21] -vlseg3bff.v v4, (a0) -# CHECK-INST: vlseg3bff.v v4, (a0) +th.vlseg3bff.v v4, (a0) +# CHECK-INST: th.vlseg3bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x53] -vlseg3bff.v v4, 0(a0) -# CHECK-INST: vlseg3bff.v v4, (a0) +th.vlseg3bff.v v4, 0(a0) +# CHECK-INST: th.vlseg3bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x53] -vlseg3bff.v v4, (a0), v0.t -# CHECK-INST: vlseg3bff.v v4, (a0), v0.t +th.vlseg3bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x51] -vlseg3hff.v v4, (a0) -# CHECK-INST: vlseg3hff.v v4, (a0) +th.vlseg3hff.v v4, (a0) +# CHECK-INST: th.vlseg3hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x53] -vlseg3hff.v v4, 0(a0) -# CHECK-INST: vlseg3hff.v v4, (a0) +th.vlseg3hff.v v4, 0(a0) +# CHECK-INST: th.vlseg3hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x53] -vlseg3hff.v v4, (a0), v0.t -# CHECK-INST: vlseg3hff.v v4, (a0), v0.t +th.vlseg3hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x51] -vlseg3wff.v v4, (a0) -# CHECK-INST: vlseg3wff.v v4, (a0) +th.vlseg3wff.v v4, (a0) +# CHECK-INST: th.vlseg3wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x53] -vlseg3wff.v v4, 0(a0) -# CHECK-INST: vlseg3wff.v v4, (a0) +th.vlseg3wff.v v4, 0(a0) +# CHECK-INST: th.vlseg3wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x53] -vlseg3wff.v v4, (a0), v0.t -# CHECK-INST: vlseg3wff.v v4, (a0), v0.t +th.vlseg3wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x51] -vlseg3buff.v v4, (a0) -# CHECK-INST: vlseg3buff.v v4, (a0) +th.vlseg3buff.v v4, (a0) +# CHECK-INST: th.vlseg3buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x43] -vlseg3buff.v v4, 0(a0) -# CHECK-INST: vlseg3buff.v v4, (a0) +th.vlseg3buff.v v4, 0(a0) +# CHECK-INST: th.vlseg3buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x43] -vlseg3buff.v v4, (a0), v0.t -# CHECK-INST: vlseg3buff.v v4, (a0), v0.t +th.vlseg3buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x41] -vlseg3huff.v v4, (a0) -# CHECK-INST: vlseg3huff.v v4, (a0) +th.vlseg3huff.v v4, (a0) +# CHECK-INST: th.vlseg3huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x43] -vlseg3huff.v v4, 0(a0) -# CHECK-INST: vlseg3huff.v v4, (a0) +th.vlseg3huff.v v4, 0(a0) +# CHECK-INST: th.vlseg3huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x43] -vlseg3huff.v v4, (a0), v0.t -# CHECK-INST: vlseg3huff.v v4, (a0), v0.t +th.vlseg3huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x41] -vlseg3wuff.v v4, (a0) -# CHECK-INST: vlseg3wuff.v v4, (a0) +th.vlseg3wuff.v v4, (a0) +# CHECK-INST: th.vlseg3wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x43] -vlseg3wuff.v v4, 0(a0) -# CHECK-INST: vlseg3wuff.v v4, (a0) +th.vlseg3wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg3wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x43] -vlseg3wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg3wuff.v v4, (a0), v0.t +th.vlseg3wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x41] -vlseg3eff.v v4, (a0) -# CHECK-INST: vlseg3eff.v v4, (a0) +th.vlseg3eff.v v4, (a0) +# CHECK-INST: th.vlseg3eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x43] -vlseg3eff.v v4, 0(a0) -# CHECK-INST: vlseg3eff.v v4, (a0) +th.vlseg3eff.v v4, 0(a0) +# CHECK-INST: th.vlseg3eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x43] -vlseg3eff.v v4, (a0), v0.t -# CHECK-INST: vlseg3eff.v v4, (a0), v0.t +th.vlseg3eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg3eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x41] -vlseg4bff.v v4, (a0) -# CHECK-INST: vlseg4bff.v v4, (a0) +th.vlseg4bff.v v4, (a0) +# CHECK-INST: th.vlseg4bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x73] -vlseg4bff.v v4, 0(a0) -# CHECK-INST: vlseg4bff.v v4, (a0) +th.vlseg4bff.v v4, 0(a0) +# CHECK-INST: th.vlseg4bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x73] -vlseg4bff.v v4, (a0), v0.t -# CHECK-INST: vlseg4bff.v v4, (a0), v0.t +th.vlseg4bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x71] -vlseg4hff.v v4, (a0) -# CHECK-INST: vlseg4hff.v v4, (a0) +th.vlseg4hff.v v4, (a0) +# CHECK-INST: th.vlseg4hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x73] -vlseg4hff.v v4, 0(a0) -# CHECK-INST: vlseg4hff.v v4, (a0) +th.vlseg4hff.v v4, 0(a0) +# CHECK-INST: th.vlseg4hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x73] -vlseg4hff.v v4, (a0), v0.t -# CHECK-INST: vlseg4hff.v v4, (a0), v0.t +th.vlseg4hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x71] -vlseg4wff.v v4, (a0) -# CHECK-INST: vlseg4wff.v v4, (a0) +th.vlseg4wff.v v4, (a0) +# CHECK-INST: th.vlseg4wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x73] -vlseg4wff.v v4, 0(a0) -# CHECK-INST: vlseg4wff.v v4, (a0) +th.vlseg4wff.v v4, 0(a0) +# CHECK-INST: th.vlseg4wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x73] -vlseg4wff.v v4, (a0), v0.t -# CHECK-INST: vlseg4wff.v v4, (a0), v0.t +th.vlseg4wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x71] -vlseg4buff.v v4, (a0) -# CHECK-INST: vlseg4buff.v v4, (a0) +th.vlseg4buff.v v4, (a0) +# CHECK-INST: th.vlseg4buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x63] -vlseg4buff.v v4, 0(a0) -# CHECK-INST: vlseg4buff.v v4, (a0) +th.vlseg4buff.v v4, 0(a0) +# CHECK-INST: th.vlseg4buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x63] -vlseg4buff.v v4, (a0), v0.t -# CHECK-INST: vlseg4buff.v v4, (a0), v0.t +th.vlseg4buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x61] -vlseg4huff.v v4, (a0) -# CHECK-INST: vlseg4huff.v v4, (a0) +th.vlseg4huff.v v4, (a0) +# CHECK-INST: th.vlseg4huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x63] -vlseg4huff.v v4, 0(a0) -# CHECK-INST: vlseg4huff.v v4, (a0) +th.vlseg4huff.v v4, 0(a0) +# CHECK-INST: th.vlseg4huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x63] -vlseg4huff.v v4, (a0), v0.t -# CHECK-INST: vlseg4huff.v v4, (a0), v0.t +th.vlseg4huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x61] -vlseg4wuff.v v4, (a0) -# CHECK-INST: vlseg4wuff.v v4, (a0) +th.vlseg4wuff.v v4, (a0) +# CHECK-INST: th.vlseg4wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x63] -vlseg4wuff.v v4, 0(a0) -# CHECK-INST: vlseg4wuff.v v4, (a0) +th.vlseg4wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg4wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x63] -vlseg4wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg4wuff.v v4, (a0), v0.t +th.vlseg4wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x61] -vlseg4eff.v v4, (a0) -# CHECK-INST: vlseg4eff.v v4, (a0) +th.vlseg4eff.v v4, (a0) +# CHECK-INST: th.vlseg4eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x63] -vlseg4eff.v v4, 0(a0) -# CHECK-INST: vlseg4eff.v v4, (a0) +th.vlseg4eff.v v4, 0(a0) +# CHECK-INST: th.vlseg4eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x63] -vlseg4eff.v v4, (a0), v0.t -# CHECK-INST: vlseg4eff.v v4, (a0), v0.t +th.vlseg4eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg4eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x61] -vlseg5bff.v v4, (a0) -# CHECK-INST: vlseg5bff.v v4, (a0) +th.vlseg5bff.v v4, (a0) +# CHECK-INST: th.vlseg5bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x93] -vlseg5bff.v v4, 0(a0) -# CHECK-INST: vlseg5bff.v v4, (a0) +th.vlseg5bff.v v4, 0(a0) +# CHECK-INST: th.vlseg5bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x93] -vlseg5bff.v v4, (a0), v0.t -# CHECK-INST: vlseg5bff.v v4, (a0), v0.t +th.vlseg5bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x91] -vlseg5hff.v v4, (a0) -# CHECK-INST: vlseg5hff.v v4, (a0) +th.vlseg5hff.v v4, (a0) +# CHECK-INST: th.vlseg5hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x93] -vlseg5hff.v v4, 0(a0) -# CHECK-INST: vlseg5hff.v v4, (a0) +th.vlseg5hff.v v4, 0(a0) +# CHECK-INST: th.vlseg5hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x93] -vlseg5hff.v v4, (a0), v0.t -# CHECK-INST: vlseg5hff.v v4, (a0), v0.t +th.vlseg5hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x91] -vlseg5wff.v v4, (a0) -# CHECK-INST: vlseg5wff.v v4, (a0) +th.vlseg5wff.v v4, (a0) +# CHECK-INST: th.vlseg5wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x93] -vlseg5wff.v v4, 0(a0) -# CHECK-INST: vlseg5wff.v v4, (a0) +th.vlseg5wff.v v4, 0(a0) +# CHECK-INST: th.vlseg5wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x93] -vlseg5wff.v v4, (a0), v0.t -# CHECK-INST: vlseg5wff.v v4, (a0), v0.t +th.vlseg5wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x91] -vlseg5buff.v v4, (a0) -# CHECK-INST: vlseg5buff.v v4, (a0) +th.vlseg5buff.v v4, (a0) +# CHECK-INST: th.vlseg5buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x83] -vlseg5buff.v v4, 0(a0) -# CHECK-INST: vlseg5buff.v v4, (a0) +th.vlseg5buff.v v4, 0(a0) +# CHECK-INST: th.vlseg5buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0x83] -vlseg5buff.v v4, (a0), v0.t -# CHECK-INST: vlseg5buff.v v4, (a0), v0.t +th.vlseg5buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0x81] -vlseg5huff.v v4, (a0) -# CHECK-INST: vlseg5huff.v v4, (a0) +th.vlseg5huff.v v4, (a0) +# CHECK-INST: th.vlseg5huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x83] -vlseg5huff.v v4, 0(a0) -# CHECK-INST: vlseg5huff.v v4, (a0) +th.vlseg5huff.v v4, 0(a0) +# CHECK-INST: th.vlseg5huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0x83] -vlseg5huff.v v4, (a0), v0.t -# CHECK-INST: vlseg5huff.v v4, (a0), v0.t +th.vlseg5huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0x81] -vlseg5wuff.v v4, (a0) -# CHECK-INST: vlseg5wuff.v v4, (a0) +th.vlseg5wuff.v v4, (a0) +# CHECK-INST: th.vlseg5wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x83] -vlseg5wuff.v v4, 0(a0) -# CHECK-INST: vlseg5wuff.v v4, (a0) +th.vlseg5wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg5wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0x83] -vlseg5wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg5wuff.v v4, (a0), v0.t +th.vlseg5wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0x81] -vlseg5eff.v v4, (a0) -# CHECK-INST: vlseg5eff.v v4, (a0) +th.vlseg5eff.v v4, (a0) +# CHECK-INST: th.vlseg5eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x83] -vlseg5eff.v v4, 0(a0) -# CHECK-INST: vlseg5eff.v v4, (a0) +th.vlseg5eff.v v4, 0(a0) +# CHECK-INST: th.vlseg5eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0x83] -vlseg5eff.v v4, (a0), v0.t -# CHECK-INST: vlseg5eff.v v4, (a0), v0.t +th.vlseg5eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg5eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0x81] -vlseg6bff.v v4, (a0) -# CHECK-INST: vlseg6bff.v v4, (a0) +th.vlseg6bff.v v4, (a0) +# CHECK-INST: th.vlseg6bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xb3] -vlseg6bff.v v4, 0(a0) -# CHECK-INST: vlseg6bff.v v4, (a0) +th.vlseg6bff.v v4, 0(a0) +# CHECK-INST: th.vlseg6bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xb3] -vlseg6bff.v v4, (a0), v0.t -# CHECK-INST: vlseg6bff.v v4, (a0), v0.t +th.vlseg6bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xb1] -vlseg6hff.v v4, (a0) -# CHECK-INST: vlseg6hff.v v4, (a0) +th.vlseg6hff.v v4, (a0) +# CHECK-INST: th.vlseg6hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xb3] -vlseg6hff.v v4, 0(a0) -# CHECK-INST: vlseg6hff.v v4, (a0) +th.vlseg6hff.v v4, 0(a0) +# CHECK-INST: th.vlseg6hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xb3] -vlseg6hff.v v4, (a0), v0.t -# CHECK-INST: vlseg6hff.v v4, (a0), v0.t +th.vlseg6hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xb1] -vlseg6wff.v v4, (a0) -# CHECK-INST: vlseg6wff.v v4, (a0) +th.vlseg6wff.v v4, (a0) +# CHECK-INST: th.vlseg6wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xb3] -vlseg6wff.v v4, 0(a0) -# CHECK-INST: vlseg6wff.v v4, (a0) +th.vlseg6wff.v v4, 0(a0) +# CHECK-INST: th.vlseg6wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xb3] -vlseg6wff.v v4, (a0), v0.t -# CHECK-INST: vlseg6wff.v v4, (a0), v0.t +th.vlseg6wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xb1] -vlseg6buff.v v4, (a0) -# CHECK-INST: vlseg6buff.v v4, (a0) +th.vlseg6buff.v v4, (a0) +# CHECK-INST: th.vlseg6buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xa3] -vlseg6buff.v v4, 0(a0) -# CHECK-INST: vlseg6buff.v v4, (a0) +th.vlseg6buff.v v4, 0(a0) +# CHECK-INST: th.vlseg6buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xa3] -vlseg6buff.v v4, (a0), v0.t -# CHECK-INST: vlseg6buff.v v4, (a0), v0.t +th.vlseg6buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xa1] -vlseg6huff.v v4, (a0) -# CHECK-INST: vlseg6huff.v v4, (a0) +th.vlseg6huff.v v4, (a0) +# CHECK-INST: th.vlseg6huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xa3] -vlseg6huff.v v4, 0(a0) -# CHECK-INST: vlseg6huff.v v4, (a0) +th.vlseg6huff.v v4, 0(a0) +# CHECK-INST: th.vlseg6huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xa3] -vlseg6huff.v v4, (a0), v0.t -# CHECK-INST: vlseg6huff.v v4, (a0), v0.t +th.vlseg6huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xa1] -vlseg6wuff.v v4, (a0) -# CHECK-INST: vlseg6wuff.v v4, (a0) +th.vlseg6wuff.v v4, (a0) +# CHECK-INST: th.vlseg6wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xa3] -vlseg6wuff.v v4, 0(a0) -# CHECK-INST: vlseg6wuff.v v4, (a0) +th.vlseg6wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg6wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xa3] -vlseg6wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg6wuff.v v4, (a0), v0.t +th.vlseg6wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xa1] -vlseg6eff.v v4, (a0) -# CHECK-INST: vlseg6eff.v v4, (a0) +th.vlseg6eff.v v4, (a0) +# CHECK-INST: th.vlseg6eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xa3] -vlseg6eff.v v4, 0(a0) -# CHECK-INST: vlseg6eff.v v4, (a0) +th.vlseg6eff.v v4, 0(a0) +# CHECK-INST: th.vlseg6eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xa3] -vlseg6eff.v v4, (a0), v0.t -# CHECK-INST: vlseg6eff.v v4, (a0), v0.t +th.vlseg6eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg6eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0xa1] -vlseg7bff.v v4, (a0) -# CHECK-INST: vlseg7bff.v v4, (a0) +th.vlseg7bff.v v4, (a0) +# CHECK-INST: th.vlseg7bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xd3] -vlseg7bff.v v4, 0(a0) -# CHECK-INST: vlseg7bff.v v4, (a0) +th.vlseg7bff.v v4, 0(a0) +# CHECK-INST: th.vlseg7bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xd3] -vlseg7bff.v v4, (a0), v0.t -# CHECK-INST: vlseg7bff.v v4, (a0), v0.t +th.vlseg7bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xd1] -vlseg7hff.v v4, (a0) -# CHECK-INST: vlseg7hff.v v4, (a0) +th.vlseg7hff.v v4, (a0) +# CHECK-INST: th.vlseg7hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xd3] -vlseg7hff.v v4, 0(a0) -# CHECK-INST: vlseg7hff.v v4, (a0) +th.vlseg7hff.v v4, 0(a0) +# CHECK-INST: th.vlseg7hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xd3] -vlseg7hff.v v4, (a0), v0.t -# CHECK-INST: vlseg7hff.v v4, (a0), v0.t +th.vlseg7hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xd1] -vlseg7wff.v v4, (a0) -# CHECK-INST: vlseg7wff.v v4, (a0) +th.vlseg7wff.v v4, (a0) +# CHECK-INST: th.vlseg7wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xd3] -vlseg7wff.v v4, 0(a0) -# CHECK-INST: vlseg7wff.v v4, (a0) +th.vlseg7wff.v v4, 0(a0) +# CHECK-INST: th.vlseg7wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xd3] -vlseg7wff.v v4, (a0), v0.t -# CHECK-INST: vlseg7wff.v v4, (a0), v0.t +th.vlseg7wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xd1] -vlseg7buff.v v4, (a0) -# CHECK-INST: vlseg7buff.v v4, (a0) +th.vlseg7buff.v v4, (a0) +# CHECK-INST: th.vlseg7buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xc3] -vlseg7buff.v v4, 0(a0) -# CHECK-INST: vlseg7buff.v v4, (a0) +th.vlseg7buff.v v4, 0(a0) +# CHECK-INST: th.vlseg7buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xc3] -vlseg7buff.v v4, (a0), v0.t -# CHECK-INST: vlseg7buff.v v4, (a0), v0.t +th.vlseg7buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xc1] -vlseg7huff.v v4, (a0) -# CHECK-INST: vlseg7huff.v v4, (a0) +th.vlseg7huff.v v4, (a0) +# CHECK-INST: th.vlseg7huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xc3] -vlseg7huff.v v4, 0(a0) -# CHECK-INST: vlseg7huff.v v4, (a0) +th.vlseg7huff.v v4, 0(a0) +# CHECK-INST: th.vlseg7huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xc3] -vlseg7huff.v v4, (a0), v0.t -# CHECK-INST: vlseg7huff.v v4, (a0), v0.t +th.vlseg7huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xc1] -vlseg7wuff.v v4, (a0) -# CHECK-INST: vlseg7wuff.v v4, (a0) +th.vlseg7wuff.v v4, (a0) +# CHECK-INST: th.vlseg7wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xc3] -vlseg7wuff.v v4, 0(a0) -# CHECK-INST: vlseg7wuff.v v4, (a0) +th.vlseg7wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg7wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xc3] -vlseg7wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg7wuff.v v4, (a0), v0.t +th.vlseg7wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xc1] -vlseg7eff.v v4, (a0) -# CHECK-INST: vlseg7eff.v v4, (a0) +th.vlseg7eff.v v4, (a0) +# CHECK-INST: th.vlseg7eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xc3] -vlseg7eff.v v4, 0(a0) -# CHECK-INST: vlseg7eff.v v4, (a0) +th.vlseg7eff.v v4, 0(a0) +# CHECK-INST: th.vlseg7eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xc3] -vlseg7eff.v v4, (a0), v0.t -# CHECK-INST: vlseg7eff.v v4, (a0), v0.t +th.vlseg7eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg7eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0xc1] -vlseg8bff.v v4, (a0) -# CHECK-INST: vlseg8bff.v v4, (a0) +th.vlseg8bff.v v4, (a0) +# CHECK-INST: th.vlseg8bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xf3] -vlseg8bff.v v4, 0(a0) -# CHECK-INST: vlseg8bff.v v4, (a0) +th.vlseg8bff.v v4, 0(a0) +# CHECK-INST: th.vlseg8bff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xf3] -vlseg8bff.v v4, (a0), v0.t -# CHECK-INST: vlseg8bff.v v4, (a0), v0.t +th.vlseg8bff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8bff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xf1] -vlseg8hff.v v4, (a0) -# CHECK-INST: vlseg8hff.v v4, (a0) +th.vlseg8hff.v v4, (a0) +# CHECK-INST: th.vlseg8hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xf3] -vlseg8hff.v v4, 0(a0) -# CHECK-INST: vlseg8hff.v v4, (a0) +th.vlseg8hff.v v4, 0(a0) +# CHECK-INST: th.vlseg8hff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xf3] -vlseg8hff.v v4, (a0), v0.t -# CHECK-INST: vlseg8hff.v v4, (a0), v0.t +th.vlseg8hff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8hff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xf1] -vlseg8wff.v v4, (a0) -# CHECK-INST: vlseg8wff.v v4, (a0) +th.vlseg8wff.v v4, (a0) +# CHECK-INST: th.vlseg8wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xf3] -vlseg8wff.v v4, 0(a0) -# CHECK-INST: vlseg8wff.v v4, (a0) +th.vlseg8wff.v v4, 0(a0) +# CHECK-INST: th.vlseg8wff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xf3] -vlseg8wff.v v4, (a0), v0.t -# CHECK-INST: vlseg8wff.v v4, (a0), v0.t +th.vlseg8wff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8wff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xf1] -vlseg8buff.v v4, (a0) -# CHECK-INST: vlseg8buff.v v4, (a0) +th.vlseg8buff.v v4, (a0) +# CHECK-INST: th.vlseg8buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xe3] -vlseg8buff.v v4, 0(a0) -# CHECK-INST: vlseg8buff.v v4, (a0) +th.vlseg8buff.v v4, 0(a0) +# CHECK-INST: th.vlseg8buff.v v4, (a0) # CHECK-ENCODING: [0x07,0x02,0x05,0xe3] -vlseg8buff.v v4, (a0), v0.t -# CHECK-INST: vlseg8buff.v v4, (a0), v0.t +th.vlseg8buff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8buff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x02,0x05,0xe1] -vlseg8huff.v v4, (a0) -# CHECK-INST: vlseg8huff.v v4, (a0) +th.vlseg8huff.v v4, (a0) +# CHECK-INST: th.vlseg8huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xe3] -vlseg8huff.v v4, 0(a0) -# CHECK-INST: vlseg8huff.v v4, (a0) +th.vlseg8huff.v v4, 0(a0) +# CHECK-INST: th.vlseg8huff.v v4, (a0) # CHECK-ENCODING: [0x07,0x52,0x05,0xe3] -vlseg8huff.v v4, (a0), v0.t -# CHECK-INST: vlseg8huff.v v4, (a0), v0.t +th.vlseg8huff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8huff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x52,0x05,0xe1] -vlseg8wuff.v v4, (a0) -# CHECK-INST: vlseg8wuff.v v4, (a0) +th.vlseg8wuff.v v4, (a0) +# CHECK-INST: th.vlseg8wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xe3] -vlseg8wuff.v v4, 0(a0) -# CHECK-INST: vlseg8wuff.v v4, (a0) +th.vlseg8wuff.v v4, 0(a0) +# CHECK-INST: th.vlseg8wuff.v v4, (a0) # CHECK-ENCODING: [0x07,0x62,0x05,0xe3] -vlseg8wuff.v v4, (a0), v0.t -# CHECK-INST: vlseg8wuff.v v4, (a0), v0.t +th.vlseg8wuff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8wuff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x62,0x05,0xe1] -vlseg8eff.v v4, (a0) -# CHECK-INST: vlseg8eff.v v4, (a0) +th.vlseg8eff.v v4, (a0) +# CHECK-INST: th.vlseg8eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xe3] -vlseg8eff.v v4, 0(a0) -# CHECK-INST: vlseg8eff.v v4, (a0) +th.vlseg8eff.v v4, 0(a0) +# CHECK-INST: th.vlseg8eff.v v4, (a0) # CHECK-ENCODING: [0x07,0x72,0x05,0xe3] -vlseg8eff.v v4, (a0), v0.t -# CHECK-INST: vlseg8eff.v v4, (a0), v0.t +th.vlseg8eff.v v4, (a0), v0.t +# CHECK-INST: th.vlseg8eff.v v4, (a0), v0.t # CHECK-ENCODING: [0x07,0x72,0x05,0xe1] -vamoaddw.v v4, v8, (a1), v4 -# CHECK-INST: vamoaddw.v v4, v8, (a1), v4 +th.vamoaddw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoaddw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x06] -vamoaddw.v zero, v8, (a1), v4 -# CHECK-INST: vamoaddw.v x0, v8, (a1), v4 +th.vamoaddw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoaddw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x02] -vamoaddd.v v4, v8, (a1), v4 -# CHECK-INST: vamoaddd.v v4, v8, (a1), v4 +th.vamoaddd.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoaddd.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x06] -vamoaddd.v zero, v8, (a1), v4 -# CHECK-INST: vamoaddd.v x0, v8, (a1), v4 +th.vamoaddd.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoaddd.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x02] -vamoaddw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoaddw.v v4, v8, (a1), v4, v0.t +th.vamoaddw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoaddw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x04] -vamoaddw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoaddw.v x0, v8, (a1), v4, v0.t +th.vamoaddw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoaddw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x00] -vamoaddd.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoaddd.v v4, v8, (a1), v4, v0.t +th.vamoaddd.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoaddd.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x04] -vamoaddd.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoaddd.v x0, v8, (a1), v4, v0.t +th.vamoaddd.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoaddd.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x00] -vamoswapw.v v4, v8, (a1), v4 -# CHECK-INST: vamoswapw.v v4, v8, (a1), v4 +th.vamoswapw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoswapw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x0e] -vamoswapw.v zero, v8, (a1), v4 -# CHECK-INST: vamoswapw.v x0, v8, (a1), v4 +th.vamoswapw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoswapw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x0a] -vamoswapd.v v4, v8, (a1), v4 -# CHECK-INST: vamoswapd.v v4, v8, (a1), v4 +th.vamoswapd.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoswapd.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x0e] -vamoswapd.v zero, v8, (a1), v4 -# CHECK-INST: vamoswapd.v x0, v8, (a1), v4 +th.vamoswapd.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoswapd.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x0a] -vamoswapw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoswapw.v v4, v8, (a1), v4, v0.t +th.vamoswapw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoswapw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x0c] -vamoswapw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoswapw.v x0, v8, (a1), v4, v0.t +th.vamoswapw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoswapw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x08] -vamoswapd.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoswapd.v v4, v8, (a1), v4, v0.t +th.vamoswapd.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoswapd.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x0c] -vamoswapd.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoswapd.v x0, v8, (a1), v4, v0.t +th.vamoswapd.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoswapd.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x08] -vamoxorw.v v4, v8, (a1), v4 -# CHECK-INST: vamoxorw.v v4, v8, (a1), v4 +th.vamoxorw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoxorw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x26] -vamoxorw.v zero, v8, (a1), v4 -# CHECK-INST: vamoxorw.v x0, v8, (a1), v4 +th.vamoxorw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoxorw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x22] -vamoxord.v v4, v8, (a1), v4 -# CHECK-INST: vamoxord.v v4, v8, (a1), v4 +th.vamoxord.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoxord.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x26] -vamoxord.v zero, v8, (a1), v4 -# CHECK-INST: vamoxord.v x0, v8, (a1), v4 +th.vamoxord.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoxord.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x22] -vamoxorw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoxorw.v v4, v8, (a1), v4, v0.t +th.vamoxorw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoxorw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x24] -vamoxorw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoxorw.v x0, v8, (a1), v4, v0.t +th.vamoxorw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoxorw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x20] -vamoxord.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoxord.v v4, v8, (a1), v4, v0.t +th.vamoxord.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoxord.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x24] -vamoxord.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoxord.v x0, v8, (a1), v4, v0.t +th.vamoxord.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoxord.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x20] -vamoandw.v v4, v8, (a1), v4 -# CHECK-INST: vamoandw.v v4, v8, (a1), v4 +th.vamoandw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoandw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x66] -vamoandw.v zero, v8, (a1), v4 -# CHECK-INST: vamoandw.v x0, v8, (a1), v4 +th.vamoandw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoandw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x62] -vamoandd.v v4, v8, (a1), v4 -# CHECK-INST: vamoandd.v v4, v8, (a1), v4 +th.vamoandd.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoandd.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x66] -vamoandd.v zero, v8, (a1), v4 -# CHECK-INST: vamoandd.v x0, v8, (a1), v4 +th.vamoandd.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoandd.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x62] -vamoandw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoandw.v v4, v8, (a1), v4, v0.t +th.vamoandw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoandw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x64] -vamoandw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoandw.v x0, v8, (a1), v4, v0.t +th.vamoandw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoandw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x60] -vamoandd.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoandd.v v4, v8, (a1), v4, v0.t +th.vamoandd.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoandd.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x64] -vamoandd.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoandd.v x0, v8, (a1), v4, v0.t +th.vamoandd.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoandd.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x60] -vamoorw.v v4, v8, (a1), v4 -# CHECK-INST: vamoorw.v v4, v8, (a1), v4 +th.vamoorw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoorw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x46] -vamoorw.v zero, v8, (a1), v4 -# CHECK-INST: vamoorw.v x0, v8, (a1), v4 +th.vamoorw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoorw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x42] -vamoord.v v4, v8, (a1), v4 -# CHECK-INST: vamoord.v v4, v8, (a1), v4 +th.vamoord.v v4, v8, (a1), v4 +# CHECK-INST: th.vamoord.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x46] -vamoord.v zero, v8, (a1), v4 -# CHECK-INST: vamoord.v x0, v8, (a1), v4 +th.vamoord.v zero, v8, (a1), v4 +# CHECK-INST: th.vamoord.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x42] -vamoorw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoorw.v v4, v8, (a1), v4, v0.t +th.vamoorw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoorw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x44] -vamoorw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoorw.v x0, v8, (a1), v4, v0.t +th.vamoorw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoorw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x40] -vamoord.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamoord.v v4, v8, (a1), v4, v0.t +th.vamoord.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoord.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x44] -vamoord.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamoord.v x0, v8, (a1), v4, v0.t +th.vamoord.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamoord.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x40] -vamominw.v v4, v8, (a1), v4 -# CHECK-INST: vamominw.v v4, v8, (a1), v4 +th.vamominw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamominw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x86] -vamominw.v zero, v8, (a1), v4 -# CHECK-INST: vamominw.v x0, v8, (a1), v4 +th.vamominw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamominw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0x82] -vamomind.v v4, v8, (a1), v4 -# CHECK-INST: vamomind.v v4, v8, (a1), v4 +th.vamomind.v v4, v8, (a1), v4 +# CHECK-INST: th.vamomind.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x86] -vamomind.v zero, v8, (a1), v4 -# CHECK-INST: vamomind.v x0, v8, (a1), v4 +th.vamomind.v zero, v8, (a1), v4 +# CHECK-INST: th.vamomind.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0x82] -vamominw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamominw.v v4, v8, (a1), v4, v0.t +th.vamominw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamominw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x84] -vamominw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamominw.v x0, v8, (a1), v4, v0.t +th.vamominw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamominw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0x80] -vamomind.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamomind.v v4, v8, (a1), v4, v0.t +th.vamomind.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomind.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x84] -vamomind.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamomind.v x0, v8, (a1), v4, v0.t +th.vamomind.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomind.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0x80] -vamomaxw.v v4, v8, (a1), v4 -# CHECK-INST: vamomaxw.v v4, v8, (a1), v4 +th.vamomaxw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamomaxw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0xa6] -vamomaxw.v zero, v8, (a1), v4 -# CHECK-INST: vamomaxw.v x0, v8, (a1), v4 +th.vamomaxw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamomaxw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0xa2] -vamomaxd.v v4, v8, (a1), v4 -# CHECK-INST: vamomaxd.v v4, v8, (a1), v4 +th.vamomaxd.v v4, v8, (a1), v4 +# CHECK-INST: th.vamomaxd.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0xa6] -vamomaxd.v zero, v8, (a1), v4 -# CHECK-INST: vamomaxd.v x0, v8, (a1), v4 +th.vamomaxd.v zero, v8, (a1), v4 +# CHECK-INST: th.vamomaxd.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0xa2] -vamomaxw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxw.v v4, v8, (a1), v4, v0.t +th.vamomaxw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0xa4] -vamomaxw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxw.v x0, v8, (a1), v4, v0.t +th.vamomaxw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0xa0] -vamomaxd.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxd.v v4, v8, (a1), v4, v0.t +th.vamomaxd.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxd.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0xa4] -vamomaxd.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxd.v x0, v8, (a1), v4, v0.t +th.vamomaxd.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxd.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0xa0] -vamominuw.v v4, v8, (a1), v4 -# CHECK-INST: vamominuw.v v4, v8, (a1), v4 +th.vamominuw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamominuw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0xc6] -vamominuw.v zero, v8, (a1), v4 -# CHECK-INST: vamominuw.v x0, v8, (a1), v4 +th.vamominuw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamominuw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0xc2] -vamominud.v v4, v8, (a1), v4 -# CHECK-INST: vamominud.v v4, v8, (a1), v4 +th.vamominud.v v4, v8, (a1), v4 +# CHECK-INST: th.vamominud.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0xc6] -vamominud.v zero, v8, (a1), v4 -# CHECK-INST: vamominud.v x0, v8, (a1), v4 +th.vamominud.v zero, v8, (a1), v4 +# CHECK-INST: th.vamominud.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0xc2] -vamominuw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamominuw.v v4, v8, (a1), v4, v0.t +th.vamominuw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamominuw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0xc4] -vamominuw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamominuw.v x0, v8, (a1), v4, v0.t +th.vamominuw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamominuw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0xc0] -vamominud.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamominud.v v4, v8, (a1), v4, v0.t +th.vamominud.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamominud.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0xc4] -vamominud.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamominud.v x0, v8, (a1), v4, v0.t +th.vamominud.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamominud.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0xc0] -vamomaxuw.v v4, v8, (a1), v4 -# CHECK-INST: vamomaxuw.v v4, v8, (a1), v4 +th.vamomaxuw.v v4, v8, (a1), v4 +# CHECK-INST: th.vamomaxuw.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0xe6] -vamomaxuw.v zero, v8, (a1), v4 -# CHECK-INST: vamomaxuw.v x0, v8, (a1), v4 +th.vamomaxuw.v zero, v8, (a1), v4 +# CHECK-INST: th.vamomaxuw.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xe2,0x85,0xe2] -vamomaxud.v v4, v8, (a1), v4 -# CHECK-INST: vamomaxud.v v4, v8, (a1), v4 +th.vamomaxud.v v4, v8, (a1), v4 +# CHECK-INST: th.vamomaxud.v v4, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0xe6] -vamomaxud.v zero, v8, (a1), v4 -# CHECK-INST: vamomaxud.v x0, v8, (a1), v4 +th.vamomaxud.v zero, v8, (a1), v4 +# CHECK-INST: th.vamomaxud.v x0, v8, (a1), v4 # CHECK-ENCODING: [0x2f,0xf2,0x85,0xe2] -vamomaxuw.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxuw.v v4, v8, (a1), v4, v0.t +th.vamomaxuw.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxuw.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0xe4] -vamomaxuw.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxuw.v x0, v8, (a1), v4, v0.t +th.vamomaxuw.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxuw.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xe2,0x85,0xe0] -vamomaxud.v v4, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxud.v v4, v8, (a1), v4, v0.t +th.vamomaxud.v v4, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxud.v v4, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0xe4] -vamomaxud.v zero, v8, (a1), v4, v0.t -# CHECK-INST: vamomaxud.v x0, v8, (a1), v4, v0.t +th.vamomaxud.v zero, v8, (a1), v4, v0.t +# CHECK-INST: th.vamomaxud.v x0, v8, (a1), v4, v0.t # CHECK-ENCODING: [0x2f,0xf2,0x85,0xe0] -vadd.vv v4, v8, v12 -# CHECK-INST: vadd.vv v4, v8, v12 +th.vadd.vv v4, v8, v12 +# CHECK-INST: th.vadd.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x02] -vadd.vx v4, v8, a1 -# CHECK-INST: vadd.vx v4, v8, a1 +th.vadd.vx v4, v8, a1 +# CHECK-INST: th.vadd.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x02] -vadd.vi v4, v8, 15 -# CHECK-INST: vadd.vi v4, v8, 15 +th.vadd.vi v4, v8, 15 +# CHECK-INST: th.vadd.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x02] -vadd.vi v4, v8, -16 -# CHECK-INST: vadd.vi v4, v8, -16 +th.vadd.vi v4, v8, -16 +# CHECK-INST: th.vadd.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x02] -vadd.vv v4, v8, v12, v0.t -# CHECK-INST: vadd.vv v4, v8, v12, v0.t +th.vadd.vv v4, v8, v12, v0.t +# CHECK-INST: th.vadd.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x00] -vadd.vx v4, v8, a1, v0.t -# CHECK-INST: vadd.vx v4, v8, a1, v0.t +th.vadd.vx v4, v8, a1, v0.t +# CHECK-INST: th.vadd.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x00] -vadd.vi v4, v8, 15, v0.t -# CHECK-INST: vadd.vi v4, v8, 15, v0.t +th.vadd.vi v4, v8, 15, v0.t +# CHECK-INST: th.vadd.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x00] -vadd.vi v4, v8, -16, v0.t -# CHECK-INST: vadd.vi v4, v8, -16, v0.t +th.vadd.vi v4, v8, -16, v0.t +# CHECK-INST: th.vadd.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x00] -vsub.vv v4, v8, v12 -# CHECK-INST: vsub.vv v4, v8, v12 +th.vsub.vv v4, v8, v12 +# CHECK-INST: th.vsub.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x0a] -vsub.vx v4, v8, a1 -# CHECK-INST: vsub.vx v4, v8, a1 +th.vsub.vx v4, v8, a1 +# CHECK-INST: th.vsub.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x0a] -vrsub.vx v4, v8, a1 -# CHECK-INST: vrsub.vx v4, v8, a1 +th.vrsub.vx v4, v8, a1 +# CHECK-INST: th.vrsub.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x0e] -vrsub.vi v4, v8, 15 -# CHECK-INST: vrsub.vi v4, v8, 15 +th.vrsub.vi v4, v8, 15 +# CHECK-INST: th.vrsub.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x0e] -vrsub.vi v4, v8, -16 -# CHECK-INST: vrsub.vi v4, v8, -16 +th.vrsub.vi v4, v8, -16 +# CHECK-INST: th.vrsub.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x0e] -vsub.vv v4, v8, v12, v0.t -# CHECK-INST: vsub.vv v4, v8, v12, v0.t +th.vsub.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsub.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x08] -vsub.vx v4, v8, a1, v0.t -# CHECK-INST: vsub.vx v4, v8, a1, v0.t +th.vsub.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsub.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x08] -vrsub.vx v4, v8, a1, v0.t -# CHECK-INST: vrsub.vx v4, v8, a1, v0.t +th.vrsub.vx v4, v8, a1, v0.t +# CHECK-INST: th.vrsub.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x0c] -vrsub.vi v4, v8, 15, v0.t -# CHECK-INST: vrsub.vi v4, v8, 15, v0.t +th.vrsub.vi v4, v8, 15, v0.t +# CHECK-INST: th.vrsub.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x0c] -vrsub.vi v4, v8, -16, v0.t -# CHECK-INST: vrsub.vi v4, v8, -16, v0.t +th.vrsub.vi v4, v8, -16, v0.t +# CHECK-INST: th.vrsub.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x0c] -vwcvt.x.x.v v4, v8 -# CHECK-INST: vwcvt.x.x.v v4, v8 +th.vwcvt.x.x.v v4, v8 +# CHECK-INST: th.vwcvt.x.x.v v4, v8 # CHECK-ENCODING: [0x57,0x62,0x80,0xc6] -vwcvtu.x.x.v v4, v8 -# CHECK-INST: vwcvtu.x.x.v v4, v8 +th.vwcvtu.x.x.v v4, v8 +# CHECK-INST: th.vwcvtu.x.x.v v4, v8 # CHECK-ENCODING: [0x57,0x62,0x80,0xc2] -vwcvt.x.x.v v4, v8, v0.t -# CHECK-INST: vwcvt.x.x.v v4, v8, v0.t +th.vwcvt.x.x.v v4, v8, v0.t +# CHECK-INST: th.vwcvt.x.x.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x62,0x80,0xc4] -vwcvtu.x.x.v v4, v8, v0.t -# CHECK-INST: vwcvtu.x.x.v v4, v8, v0.t +th.vwcvtu.x.x.v v4, v8, v0.t +# CHECK-INST: th.vwcvtu.x.x.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x62,0x80,0xc0] -vwaddu.vv v4, v8, v12 -# CHECK-INST: vwaddu.vv v4, v8, v12 +th.vwaddu.vv v4, v8, v12 +# CHECK-INST: th.vwaddu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xc2] -vwaddu.vx v4, v8, a1 -# CHECK-INST: vwaddu.vx v4, v8, a1 +th.vwaddu.vx v4, v8, a1 +# CHECK-INST: th.vwaddu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xc2] -vwaddu.vv v4, v8, v12, v0.t -# CHECK-INST: vwaddu.vv v4, v8, v12, v0.t +th.vwaddu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwaddu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xc0] -vwaddu.vx v4, v8, a1, v0.t -# CHECK-INST: vwaddu.vx v4, v8, a1, v0.t +th.vwaddu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwaddu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xc0] -vwsubu.vv v4, v8, v12 -# CHECK-INST: vwsubu.vv v4, v8, v12 +th.vwsubu.vv v4, v8, v12 +# CHECK-INST: th.vwsubu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xca] -vwsubu.vx v4, v8, a1 -# CHECK-INST: vwsubu.vx v4, v8, a1 +th.vwsubu.vx v4, v8, a1 +# CHECK-INST: th.vwsubu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xca] -vwsubu.vv v4, v8, v12, v0.t -# CHECK-INST: vwsubu.vv v4, v8, v12, v0.t +th.vwsubu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwsubu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xc8] -vwsubu.vx v4, v8, a1, v0.t -# CHECK-INST: vwsubu.vx v4, v8, a1, v0.t +th.vwsubu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwsubu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xc8] -vwadd.vv v4, v8, v12 -# CHECK-INST: vwadd.vv v4, v8, v12 +th.vwadd.vv v4, v8, v12 +# CHECK-INST: th.vwadd.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xc6] -vwadd.vx v4, v8, a1 -# CHECK-INST: vwadd.vx v4, v8, a1 +th.vwadd.vx v4, v8, a1 +# CHECK-INST: th.vwadd.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xc6] -vwadd.vv v4, v8, v12, v0.t -# CHECK-INST: vwadd.vv v4, v8, v12, v0.t +th.vwadd.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwadd.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xc4] -vwadd.vx v4, v8, a1, v0.t -# CHECK-INST: vwadd.vx v4, v8, a1, v0.t +th.vwadd.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwadd.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xc4] -vwsub.vv v4, v8, v12 -# CHECK-INST: vwsub.vv v4, v8, v12 +th.vwsub.vv v4, v8, v12 +# CHECK-INST: th.vwsub.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xce] -vwsub.vx v4, v8, a1 -# CHECK-INST: vwsub.vx v4, v8, a1 +th.vwsub.vx v4, v8, a1 +# CHECK-INST: th.vwsub.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xce] -vwsub.vv v4, v8, v12, v0.t -# CHECK-INST: vwsub.vv v4, v8, v12, v0.t +th.vwsub.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwsub.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xcc] -vwsub.vx v4, v8, a1, v0.t -# CHECK-INST: vwsub.vx v4, v8, a1, v0.t +th.vwsub.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwsub.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xcc] -vwaddu.wv v4, v8, v12 -# CHECK-INST: vwaddu.wv v4, v8, v12 +th.vwaddu.wv v4, v8, v12 +# CHECK-INST: th.vwaddu.wv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xd2] -vwaddu.wx v4, v8, a1 -# CHECK-INST: vwaddu.wx v4, v8, a1 +th.vwaddu.wx v4, v8, a1 +# CHECK-INST: th.vwaddu.wx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xd2] -vwaddu.wv v4, v8, v12, v0.t -# CHECK-INST: vwaddu.wv v4, v8, v12, v0.t +th.vwaddu.wv v4, v8, v12, v0.t +# CHECK-INST: th.vwaddu.wv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xd0] -vwaddu.wx v4, v8, a1, v0.t -# CHECK-INST: vwaddu.wx v4, v8, a1, v0.t +th.vwaddu.wx v4, v8, a1, v0.t +# CHECK-INST: th.vwaddu.wx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xd0] -vwsubu.wv v4, v8, v12 -# CHECK-INST: vwsubu.wv v4, v8, v12 +th.vwsubu.wv v4, v8, v12 +# CHECK-INST: th.vwsubu.wv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xda] -vwsubu.wx v4, v8, a1 -# CHECK-INST: vwsubu.wx v4, v8, a1 +th.vwsubu.wx v4, v8, a1 +# CHECK-INST: th.vwsubu.wx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xda] -vwsubu.wv v4, v8, v12, v0.t -# CHECK-INST: vwsubu.wv v4, v8, v12, v0.t +th.vwsubu.wv v4, v8, v12, v0.t +# CHECK-INST: th.vwsubu.wv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xd8] -vwsubu.wx v4, v8, a1, v0.t -# CHECK-INST: vwsubu.wx v4, v8, a1, v0.t +th.vwsubu.wx v4, v8, a1, v0.t +# CHECK-INST: th.vwsubu.wx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xd8] -vwadd.wv v4, v8, v12 -# CHECK-INST: vwadd.wv v4, v8, v12 +th.vwadd.wv v4, v8, v12 +# CHECK-INST: th.vwadd.wv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xd6] -vwadd.wx v4, v8, a1 -# CHECK-INST: vwadd.wx v4, v8, a1 +th.vwadd.wx v4, v8, a1 +# CHECK-INST: th.vwadd.wx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xd6] -vwadd.wv v4, v8, v12, v0.t -# CHECK-INST: vwadd.wv v4, v8, v12, v0.t +th.vwadd.wv v4, v8, v12, v0.t +# CHECK-INST: th.vwadd.wv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xd4] -vwadd.wx v4, v8, a1, v0.t -# CHECK-INST: vwadd.wx v4, v8, a1, v0.t +th.vwadd.wx v4, v8, a1, v0.t +# CHECK-INST: th.vwadd.wx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xd4] -vwsub.wv v4, v8, v12 -# CHECK-INST: vwsub.wv v4, v8, v12 +th.vwsub.wv v4, v8, v12 +# CHECK-INST: th.vwsub.wv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xde] -vwsub.wx v4, v8, a1 -# CHECK-INST: vwsub.wx v4, v8, a1 +th.vwsub.wx v4, v8, a1 +# CHECK-INST: th.vwsub.wx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xde] -vwsub.wv v4, v8, v12, v0.t -# CHECK-INST: vwsub.wv v4, v8, v12, v0.t +th.vwsub.wv v4, v8, v12, v0.t +# CHECK-INST: th.vwsub.wv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xdc] -vwsub.wx v4, v8, a1, v0.t -# CHECK-INST: vwsub.wx v4, v8, a1, v0.t +th.vwsub.wx v4, v8, a1, v0.t +# CHECK-INST: th.vwsub.wx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xdc] -vadc.vvm v4, v8, v12, v0 -# CHECK-INST: vadc.vvm v4, v8, v12, v0 +th.vadc.vvm v4, v8, v12, v0 +# CHECK-INST: th.vadc.vvm v4, v8, v12, v0 # CHECK-ENCODING: [0x57,0x02,0x86,0x42] -vadc.vxm v4, v8, a1, v0 -# CHECK-INST: vadc.vxm v4, v8, a1, v0 +th.vadc.vxm v4, v8, a1, v0 +# CHECK-INST: th.vadc.vxm v4, v8, a1, v0 # CHECK-ENCODING: [0x57,0xc2,0x85,0x42] -vadc.vim v4, v8, 15, v0 -# CHECK-INST: vadc.vim v4, v8, 15, v0 +th.vadc.vim v4, v8, 15, v0 +# CHECK-INST: th.vadc.vim v4, v8, 15, v0 # CHECK-ENCODING: [0x57,0xb2,0x87,0x42] -vadc.vim v4, v8, -16, v0 -# CHECK-INST: vadc.vim v4, v8, -16, v0 +th.vadc.vim v4, v8, -16, v0 +# CHECK-INST: th.vadc.vim v4, v8, -16, v0 # CHECK-ENCODING: [0x57,0x32,0x88,0x42] -vmadc.vvm v4, v8, v12, v0 -# CHECK-INST: vmadc.vvm v4, v8, v12, v0 +th.vmadc.vvm v4, v8, v12, v0 +# CHECK-INST: th.vmadc.vvm v4, v8, v12, v0 # CHECK-ENCODING: [0x57,0x02,0x86,0x46] -vmadc.vxm v4, v8, a1, v0 -# CHECK-INST: vmadc.vxm v4, v8, a1, v0 +th.vmadc.vxm v4, v8, a1, v0 +# CHECK-INST: th.vmadc.vxm v4, v8, a1, v0 # CHECK-ENCODING: [0x57,0xc2,0x85,0x46] -vmadc.vim v4, v8, 15, v0 -# CHECK-INST: vmadc.vim v4, v8, 15, v0 +th.vmadc.vim v4, v8, 15, v0 +# CHECK-INST: th.vmadc.vim v4, v8, 15, v0 # CHECK-ENCODING: [0x57,0xb2,0x87,0x46] -vmadc.vim v4, v8, -16, v0 -# CHECK-INST: vmadc.vim v4, v8, -16, v0 +th.vmadc.vim v4, v8, -16, v0 +# CHECK-INST: th.vmadc.vim v4, v8, -16, v0 # CHECK-ENCODING: [0x57,0x32,0x88,0x46] -vsbc.vvm v4, v8, v12, v0 -# CHECK-INST: vsbc.vvm v4, v8, v12, v0 +th.vsbc.vvm v4, v8, v12, v0 +# CHECK-INST: th.vsbc.vvm v4, v8, v12, v0 # CHECK-ENCODING: [0x57,0x02,0x86,0x4a] -vsbc.vxm v4, v8, a1, v0 -# CHECK-INST: vsbc.vxm v4, v8, a1, v0 +th.vsbc.vxm v4, v8, a1, v0 +# CHECK-INST: th.vsbc.vxm v4, v8, a1, v0 # CHECK-ENCODING: [0x57,0xc2,0x85,0x4a] -vmsbc.vvm v4, v8, v12, v0 -# CHECK-INST: vmsbc.vvm v4, v8, v12, v0 +th.vmsbc.vvm v4, v8, v12, v0 +# CHECK-INST: th.vmsbc.vvm v4, v8, v12, v0 # CHECK-ENCODING: [0x57,0x02,0x86,0x4e] -vmsbc.vxm v4, v8, a1, v0 -# CHECK-INST: vmsbc.vxm v4, v8, a1, v0 +th.vmsbc.vxm v4, v8, a1, v0 +# CHECK-INST: th.vmsbc.vxm v4, v8, a1, v0 # CHECK-ENCODING: [0x57,0xc2,0x85,0x4e] -vnot.v v4, v8 -# CHECK-INST: vnot.v v4, v8 +th.vnot.v v4, v8 +# CHECK-INST: th.vnot.v v4, v8 # CHECK-ENCODING: [0x57,0xb2,0x8f,0x2e] -vnot.v v4, v8, v0.t -# CHECK-INST: vnot.v v4, v8, v0.t +th.vnot.v v4, v8, v0.t +# CHECK-INST: th.vnot.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0x2c] -vand.vv v4, v8, v12 -# CHECK-INST: vand.vv v4, v8, v12 +th.vand.vv v4, v8, v12 +# CHECK-INST: th.vand.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x26] -vand.vx v4, v8, a1 -# CHECK-INST: vand.vx v4, v8, a1 +th.vand.vx v4, v8, a1 +# CHECK-INST: th.vand.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x26] -vand.vi v4, v8, 15 -# CHECK-INST: vand.vi v4, v8, 15 +th.vand.vi v4, v8, 15 +# CHECK-INST: th.vand.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x26] -vand.vi v4, v8, -16 -# CHECK-INST: vand.vi v4, v8, -16 +th.vand.vi v4, v8, -16 +# CHECK-INST: th.vand.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x26] -vand.vv v4, v8, v12, v0.t -# CHECK-INST: vand.vv v4, v8, v12, v0.t +th.vand.vv v4, v8, v12, v0.t +# CHECK-INST: th.vand.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x24] -vand.vx v4, v8, a1, v0.t -# CHECK-INST: vand.vx v4, v8, a1, v0.t +th.vand.vx v4, v8, a1, v0.t +# CHECK-INST: th.vand.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x24] -vand.vi v4, v8, 15, v0.t -# CHECK-INST: vand.vi v4, v8, 15, v0.t +th.vand.vi v4, v8, 15, v0.t +# CHECK-INST: th.vand.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x24] -vand.vi v4, v8, -16, v0.t -# CHECK-INST: vand.vi v4, v8, -16, v0.t +th.vand.vi v4, v8, -16, v0.t +# CHECK-INST: th.vand.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x24] -vor.vv v4, v8, v12 -# CHECK-INST: vor.vv v4, v8, v12 +th.vor.vv v4, v8, v12 +# CHECK-INST: th.vor.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x2a] -vor.vx v4, v8, a1 -# CHECK-INST: vor.vx v4, v8, a1 +th.vor.vx v4, v8, a1 +# CHECK-INST: th.vor.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x2a] -vor.vi v4, v8, 15 -# CHECK-INST: vor.vi v4, v8, 15 +th.vor.vi v4, v8, 15 +# CHECK-INST: th.vor.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x2a] -vor.vi v4, v8, -16 -# CHECK-INST: vor.vi v4, v8, -16 +th.vor.vi v4, v8, -16 +# CHECK-INST: th.vor.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x2a] -vor.vv v4, v8, v12, v0.t -# CHECK-INST: vor.vv v4, v8, v12, v0.t +th.vor.vv v4, v8, v12, v0.t +# CHECK-INST: th.vor.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x28] -vor.vx v4, v8, a1, v0.t -# CHECK-INST: vor.vx v4, v8, a1, v0.t +th.vor.vx v4, v8, a1, v0.t +# CHECK-INST: th.vor.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x28] -vor.vi v4, v8, 15, v0.t -# CHECK-INST: vor.vi v4, v8, 15, v0.t +th.vor.vi v4, v8, 15, v0.t +# CHECK-INST: th.vor.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x28] -vor.vi v4, v8, -16, v0.t -# CHECK-INST: vor.vi v4, v8, -16, v0.t +th.vor.vi v4, v8, -16, v0.t +# CHECK-INST: th.vor.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x28] -vxor.vv v4, v8, v12 -# CHECK-INST: vxor.vv v4, v8, v12 +th.vxor.vv v4, v8, v12 +# CHECK-INST: th.vxor.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x2e] -vxor.vx v4, v8, a1 -# CHECK-INST: vxor.vx v4, v8, a1 +th.vxor.vx v4, v8, a1 +# CHECK-INST: th.vxor.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x2e] -vxor.vi v4, v8, 15 -# CHECK-INST: vxor.vi v4, v8, 15 +th.vxor.vi v4, v8, 15 +# CHECK-INST: th.vxor.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x2e] -vxor.vi v4, v8, -16 -# CHECK-INST: vxor.vi v4, v8, -16 +th.vxor.vi v4, v8, -16 +# CHECK-INST: th.vxor.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x2e] -vxor.vv v4, v8, v12, v0.t -# CHECK-INST: vxor.vv v4, v8, v12, v0.t +th.vxor.vv v4, v8, v12, v0.t +# CHECK-INST: th.vxor.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x2c] -vxor.vx v4, v8, a1, v0.t -# CHECK-INST: vxor.vx v4, v8, a1, v0.t +th.vxor.vx v4, v8, a1, v0.t +# CHECK-INST: th.vxor.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x2c] -vxor.vi v4, v8, 15, v0.t -# CHECK-INST: vxor.vi v4, v8, 15, v0.t +th.vxor.vi v4, v8, 15, v0.t +# CHECK-INST: th.vxor.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x2c] -vxor.vi v4, v8, -16, v0.t -# CHECK-INST: vxor.vi v4, v8, -16, v0.t +th.vxor.vi v4, v8, -16, v0.t +# CHECK-INST: th.vxor.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x2c] -vsll.vv v4, v8, v12 -# CHECK-INST: vsll.vv v4, v8, v12 +th.vsll.vv v4, v8, v12 +# CHECK-INST: th.vsll.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x96] -vsll.vx v4, v8, a1 -# CHECK-INST: vsll.vx v4, v8, a1 +th.vsll.vx v4, v8, a1 +# CHECK-INST: th.vsll.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x96] -vsll.vi v4, v8, 1 -# CHECK-INST: vsll.vi v4, v8, 1 +th.vsll.vi v4, v8, 1 +# CHECK-INST: th.vsll.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0x96] -vsll.vi v4, v8, 31 -# CHECK-INST: vsll.vi v4, v8, 31 +th.vsll.vi v4, v8, 31 +# CHECK-INST: th.vsll.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0x96] -vsll.vv v4, v8, v12, v0.t -# CHECK-INST: vsll.vv v4, v8, v12, v0.t +th.vsll.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsll.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x94] -vsll.vx v4, v8, a1, v0.t -# CHECK-INST: vsll.vx v4, v8, a1, v0.t +th.vsll.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsll.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x94] -vsll.vi v4, v8, 1, v0.t -# CHECK-INST: vsll.vi v4, v8, 1, v0.t +th.vsll.vi v4, v8, 1, v0.t +# CHECK-INST: th.vsll.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0x94] -vsll.vi v4, v8, 31, v0.t -# CHECK-INST: vsll.vi v4, v8, 31, v0.t +th.vsll.vi v4, v8, 31, v0.t +# CHECK-INST: th.vsll.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0x94] -vsrl.vv v4, v8, v12 -# CHECK-INST: vsrl.vv v4, v8, v12 +th.vsrl.vv v4, v8, v12 +# CHECK-INST: th.vsrl.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xa2] -vsrl.vx v4, v8, a1 -# CHECK-INST: vsrl.vx v4, v8, a1 +th.vsrl.vx v4, v8, a1 +# CHECK-INST: th.vsrl.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xa2] -vsrl.vi v4, v8, 1 -# CHECK-INST: vsrl.vi v4, v8, 1 +th.vsrl.vi v4, v8, 1 +# CHECK-INST: th.vsrl.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xa2] -vsrl.vi v4, v8, 31 -# CHECK-INST: vsrl.vi v4, v8, 31 +th.vsrl.vi v4, v8, 31 +# CHECK-INST: th.vsrl.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xa2] -vsrl.vv v4, v8, v12, v0.t -# CHECK-INST: vsrl.vv v4, v8, v12, v0.t +th.vsrl.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsrl.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xa0] -vsrl.vx v4, v8, a1, v0.t -# CHECK-INST: vsrl.vx v4, v8, a1, v0.t +th.vsrl.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsrl.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xa0] -vsrl.vi v4, v8, 1, v0.t -# CHECK-INST: vsrl.vi v4, v8, 1, v0.t +th.vsrl.vi v4, v8, 1, v0.t +# CHECK-INST: th.vsrl.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xa0] -vsrl.vi v4, v8, 31, v0.t -# CHECK-INST: vsrl.vi v4, v8, 31, v0.t +th.vsrl.vi v4, v8, 31, v0.t +# CHECK-INST: th.vsrl.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xa0] -vsra.vv v4, v8, v12 -# CHECK-INST: vsra.vv v4, v8, v12 +th.vsra.vv v4, v8, v12 +# CHECK-INST: th.vsra.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xa6] -vsra.vx v4, v8, a1 -# CHECK-INST: vsra.vx v4, v8, a1 +th.vsra.vx v4, v8, a1 +# CHECK-INST: th.vsra.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xa6] -vsra.vi v4, v8, 1 -# CHECK-INST: vsra.vi v4, v8, 1 +th.vsra.vi v4, v8, 1 +# CHECK-INST: th.vsra.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xa6] -vsra.vi v4, v8, 31 -# CHECK-INST: vsra.vi v4, v8, 31 +th.vsra.vi v4, v8, 31 +# CHECK-INST: th.vsra.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xa6] -vsra.vv v4, v8, v12, v0.t -# CHECK-INST: vsra.vv v4, v8, v12, v0.t +th.vsra.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsra.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xa4] -vsra.vx v4, v8, a1, v0.t -# CHECK-INST: vsra.vx v4, v8, a1, v0.t +th.vsra.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsra.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xa4] -vsra.vi v4, v8, 1, v0.t -# CHECK-INST: vsra.vi v4, v8, 1, v0.t +th.vsra.vi v4, v8, 1, v0.t +# CHECK-INST: th.vsra.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xa4] -vsra.vi v4, v8, 31, v0.t -# CHECK-INST: vsra.vi v4, v8, 31, v0.t +th.vsra.vi v4, v8, 31, v0.t +# CHECK-INST: th.vsra.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xa4] -vnsrl.vv v4, v8, v12 -# CHECK-INST: vnsrl.vv v4, v8, v12 +th.vnsrl.vv v4, v8, v12 +# CHECK-INST: th.vnsrl.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xb2] -vnsrl.vx v4, v8, a1 -# CHECK-INST: vnsrl.vx v4, v8, a1 +th.vnsrl.vx v4, v8, a1 +# CHECK-INST: th.vnsrl.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xb2] -vnsrl.vi v4, v8, 1 -# CHECK-INST: vnsrl.vi v4, v8, 1 +th.vnsrl.vi v4, v8, 1 +# CHECK-INST: th.vnsrl.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xb2] -vnsrl.vi v4, v8, 31 -# CHECK-INST: vnsrl.vi v4, v8, 31 +th.vnsrl.vi v4, v8, 31 +# CHECK-INST: th.vnsrl.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xb2] -vnsrl.vv v4, v8, v12, v0.t -# CHECK-INST: vnsrl.vv v4, v8, v12, v0.t +th.vnsrl.vv v4, v8, v12, v0.t +# CHECK-INST: th.vnsrl.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xb0] -vnsrl.vx v4, v8, a1, v0.t -# CHECK-INST: vnsrl.vx v4, v8, a1, v0.t +th.vnsrl.vx v4, v8, a1, v0.t +# CHECK-INST: th.vnsrl.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xb0] -vnsrl.vi v4, v8, 1, v0.t -# CHECK-INST: vnsrl.vi v4, v8, 1, v0.t +th.vnsrl.vi v4, v8, 1, v0.t +# CHECK-INST: th.vnsrl.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xb0] -vnsrl.vi v4, v8, 31, v0.t -# CHECK-INST: vnsrl.vi v4, v8, 31, v0.t +th.vnsrl.vi v4, v8, 31, v0.t +# CHECK-INST: th.vnsrl.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xb0] -vnsra.vv v4, v8, v12 -# CHECK-INST: vnsra.vv v4, v8, v12 +th.vnsra.vv v4, v8, v12 +# CHECK-INST: th.vnsra.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xb6] -vnsra.vx v4, v8, a1 -# CHECK-INST: vnsra.vx v4, v8, a1 +th.vnsra.vx v4, v8, a1 +# CHECK-INST: th.vnsra.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xb6] -vnsra.vi v4, v8, 1 -# CHECK-INST: vnsra.vi v4, v8, 1 +th.vnsra.vi v4, v8, 1 +# CHECK-INST: th.vnsra.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xb6] -vnsra.vi v4, v8, 31 -# CHECK-INST: vnsra.vi v4, v8, 31 +th.vnsra.vi v4, v8, 31 +# CHECK-INST: th.vnsra.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xb6] -vnsra.vv v4, v8, v12, v0.t -# CHECK-INST: vnsra.vv v4, v8, v12, v0.t +th.vnsra.vv v4, v8, v12, v0.t +# CHECK-INST: th.vnsra.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xb4] -vnsra.vx v4, v8, a1, v0.t -# CHECK-INST: vnsra.vx v4, v8, a1, v0.t +th.vnsra.vx v4, v8, a1, v0.t +# CHECK-INST: th.vnsra.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xb4] -vnsra.vi v4, v8, 1, v0.t -# CHECK-INST: vnsra.vi v4, v8, 1, v0.t +th.vnsra.vi v4, v8, 1, v0.t +# CHECK-INST: th.vnsra.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xb4] -vnsra.vi v4, v8, 31, v0.t -# CHECK-INST: vnsra.vi v4, v8, 31, v0.t +th.vnsra.vi v4, v8, 31, v0.t +# CHECK-INST: th.vnsra.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xb4] -vmsgt.vv v4, v8, v12 -# CHECK-INST: vmslt.vv v4, v12, v8 +th.vmsgt.vv v4, v8, v12 +# CHECK-INST: th.vmslt.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0xc4,0x6e] -vmsgtu.vv v4, v8, v12 -# CHECK-INST: vmsltu.vv v4, v12, v8 +th.vmsgtu.vv v4, v8, v12 +# CHECK-INST: th.vmsltu.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0xc4,0x6a] -vmsge.vv v4, v8, v12 -# CHECK-INST: vmsle.vv v4, v12, v8 +th.vmsge.vv v4, v8, v12 +# CHECK-INST: th.vmsle.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0xc4,0x76] -vmsgeu.vv v4, v8, v12 -# CHECK-INST: vmsleu.vv v4, v12, v8 +th.vmsgeu.vv v4, v8, v12 +# CHECK-INST: th.vmsleu.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0xc4,0x72] -vmsgt.vv v4, v8, v12, v0.t -# CHECK-INST: vmslt.vv v4, v12, v8, v0.t +th.vmsgt.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmslt.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0xc4,0x6c] -vmsgtu.vv v4, v8, v12, v0.t -# CHECK-INST: vmsltu.vv v4, v12, v8, v0.t +th.vmsgtu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsltu.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0xc4,0x68] -vmsge.vv v4, v8, v12, v0.t -# CHECK-INST: vmsle.vv v4, v12, v8, v0.t +th.vmsge.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsle.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0xc4,0x74] -vmsgeu.vv v4, v8, v12, v0.t -# CHECK-INST: vmsleu.vv v4, v12, v8, v0.t +th.vmsgeu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsleu.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0xc4,0x70] -vmsge.vx v4, v8, a1 -# CHECK-INST: vmslt.vx v4, v8, a1 +th.vmsge.vx v4, v8, a1 +# CHECK-INST: th.vmslt.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x6e] -# CHECK-INST: vmnot.m v4, v4 +# CHECK-INST: th.vmnot.m v4, v4 # CHECK-ENCODING: [0x57,0x22,0x42,0x76] -vmsgeu.vx v4, v8, a1 -# CHECK-INST: vmsltu.vx v4, v8, a1 +th.vmsgeu.vx v4, v8, a1 +# CHECK-INST: th.vmsltu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x6a] -# CHECK-INST: vmnot.m v4, v4 +# CHECK-INST: th.vmnot.m v4, v4 # CHECK-ENCODING: [0x57,0x22,0x42,0x76] -vmsge.vx v8, v12, a2, v0.t -# CHECK-INST: vmslt.vx v8, v12, a2, v0.t +th.vmsge.vx v8, v12, a2, v0.t +# CHECK-INST: th.vmslt.vx v8, v12, a2, v0.t # CHECK-ENCODING: [0x57,0x44,0xc6,0x6c] -# CHECK-INST: vmxor.mm v8, v8, v0 +# CHECK-INST: th.vmxor.mm v8, v8, v0 # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] -vmsgeu.vx v8, v12, a2, v0.t -# CHECK-INST: vmsltu.vx v8, v12, a2, v0.t +th.vmsgeu.vx v8, v12, a2, v0.t +# CHECK-INST: th.vmsltu.vx v8, v12, a2, v0.t # CHECK-ENCODING: [0x57,0x44,0xc6,0x68] -# CHECK-INST: vmxor.mm v8, v8, v0 +# CHECK-INST: th.vmxor.mm v8, v8, v0 # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] -vmsge.vx v4, v8, a1, v0.t, v12 -# CHECK-INST: vmslt.vx v12, v8, a1 +th.vmsge.vx v4, v8, a1, v0.t, v12 +# CHECK-INST: th.vmslt.vx v12, v8, a1 # TODO: GCC produces vmslt.vx v12, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc6,0x85,0x6e] -# CHECK-INST: vmandnot.mm v4, v4, v12 +# CHECK-INST: th.vmandnot.mm v4, v4, v12 # CHECK-ENCODING: [0x57,0x22,0x46,0x62] -vmsgeu.vx v4, v8, a1, v0.t, v12 -# CHECK-INST: vmsltu.vx v12, v8, a1 +th.vmsgeu.vx v4, v8, a1, v0.t, v12 +# CHECK-INST: th.vmsltu.vx v12, v8, a1 # TODO: GCC produces vmsltu.vx v12, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc6,0x85,0x6a] -# CHECK-INST: vmandnot.mm v4, v4, v12 +# CHECK-INST: th.vmandnot.mm v4, v4, v12 # CHECK-ENCODING: [0x57,0x22,0x46,0x62] -vmslt.vi v4, v8, 16 -# CHECK-INST: vmsle.vi v4, v8, 15 +th.vmslt.vi v4, v8, 16 +# CHECK-INST: th.vmsle.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x76] -vmslt.vi v4, v8, -15 -# CHECK-INST: vmsle.vi v4, v8, -16 +th.vmslt.vi v4, v8, -15 +# CHECK-INST: th.vmsle.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x76] -vmsltu.vi v4, v8, 16 -# CHECK-INST: vmsleu.vi v4, v8, 15 +th.vmsltu.vi v4, v8, 16 +# CHECK-INST: th.vmsleu.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x72] -vmsltu.vi v4, v8, -15 -# CHECK-INST: vmsleu.vi v4, v8, -16 +th.vmsltu.vi v4, v8, -15 +# CHECK-INST: th.vmsleu.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x72] -vmsge.vi v4, v8, 16 -# CHECK-INST: vmsgt.vi v4, v8, 15 +th.vmsge.vi v4, v8, 16 +# CHECK-INST: th.vmsgt.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x7e] -vmsge.vi v4, v8, -15 -# CHECK-INST: vmsgt.vi v4, v8, -16 +th.vmsge.vi v4, v8, -15 +# CHECK-INST: th.vmsgt.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x7e] -vmsgeu.vi v4, v8, 16 -# CHECK-INST: vmsgtu.vi v4, v8, 15 +th.vmsgeu.vi v4, v8, 16 +# CHECK-INST: th.vmsgtu.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x7a] -vmsgeu.vi v4, v8, -15 -# CHECK-INST: vmsgtu.vi v4, v8, -16 +th.vmsgeu.vi v4, v8, -15 +# CHECK-INST: th.vmsgtu.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x7a] -vmslt.vi v4, v8, 16, v0.t -# CHECK-INST: vmsle.vi v4, v8, 15, v0.t +th.vmslt.vi v4, v8, 16, v0.t +# CHECK-INST: th.vmsle.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x74] -vmslt.vi v4, v8, -15, v0.t -# CHECK-INST: vmsle.vi v4, v8, -16, v0.t +th.vmslt.vi v4, v8, -15, v0.t +# CHECK-INST: th.vmsle.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x74] -vmsltu.vi v4, v8, 16, v0.t -# CHECK-INST: vmsleu.vi v4, v8, 15, v0.t +th.vmsltu.vi v4, v8, 16, v0.t +# CHECK-INST: th.vmsleu.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x70] -vmsltu.vi v4, v8, -15, v0.t -# CHECK-INST: vmsleu.vi v4, v8, -16, v0.t +th.vmsltu.vi v4, v8, -15, v0.t +# CHECK-INST: th.vmsleu.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x70] -vmsge.vi v4, v8, 16, v0.t -# CHECK-INST: vmsgt.vi v4, v8, 15, v0.t +th.vmsge.vi v4, v8, 16, v0.t +# CHECK-INST: th.vmsgt.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x7c] -vmsge.vi v4, v8, -15, v0.t -# CHECK-INST: vmsgt.vi v4, v8, -16, v0.t +th.vmsge.vi v4, v8, -15, v0.t +# CHECK-INST: th.vmsgt.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x7c] -vmsgeu.vi v4, v8, 16, v0.t -# CHECK-INST: vmsgtu.vi v4, v8, 15, v0.t +th.vmsgeu.vi v4, v8, 16, v0.t +# CHECK-INST: th.vmsgtu.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x78] -vmsgeu.vi v4, v8, -15, v0.t -# CHECK-INST: vmsgtu.vi v4, v8, -16, v0.t +th.vmsgeu.vi v4, v8, -15, v0.t +# CHECK-INST: th.vmsgtu.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x78] -vmseq.vv v4, v8, v12 -# CHECK-INST: vmseq.vv v4, v8, v12 +th.vmseq.vv v4, v8, v12 +# CHECK-INST: th.vmseq.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x62] -vmseq.vx v4, v8, a1 -# CHECK-INST: vmseq.vx v4, v8, a1 +th.vmseq.vx v4, v8, a1 +# CHECK-INST: th.vmseq.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x62] -vmseq.vi v4, v8, 15 -# CHECK-INST: vmseq.vi v4, v8, 15 +th.vmseq.vi v4, v8, 15 +# CHECK-INST: th.vmseq.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x62] -vmseq.vi v4, v8, -16 -# CHECK-INST: vmseq.vi v4, v8, -16 +th.vmseq.vi v4, v8, -16 +# CHECK-INST: th.vmseq.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x62] -vmseq.vv v4, v8, v12, v0.t -# CHECK-INST: vmseq.vv v4, v8, v12, v0.t +th.vmseq.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmseq.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x60] -vmseq.vx v4, v8, a1, v0.t -# CHECK-INST: vmseq.vx v4, v8, a1, v0.t +th.vmseq.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmseq.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x60] -vmseq.vi v4, v8, 15, v0.t -# CHECK-INST: vmseq.vi v4, v8, 15, v0.t +th.vmseq.vi v4, v8, 15, v0.t +# CHECK-INST: th.vmseq.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x60] -vmseq.vi v4, v8, -16, v0.t -# CHECK-INST: vmseq.vi v4, v8, -16, v0.t +th.vmseq.vi v4, v8, -16, v0.t +# CHECK-INST: th.vmseq.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x60] -vmsne.vv v4, v8, v12 -# CHECK-INST: vmsne.vv v4, v8, v12 +th.vmsne.vv v4, v8, v12 +# CHECK-INST: th.vmsne.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x66] -vmsne.vx v4, v8, a1 -# CHECK-INST: vmsne.vx v4, v8, a1 +th.vmsne.vx v4, v8, a1 +# CHECK-INST: th.vmsne.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x66] -vmsne.vi v4, v8, 15 -# CHECK-INST: vmsne.vi v4, v8, 15 +th.vmsne.vi v4, v8, 15 +# CHECK-INST: th.vmsne.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x66] -vmsne.vi v4, v8, -16 -# CHECK-INST: vmsne.vi v4, v8, -16 +th.vmsne.vi v4, v8, -16 +# CHECK-INST: th.vmsne.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x66] -vmsne.vv v4, v8, v12, v0.t -# CHECK-INST: vmsne.vv v4, v8, v12, v0.t +th.vmsne.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsne.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x64] -vmsne.vx v4, v8, a1, v0.t -# CHECK-INST: vmsne.vx v4, v8, a1, v0.t +th.vmsne.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmsne.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x64] -vmsne.vi v4, v8, 15, v0.t -# CHECK-INST: vmsne.vi v4, v8, 15, v0.t +th.vmsne.vi v4, v8, 15, v0.t +# CHECK-INST: th.vmsne.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x64] -vmsne.vi v4, v8, -16, v0.t -# CHECK-INST: vmsne.vi v4, v8, -16, v0.t +th.vmsne.vi v4, v8, -16, v0.t +# CHECK-INST: th.vmsne.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x64] -vmsltu.vv v4, v8, v12 -# CHECK-INST: vmsltu.vv v4, v8, v12 +th.vmsltu.vv v4, v8, v12 +# CHECK-INST: th.vmsltu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x6a] -vmsltu.vx v4, v8, a1 -# CHECK-INST: vmsltu.vx v4, v8, a1 +th.vmsltu.vx v4, v8, a1 +# CHECK-INST: th.vmsltu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x6a] -vmsltu.vv v4, v8, v12, v0.t -# CHECK-INST: vmsltu.vv v4, v8, v12, v0.t +th.vmsltu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsltu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x68] -vmsltu.vx v4, v8, a1, v0.t -# CHECK-INST: vmsltu.vx v4, v8, a1, v0.t +th.vmsltu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmsltu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x68] -vmslt.vv v4, v8, v12 -# CHECK-INST: vmslt.vv v4, v8, v12 +th.vmslt.vv v4, v8, v12 +# CHECK-INST: th.vmslt.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x6e] -vmslt.vx v4, v8, a1 -# CHECK-INST: vmslt.vx v4, v8, a1 +th.vmslt.vx v4, v8, a1 +# CHECK-INST: th.vmslt.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x6e] -vmslt.vv v4, v8, v12, v0.t -# CHECK-INST: vmslt.vv v4, v8, v12, v0.t +th.vmslt.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmslt.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x6c] -vmslt.vx v4, v8, a1, v0.t -# CHECK-INST: vmslt.vx v4, v8, a1, v0.t +th.vmslt.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmslt.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x6c] -vmsleu.vv v4, v8, v12 -# CHECK-INST: vmsleu.vv v4, v8, v12 +th.vmsleu.vv v4, v8, v12 +# CHECK-INST: th.vmsleu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x72] -vmsleu.vx v4, v8, a1 -# CHECK-INST: vmsleu.vx v4, v8, a1 +th.vmsleu.vx v4, v8, a1 +# CHECK-INST: th.vmsleu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x72] -vmsleu.vi v4, v8, 15 -# CHECK-INST: vmsleu.vi v4, v8, 15 +th.vmsleu.vi v4, v8, 15 +# CHECK-INST: th.vmsleu.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x72] -vmsleu.vi v4, v8, -16 -# CHECK-INST: vmsleu.vi v4, v8, -16 +th.vmsleu.vi v4, v8, -16 +# CHECK-INST: th.vmsleu.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x72] -vmsleu.vv v4, v8, v12, v0.t -# CHECK-INST: vmsleu.vv v4, v8, v12, v0.t +th.vmsleu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsleu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x70] -vmsleu.vx v4, v8, a1, v0.t -# CHECK-INST: vmsleu.vx v4, v8, a1, v0.t +th.vmsleu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmsleu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x70] -vmsleu.vi v4, v8, 15, v0.t -# CHECK-INST: vmsleu.vi v4, v8, 15, v0.t +th.vmsleu.vi v4, v8, 15, v0.t +# CHECK-INST: th.vmsleu.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x70] -vmsleu.vi v4, v8, -16, v0.t -# CHECK-INST: vmsleu.vi v4, v8, -16, v0.t +th.vmsleu.vi v4, v8, -16, v0.t +# CHECK-INST: th.vmsleu.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x70] -vmsle.vv v4, v8, v12 -# CHECK-INST: vmsle.vv v4, v8, v12 +th.vmsle.vv v4, v8, v12 +# CHECK-INST: th.vmsle.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x76] -vmsle.vx v4, v8, a1 -# CHECK-INST: vmsle.vx v4, v8, a1 +th.vmsle.vx v4, v8, a1 +# CHECK-INST: th.vmsle.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x76] -vmsle.vi v4, v8, 15 -# CHECK-INST: vmsle.vi v4, v8, 15 +th.vmsle.vi v4, v8, 15 +# CHECK-INST: th.vmsle.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x76] -vmsle.vi v4, v8, -16 -# CHECK-INST: vmsle.vi v4, v8, -16 +th.vmsle.vi v4, v8, -16 +# CHECK-INST: th.vmsle.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x76] -vmsle.vv v4, v8, v12, v0.t -# CHECK-INST: vmsle.vv v4, v8, v12, v0.t +th.vmsle.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmsle.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x74] -vmsle.vx v4, v8, a1, v0.t -# CHECK-INST: vmsle.vx v4, v8, a1, v0.t +th.vmsle.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmsle.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x74] -vmsle.vi v4, v8, 15, v0.t -# CHECK-INST: vmsle.vi v4, v8, 15, v0.t +th.vmsle.vi v4, v8, 15, v0.t +# CHECK-INST: th.vmsle.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x74] -vmsle.vi v4, v8, -16, v0.t -# CHECK-INST: vmsle.vi v4, v8, -16, v0.t +th.vmsle.vi v4, v8, -16, v0.t +# CHECK-INST: th.vmsle.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x74] -vmsgtu.vx v4, v8, a1 -# CHECK-INST: vmsgtu.vx v4, v8, a1 +th.vmsgtu.vx v4, v8, a1 +# CHECK-INST: th.vmsgtu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x7a] -vmsgtu.vi v4, v8, 15 -# CHECK-INST: vmsgtu.vi v4, v8, 15 +th.vmsgtu.vi v4, v8, 15 +# CHECK-INST: th.vmsgtu.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x7a] -vmsgtu.vi v4, v8, -16 -# CHECK-INST: vmsgtu.vi v4, v8, -16 +th.vmsgtu.vi v4, v8, -16 +# CHECK-INST: th.vmsgtu.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x7a] -vmsgtu.vx v4, v8, a1, v0.t -# CHECK-INST: vmsgtu.vx v4, v8, a1, v0.t +th.vmsgtu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmsgtu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x78] -vmsgtu.vi v4, v8, 15, v0.t -# CHECK-INST: vmsgtu.vi v4, v8, 15, v0.t +th.vmsgtu.vi v4, v8, 15, v0.t +# CHECK-INST: th.vmsgtu.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x78] -vmsgtu.vi v4, v8, -16, v0.t -# CHECK-INST: vmsgtu.vi v4, v8, -16, v0.t +th.vmsgtu.vi v4, v8, -16, v0.t +# CHECK-INST: th.vmsgtu.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x78] -vmsgt.vx v4, v8, a1 -# CHECK-INST: vmsgt.vx v4, v8, a1 +th.vmsgt.vx v4, v8, a1 +# CHECK-INST: th.vmsgt.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x7e] -vmsgt.vi v4, v8, 15 -# CHECK-INST: vmsgt.vi v4, v8, 15 +th.vmsgt.vi v4, v8, 15 +# CHECK-INST: th.vmsgt.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x7e] -vmsgt.vi v4, v8, -16 -# CHECK-INST: vmsgt.vi v4, v8, -16 +th.vmsgt.vi v4, v8, -16 +# CHECK-INST: th.vmsgt.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x7e] -vmsgt.vx v4, v8, a1, v0.t -# CHECK-INST: vmsgt.vx v4, v8, a1, v0.t +th.vmsgt.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmsgt.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x7c] -vmsgt.vi v4, v8, 15, v0.t -# CHECK-INST: vmsgt.vi v4, v8, 15, v0.t +th.vmsgt.vi v4, v8, 15, v0.t +# CHECK-INST: th.vmsgt.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x7c] -vmsgt.vi v4, v8, -16, v0.t -# CHECK-INST: vmsgt.vi v4, v8, -16, v0.t +th.vmsgt.vi v4, v8, -16, v0.t +# CHECK-INST: th.vmsgt.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x7c] -vminu.vv v4, v8, v12 -# CHECK-INST: vminu.vv v4, v8, v12 +th.vminu.vv v4, v8, v12 +# CHECK-INST: th.vminu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x12] -vminu.vx v4, v8, a1 -# CHECK-INST: vminu.vx v4, v8, a1 +th.vminu.vx v4, v8, a1 +# CHECK-INST: th.vminu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x12] -vminu.vv v4, v8, v12, v0.t -# CHECK-INST: vminu.vv v4, v8, v12, v0.t +th.vminu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vminu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x10] -vminu.vx v4, v8, a1, v0.t -# CHECK-INST: vminu.vx v4, v8, a1, v0.t +th.vminu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vminu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x10] -vmin.vv v4, v8, v12 -# CHECK-INST: vmin.vv v4, v8, v12 +th.vmin.vv v4, v8, v12 +# CHECK-INST: th.vmin.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x16] -vmin.vx v4, v8, a1 -# CHECK-INST: vmin.vx v4, v8, a1 +th.vmin.vx v4, v8, a1 +# CHECK-INST: th.vmin.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x16] -vmin.vv v4, v8, v12, v0.t -# CHECK-INST: vmin.vv v4, v8, v12, v0.t +th.vmin.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmin.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x14] -vmin.vx v4, v8, a1, v0.t -# CHECK-INST: vmin.vx v4, v8, a1, v0.t +th.vmin.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmin.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x14] -vmaxu.vv v4, v8, v12 -# CHECK-INST: vmaxu.vv v4, v8, v12 +th.vmaxu.vv v4, v8, v12 +# CHECK-INST: th.vmaxu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x1a] -vmaxu.vx v4, v8, a1 -# CHECK-INST: vmaxu.vx v4, v8, a1 +th.vmaxu.vx v4, v8, a1 +# CHECK-INST: th.vmaxu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x1a] -vmaxu.vv v4, v8, v12, v0.t -# CHECK-INST: vmaxu.vv v4, v8, v12, v0.t +th.vmaxu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmaxu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x18] -vmaxu.vx v4, v8, a1, v0.t -# CHECK-INST: vmaxu.vx v4, v8, a1, v0.t +th.vmaxu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmaxu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x18] -vmax.vv v4, v8, v12 -# CHECK-INST: vmax.vv v4, v8, v12 +th.vmax.vv v4, v8, v12 +# CHECK-INST: th.vmax.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x1e] -vmax.vx v4, v8, a1 -# CHECK-INST: vmax.vx v4, v8, a1 +th.vmax.vx v4, v8, a1 +# CHECK-INST: th.vmax.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x1e] -vmax.vv v4, v8, v12, v0.t -# CHECK-INST: vmax.vv v4, v8, v12, v0.t +th.vmax.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmax.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x1c] -vmax.vx v4, v8, a1, v0.t -# CHECK-INST: vmax.vx v4, v8, a1, v0.t +th.vmax.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmax.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x1c] -vmul.vv v4, v8, v12 -# CHECK-INST: vmul.vv v4, v8, v12 +th.vmul.vv v4, v8, v12 +# CHECK-INST: th.vmul.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x96] -vmul.vx v4, v8, a1 -# CHECK-INST: vmul.vx v4, v8, a1 +th.vmul.vx v4, v8, a1 +# CHECK-INST: th.vmul.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x96] -vmul.vv v4, v8, v12, v0.t -# CHECK-INST: vmul.vv v4, v8, v12, v0.t +th.vmul.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmul.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x94] -vmul.vx v4, v8, a1, v0.t -# CHECK-INST: vmul.vx v4, v8, a1, v0.t +th.vmul.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmul.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x94] -vmulh.vv v4, v8, v12 -# CHECK-INST: vmulh.vv v4, v8, v12 +th.vmulh.vv v4, v8, v12 +# CHECK-INST: th.vmulh.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x9e] -vmulh.vx v4, v8, a1 -# CHECK-INST: vmulh.vx v4, v8, a1 +th.vmulh.vx v4, v8, a1 +# CHECK-INST: th.vmulh.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x9e] -vmulh.vv v4, v8, v12, v0.t -# CHECK-INST: vmulh.vv v4, v8, v12, v0.t +th.vmulh.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmulh.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x9c] -vmulh.vx v4, v8, a1, v0.t -# CHECK-INST: vmulh.vx v4, v8, a1, v0.t +th.vmulh.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmulh.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x9c] -vmulhu.vv v4, v8, v12 -# CHECK-INST: vmulhu.vv v4, v8, v12 +th.vmulhu.vv v4, v8, v12 +# CHECK-INST: th.vmulhu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x92] -vmulhu.vx v4, v8, a1 -# CHECK-INST: vmulhu.vx v4, v8, a1 +th.vmulhu.vx v4, v8, a1 +# CHECK-INST: th.vmulhu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x92] -vmulhu.vv v4, v8, v12, v0.t -# CHECK-INST: vmulhu.vv v4, v8, v12, v0.t +th.vmulhu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmulhu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x90] -vmulhu.vx v4, v8, a1, v0.t -# CHECK-INST: vmulhu.vx v4, v8, a1, v0.t +th.vmulhu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmulhu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x90] -vmulhsu.vv v4, v8, v12 -# CHECK-INST: vmulhsu.vv v4, v8, v12 +th.vmulhsu.vv v4, v8, v12 +# CHECK-INST: th.vmulhsu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x9a] -vmulhsu.vx v4, v8, a1 -# CHECK-INST: vmulhsu.vx v4, v8, a1 +th.vmulhsu.vx v4, v8, a1 +# CHECK-INST: th.vmulhsu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x9a] -vmulhsu.vv v4, v8, v12, v0.t -# CHECK-INST: vmulhsu.vv v4, v8, v12, v0.t +th.vmulhsu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmulhsu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x98] -vmulhsu.vx v4, v8, a1, v0.t -# CHECK-INST: vmulhsu.vx v4, v8, a1, v0.t +th.vmulhsu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vmulhsu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x98] -vwmul.vv v4, v8, v12 -# CHECK-INST: vwmul.vv v4, v8, v12 +th.vwmul.vv v4, v8, v12 +# CHECK-INST: th.vwmul.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xee] -vwmul.vx v4, v8, a1 -# CHECK-INST: vwmul.vx v4, v8, a1 +th.vwmul.vx v4, v8, a1 +# CHECK-INST: th.vwmul.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xee] -vwmul.vv v4, v8, v12, v0.t -# CHECK-INST: vwmul.vv v4, v8, v12, v0.t +th.vwmul.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwmul.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xec] -vwmul.vx v4, v8, a1, v0.t -# CHECK-INST: vwmul.vx v4, v8, a1, v0.t +th.vwmul.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwmul.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xec] -vwmulu.vv v4, v8, v12 -# CHECK-INST: vwmulu.vv v4, v8, v12 +th.vwmulu.vv v4, v8, v12 +# CHECK-INST: th.vwmulu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xe2] -vwmulu.vx v4, v8, a1 -# CHECK-INST: vwmulu.vx v4, v8, a1 +th.vwmulu.vx v4, v8, a1 +# CHECK-INST: th.vwmulu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xe2] -vwmulu.vv v4, v8, v12, v0.t -# CHECK-INST: vwmulu.vv v4, v8, v12, v0.t +th.vwmulu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwmulu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xe0] -vwmulu.vx v4, v8, a1, v0.t -# CHECK-INST: vwmulu.vx v4, v8, a1, v0.t +th.vwmulu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwmulu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xe0] -vwmulsu.vv v4, v8, v12 -# CHECK-INST: vwmulsu.vv v4, v8, v12 +th.vwmulsu.vv v4, v8, v12 +# CHECK-INST: th.vwmulsu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0xea] -vwmulsu.vx v4, v8, a1 -# CHECK-INST: vwmulsu.vx v4, v8, a1 +th.vwmulsu.vx v4, v8, a1 +# CHECK-INST: th.vwmulsu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0xea] -vwmulsu.vv v4, v8, v12, v0.t -# CHECK-INST: vwmulsu.vv v4, v8, v12, v0.t +th.vwmulsu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vwmulsu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xe8] -vwmulsu.vx v4, v8, a1, v0.t -# CHECK-INST: vwmulsu.vx v4, v8, a1, v0.t +th.vwmulsu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vwmulsu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xe8] -vmacc.vv v4, v12, v8 -# CHECK-INST: vmacc.vv v4, v12, v8 +th.vmacc.vv v4, v12, v8 +# CHECK-INST: th.vmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xb6] -vmacc.vx v4, a1, v8 -# CHECK-INST: vmacc.vx v4, a1, v8 +th.vmacc.vx v4, a1, v8 +# CHECK-INST: th.vmacc.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xb6] -vmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vmacc.vv v4, v12, v8, v0.t +th.vmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xb4] -vmacc.vx v4, a1, v8, v0.t -# CHECK-INST: vmacc.vx v4, a1, v8, v0.t +th.vmacc.vx v4, a1, v8, v0.t +# CHECK-INST: th.vmacc.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xb4] -vnmsac.vv v4, v12, v8 -# CHECK-INST: vnmsac.vv v4, v12, v8 +th.vnmsac.vv v4, v12, v8 +# CHECK-INST: th.vnmsac.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xbe] -vnmsac.vx v4, a1, v8 -# CHECK-INST: vnmsac.vx v4, a1, v8 +th.vnmsac.vx v4, a1, v8 +# CHECK-INST: th.vnmsac.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xbe] -vnmsac.vv v4, v12, v8, v0.t -# CHECK-INST: vnmsac.vv v4, v12, v8, v0.t +th.vnmsac.vv v4, v12, v8, v0.t +# CHECK-INST: th.vnmsac.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xbc] -vnmsac.vx v4, a1, v8, v0.t -# CHECK-INST: vnmsac.vx v4, a1, v8, v0.t +th.vnmsac.vx v4, a1, v8, v0.t +# CHECK-INST: th.vnmsac.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xbc] -vmadd.vv v4, v12, v8 -# CHECK-INST: vmadd.vv v4, v12, v8 +th.vmadd.vv v4, v12, v8 +# CHECK-INST: th.vmadd.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xa6] -vmadd.vx v4, a1, v8 -# CHECK-INST: vmadd.vx v4, a1, v8 +th.vmadd.vx v4, a1, v8 +# CHECK-INST: th.vmadd.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xa6] -vmadd.vv v4, v12, v8, v0.t -# CHECK-INST: vmadd.vv v4, v12, v8, v0.t +th.vmadd.vv v4, v12, v8, v0.t +# CHECK-INST: th.vmadd.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xa4] -vmadd.vx v4, a1, v8, v0.t -# CHECK-INST: vmadd.vx v4, a1, v8, v0.t +th.vmadd.vx v4, a1, v8, v0.t +# CHECK-INST: th.vmadd.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xa4] -vnmsub.vv v4, v12, v8 -# CHECK-INST: vnmsub.vv v4, v12, v8 +th.vnmsub.vv v4, v12, v8 +# CHECK-INST: th.vnmsub.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xae] -vnmsub.vx v4, a1, v8 -# CHECK-INST: vnmsub.vx v4, a1, v8 +th.vnmsub.vx v4, a1, v8 +# CHECK-INST: th.vnmsub.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xae] -vnmsub.vv v4, v12, v8, v0.t -# CHECK-INST: vnmsub.vv v4, v12, v8, v0.t +th.vnmsub.vv v4, v12, v8, v0.t +# CHECK-INST: th.vnmsub.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xac] -vnmsub.vx v4, a1, v8, v0.t -# CHECK-INST: vnmsub.vx v4, a1, v8, v0.t +th.vnmsub.vx v4, a1, v8, v0.t +# CHECK-INST: th.vnmsub.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xac] -vwmaccu.vv v4, v12, v8 -# CHECK-INST: vwmaccu.vv v4, v12, v8 +th.vwmaccu.vv v4, v12, v8 +# CHECK-INST: th.vwmaccu.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xf2] -vwmaccu.vx v4, a1, v8 -# CHECK-INST: vwmaccu.vx v4, a1, v8 +th.vwmaccu.vx v4, a1, v8 +# CHECK-INST: th.vwmaccu.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xf2] -vwmaccu.vv v4, v12, v8, v0.t -# CHECK-INST: vwmaccu.vv v4, v12, v8, v0.t +th.vwmaccu.vv v4, v12, v8, v0.t +# CHECK-INST: th.vwmaccu.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xf0] -vwmaccu.vx v4, a1, v8, v0.t -# CHECK-INST: vwmaccu.vx v4, a1, v8, v0.t +th.vwmaccu.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwmaccu.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xf0] -vwmacc.vv v4, v12, v8 -# CHECK-INST: vwmacc.vv v4, v12, v8 +th.vwmacc.vv v4, v12, v8 +# CHECK-INST: th.vwmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xf6] -vwmacc.vx v4, a1, v8 -# CHECK-INST: vwmacc.vx v4, a1, v8 +th.vwmacc.vx v4, a1, v8 +# CHECK-INST: th.vwmacc.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xf6] -vwmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vwmacc.vv v4, v12, v8, v0.t +th.vwmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vwmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xf4] -vwmacc.vx v4, a1, v8, v0.t -# CHECK-INST: vwmacc.vx v4, a1, v8, v0.t +th.vwmacc.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwmacc.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xf4] -vwmaccsu.vv v4, v12, v8 -# CHECK-INST: vwmaccsu.vv v4, v12, v8 +th.vwmaccsu.vv v4, v12, v8 +# CHECK-INST: th.vwmaccsu.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x22,0x86,0xfa] -vwmaccsu.vx v4, a1, v8 -# CHECK-INST: vwmaccsu.vx v4, a1, v8 +th.vwmaccsu.vx v4, a1, v8 +# CHECK-INST: th.vwmaccsu.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xfa] -vwmaccsu.vv v4, v12, v8, v0.t -# CHECK-INST: vwmaccsu.vv v4, v12, v8, v0.t +th.vwmaccsu.vv v4, v12, v8, v0.t +# CHECK-INST: th.vwmaccsu.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0xf8] -vwmaccsu.vx v4, a1, v8, v0.t -# CHECK-INST: vwmaccsu.vx v4, a1, v8, v0.t +th.vwmaccsu.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwmaccsu.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xf8] -vwmaccus.vx v4, a1, v8 -# CHECK-INST: vwmaccus.vx v4, a1, v8 +th.vwmaccus.vx v4, a1, v8 +# CHECK-INST: th.vwmaccus.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xe2,0x85,0xfe] -vwmaccus.vx v4, a1, v8, v0.t -# CHECK-INST: vwmaccus.vx v4, a1, v8, v0.t +th.vwmaccus.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwmaccus.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0xfc] -vdivu.vv v4, v8, v12 -# CHECK-INST: vdivu.vv v4, v8, v12 +th.vdivu.vv v4, v8, v12 +# CHECK-INST: th.vdivu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x82] -vdivu.vx v4, v8, a1 -# CHECK-INST: vdivu.vx v4, v8, a1 +th.vdivu.vx v4, v8, a1 +# CHECK-INST: th.vdivu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x82] -vdivu.vv v4, v8, v12, v0.t -# CHECK-INST: vdivu.vv v4, v8, v12, v0.t +th.vdivu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vdivu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x80] -vdivu.vx v4, v8, a1, v0.t -# CHECK-INST: vdivu.vx v4, v8, a1, v0.t +th.vdivu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vdivu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x80] -vdiv.vv v4, v8, v12 -# CHECK-INST: vdiv.vv v4, v8, v12 +th.vdiv.vv v4, v8, v12 +# CHECK-INST: th.vdiv.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x86] -vdiv.vx v4, v8, a1 -# CHECK-INST: vdiv.vx v4, v8, a1 +th.vdiv.vx v4, v8, a1 +# CHECK-INST: th.vdiv.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x86] -vdiv.vv v4, v8, v12, v0.t -# CHECK-INST: vdiv.vv v4, v8, v12, v0.t +th.vdiv.vv v4, v8, v12, v0.t +# CHECK-INST: th.vdiv.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x84] -vdiv.vx v4, v8, a1, v0.t -# CHECK-INST: vdiv.vx v4, v8, a1, v0.t +th.vdiv.vx v4, v8, a1, v0.t +# CHECK-INST: th.vdiv.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x84] -vremu.vv v4, v8, v12 -# CHECK-INST: vremu.vv v4, v8, v12 +th.vremu.vv v4, v8, v12 +# CHECK-INST: th.vremu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x8a] -vremu.vx v4, v8, a1 -# CHECK-INST: vremu.vx v4, v8, a1 +th.vremu.vx v4, v8, a1 +# CHECK-INST: th.vremu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x8a] -vremu.vv v4, v8, v12, v0.t -# CHECK-INST: vremu.vv v4, v8, v12, v0.t +th.vremu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vremu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x88] -vremu.vx v4, v8, a1, v0.t -# CHECK-INST: vremu.vx v4, v8, a1, v0.t +th.vremu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vremu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x88] -vrem.vv v4, v8, v12 -# CHECK-INST: vrem.vv v4, v8, v12 +th.vrem.vv v4, v8, v12 +# CHECK-INST: th.vrem.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x8e] -vrem.vx v4, v8, a1 -# CHECK-INST: vrem.vx v4, v8, a1 +th.vrem.vx v4, v8, a1 +# CHECK-INST: th.vrem.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x8e] -vrem.vv v4, v8, v12, v0.t -# CHECK-INST: vrem.vv v4, v8, v12, v0.t +th.vrem.vv v4, v8, v12, v0.t +# CHECK-INST: th.vrem.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x8c] -vrem.vx v4, v8, a1, v0.t -# CHECK-INST: vrem.vx v4, v8, a1, v0.t +th.vrem.vx v4, v8, a1, v0.t +# CHECK-INST: th.vrem.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x8c] -vmerge.vvm v4, v8, v12, v0 -# CHECK-INST: vmerge.vvm v4, v8, v12, v0 +th.vmerge.vvm v4, v8, v12, v0 +# CHECK-INST: th.vmerge.vvm v4, v8, v12, v0 # CHECK-ENCODING: [0x57,0x02,0x86,0x5c] -vmerge.vxm v4, v8, a1, v0 -# CHECK-INST: vmerge.vxm v4, v8, a1, v0 +th.vmerge.vxm v4, v8, a1, v0 +# CHECK-INST: th.vmerge.vxm v4, v8, a1, v0 # CHECK-ENCODING: [0x57,0xc2,0x85,0x5c] -vmerge.vim v4, v8, 15, v0 -# CHECK-INST: vmerge.vim v4, v8, 15, v0 +th.vmerge.vim v4, v8, 15, v0 +# CHECK-INST: th.vmerge.vim v4, v8, 15, v0 # CHECK-ENCODING: [0x57,0xb2,0x87,0x5c] -vmerge.vim v4, v8, -16, v0 -# CHECK-INST: vmerge.vim v4, v8, -16, v0 +th.vmerge.vim v4, v8, -16, v0 +# CHECK-INST: th.vmerge.vim v4, v8, -16, v0 # CHECK-ENCODING: [0x57,0x32,0x88,0x5c] -vmv.v.v v8, v12 -# CHECK-INST: vmv.v.v v8, v12 +th.vmv.v.v v8, v12 +# CHECK-INST: th.vmv.v.v v8, v12 # CHECK-ENCODING: [0x57,0x04,0x06,0x5e] -vmv.v.x v8, a1 -# CHECK-INST: vmv.v.x v8, a1 +th.vmv.v.x v8, a1 +# CHECK-INST: th.vmv.v.x v8, a1 # CHECK-ENCODING: [0x57,0xc4,0x05,0x5e] -vmv.v.i v8, 15 -# CHECK-INST: vmv.v.i v8, 15 +th.vmv.v.i v8, 15 +# CHECK-INST: th.vmv.v.i v8, 15 # CHECK-ENCODING: [0x57,0xb4,0x07,0x5e] -vmv.v.i v8, -16 -# CHECK-INST: vmv.v.i v8, -16 +th.vmv.v.i v8, -16 +# CHECK-INST: th.vmv.v.i v8, -16 # CHECK-ENCODING: [0x57,0x34,0x08,0x5e] -vsaddu.vv v4, v8, v12 -# CHECK-INST: vsaddu.vv v4, v8, v12 +th.vsaddu.vv v4, v8, v12 +# CHECK-INST: th.vsaddu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x82] -vsaddu.vx v4, v8, a1 -# CHECK-INST: vsaddu.vx v4, v8, a1 +th.vsaddu.vx v4, v8, a1 +# CHECK-INST: th.vsaddu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x82] -vsaddu.vi v4, v8, 15 -# CHECK-INST: vsaddu.vi v4, v8, 15 +th.vsaddu.vi v4, v8, 15 +# CHECK-INST: th.vsaddu.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x82] -vsaddu.vi v4, v8, -16 -# CHECK-INST: vsaddu.vi v4, v8, -16 +th.vsaddu.vi v4, v8, -16 +# CHECK-INST: th.vsaddu.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x82] -vsaddu.vv v4, v8, v12, v0.t -# CHECK-INST: vsaddu.vv v4, v8, v12, v0.t +th.vsaddu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsaddu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x80] -vsaddu.vx v4, v8, a1, v0.t -# CHECK-INST: vsaddu.vx v4, v8, a1, v0.t +th.vsaddu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsaddu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x80] -vsaddu.vi v4, v8, 15, v0.t -# CHECK-INST: vsaddu.vi v4, v8, 15, v0.t +th.vsaddu.vi v4, v8, 15, v0.t +# CHECK-INST: th.vsaddu.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x80] -vsaddu.vi v4, v8, -16, v0.t -# CHECK-INST: vsaddu.vi v4, v8, -16, v0.t +th.vsaddu.vi v4, v8, -16, v0.t +# CHECK-INST: th.vsaddu.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x80] -vsadd.vv v4, v8, v12 -# CHECK-INST: vsadd.vv v4, v8, v12 +th.vsadd.vv v4, v8, v12 +# CHECK-INST: th.vsadd.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x86] -vsadd.vx v4, v8, a1 -# CHECK-INST: vsadd.vx v4, v8, a1 +th.vsadd.vx v4, v8, a1 +# CHECK-INST: th.vsadd.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x86] -vsadd.vi v4, v8, 15 -# CHECK-INST: vsadd.vi v4, v8, 15 +th.vsadd.vi v4, v8, 15 +# CHECK-INST: th.vsadd.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x86] -vsadd.vi v4, v8, -16 -# CHECK-INST: vsadd.vi v4, v8, -16 +th.vsadd.vi v4, v8, -16 +# CHECK-INST: th.vsadd.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x86] -vsadd.vv v4, v8, v12, v0.t -# CHECK-INST: vsadd.vv v4, v8, v12, v0.t +th.vsadd.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsadd.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x84] -vsadd.vx v4, v8, a1, v0.t -# CHECK-INST: vsadd.vx v4, v8, a1, v0.t +th.vsadd.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsadd.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x84] -vsadd.vi v4, v8, 15, v0.t -# CHECK-INST: vsadd.vi v4, v8, 15, v0.t +th.vsadd.vi v4, v8, 15, v0.t +# CHECK-INST: th.vsadd.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x84] -vsadd.vi v4, v8, -16, v0.t -# CHECK-INST: vsadd.vi v4, v8, -16, v0.t +th.vsadd.vi v4, v8, -16, v0.t +# CHECK-INST: th.vsadd.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x84] -vssubu.vv v4, v8, v12 -# CHECK-INST: vssubu.vv v4, v8, v12 +th.vssubu.vv v4, v8, v12 +# CHECK-INST: th.vssubu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x8a] -vssubu.vx v4, v8, a1 -# CHECK-INST: vssubu.vx v4, v8, a1 +th.vssubu.vx v4, v8, a1 +# CHECK-INST: th.vssubu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x8a] -vssubu.vv v4, v8, v12, v0.t -# CHECK-INST: vssubu.vv v4, v8, v12, v0.t +th.vssubu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vssubu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x88] -vssubu.vx v4, v8, a1, v0.t -# CHECK-INST: vssubu.vx v4, v8, a1, v0.t +th.vssubu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vssubu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x88] -vssub.vv v4, v8, v12 -# CHECK-INST: vssub.vv v4, v8, v12 +th.vssub.vv v4, v8, v12 +# CHECK-INST: th.vssub.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x8e] -vssub.vx v4, v8, a1 -# CHECK-INST: vssub.vx v4, v8, a1 +th.vssub.vx v4, v8, a1 +# CHECK-INST: th.vssub.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x8e] -vssub.vv v4, v8, v12, v0.t -# CHECK-INST: vssub.vv v4, v8, v12, v0.t +th.vssub.vv v4, v8, v12, v0.t +# CHECK-INST: th.vssub.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x8c] -vssub.vx v4, v8, a1, v0.t -# CHECK-INST: vssub.vx v4, v8, a1, v0.t +th.vssub.vx v4, v8, a1, v0.t +# CHECK-INST: th.vssub.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x8c] -vaadd.vv v4, v8, v12 -# CHECK-INST: vaadd.vv v4, v8, v12 +th.vaadd.vv v4, v8, v12 +# CHECK-INST: th.vaadd.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x92] -vaadd.vx v4, v8, a1 -# CHECK-INST: vaadd.vx v4, v8, a1 +th.vaadd.vx v4, v8, a1 +# CHECK-INST: th.vaadd.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x92] -vaadd.vi v4, v8, 15 -# CHECK-INST: vaadd.vi v4, v8, 15 +th.vaadd.vi v4, v8, 15 +# CHECK-INST: th.vaadd.vi v4, v8, 15 # CHECK-ENCODING: [0x57,0xb2,0x87,0x92] -vaadd.vi v4, v8, -16 -# CHECK-INST: vaadd.vi v4, v8, -16 +th.vaadd.vi v4, v8, -16 +# CHECK-INST: th.vaadd.vi v4, v8, -16 # CHECK-ENCODING: [0x57,0x32,0x88,0x92] -vaadd.vv v4, v8, v12, v0.t -# CHECK-INST: vaadd.vv v4, v8, v12, v0.t +th.vaadd.vv v4, v8, v12, v0.t +# CHECK-INST: th.vaadd.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x90] -vaadd.vx v4, v8, a1, v0.t -# CHECK-INST: vaadd.vx v4, v8, a1, v0.t +th.vaadd.vx v4, v8, a1, v0.t +# CHECK-INST: th.vaadd.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x90] -vaadd.vi v4, v8, 15, v0.t -# CHECK-INST: vaadd.vi v4, v8, 15, v0.t +th.vaadd.vi v4, v8, 15, v0.t +# CHECK-INST: th.vaadd.vi v4, v8, 15, v0.t # CHECK-ENCODING: [0x57,0xb2,0x87,0x90] -vaadd.vi v4, v8, -16, v0.t -# CHECK-INST: vaadd.vi v4, v8, -16, v0.t +th.vaadd.vi v4, v8, -16, v0.t +# CHECK-INST: th.vaadd.vi v4, v8, -16, v0.t # CHECK-ENCODING: [0x57,0x32,0x88,0x90] -vasub.vv v4, v8, v12 -# CHECK-INST: vasub.vv v4, v8, v12 +th.vasub.vv v4, v8, v12 +# CHECK-INST: th.vasub.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x9a] -vasub.vx v4, v8, a1 -# CHECK-INST: vasub.vx v4, v8, a1 +th.vasub.vx v4, v8, a1 +# CHECK-INST: th.vasub.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x9a] -vasub.vv v4, v8, v12, v0.t -# CHECK-INST: vasub.vv v4, v8, v12, v0.t +th.vasub.vv v4, v8, v12, v0.t +# CHECK-INST: th.vasub.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x98] -vasub.vx v4, v8, a1, v0.t -# CHECK-INST: vasub.vx v4, v8, a1, v0.t +th.vasub.vx v4, v8, a1, v0.t +# CHECK-INST: th.vasub.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x98] -vsmul.vv v4, v8, v12 -# CHECK-INST: vsmul.vv v4, v8, v12 +th.vsmul.vv v4, v8, v12 +# CHECK-INST: th.vsmul.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x9e] -vsmul.vx v4, v8, a1 -# CHECK-INST: vsmul.vx v4, v8, a1 +th.vsmul.vx v4, v8, a1 +# CHECK-INST: th.vsmul.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x9e] -vsmul.vv v4, v8, v12, v0.t -# CHECK-INST: vsmul.vv v4, v8, v12, v0.t +th.vsmul.vv v4, v8, v12, v0.t +# CHECK-INST: th.vsmul.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x9c] -vsmul.vx v4, v8, a1, v0.t -# CHECK-INST: vsmul.vx v4, v8, a1, v0.t +th.vsmul.vx v4, v8, a1, v0.t +# CHECK-INST: th.vsmul.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x9c] -vwsmaccu.vv v4, v12, v8 -# CHECK-INST: vwsmaccu.vv v4, v12, v8 +th.vwsmaccu.vv v4, v12, v8 +# CHECK-INST: th.vwsmaccu.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0x86,0xf2] -vwsmaccu.vx v4, a1, v8 -# CHECK-INST: vwsmaccu.vx v4, a1, v8 +th.vwsmaccu.vx v4, a1, v8 +# CHECK-INST: th.vwsmaccu.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xc2,0x85,0xf2] -vwsmacc.vv v4, v12, v8 -# CHECK-INST: vwsmacc.vv v4, v12, v8 +th.vwsmacc.vv v4, v12, v8 +# CHECK-INST: th.vwsmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0x86,0xf6] -vwsmacc.vx v4, a1, v8 -# CHECK-INST: vwsmacc.vx v4, a1, v8 +th.vwsmacc.vx v4, a1, v8 +# CHECK-INST: th.vwsmacc.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xc2,0x85,0xf6] -vwsmaccsu.vv v4, v12, v8 -# CHECK-INST: vwsmaccsu.vv v4, v12, v8 +th.vwsmaccsu.vv v4, v12, v8 +# CHECK-INST: th.vwsmaccsu.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x02,0x86,0xfa] -vwsmaccsu.vx v4, a1, v8 -# CHECK-INST: vwsmaccsu.vx v4, a1, v8 +th.vwsmaccsu.vx v4, a1, v8 +# CHECK-INST: th.vwsmaccsu.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xc2,0x85,0xfa] -vwsmaccus.vx v4, a1, v8 -# CHECK-INST: vwsmaccus.vx v4, a1, v8 +th.vwsmaccus.vx v4, a1, v8 +# CHECK-INST: th.vwsmaccus.vx v4, a1, v8 # CHECK-ENCODING: [0x57,0xc2,0x85,0xfe] -vwsmaccu.vv v4, v12, v8, v0.t -# CHECK-INST: vwsmaccu.vv v4, v12, v8, v0.t +th.vwsmaccu.vv v4, v12, v8, v0.t +# CHECK-INST: th.vwsmaccu.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xf0] -vwsmaccu.vx v4, a1, v8, v0.t -# CHECK-INST: vwsmaccu.vx v4, a1, v8, v0.t +th.vwsmaccu.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwsmaccu.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xf0] -vwsmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vwsmacc.vv v4, v12, v8, v0.t +th.vwsmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vwsmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xf4] -vwsmacc.vx v4, a1, v8, v0.t -# CHECK-INST: vwsmacc.vx v4, a1, v8, v0.t +th.vwsmacc.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwsmacc.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xf4] -vwsmaccsu.vv v4, v12, v8, v0.t -# CHECK-INST: vwsmaccsu.vv v4, v12, v8, v0.t +th.vwsmaccsu.vv v4, v12, v8, v0.t +# CHECK-INST: th.vwsmaccsu.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xf8] -vwsmaccsu.vx v4, a1, v8, v0.t -# CHECK-INST: vwsmaccsu.vx v4, a1, v8, v0.t +th.vwsmaccsu.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwsmaccsu.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xf8] -vwsmaccus.vx v4, a1, v8, v0.t -# CHECK-INST: vwsmaccus.vx v4, a1, v8, v0.t +th.vwsmaccus.vx v4, a1, v8, v0.t +# CHECK-INST: th.vwsmaccus.vx v4, a1, v8, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xfc] -vssrl.vv v4, v8, v12 -# CHECK-INST: vssrl.vv v4, v8, v12 +th.vssrl.vv v4, v8, v12 +# CHECK-INST: th.vssrl.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xaa] -vssrl.vx v4, v8, a1 -# CHECK-INST: vssrl.vx v4, v8, a1 +th.vssrl.vx v4, v8, a1 +# CHECK-INST: th.vssrl.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xaa] -vssrl.vi v4, v8, 1 -# CHECK-INST: vssrl.vi v4, v8, 1 +th.vssrl.vi v4, v8, 1 +# CHECK-INST: th.vssrl.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xaa] -vssrl.vi v4, v8, 31 -# CHECK-INST: vssrl.vi v4, v8, 31 +th.vssrl.vi v4, v8, 31 +# CHECK-INST: th.vssrl.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xaa] -vssrl.vv v4, v8, v12, v0.t -# CHECK-INST: vssrl.vv v4, v8, v12, v0.t +th.vssrl.vv v4, v8, v12, v0.t +# CHECK-INST: th.vssrl.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xa8] -vssrl.vx v4, v8, a1, v0.t -# CHECK-INST: vssrl.vx v4, v8, a1, v0.t +th.vssrl.vx v4, v8, a1, v0.t +# CHECK-INST: th.vssrl.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xa8] -vssrl.vi v4, v8, 1, v0.t -# CHECK-INST: vssrl.vi v4, v8, 1, v0.t +th.vssrl.vi v4, v8, 1, v0.t +# CHECK-INST: th.vssrl.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xa8] -vssrl.vi v4, v8, 31, v0.t -# CHECK-INST: vssrl.vi v4, v8, 31, v0.t +th.vssrl.vi v4, v8, 31, v0.t +# CHECK-INST: th.vssrl.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xa8] -vssra.vv v4, v8, v12 -# CHECK-INST: vssra.vv v4, v8, v12 +th.vssra.vv v4, v8, v12 +# CHECK-INST: th.vssra.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xae] -vssra.vx v4, v8, a1 -# CHECK-INST: vssra.vx v4, v8, a1 +th.vssra.vx v4, v8, a1 +# CHECK-INST: th.vssra.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xae] -vssra.vi v4, v8, 1 -# CHECK-INST: vssra.vi v4, v8, 1 +th.vssra.vi v4, v8, 1 +# CHECK-INST: th.vssra.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xae] -vssra.vi v4, v8, 31 -# CHECK-INST: vssra.vi v4, v8, 31 +th.vssra.vi v4, v8, 31 +# CHECK-INST: th.vssra.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xae] -vssra.vv v4, v8, v12, v0.t -# CHECK-INST: vssra.vv v4, v8, v12, v0.t +th.vssra.vv v4, v8, v12, v0.t +# CHECK-INST: th.vssra.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xac] -vssra.vx v4, v8, a1, v0.t -# CHECK-INST: vssra.vx v4, v8, a1, v0.t +th.vssra.vx v4, v8, a1, v0.t +# CHECK-INST: th.vssra.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xac] -vssra.vi v4, v8, 1, v0.t -# CHECK-INST: vssra.vi v4, v8, 1, v0.t +th.vssra.vi v4, v8, 1, v0.t +# CHECK-INST: th.vssra.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xac] -vssra.vi v4, v8, 31, v0.t -# CHECK-INST: vssra.vi v4, v8, 31, v0.t +th.vssra.vi v4, v8, 31, v0.t +# CHECK-INST: th.vssra.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xac] -vnclipu.vv v4, v8, v12 -# CHECK-INST: vnclipu.vv v4, v8, v12 +th.vnclipu.vv v4, v8, v12 +# CHECK-INST: th.vnclipu.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xba] -vnclipu.vx v4, v8, a1 -# CHECK-INST: vnclipu.vx v4, v8, a1 +th.vnclipu.vx v4, v8, a1 +# CHECK-INST: th.vnclipu.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xba] -vnclipu.vi v4, v8, 1 -# CHECK-INST: vnclipu.vi v4, v8, 1 +th.vnclipu.vi v4, v8, 1 +# CHECK-INST: th.vnclipu.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xba] -vnclipu.vi v4, v8, 31 -# CHECK-INST: vnclipu.vi v4, v8, 31 +th.vnclipu.vi v4, v8, 31 +# CHECK-INST: th.vnclipu.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xba] -vnclipu.vv v4, v8, v12, v0.t -# CHECK-INST: vnclipu.vv v4, v8, v12, v0.t +th.vnclipu.vv v4, v8, v12, v0.t +# CHECK-INST: th.vnclipu.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xb8] -vnclipu.vx v4, v8, a1, v0.t -# CHECK-INST: vnclipu.vx v4, v8, a1, v0.t +th.vnclipu.vx v4, v8, a1, v0.t +# CHECK-INST: th.vnclipu.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xb8] -vnclipu.vi v4, v8, 1, v0.t -# CHECK-INST: vnclipu.vi v4, v8, 1, v0.t +th.vnclipu.vi v4, v8, 1, v0.t +# CHECK-INST: th.vnclipu.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xb8] -vnclipu.vi v4, v8, 31, v0.t -# CHECK-INST: vnclipu.vi v4, v8, 31, v0.t +th.vnclipu.vi v4, v8, 31, v0.t +# CHECK-INST: th.vnclipu.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xb8] -vnclip.vv v4, v8, v12 -# CHECK-INST: vnclip.vv v4, v8, v12 +th.vnclip.vv v4, v8, v12 +# CHECK-INST: th.vnclip.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xbe] -vnclip.vx v4, v8, a1 -# CHECK-INST: vnclip.vx v4, v8, a1 +th.vnclip.vx v4, v8, a1 +# CHECK-INST: th.vnclip.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0xbe] -vnclip.vi v4, v8, 1 -# CHECK-INST: vnclip.vi v4, v8, 1 +th.vnclip.vi v4, v8, 1 +# CHECK-INST: th.vnclip.vi v4, v8, 1 # CHECK-ENCODING: [0x57,0xb2,0x80,0xbe] -vnclip.vi v4, v8, 31 -# CHECK-INST: vnclip.vi v4, v8, 31 +th.vnclip.vi v4, v8, 31 +# CHECK-INST: th.vnclip.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0xbe] -vnclip.vv v4, v8, v12, v0.t -# CHECK-INST: vnclip.vv v4, v8, v12, v0.t +th.vnclip.vv v4, v8, v12, v0.t +# CHECK-INST: th.vnclip.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xbc] -vnclip.vx v4, v8, a1, v0.t -# CHECK-INST: vnclip.vx v4, v8, a1, v0.t +th.vnclip.vx v4, v8, a1, v0.t +# CHECK-INST: th.vnclip.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0xbc] -vnclip.vi v4, v8, 1, v0.t -# CHECK-INST: vnclip.vi v4, v8, 1, v0.t +th.vnclip.vi v4, v8, 1, v0.t +# CHECK-INST: th.vnclip.vi v4, v8, 1, v0.t # CHECK-ENCODING: [0x57,0xb2,0x80,0xbc] -vnclip.vi v4, v8, 31, v0.t -# CHECK-INST: vnclip.vi v4, v8, 31, v0.t +th.vnclip.vi v4, v8, 31, v0.t +# CHECK-INST: th.vnclip.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0xbc] -vfadd.vv v4, v8, v12 -# CHECK-INST: vfadd.vv v4, v8, v12 +th.vfadd.vv v4, v8, v12 +# CHECK-INST: th.vfadd.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x02] -vfadd.vf v4, v8, fa2 -# CHECK-INST: vfadd.vf v4, v8, fa2 +th.vfadd.vf v4, v8, fa2 +# CHECK-INST: th.vfadd.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x02] -vfadd.vv v4, v8, v12, v0.t -# CHECK-INST: vfadd.vv v4, v8, v12, v0.t +th.vfadd.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfadd.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x00] -vfadd.vf v4, v8, fa2, v0.t -# CHECK-INST: vfadd.vf v4, v8, fa2, v0.t +th.vfadd.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfadd.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x00] -vfsub.vv v4, v8, v12 -# CHECK-INST: vfsub.vv v4, v8, v12 +th.vfsub.vv v4, v8, v12 +# CHECK-INST: th.vfsub.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x0a] -vfsub.vf v4, v8, fa2 -# CHECK-INST: vfsub.vf v4, v8, fa2 +th.vfsub.vf v4, v8, fa2 +# CHECK-INST: th.vfsub.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x0a] -vfsub.vv v4, v8, v12, v0.t -# CHECK-INST: vfsub.vv v4, v8, v12, v0.t +th.vfsub.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfsub.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x08] -vfsub.vf v4, v8, fa2, v0.t -# CHECK-INST: vfsub.vf v4, v8, fa2, v0.t +th.vfsub.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfsub.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x08] -vfrsub.vf v4, v8, fa2 -# CHECK-INST: vfrsub.vf v4, v8, fa2 +th.vfrsub.vf v4, v8, fa2 +# CHECK-INST: th.vfrsub.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x9e] -vfrsub.vf v4, v8, fa2, v0.t -# CHECK-INST: vfrsub.vf v4, v8, fa2, v0.t +th.vfrsub.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfrsub.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x9c] -vfwadd.vv v4, v8, v12 -# CHECK-INST: vfwadd.vv v4, v8, v12 +th.vfwadd.vv v4, v8, v12 +# CHECK-INST: th.vfwadd.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xc2] -vfwadd.vf v4, v8, fa2 -# CHECK-INST: vfwadd.vf v4, v8, fa2 +th.vfwadd.vf v4, v8, fa2 +# CHECK-INST: th.vfwadd.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0xc2] -vfwadd.vv v4, v8, v12, v0.t -# CHECK-INST: vfwadd.vv v4, v8, v12, v0.t +th.vfwadd.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfwadd.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xc0] -vfwadd.vf v4, v8, fa2, v0.t -# CHECK-INST: vfwadd.vf v4, v8, fa2, v0.t +th.vfwadd.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfwadd.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xc0] -vfwsub.vv v4, v8, v12 -# CHECK-INST: vfwsub.vv v4, v8, v12 +th.vfwsub.vv v4, v8, v12 +# CHECK-INST: th.vfwsub.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xca] -vfwsub.vf v4, v8, fa2 -# CHECK-INST: vfwsub.vf v4, v8, fa2 +th.vfwsub.vf v4, v8, fa2 +# CHECK-INST: th.vfwsub.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0xca] -vfwsub.vv v4, v8, v12, v0.t -# CHECK-INST: vfwsub.vv v4, v8, v12, v0.t +th.vfwsub.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfwsub.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xc8] -vfwsub.vf v4, v8, fa2, v0.t -# CHECK-INST: vfwsub.vf v4, v8, fa2, v0.t +th.vfwsub.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfwsub.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xc8] -vfwadd.wv v4, v8, v12 -# CHECK-INST: vfwadd.wv v4, v8, v12 +th.vfwadd.wv v4, v8, v12 +# CHECK-INST: th.vfwadd.wv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xd2] -vfwadd.wf v4, v8, fa2 -# CHECK-INST: vfwadd.wf v4, v8, fa2 +th.vfwadd.wf v4, v8, fa2 +# CHECK-INST: th.vfwadd.wf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0xd2] -vfwadd.wv v4, v8, v12, v0.t -# CHECK-INST: vfwadd.wv v4, v8, v12, v0.t +th.vfwadd.wv v4, v8, v12, v0.t +# CHECK-INST: th.vfwadd.wv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xd0] -vfwadd.wf v4, v8, fa2, v0.t -# CHECK-INST: vfwadd.wf v4, v8, fa2, v0.t +th.vfwadd.wf v4, v8, fa2, v0.t +# CHECK-INST: th.vfwadd.wf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xd0] -vfwsub.wv v4, v8, v12 -# CHECK-INST: vfwsub.wv v4, v8, v12 +th.vfwsub.wv v4, v8, v12 +# CHECK-INST: th.vfwsub.wv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xda] -vfwsub.wf v4, v8, fa2 -# CHECK-INST: vfwsub.wf v4, v8, fa2 +th.vfwsub.wf v4, v8, fa2 +# CHECK-INST: th.vfwsub.wf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0xda] -vfwsub.wv v4, v8, v12, v0.t -# CHECK-INST: vfwsub.wv v4, v8, v12, v0.t +th.vfwsub.wv v4, v8, v12, v0.t +# CHECK-INST: th.vfwsub.wv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xd8] -vfwsub.wf v4, v8, fa2, v0.t -# CHECK-INST: vfwsub.wf v4, v8, fa2, v0.t +th.vfwsub.wf v4, v8, fa2, v0.t +# CHECK-INST: th.vfwsub.wf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xd8] -vfmul.vv v4, v8, v12 -# CHECK-INST: vfmul.vv v4, v8, v12 +th.vfmul.vv v4, v8, v12 +# CHECK-INST: th.vfmul.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x92] -vfmul.vf v4, v8, fa2 -# CHECK-INST: vfmul.vf v4, v8, fa2 +th.vfmul.vf v4, v8, fa2 +# CHECK-INST: th.vfmul.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x92] -vfmul.vv v4, v8, v12, v0.t -# CHECK-INST: vfmul.vv v4, v8, v12, v0.t +th.vfmul.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfmul.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x90] -vfmul.vf v4, v8, fa2, v0.t -# CHECK-INST: vfmul.vf v4, v8, fa2, v0.t +th.vfmul.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfmul.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x90] -vfdiv.vv v4, v8, v12 -# CHECK-INST: vfdiv.vv v4, v8, v12 +th.vfdiv.vv v4, v8, v12 +# CHECK-INST: th.vfdiv.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x82] -vfdiv.vf v4, v8, fa2 -# CHECK-INST: vfdiv.vf v4, v8, fa2 +th.vfdiv.vf v4, v8, fa2 +# CHECK-INST: th.vfdiv.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x82] -vfdiv.vv v4, v8, v12, v0.t -# CHECK-INST: vfdiv.vv v4, v8, v12, v0.t +th.vfdiv.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfdiv.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x80] -vfdiv.vf v4, v8, fa2, v0.t -# CHECK-INST: vfdiv.vf v4, v8, fa2, v0.t +th.vfdiv.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfdiv.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x80] -vfrdiv.vf v4, v8, fa2 -# CHECK-INST: vfrdiv.vf v4, v8, fa2 +th.vfrdiv.vf v4, v8, fa2 +# CHECK-INST: th.vfrdiv.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x86] -vfrdiv.vf v4, v8, fa2, v0.t -# CHECK-INST: vfrdiv.vf v4, v8, fa2, v0.t +th.vfrdiv.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfrdiv.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x84] -vfwmul.vv v4, v8, v12 -# CHECK-INST: vfwmul.vv v4, v8, v12 +th.vfwmul.vv v4, v8, v12 +# CHECK-INST: th.vfwmul.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xe2] -vfwmul.vf v4, v8, fa2 -# CHECK-INST: vfwmul.vf v4, v8, fa2 +th.vfwmul.vf v4, v8, fa2 +# CHECK-INST: th.vfwmul.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0xe2] -vfwmul.vv v4, v8, v12, v0.t -# CHECK-INST: vfwmul.vv v4, v8, v12, v0.t +th.vfwmul.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfwmul.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xe0] -vfwmul.vf v4, v8, fa2, v0.t -# CHECK-INST: vfwmul.vf v4, v8, fa2, v0.t +th.vfwmul.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfwmul.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xe0] -vfmadd.vv v4, v12, v8 -# CHECK-INST: vfmadd.vv v4, v12, v8 +th.vfmadd.vv v4, v12, v8 +# CHECK-INST: th.vfmadd.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xa2] -vfmadd.vf v4, fa2, v8 -# CHECK-INST: vfmadd.vf v4, fa2, v8 +th.vfmadd.vf v4, fa2, v8 +# CHECK-INST: th.vfmadd.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xa2] -vfnmadd.vv v4, v12, v8 -# CHECK-INST: vfnmadd.vv v4, v12, v8 +th.vfnmadd.vv v4, v12, v8 +# CHECK-INST: th.vfnmadd.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xa6] -vfnmadd.vf v4, fa2, v8 -# CHECK-INST: vfnmadd.vf v4, fa2, v8 +th.vfnmadd.vf v4, fa2, v8 +# CHECK-INST: th.vfnmadd.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xa6] -vfmsub.vv v4, v12, v8 -# CHECK-INST: vfmsub.vv v4, v12, v8 +th.vfmsub.vv v4, v12, v8 +# CHECK-INST: th.vfmsub.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xaa] -vfmsub.vf v4, fa2, v8 -# CHECK-INST: vfmsub.vf v4, fa2, v8 +th.vfmsub.vf v4, fa2, v8 +# CHECK-INST: th.vfmsub.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xaa] -vfnmsub.vv v4, v12, v8 -# CHECK-INST: vfnmsub.vv v4, v12, v8 +th.vfnmsub.vv v4, v12, v8 +# CHECK-INST: th.vfnmsub.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xae] -vfnmsub.vf v4, fa2, v8 -# CHECK-INST: vfnmsub.vf v4, fa2, v8 +th.vfnmsub.vf v4, fa2, v8 +# CHECK-INST: th.vfnmsub.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xae] -vfmadd.vv v4, v12, v8, v0.t -# CHECK-INST: vfmadd.vv v4, v12, v8, v0.t +th.vfmadd.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfmadd.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xa0] -vfmadd.vf v4, fa2, v8, v0.t -# CHECK-INST: vfmadd.vf v4, fa2, v8, v0.t +th.vfmadd.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfmadd.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xa0] -vfnmadd.vv v4, v12, v8, v0.t -# CHECK-INST: vfnmadd.vv v4, v12, v8, v0.t +th.vfnmadd.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfnmadd.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xa4] -vfnmadd.vf v4, fa2, v8, v0.t -# CHECK-INST: vfnmadd.vf v4, fa2, v8, v0.t +th.vfnmadd.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfnmadd.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xa4] -vfmsub.vv v4, v12, v8, v0.t -# CHECK-INST: vfmsub.vv v4, v12, v8, v0.t +th.vfmsub.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfmsub.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xa8] -vfmsub.vf v4, fa2, v8, v0.t -# CHECK-INST: vfmsub.vf v4, fa2, v8, v0.t +th.vfmsub.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfmsub.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xa8] -vfnmsub.vv v4, v12, v8, v0.t -# CHECK-INST: vfnmsub.vv v4, v12, v8, v0.t +th.vfnmsub.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfnmsub.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xac] -vfnmsub.vf v4, fa2, v8, v0.t -# CHECK-INST: vfnmsub.vf v4, fa2, v8, v0.t +th.vfnmsub.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfnmsub.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xac] -vfmacc.vv v4, v12, v8 -# CHECK-INST: vfmacc.vv v4, v12, v8 +th.vfmacc.vv v4, v12, v8 +# CHECK-INST: th.vfmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xb2] -vfmacc.vf v4, fa2, v8 -# CHECK-INST: vfmacc.vf v4, fa2, v8 +th.vfmacc.vf v4, fa2, v8 +# CHECK-INST: th.vfmacc.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xb2] -vfnmacc.vv v4, v12, v8 -# CHECK-INST: vfnmacc.vv v4, v12, v8 +th.vfnmacc.vv v4, v12, v8 +# CHECK-INST: th.vfnmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xb6] -vfnmacc.vf v4, fa2, v8 -# CHECK-INST: vfnmacc.vf v4, fa2, v8 +th.vfnmacc.vf v4, fa2, v8 +# CHECK-INST: th.vfnmacc.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xb6] -vfmsac.vv v4, v12, v8 -# CHECK-INST: vfmsac.vv v4, v12, v8 +th.vfmsac.vv v4, v12, v8 +# CHECK-INST: th.vfmsac.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xba] -vfmsac.vf v4, fa2, v8 -# CHECK-INST: vfmsac.vf v4, fa2, v8 +th.vfmsac.vf v4, fa2, v8 +# CHECK-INST: th.vfmsac.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xba] -vfnmsac.vv v4, v12, v8 -# CHECK-INST: vfnmsac.vv v4, v12, v8 +th.vfnmsac.vv v4, v12, v8 +# CHECK-INST: th.vfnmsac.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xbe] -vfnmsac.vf v4, fa2, v8 -# CHECK-INST: vfnmsac.vf v4, fa2, v8 +th.vfnmsac.vf v4, fa2, v8 +# CHECK-INST: th.vfnmsac.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xbe] -vfmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vfmacc.vv v4, v12, v8, v0.t +th.vfmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xb0] -vfmacc.vf v4, fa2, v8, v0.t -# CHECK-INST: vfmacc.vf v4, fa2, v8, v0.t +th.vfmacc.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfmacc.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xb0] -vfnmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vfnmacc.vv v4, v12, v8, v0.t +th.vfnmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfnmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xb4] -vfnmacc.vf v4, fa2, v8, v0.t -# CHECK-INST: vfnmacc.vf v4, fa2, v8, v0.t +th.vfnmacc.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfnmacc.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xb4] -vfmsac.vv v4, v12, v8, v0.t -# CHECK-INST: vfmsac.vv v4, v12, v8, v0.t +th.vfmsac.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfmsac.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xb8] -vfmsac.vf v4, fa2, v8, v0.t -# CHECK-INST: vfmsac.vf v4, fa2, v8, v0.t +th.vfmsac.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfmsac.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xb8] -vfnmsac.vv v4, v12, v8, v0.t -# CHECK-INST: vfnmsac.vv v4, v12, v8, v0.t +th.vfnmsac.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfnmsac.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xbc] -vfnmsac.vf v4, fa2, v8, v0.t -# CHECK-INST: vfnmsac.vf v4, fa2, v8, v0.t +th.vfnmsac.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfnmsac.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xbc] -vfwmacc.vv v4, v12, v8 -# CHECK-INST: vfwmacc.vv v4, v12, v8 +th.vfwmacc.vv v4, v12, v8 +# CHECK-INST: th.vfwmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xf2] -vfwmacc.vf v4, fa2, v8 -# CHECK-INST: vfwmacc.vf v4, fa2, v8 +th.vfwmacc.vf v4, fa2, v8 +# CHECK-INST: th.vfwmacc.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xf2] -vfwnmacc.vv v4, v12, v8 -# CHECK-INST: vfwnmacc.vv v4, v12, v8 +th.vfwnmacc.vv v4, v12, v8 +# CHECK-INST: th.vfwnmacc.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xf6] -vfwnmacc.vf v4, fa2, v8 -# CHECK-INST: vfwnmacc.vf v4, fa2, v8 +th.vfwnmacc.vf v4, fa2, v8 +# CHECK-INST: th.vfwnmacc.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xf6] -vfwmsac.vv v4, v12, v8 -# CHECK-INST: vfwmsac.vv v4, v12, v8 +th.vfwmsac.vv v4, v12, v8 +# CHECK-INST: th.vfwmsac.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xfa] -vfwmsac.vf v4, fa2, v8 -# CHECK-INST: vfwmsac.vf v4, fa2, v8 +th.vfwmsac.vf v4, fa2, v8 +# CHECK-INST: th.vfwmsac.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xfa] -vfwnmsac.vv v4, v12, v8 -# CHECK-INST: vfwnmsac.vv v4, v12, v8 +th.vfwnmsac.vv v4, v12, v8 +# CHECK-INST: th.vfwnmsac.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0xfe] -vfwnmsac.vf v4, fa2, v8 -# CHECK-INST: vfwnmsac.vf v4, fa2, v8 +th.vfwnmsac.vf v4, fa2, v8 +# CHECK-INST: th.vfwnmsac.vf v4, fa2, v8 # CHECK-ENCODING: [0x57,0x52,0x86,0xfe] -vfwmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vfwmacc.vv v4, v12, v8, v0.t +th.vfwmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfwmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xf0] -vfwmacc.vf v4, fa2, v8, v0.t -# CHECK-INST: vfwmacc.vf v4, fa2, v8, v0.t +th.vfwmacc.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfwmacc.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xf0] -vfwnmacc.vv v4, v12, v8, v0.t -# CHECK-INST: vfwnmacc.vv v4, v12, v8, v0.t +th.vfwnmacc.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfwnmacc.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xf4] -vfwnmacc.vf v4, fa2, v8, v0.t -# CHECK-INST: vfwnmacc.vf v4, fa2, v8, v0.t +th.vfwnmacc.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfwnmacc.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xf4] -vfwmsac.vv v4, v12, v8, v0.t -# CHECK-INST: vfwmsac.vv v4, v12, v8, v0.t +th.vfwmsac.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfwmsac.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xf8] -vfwmsac.vf v4, fa2, v8, v0.t -# CHECK-INST: vfwmsac.vf v4, fa2, v8, v0.t +th.vfwmsac.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfwmsac.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xf8] -vfwnmsac.vv v4, v12, v8, v0.t -# CHECK-INST: vfwnmsac.vv v4, v12, v8, v0.t +th.vfwnmsac.vv v4, v12, v8, v0.t +# CHECK-INST: th.vfwnmsac.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xfc] -vfwnmsac.vf v4, fa2, v8, v0.t -# CHECK-INST: vfwnmsac.vf v4, fa2, v8, v0.t +th.vfwnmsac.vf v4, fa2, v8, v0.t +# CHECK-INST: th.vfwnmsac.vf v4, fa2, v8, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0xfc] -vfsqrt.v v4, v8 -# CHECK-INST: vfsqrt.v v4, v8 +th.vfsqrt.v v4, v8 +# CHECK-INST: th.vfsqrt.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x80,0x8e] -vfsqrt.v v4, v8, v0.t -# CHECK-INST: vfsqrt.v v4, v8, v0.t +th.vfsqrt.v v4, v8, v0.t +# CHECK-INST: th.vfsqrt.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x80,0x8c] -vfmin.vv v4, v8, v12 -# CHECK-INST: vfmin.vv v4, v8, v12 +th.vfmin.vv v4, v8, v12 +# CHECK-INST: th.vfmin.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x12] -vfmin.vf v4, v8, fa2 -# CHECK-INST: vfmin.vf v4, v8, fa2 +th.vfmin.vf v4, v8, fa2 +# CHECK-INST: th.vfmin.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x12] -vfmax.vv v4, v8, v12 -# CHECK-INST: vfmax.vv v4, v8, v12 +th.vfmax.vv v4, v8, v12 +# CHECK-INST: th.vfmax.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x1a] -vfmax.vf v4, v8, fa2 -# CHECK-INST: vfmax.vf v4, v8, fa2 +th.vfmax.vf v4, v8, fa2 +# CHECK-INST: th.vfmax.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x1a] -vfmin.vv v4, v8, v12, v0.t -# CHECK-INST: vfmin.vv v4, v8, v12, v0.t +th.vfmin.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfmin.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x10] -vfmin.vf v4, v8, fa2, v0.t -# CHECK-INST: vfmin.vf v4, v8, fa2, v0.t +th.vfmin.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfmin.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x10] -vfmax.vv v4, v8, v12, v0.t -# CHECK-INST: vfmax.vv v4, v8, v12, v0.t +th.vfmax.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfmax.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x18] -vfmax.vf v4, v8, fa2, v0.t -# CHECK-INST: vfmax.vf v4, v8, fa2, v0.t +th.vfmax.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfmax.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x18] -vfsgnj.vv v4, v8, v12 -# CHECK-INST: vfsgnj.vv v4, v8, v12 +th.vfsgnj.vv v4, v8, v12 +# CHECK-INST: th.vfsgnj.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x22] -vfsgnj.vf v4, v8, fa2 -# CHECK-INST: vfsgnj.vf v4, v8, fa2 +th.vfsgnj.vf v4, v8, fa2 +# CHECK-INST: th.vfsgnj.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x22] -vfsgnjn.vv v4, v8, v12 -# CHECK-INST: vfsgnjn.vv v4, v8, v12 +th.vfsgnjn.vv v4, v8, v12 +# CHECK-INST: th.vfsgnjn.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x26] -vfsgnjn.vf v4, v8, fa2 -# CHECK-INST: vfsgnjn.vf v4, v8, fa2 +th.vfsgnjn.vf v4, v8, fa2 +# CHECK-INST: th.vfsgnjn.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x26] -vfsgnjx.vv v4, v8, v12 -# CHECK-INST: vfsgnjx.vv v4, v8, v12 +th.vfsgnjx.vv v4, v8, v12 +# CHECK-INST: th.vfsgnjx.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x2a] -vfsgnjx.vf v4, v8, fa2 -# CHECK-INST: vfsgnjx.vf v4, v8, fa2 +th.vfsgnjx.vf v4, v8, fa2 +# CHECK-INST: th.vfsgnjx.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x2a] -vfsgnj.vv v4, v8, v12, v0.t -# CHECK-INST: vfsgnj.vv v4, v8, v12, v0.t +th.vfsgnj.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfsgnj.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x20] -vfsgnj.vf v4, v8, fa2, v0.t -# CHECK-INST: vfsgnj.vf v4, v8, fa2, v0.t +th.vfsgnj.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfsgnj.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x20] -vfsgnjn.vv v4, v8, v12, v0.t -# CHECK-INST: vfsgnjn.vv v4, v8, v12, v0.t +th.vfsgnjn.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfsgnjn.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x24] -vfsgnjn.vf v4, v8, fa2, v0.t -# CHECK-INST: vfsgnjn.vf v4, v8, fa2, v0.t +th.vfsgnjn.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfsgnjn.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x24] -vfsgnjx.vv v4, v8, v12, v0.t -# CHECK-INST: vfsgnjx.vv v4, v8, v12, v0.t +th.vfsgnjx.vv v4, v8, v12, v0.t +# CHECK-INST: th.vfsgnjx.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x28] -vfsgnjx.vf v4, v8, fa2, v0.t -# CHECK-INST: vfsgnjx.vf v4, v8, fa2, v0.t +th.vfsgnjx.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vfsgnjx.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x28] -vmfgt.vv v4, v8, v12 -# CHECK-INST: vmflt.vv v4, v12, v8 +th.vmfgt.vv v4, v8, v12 +# CHECK-INST: th.vmflt.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0xc4,0x6e] -vmfge.vv v4, v8, v12 -# CHECK-INST: vmfle.vv v4, v12, v8 +th.vmfge.vv v4, v8, v12 +# CHECK-INST: th.vmfle.vv v4, v12, v8 # CHECK-ENCODING: [0x57,0x12,0xc4,0x66] -vmfgt.vv v4, v8, v12, v0.t -# CHECK-INST: vmflt.vv v4, v12, v8, v0.t +th.vmfgt.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmflt.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0xc4,0x6c] -vmfge.vv v4, v8, v12, v0.t -# CHECK-INST: vmfle.vv v4, v12, v8, v0.t +th.vmfge.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmfle.vv v4, v12, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0xc4,0x64] -vmfeq.vv v4, v8, v12 -# CHECK-INST: vmfeq.vv v4, v8, v12 +th.vmfeq.vv v4, v8, v12 +# CHECK-INST: th.vmfeq.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x62] -vmfeq.vf v4, v8, fa2 -# CHECK-INST: vmfeq.vf v4, v8, fa2 +th.vmfeq.vf v4, v8, fa2 +# CHECK-INST: th.vmfeq.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x62] -vmfne.vv v4, v8, v12 -# CHECK-INST: vmfne.vv v4, v8, v12 +th.vmfne.vv v4, v8, v12 +# CHECK-INST: th.vmfne.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x72] -vmfne.vf v4, v8, fa2 -# CHECK-INST: vmfne.vf v4, v8, fa2 +th.vmfne.vf v4, v8, fa2 +# CHECK-INST: th.vmfne.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x72] -vmflt.vv v4, v8, v12 -# CHECK-INST: vmflt.vv v4, v8, v12 +th.vmflt.vv v4, v8, v12 +# CHECK-INST: th.vmflt.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x6e] -vmflt.vf v4, v8, fa2 -# CHECK-INST: vmflt.vf v4, v8, fa2 +th.vmflt.vf v4, v8, fa2 +# CHECK-INST: th.vmflt.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x6e] -vmfle.vv v4, v8, v12 -# CHECK-INST: vmfle.vv v4, v8, v12 +th.vmfle.vv v4, v8, v12 +# CHECK-INST: th.vmfle.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x66] -vmfle.vf v4, v8, fa2 -# CHECK-INST: vmfle.vf v4, v8, fa2 +th.vmfle.vf v4, v8, fa2 +# CHECK-INST: th.vmfle.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x66] -vmfgt.vf v4, v8, fa2 -# CHECK-INST: vmfgt.vf v4, v8, fa2 +th.vmfgt.vf v4, v8, fa2 +# CHECK-INST: th.vmfgt.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x76] -vmfge.vf v4, v8, fa2 -# CHECK-INST: vmfge.vf v4, v8, fa2 +th.vmfge.vf v4, v8, fa2 +# CHECK-INST: th.vmfge.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x7e] -vmfeq.vv v4, v8, v12, v0.t -# CHECK-INST: vmfeq.vv v4, v8, v12, v0.t +th.vmfeq.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmfeq.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x60] -vmfeq.vf v4, v8, fa2, v0.t -# CHECK-INST: vmfeq.vf v4, v8, fa2, v0.t +th.vmfeq.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmfeq.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x60] -vmfne.vv v4, v8, v12, v0.t -# CHECK-INST: vmfne.vv v4, v8, v12, v0.t +th.vmfne.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmfne.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x70] -vmfne.vf v4, v8, fa2, v0.t -# CHECK-INST: vmfne.vf v4, v8, fa2, v0.t +th.vmfne.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmfne.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x70] -vmflt.vv v4, v8, v12, v0.t -# CHECK-INST: vmflt.vv v4, v8, v12, v0.t +th.vmflt.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmflt.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x6c] -vmflt.vf v4, v8, fa2, v0.t -# CHECK-INST: vmflt.vf v4, v8, fa2, v0.t +th.vmflt.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmflt.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x6c] -vmfle.vv v4, v8, v12, v0.t -# CHECK-INST: vmfle.vv v4, v8, v12, v0.t +th.vmfle.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmfle.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x64] -vmfle.vf v4, v8, fa2, v0.t -# CHECK-INST: vmfle.vf v4, v8, fa2, v0.t +th.vmfle.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmfle.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x64] -vmfgt.vf v4, v8, fa2, v0.t -# CHECK-INST: vmfgt.vf v4, v8, fa2, v0.t +th.vmfgt.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmfgt.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x74] -vmfge.vf v4, v8, fa2, v0.t -# CHECK-INST: vmfge.vf v4, v8, fa2, v0.t +th.vmfge.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmfge.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x7c] -vmford.vv v4, v8, v12 -# CHECK-INST: vmford.vv v4, v8, v12 +th.vmford.vv v4, v8, v12 +# CHECK-INST: th.vmford.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x6a] -vmford.vf v4, v8, fa2 -# CHECK-INST: vmford.vf v4, v8, fa2 +th.vmford.vf v4, v8, fa2 +# CHECK-INST: th.vmford.vf v4, v8, fa2 # CHECK-ENCODING: [0x57,0x52,0x86,0x6a] -vmford.vv v4, v8, v12, v0.t -# CHECK-INST: vmford.vv v4, v8, v12, v0.t +th.vmford.vv v4, v8, v12, v0.t +# CHECK-INST: th.vmford.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x68] -vmford.vf v4, v8, fa2, v0.t -# CHECK-INST: vmford.vf v4, v8, fa2, v0.t +th.vmford.vf v4, v8, fa2, v0.t +# CHECK-INST: th.vmford.vf v4, v8, fa2, v0.t # CHECK-ENCODING: [0x57,0x52,0x86,0x68] -vfclass.v v4, v8 -# CHECK-INST: vfclass.v v4, v8 +th.vfclass.v v4, v8 +# CHECK-INST: th.vfclass.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x88,0x8e] -vfclass.v v4, v8, v0.t -# CHECK-INST: vfclass.v v4, v8, v0.t +th.vfclass.v v4, v8, v0.t +# CHECK-INST: th.vfclass.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x88,0x8c] -vfmerge.vfm v4, v8, fa2, v0 -# CHECK-INST: vfmerge.vfm v4, v8, fa2, v0 +th.vfmerge.vfm v4, v8, fa2, v0 +# CHECK-INST: th.vfmerge.vfm v4, v8, fa2, v0 # CHECK-ENCODING: [0x57,0x52,0x86,0x5c] -vfmv.v.f v4, fa1 -# CHECK-INST: vfmv.v.f v4, fa1 +th.vfmv.v.f v4, fa1 +# CHECK-INST: th.vfmv.v.f v4, fa1 # CHECK-ENCODING: [0x57,0xd2,0x05,0x5e] -vfcvt.xu.f.v v4, v8 -# CHECK-INST: vfcvt.xu.f.v v4, v8 +th.vfcvt.xu.f.v v4, v8 +# CHECK-INST: th.vfcvt.xu.f.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x80,0x8a] -vfcvt.x.f.v v4, v8 -# CHECK-INST: vfcvt.x.f.v v4, v8 +th.vfcvt.x.f.v v4, v8 +# CHECK-INST: th.vfcvt.x.f.v v4, v8 # CHECK-ENCODING: [0x57,0x92,0x80,0x8a] -vfcvt.f.xu.v v4, v8 -# CHECK-INST: vfcvt.f.xu.v v4, v8 +th.vfcvt.f.xu.v v4, v8 +# CHECK-INST: th.vfcvt.f.xu.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x81,0x8a] -vfcvt.f.x.v v4, v8 -# CHECK-INST: vfcvt.f.x.v v4, v8 +th.vfcvt.f.x.v v4, v8 +# CHECK-INST: th.vfcvt.f.x.v v4, v8 # CHECK-ENCODING: [0x57,0x92,0x81,0x8a] -vfcvt.xu.f.v v4, v8, v0.t -# CHECK-INST: vfcvt.xu.f.v v4, v8, v0.t +th.vfcvt.xu.f.v v4, v8, v0.t +# CHECK-INST: th.vfcvt.xu.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x80,0x88] -vfcvt.x.f.v v4, v8, v0.t -# CHECK-INST: vfcvt.x.f.v v4, v8, v0.t +th.vfcvt.x.f.v v4, v8, v0.t +# CHECK-INST: th.vfcvt.x.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x92,0x80,0x88] -vfcvt.f.xu.v v4, v8, v0.t -# CHECK-INST: vfcvt.f.xu.v v4, v8, v0.t +th.vfcvt.f.xu.v v4, v8, v0.t +# CHECK-INST: th.vfcvt.f.xu.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x81,0x88] -vfcvt.f.x.v v4, v8, v0.t -# CHECK-INST: vfcvt.f.x.v v4, v8, v0.t +th.vfcvt.f.x.v v4, v8, v0.t +# CHECK-INST: th.vfcvt.f.x.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x92,0x81,0x88] -vfwcvt.xu.f.v v4, v8 -# CHECK-INST: vfwcvt.xu.f.v v4, v8 +th.vfwcvt.xu.f.v v4, v8 +# CHECK-INST: th.vfwcvt.xu.f.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x84,0x8a] -vfwcvt.x.f.v v4, v8 -# CHECK-INST: vfwcvt.x.f.v v4, v8 +th.vfwcvt.x.f.v v4, v8 +# CHECK-INST: th.vfwcvt.x.f.v v4, v8 # CHECK-ENCODING: [0x57,0x92,0x84,0x8a] -vfwcvt.f.xu.v v4, v8 -# CHECK-INST: vfwcvt.f.xu.v v4, v8 +th.vfwcvt.f.xu.v v4, v8 +# CHECK-INST: th.vfwcvt.f.xu.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x85,0x8a] -vfwcvt.f.x.v v4, v8 -# CHECK-INST: vfwcvt.f.x.v v4, v8 +th.vfwcvt.f.x.v v4, v8 +# CHECK-INST: th.vfwcvt.f.x.v v4, v8 # CHECK-ENCODING: [0x57,0x92,0x85,0x8a] -vfwcvt.f.f.v v4, v8 -# CHECK-INST: vfwcvt.f.f.v v4, v8 +th.vfwcvt.f.f.v v4, v8 +# CHECK-INST: th.vfwcvt.f.f.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x86,0x8a] -vfwcvt.xu.f.v v4, v8, v0.t -# CHECK-INST: vfwcvt.xu.f.v v4, v8, v0.t +th.vfwcvt.xu.f.v v4, v8, v0.t +# CHECK-INST: th.vfwcvt.xu.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x84,0x88] -vfwcvt.x.f.v v4, v8, v0.t -# CHECK-INST: vfwcvt.x.f.v v4, v8, v0.t +th.vfwcvt.x.f.v v4, v8, v0.t +# CHECK-INST: th.vfwcvt.x.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x92,0x84,0x88] -vfwcvt.f.xu.v v4, v8, v0.t -# CHECK-INST: vfwcvt.f.xu.v v4, v8, v0.t +th.vfwcvt.f.xu.v v4, v8, v0.t +# CHECK-INST: th.vfwcvt.f.xu.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x85,0x88] -vfwcvt.f.x.v v4, v8, v0.t -# CHECK-INST: vfwcvt.f.x.v v4, v8, v0.t +th.vfwcvt.f.x.v v4, v8, v0.t +# CHECK-INST: th.vfwcvt.f.x.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x92,0x85,0x88] -vfwcvt.f.f.v v4, v8, v0.t -# CHECK-INST: vfwcvt.f.f.v v4, v8, v0.t +th.vfwcvt.f.f.v v4, v8, v0.t +# CHECK-INST: th.vfwcvt.f.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x88] -vfncvt.xu.f.v v4, v8 -# CHECK-INST: vfncvt.xu.f.v v4, v8 +th.vfncvt.xu.f.v v4, v8 +# CHECK-INST: th.vfncvt.xu.f.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x88,0x8a] -vfncvt.x.f.v v4, v8 -# CHECK-INST: vfncvt.x.f.v v4, v8 +th.vfncvt.x.f.v v4, v8 +# CHECK-INST: th.vfncvt.x.f.v v4, v8 # CHECK-ENCODING: [0x57,0x92,0x88,0x8a] -vfncvt.f.xu.v v4, v8 -# CHECK-INST: vfncvt.f.xu.v v4, v8 +th.vfncvt.f.xu.v v4, v8 +# CHECK-INST: th.vfncvt.f.xu.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x89,0x8a] -vfncvt.f.x.v v4, v8 -# CHECK-INST: vfncvt.f.x.v v4, v8 +th.vfncvt.f.x.v v4, v8 +# CHECK-INST: th.vfncvt.f.x.v v4, v8 # CHECK-ENCODING: [0x57,0x92,0x89,0x8a] -vfncvt.f.f.v v4, v8 -# CHECK-INST: vfncvt.f.f.v v4, v8 +th.vfncvt.f.f.v v4, v8 +# CHECK-INST: th.vfncvt.f.f.v v4, v8 # CHECK-ENCODING: [0x57,0x12,0x8a,0x8a] -vfncvt.xu.f.v v4, v8, v0.t -# CHECK-INST: vfncvt.xu.f.v v4, v8, v0.t +th.vfncvt.xu.f.v v4, v8, v0.t +# CHECK-INST: th.vfncvt.xu.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x88,0x88] -vfncvt.x.f.v v4, v8, v0.t -# CHECK-INST: vfncvt.x.f.v v4, v8, v0.t +th.vfncvt.x.f.v v4, v8, v0.t +# CHECK-INST: th.vfncvt.x.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x92,0x88,0x88] -vfncvt.f.xu.v v4, v8, v0.t -# CHECK-INST: vfncvt.f.xu.v v4, v8, v0.t +th.vfncvt.f.xu.v v4, v8, v0.t +# CHECK-INST: th.vfncvt.f.xu.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x89,0x88] -vfncvt.f.x.v v4, v8, v0.t -# CHECK-INST: vfncvt.f.x.v v4, v8, v0.t +th.vfncvt.f.x.v v4, v8, v0.t +# CHECK-INST: th.vfncvt.f.x.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x92,0x89,0x88] -vfncvt.f.f.v v4, v8, v0.t -# CHECK-INST: vfncvt.f.f.v v4, v8, v0.t +th.vfncvt.f.f.v v4, v8, v0.t +# CHECK-INST: th.vfncvt.f.f.v v4, v8, v0.t # CHECK-ENCODING: [0x57,0x12,0x8a,0x88] -vredsum.vs v4, v8, v12 -# CHECK-INST: vredsum.vs v4, v8, v12 +th.vredsum.vs v4, v8, v12 +# CHECK-INST: th.vredsum.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x02] -vredmaxu.vs v4, v8, v8 -# CHECK-INST: vredmaxu.vs v4, v8, v8 +th.vredmaxu.vs v4, v8, v8 +# CHECK-INST: th.vredmaxu.vs v4, v8, v8 # CHECK-ENCODING: [0x57,0x22,0x84,0x1a] -vredmax.vs v4, v8, v8 -# CHECK-INST: vredmax.vs v4, v8, v8 +th.vredmax.vs v4, v8, v8 +# CHECK-INST: th.vredmax.vs v4, v8, v8 # CHECK-ENCODING: [0x57,0x22,0x84,0x1e] -vredminu.vs v4, v8, v8 -# CHECK-INST: vredminu.vs v4, v8, v8 +th.vredminu.vs v4, v8, v8 +# CHECK-INST: th.vredminu.vs v4, v8, v8 # CHECK-ENCODING: [0x57,0x22,0x84,0x12] -vredmin.vs v4, v8, v8 -# CHECK-INST: vredmin.vs v4, v8, v8 +th.vredmin.vs v4, v8, v8 +# CHECK-INST: th.vredmin.vs v4, v8, v8 # CHECK-ENCODING: [0x57,0x22,0x84,0x16] -vredand.vs v4, v8, v12 -# CHECK-INST: vredand.vs v4, v8, v12 +th.vredand.vs v4, v8, v12 +# CHECK-INST: th.vredand.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x06] -vredor.vs v4, v8, v12 -# CHECK-INST: vredor.vs v4, v8, v12 +th.vredor.vs v4, v8, v12 +# CHECK-INST: th.vredor.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x0a] -vredxor.vs v4, v8, v12 -# CHECK-INST: vredxor.vs v4, v8, v12 +th.vredxor.vs v4, v8, v12 +# CHECK-INST: th.vredxor.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x0e] -vredsum.vs v4, v8, v12, v0.t -# CHECK-INST: vredsum.vs v4, v8, v12, v0.t +th.vredsum.vs v4, v8, v12, v0.t +# CHECK-INST: th.vredsum.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x00] -vredmaxu.vs v4, v8, v8, v0.t -# CHECK-INST: vredmaxu.vs v4, v8, v8, v0.t +th.vredmaxu.vs v4, v8, v8, v0.t +# CHECK-INST: th.vredmaxu.vs v4, v8, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x84,0x18] -vredmax.vs v4, v8, v8, v0.t -# CHECK-INST: vredmax.vs v4, v8, v8, v0.t +th.vredmax.vs v4, v8, v8, v0.t +# CHECK-INST: th.vredmax.vs v4, v8, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x84,0x1c] -vredminu.vs v4, v8, v8, v0.t -# CHECK-INST: vredminu.vs v4, v8, v8, v0.t +th.vredminu.vs v4, v8, v8, v0.t +# CHECK-INST: th.vredminu.vs v4, v8, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x84,0x10] -vredmin.vs v4, v8, v8, v0.t -# CHECK-INST: vredmin.vs v4, v8, v8, v0.t +th.vredmin.vs v4, v8, v8, v0.t +# CHECK-INST: th.vredmin.vs v4, v8, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x84,0x14] -vredand.vs v4, v8, v12, v0.t -# CHECK-INST: vredand.vs v4, v8, v12, v0.t +th.vredand.vs v4, v8, v12, v0.t +# CHECK-INST: th.vredand.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x04] -vredor.vs v4, v8, v12, v0.t -# CHECK-INST: vredor.vs v4, v8, v12, v0.t +th.vredor.vs v4, v8, v12, v0.t +# CHECK-INST: th.vredor.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x08] -vredxor.vs v4, v8, v12, v0.t -# CHECK-INST: vredxor.vs v4, v8, v12, v0.t +th.vredxor.vs v4, v8, v12, v0.t +# CHECK-INST: th.vredxor.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x22,0x86,0x0c] -vwredsumu.vs v4, v8, v12 -# CHECK-INST: vwredsumu.vs v4, v8, v12 +th.vwredsumu.vs v4, v8, v12 +# CHECK-INST: th.vwredsumu.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xc2] -vwredsum.vs v4, v8, v12 -# CHECK-INST: vwredsum.vs v4, v8, v12 +th.vwredsum.vs v4, v8, v12 +# CHECK-INST: th.vwredsum.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0xc6] -vwredsumu.vs v4, v8, v12, v0.t -# CHECK-INST: vwredsumu.vs v4, v8, v12, v0.t +th.vwredsumu.vs v4, v8, v12, v0.t +# CHECK-INST: th.vwredsumu.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xc0] -vwredsum.vs v4, v8, v12, v0.t -# CHECK-INST: vwredsum.vs v4, v8, v12, v0.t +th.vwredsum.vs v4, v8, v12, v0.t +# CHECK-INST: th.vwredsum.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0xc4] -vfredosum.vs v4, v8, v12 -# CHECK-INST: vfredosum.vs v4, v8, v12 +th.vfredosum.vs v4, v8, v12 +# CHECK-INST: th.vfredosum.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x0e] -vfredsum.vs v4, v8, v12 -# CHECK-INST: vfredsum.vs v4, v8, v12 +th.vfredsum.vs v4, v8, v12 +# CHECK-INST: th.vfredsum.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x06] -vfredmax.vs v4, v8, v12 -# CHECK-INST: vfredmax.vs v4, v8, v12 +th.vfredmax.vs v4, v8, v12 +# CHECK-INST: th.vfredmax.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x1e] -vfredmin.vs v4, v8, v12 -# CHECK-INST: vfredmin.vs v4, v8, v12 +th.vfredmin.vs v4, v8, v12 +# CHECK-INST: th.vfredmin.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0x16] -vfredosum.vs v4, v8, v12, v0.t -# CHECK-INST: vfredosum.vs v4, v8, v12, v0.t +th.vfredosum.vs v4, v8, v12, v0.t +# CHECK-INST: th.vfredosum.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x0c] -vfredsum.vs v4, v8, v12, v0.t -# CHECK-INST: vfredsum.vs v4, v8, v12, v0.t +th.vfredsum.vs v4, v8, v12, v0.t +# CHECK-INST: th.vfredsum.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x04] -vfredmax.vs v4, v8, v12, v0.t -# CHECK-INST: vfredmax.vs v4, v8, v12, v0.t +th.vfredmax.vs v4, v8, v12, v0.t +# CHECK-INST: th.vfredmax.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x1c] -vfredmin.vs v4, v8, v12, v0.t -# CHECK-INST: vfredmin.vs v4, v8, v12, v0.t +th.vfredmin.vs v4, v8, v12, v0.t +# CHECK-INST: th.vfredmin.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0x14] -vfwredosum.vs v4, v8, v12 -# CHECK-INST: vfwredosum.vs v4, v8, v12 +th.vfwredosum.vs v4, v8, v12 +# CHECK-INST: th.vfwredosum.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xce] -vfwredsum.vs v4, v8, v12 -# CHECK-INST: vfwredsum.vs v4, v8, v12 +th.vfwredsum.vs v4, v8, v12 +# CHECK-INST: th.vfwredsum.vs v4, v8, v12 # CHECK-ENCODING: [0x57,0x12,0x86,0xc6] -vfwredosum.vs v4, v8, v12, v0.t -# CHECK-INST: vfwredosum.vs v4, v8, v12, v0.t +th.vfwredosum.vs v4, v8, v12, v0.t +# CHECK-INST: th.vfwredosum.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xcc] -vfwredsum.vs v4, v8, v12, v0.t -# CHECK-INST: vfwredsum.vs v4, v8, v12, v0.t +th.vfwredsum.vs v4, v8, v12, v0.t +# CHECK-INST: th.vfwredsum.vs v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x12,0x86,0xc4] -vmcpy.m v4, v8 -# CHECK-INST: vmcpy.m v4, v8 +th.vmcpy.m v4, v8 +# CHECK-INST: th.vmcpy.m v4, v8 # CHECK-ENCODING: [0x57,0x22,0x84,0x66] -vmclr.m v4 -# CHECK-INST: vmclr.m v4 +th.vmclr.m v4 +# CHECK-INST: th.vmclr.m v4 # CHECK-ENCODING: [0x57,0x22,0x42,0x6e] -vmset.m v4 -# CHECK-INST: vmset.m v4 +th.vmset.m v4 +# CHECK-INST: th.vmset.m v4 # CHECK-ENCODING: [0x57,0x22,0x42,0x7e] -vmnot.m v4, v8 -# CHECK-INST: vmnot.m v4, v8 +th.vmnot.m v4, v8 +# CHECK-INST: th.vmnot.m v4, v8 # CHECK-ENCODING: [0x57,0x22,0x84,0x76] -vmand.mm v4, v8, v12 -# CHECK-INST: vmand.mm v4, v8, v12 +th.vmand.mm v4, v8, v12 +# CHECK-INST: th.vmand.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x66] -vmnand.mm v4, v8, v12 -# CHECK-INST: vmnand.mm v4, v8, v12 +th.vmnand.mm v4, v8, v12 +# CHECK-INST: th.vmnand.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x76] -vmandnot.mm v4, v8, v12 -# CHECK-INST: vmandnot.mm v4, v8, v12 +th.vmandnot.mm v4, v8, v12 +# CHECK-INST: th.vmandnot.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x62] -vmxor.mm v4, v8, v12 -# CHECK-INST: vmxor.mm v4, v8, v12 +th.vmxor.mm v4, v8, v12 +# CHECK-INST: th.vmxor.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x6e] -vmor.mm v4, v8, v12 -# CHECK-INST: vmor.mm v4, v8, v12 +th.vmor.mm v4, v8, v12 +# CHECK-INST: th.vmor.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x6a] -vmnor.mm v4, v8, v12 -# CHECK-INST: vmnor.mm v4, v8, v12 +th.vmnor.mm v4, v8, v12 +# CHECK-INST: th.vmnor.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x7a] -vmornot.mm v4, v8, v12 -# CHECK-INST: vmornot.mm v4, v8, v12 +th.vmornot.mm v4, v8, v12 +# CHECK-INST: th.vmornot.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x72] -vmxnor.mm v4, v8, v12 -# CHECK-INST: vmxnor.mm v4, v8, v12 +th.vmxnor.mm v4, v8, v12 +# CHECK-INST: th.vmxnor.mm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x7e] -vmpopc.m a0, v12 -# CHECK-INST: vmpopc.m a0, v12 +th.vmpopc.m a0, v12 +# CHECK-INST: th.vmpopc.m a0, v12 # CHECK-ENCODING: [0x57,0x25,0xc0,0x52] -vmfirst.m a0, v12 -# CHECK-INST: vmfirst.m a0, v12 +th.vmfirst.m a0, v12 +# CHECK-INST: th.vmfirst.m a0, v12 # CHECK-ENCODING: [0x57,0x25,0xc0,0x56] -vmsbf.m v4, v8 -# CHECK-INST: vmsbf.m v4, v8 +th.vmsbf.m v4, v8 +# CHECK-INST: th.vmsbf.m v4, v8 # CHECK-ENCODING: [0x57,0xa2,0x80,0x5a] -vmsif.m v4, v8 -# CHECK-INST: vmsif.m v4, v8 +th.vmsif.m v4, v8 +# CHECK-INST: th.vmsif.m v4, v8 # CHECK-ENCODING: [0x57,0xa2,0x81,0x5a] -vmsof.m v4, v8 -# CHECK-INST: vmsof.m v4, v8 +th.vmsof.m v4, v8 +# CHECK-INST: th.vmsof.m v4, v8 # CHECK-ENCODING: [0x57,0x22,0x81,0x5a] -viota.m v4, v8 -# CHECK-INST: viota.m v4, v8 +th.viota.m v4, v8 +# CHECK-INST: th.viota.m v4, v8 # CHECK-ENCODING: [0x57,0x22,0x88,0x5a] -vid.v v4 -# CHECK-INST: vid.v v4 +th.vid.v v4 +# CHECK-INST: th.vid.v v4 # CHECK-ENCODING: [0x57,0xa2,0x08,0x5a] -vmpopc.m a0, v12, v0.t -# CHECK-INST: vmpopc.m a0, v12, v0.t +th.vmpopc.m a0, v12, v0.t +# CHECK-INST: th.vmpopc.m a0, v12, v0.t # CHECK-ENCODING: [0x57,0x25,0xc0,0x50] -vmfirst.m a0, v12, v0.t -# CHECK-INST: vmfirst.m a0, v12, v0.t +th.vmfirst.m a0, v12, v0.t +# CHECK-INST: th.vmfirst.m a0, v12, v0.t # CHECK-ENCODING: [0x57,0x25,0xc0,0x54] -vmsbf.m v4, v8, v0.t -# CHECK-INST: vmsbf.m v4, v8, v0.t +th.vmsbf.m v4, v8, v0.t +# CHECK-INST: th.vmsbf.m v4, v8, v0.t # CHECK-ENCODING: [0x57,0xa2,0x80,0x58] -vmsif.m v4, v8, v0.t -# CHECK-INST: vmsif.m v4, v8, v0.t +th.vmsif.m v4, v8, v0.t +# CHECK-INST: th.vmsif.m v4, v8, v0.t # CHECK-ENCODING: [0x57,0xa2,0x81,0x58] -vmsof.m v4, v8, v0.t -# CHECK-INST: vmsof.m v4, v8, v0.t +th.vmsof.m v4, v8, v0.t +# CHECK-INST: th.vmsof.m v4, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x81,0x58] -viota.m v4, v8, v0.t -# CHECK-INST: viota.m v4, v8, v0.t +th.viota.m v4, v8, v0.t +# CHECK-INST: th.viota.m v4, v8, v0.t # CHECK-ENCODING: [0x57,0x22,0x88,0x58] -vid.v v4, v0.t -# CHECK-INST: vid.v v4, v0.t +th.vid.v v4, v0.t +# CHECK-INST: th.vid.v v4, v0.t # CHECK-ENCODING: [0x57,0xa2,0x08,0x58] -vmv.x.s a0, v12 -# CHECK-INST: vmv.x.s a0, v12 +th.vmv.x.s a0, v12 +# CHECK-INST: th.vmv.x.s a0, v12 # CHECK-ENCODING: [0x57,0x25,0xc0,0x32] -vext.x.v a0, v12, a2 -# CHECK-INST: vext.x.v a0, v12, a2 +th.vext.x.v a0, v12, a2 +# CHECK-INST: th.vext.x.v a0, v12, a2 # CHECK-ENCODING: [0x57,0x25,0xc6,0x32] -vmv.s.x v4, a0 -# CHECK-INST: vmv.s.x v4, a0 +th.vmv.s.x v4, a0 +# CHECK-INST: th.vmv.s.x v4, a0 # CHECK-ENCODING: [0x57,0x62,0x05,0x36] -vfmv.f.s fa0, v8 -# CHECK-INST: vfmv.f.s fa0, v8 +th.vfmv.f.s fa0, v8 +# CHECK-INST: th.vfmv.f.s fa0, v8 # CHECK-ENCODING: [0x57,0x15,0x80,0x32] -vfmv.s.f v4, fa1 -# CHECK-INST: vfmv.s.f v4, fa1 +th.vfmv.s.f v4, fa1 +# CHECK-INST: th.vfmv.s.f v4, fa1 # CHECK-ENCODING: [0x57,0xd2,0x05,0x36] -vslideup.vx v4, v8, a1 -# CHECK-INST: vslideup.vx v4, v8, a1 +th.vslideup.vx v4, v8, a1 +# CHECK-INST: th.vslideup.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x3a] -vslideup.vi v4, v8, 0 -# CHECK-INST: vslideup.vi v4, v8, 0 +th.vslideup.vi v4, v8, 0 +# CHECK-INST: th.vslideup.vi v4, v8, 0 # CHECK-ENCODING: [0x57,0x32,0x80,0x3a] -vslideup.vi v4, v8, 31 -# CHECK-INST: vslideup.vi v4, v8, 31 +th.vslideup.vi v4, v8, 31 +# CHECK-INST: th.vslideup.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0x3a] -vslidedown.vx v4, v8, a1 -# CHECK-INST: vslidedown.vx v4, v8, a1 +th.vslidedown.vx v4, v8, a1 +# CHECK-INST: th.vslidedown.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x3e] -vslidedown.vi v4, v8, 0 -# CHECK-INST: vslidedown.vi v4, v8, 0 +th.vslidedown.vi v4, v8, 0 +# CHECK-INST: th.vslidedown.vi v4, v8, 0 # CHECK-ENCODING: [0x57,0x32,0x80,0x3e] -vslidedown.vi v4, v8, 31 -# CHECK-INST: vslidedown.vi v4, v8, 31 +th.vslidedown.vi v4, v8, 31 +# CHECK-INST: th.vslidedown.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0x3e] -vslideup.vx v4, v8, a1, v0.t -# CHECK-INST: vslideup.vx v4, v8, a1, v0.t +th.vslideup.vx v4, v8, a1, v0.t +# CHECK-INST: th.vslideup.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x38] -vslideup.vi v4, v8, 0, v0.t -# CHECK-INST: vslideup.vi v4, v8, 0, v0.t +th.vslideup.vi v4, v8, 0, v0.t +# CHECK-INST: th.vslideup.vi v4, v8, 0, v0.t # CHECK-ENCODING: [0x57,0x32,0x80,0x38] -vslideup.vi v4, v8, 31, v0.t -# CHECK-INST: vslideup.vi v4, v8, 31, v0.t +th.vslideup.vi v4, v8, 31, v0.t +# CHECK-INST: th.vslideup.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0x38] -vslidedown.vx v4, v8, a1, v0.t -# CHECK-INST: vslidedown.vx v4, v8, a1, v0.t +th.vslidedown.vx v4, v8, a1, v0.t +# CHECK-INST: th.vslidedown.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x3c] -vslidedown.vi v4, v8, 0, v0.t -# CHECK-INST: vslidedown.vi v4, v8, 0, v0.t +th.vslidedown.vi v4, v8, 0, v0.t +# CHECK-INST: th.vslidedown.vi v4, v8, 0, v0.t # CHECK-ENCODING: [0x57,0x32,0x80,0x3c] -vslidedown.vi v4, v8, 31, v0.t -# CHECK-INST: vslidedown.vi v4, v8, 31, v0.t +th.vslidedown.vi v4, v8, 31, v0.t +# CHECK-INST: th.vslidedown.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0x3c] -vslide1up.vx v4, v8, a1 -# CHECK-INST: vslide1up.vx v4, v8, a1 +th.vslide1up.vx v4, v8, a1 +# CHECK-INST: th.vslide1up.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x3a] -vslide1down.vx v4, v8, a1 -# CHECK-INST: vslide1down.vx v4, v8, a1 +th.vslide1down.vx v4, v8, a1 +# CHECK-INST: th.vslide1down.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xe2,0x85,0x3e] -vslide1up.vx v4, v8, a1, v0.t -# CHECK-INST: vslide1up.vx v4, v8, a1, v0.t +th.vslide1up.vx v4, v8, a1, v0.t +# CHECK-INST: th.vslide1up.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x38] -vslide1down.vx v4, v8, a1, v0.t -# CHECK-INST: vslide1down.vx v4, v8, a1, v0.t +th.vslide1down.vx v4, v8, a1, v0.t +# CHECK-INST: th.vslide1down.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xe2,0x85,0x3c] -vrgather.vv v4, v8, v12 -# CHECK-INST: vrgather.vv v4, v8, v12 +th.vrgather.vv v4, v8, v12 +# CHECK-INST: th.vrgather.vv v4, v8, v12 # CHECK-ENCODING: [0x57,0x02,0x86,0x32] -vrgather.vx v4, v8, a1 -# CHECK-INST: vrgather.vx v4, v8, a1 +th.vrgather.vx v4, v8, a1 +# CHECK-INST: th.vrgather.vx v4, v8, a1 # CHECK-ENCODING: [0x57,0xc2,0x85,0x32] -vrgather.vi v4, v8, 0 -# CHECK-INST: vrgather.vi v4, v8, 0 +th.vrgather.vi v4, v8, 0 +# CHECK-INST: th.vrgather.vi v4, v8, 0 # CHECK-ENCODING: [0x57,0x32,0x80,0x32] -vrgather.vi v4, v8, 31 -# CHECK-INST: vrgather.vi v4, v8, 31 +th.vrgather.vi v4, v8, 31 +# CHECK-INST: th.vrgather.vi v4, v8, 31 # CHECK-ENCODING: [0x57,0xb2,0x8f,0x32] -vrgather.vv v4, v8, v12, v0.t -# CHECK-INST: vrgather.vv v4, v8, v12, v0.t +th.vrgather.vv v4, v8, v12, v0.t +# CHECK-INST: th.vrgather.vv v4, v8, v12, v0.t # CHECK-ENCODING: [0x57,0x02,0x86,0x30] -vrgather.vx v4, v8, a1, v0.t -# CHECK-INST: vrgather.vx v4, v8, a1, v0.t +th.vrgather.vx v4, v8, a1, v0.t +# CHECK-INST: th.vrgather.vx v4, v8, a1, v0.t # CHECK-ENCODING: [0x57,0xc2,0x85,0x30] -vrgather.vi v4, v8, 0, v0.t -# CHECK-INST: vrgather.vi v4, v8, 0, v0.t +th.vrgather.vi v4, v8, 0, v0.t +# CHECK-INST: th.vrgather.vi v4, v8, 0, v0.t # CHECK-ENCODING: [0x57,0x32,0x80,0x30] -vrgather.vi v4, v8, 31, v0.t -# CHECK-INST: vrgather.vi v4, v8, 31, v0.t +th.vrgather.vi v4, v8, 31, v0.t +# CHECK-INST: th.vrgather.vi v4, v8, 31, v0.t # CHECK-ENCODING: [0x57,0xb2,0x8f,0x30] -vcompress.vm v4, v8, v12 -# CHECK-INST: vcompress.vm v4, v8, v12 +th.vcompress.vm v4, v8, v12 +# CHECK-INST: th.vcompress.vm v4, v8, v12 # CHECK-ENCODING: [0x57,0x22,0x86,0x5e] csrr a0, vstart diff --git a/llvm/test/MC/RISCV/rvv0p71/vsetvl-invaild.s b/llvm/test/MC/RISCV/rvv0p71/vsetvl-invaild.s index 4952a606c0b15..ddb5b544f1dee 100644 --- a/llvm/test/MC/RISCV/rvv0p71/vsetvl-invaild.s +++ b/llvm/test/MC/RISCV/rvv0p71/vsetvl-invaild.s @@ -1,8 +1,8 @@ -# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+xtheadv %s 2>&1 | FileCheck %s -# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+xtheadvector %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s 2>&1 | FileCheck %s -vsetvli a2, a1, e8 -# CHECK: error: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] +th.vsetvli a2, a1, e8 +# CHECK: error: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8],d[1|2|4|8] for RVV0.71 vsetivli a2, 15, 208 # CHECK: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} diff --git a/llvm/test/MC/RISCV/rvv0p71/vsetvl.s b/llvm/test/MC/RISCV/rvv0p71/vsetvl.s index f26f6c76652ca..b865bdbd39a49 100644 --- a/llvm/test/MC/RISCV/rvv0p71/vsetvl.s +++ b/llvm/test/MC/RISCV/rvv0p71/vsetvl.s @@ -1,118 +1,118 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # reserved filed: vsew[2:0]=0b1xx, non-zero bits 8/9/10. -vsetvli a2, a0, 0x224 -# CHECK-INST: vsetvli a2, a0, 548 +th.vsetvli a2, a0, 0x224 +# CHECK-INST: th.vsetvli a2, a0, 548 # CHECK-ENCODING: [0x57,0x76,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 45 22 -vsetvli a2, a0, 0x8 -# CHECK-INST: vsetvli a2, a0, e32, m1, d1 +th.vsetvli a2, a0, 0x8 +# CHECK-INST: th.vsetvli a2, a0, e32, m1, d1 # CHECK-ENCODING: [0x57,0x76,0x85,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 85 00 -vsetvli a2, a0, 0x29 -# CHECK-INST: vsetvli a2, a0, e32, m2, d2 +th.vsetvli a2, a0, 0x29 +# CHECK-INST: th.vsetvli a2, a0, e32, m2, d2 # CHECK-ENCODING: [0x57,0x76,0x95,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 95 02 -vsetvli a2, a0, 0x4a -# CHECK-INST: vsetvli a2, a0, e32, m4, d4 +th.vsetvli a2, a0, 0x4a +# CHECK-INST: th.vsetvli a2, a0, e32, m4, d4 # CHECK-ENCODING: [0x57,0x76,0xa5,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 a5 04 -vsetvli a2, a0, 0x6b -# CHECK-INST: vsetvli a2, a0, e32, m8, d8 +th.vsetvli a2, a0, 0x6b +# CHECK-INST: th.vsetvli a2, a0, e32, m8, d8 # CHECK-ENCODING: [0x57,0x76,0xb5,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 b5 06 -vsetvli a2, a0, 104 -# CHECK-INST: vsetvli a2, a0, e32, m1, d8 +th.vsetvli a2, a0, 104 +# CHECK-INST: th.vsetvli a2, a0, e32, m1, d8 # CHECK-ENCODING: [0x57,0x76,0x85,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 85 06 -vsetvli a2, a0, e32, m1, d1 -# CHECK-INST: vsetvli a2, a0, e32, m1, d1 +th.vsetvli a2, a0, e32, m1, d1 +# CHECK-INST: th.vsetvli a2, a0, e32, m1, d1 # CHECK-ENCODING: [0x57,0x76,0x85,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 85 00 -vsetvli a2, a0, e32, m2, d2 -# CHECK-INST: vsetvli a2, a0, e32, m2, d2 +th.vsetvli a2, a0, e32, m2, d2 +# CHECK-INST: th.vsetvli a2, a0, e32, m2, d2 # CHECK-ENCODING: [0x57,0x76,0x95,0x02] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 95 02 -vsetvli a2, a0, e32, m4, d4 -# CHECK-INST: vsetvli a2, a0, e32, m4, d4 +th.vsetvli a2, a0, e32, m4, d4 +# CHECK-INST: th.vsetvli a2, a0, e32, m4, d4 # CHECK-ENCODING: [0x57,0x76,0xa5,0x04] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 a5 04 -vsetvli a2, a0, e32, m8, d8 -# CHECK-INST: vsetvli a2, a0, e32, m8, d8 +th.vsetvli a2, a0, e32, m8, d8 +# CHECK-INST: th.vsetvli a2, a0, e32, m8, d8 # CHECK-ENCODING: [0x57,0x76,0xb5,0x06] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 b5 06 -vsetvli a2, a0, e32, m2, d1 -# CHECK-INST: vsetvli a2, a0, e32, m2, d1 +th.vsetvli a2, a0, e32, m2, d1 +# CHECK-INST: th.vsetvli a2, a0, e32, m2, d1 # CHECK-ENCODING: [0x57,0x76,0x95,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 95 00 -vsetvli a2, a0, e32, m4, d1 -# CHECK-INST: vsetvli a2, a0, e32, m4, d1 +th.vsetvli a2, a0, e32, m4, d1 +# CHECK-INST: th.vsetvli a2, a0, e32, m4, d1 # CHECK-ENCODING: [0x57,0x76,0xa5,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 a5 00 -vsetvli a2, a0, e32, m8, d1 -# CHECK-INST: vsetvli a2, a0, e32, m8, d1 +th.vsetvli a2, a0, e32, m8, d1 +# CHECK-INST: th.vsetvli a2, a0, e32, m8, d1 # CHECK-ENCODING: [0x57,0x76,0xb5,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 b5 00 -vsetvli a2, a0, e8, m1, d1 -# CHECK-INST: vsetvli a2, a0, e8, m1, d1 +th.vsetvli a2, a0, e8, m1, d1 +# CHECK-INST: th.vsetvli a2, a0, e8, m1, d1 # CHECK-ENCODING: [0x57,0x76,0x05,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 05 00 -vsetvli a2, a0, e16, m1, d1 -# CHECK-INST: vsetvli a2, a0, e16, m1, d1 +th.vsetvli a2, a0, e16, m1, d1 +# CHECK-INST: th.vsetvli a2, a0, e16, m1, d1 # CHECK-ENCODING: [0x57,0x76,0x45,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 45 00 -vsetvli a2, a0, e32, m1, d1 -# CHECK-INST: vsetvli a2, a0, e32, m1, d1 +th.vsetvli a2, a0, e32, m1, d1 +# CHECK-INST: th.vsetvli a2, a0, e32, m1, d1 # CHECK-ENCODING: [0x57,0x76,0x85,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 85 00 -vsetvli a2, a0, e64, m1, d1 -# CHECK-INST: vsetvli a2, a0, e64, m1, d1 +th.vsetvli a2, a0, e64, m1, d1 +# CHECK-INST: th.vsetvli a2, a0, e64, m1, d1 # CHECK-ENCODING: [0x57,0x76,0xc5,0x00] -# CHECK-ERROR: invalid operand for instruction +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 c5 00 -vsetvl a2, a0, a1 -# CHECK-INST: vsetvl a2, a0, a1 +th.vsetvl a2, a0, a1 +# CHECK-INST: th.vsetvl a2, a0, a1 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 76 b5 80 diff --git a/llvm/test/MC/RISCV/rvv0p71/xor.s b/llvm/test/MC/RISCV/rvv0p71/xor.s index cfe1fb2585e74..5688164c2be6d 100644 --- a/llvm/test/MC/RISCV/rvv0p71/xor.s +++ b/llvm/test/MC/RISCV/rvv0p71/xor.s @@ -1,45 +1,45 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vxor.vv v8, v4, v20, v0.t -# CHECK-INST: vxor.vv v8, v4, v20, v0.t +th.vxor.vv v8, v4, v20, v0.t +# CHECK-INST: th.vxor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 2c -vxor.vv v8, v4, v20 -# CHECK-INST: vxor.vv v8, v4, v20 +th.vxor.vv v8, v4, v20 +# CHECK-INST: th.vxor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 04 4a 2e -vxor.vx v8, v4, a0, v0.t -# CHECK-INST: vxor.vx v8, v4, a0, v0.t +th.vxor.vx v8, v4, a0, v0.t +# CHECK-INST: th.vxor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 2c -vxor.vx v8, v4, a0 -# CHECK-INST: vxor.vx v8, v4, a0 +th.vxor.vx v8, v4, a0 +# CHECK-INST: th.vxor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 44 45 2e -vxor.vi v8, v4, 15, v0.t -# CHECK-INST: vxor.vi v8, v4, 15, v0.t +th.vxor.vi v8, v4, 15, v0.t +# CHECK-INST: th.vxor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 2c -vxor.vi v8, v4, 15 -# CHECK-INST: vxor.vi v8, v4, 15 +th.vxor.vi v8, v4, 15 +# CHECK-INST: th.vxor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions){{$}} # CHECK-UNKNOWN: 57 b4 47 2e diff --git a/llvm/test/MC/RISCV/rvv0p71/zvlsseg.s b/llvm/test/MC/RISCV/rvv0p71/zvlsseg.s index e889e6c2a9dec..ba79267f281df 100644 --- a/llvm/test/MC/RISCV/rvv0p71/zvlsseg.s +++ b/llvm/test/MC/RISCV/rvv0p71/zvlsseg.s @@ -1,3370 +1,3370 @@ -# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadv,+xtheadvlsseg %s \ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvector,+xtheadvlsseg %s \ # RUN: --riscv-no-aliases \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv,+xtheadvlsseg %s \ -# RUN: | llvm-objdump -d --mattr=+xtheadv,+xtheadvlsseg -M no-aliases - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector,+xtheadvlsseg %s \ +# RUN: | llvm-objdump -d --mattr=+xtheadvector,+xtheadvlsseg -M no-aliases - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadv,+xtheadvlsseg %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvector,+xtheadvlsseg %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vlseg2b.v v8, (a0), v0.t -# CHECK-INST: vlseg2b.v v8, (a0), v0.t +th.vlseg2b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x30] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 30 -vlseg2b.v v8, (a0) -# CHECK-INST: vlseg2b.v v8, (a0) +th.vlseg2b.v v8, (a0) +# CHECK-INST: th.vlseg2b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x32] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 32 -vlseg2h.v v8, (a0), v0.t -# CHECK-INST: vlseg2h.v v8, (a0), v0.t +th.vlseg2h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x30] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 30 -vlseg2h.v v8, (a0) -# CHECK-INST: vlseg2h.v v8, (a0) +th.vlseg2h.v v8, (a0) +# CHECK-INST: th.vlseg2h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x32] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 32 -vlseg2w.v v8, (a0), v0.t -# CHECK-INST: vlseg2w.v v8, (a0), v0.t +th.vlseg2w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x30] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 30 -vlseg2w.v v8, (a0) -# CHECK-INST: vlseg2w.v v8, (a0) +th.vlseg2w.v v8, (a0) +# CHECK-INST: th.vlseg2w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x32] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 32 -vlseg2bu.v v8, (a0), v0.t -# CHECK-INST: vlseg2bu.v v8, (a0), v0.t +th.vlseg2bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 20 -vlseg2bu.v v8, (a0) -# CHECK-INST: vlseg2bu.v v8, (a0) +th.vlseg2bu.v v8, (a0) +# CHECK-INST: th.vlseg2bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 22 -vlseg2hu.v v8, (a0), v0.t -# CHECK-INST: vlseg2hu.v v8, (a0), v0.t +th.vlseg2hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 20 -vlseg2hu.v v8, (a0) -# CHECK-INST: vlseg2hu.v v8, (a0) +th.vlseg2hu.v v8, (a0) +# CHECK-INST: th.vlseg2hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 22 -vlseg2wu.v v8, (a0), v0.t -# CHECK-INST: vlseg2wu.v v8, (a0), v0.t +th.vlseg2wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 20 -vlseg2wu.v v8, (a0) -# CHECK-INST: vlseg2wu.v v8, (a0) +th.vlseg2wu.v v8, (a0) +# CHECK-INST: th.vlseg2wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 22 -vlseg2e.v v8, (a0), v0.t -# CHECK-INST: vlseg2e.v v8, (a0), v0.t +th.vlseg2e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 20 -vlseg2e.v v8, (a0) -# CHECK-INST: vlseg2e.v v8, (a0) +th.vlseg2e.v v8, (a0) +# CHECK-INST: th.vlseg2e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 22 -vsseg2b.v v8, (a0), v0.t -# CHECK-INST: vsseg2b.v v8, (a0), v0.t +th.vsseg2b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg2b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 20 -vsseg2b.v v8, (a0) -# CHECK-INST: vsseg2b.v v8, (a0) +th.vsseg2b.v v8, (a0) +# CHECK-INST: th.vsseg2b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 22 -vsseg2h.v v8, (a0), v0.t -# CHECK-INST: vsseg2h.v v8, (a0), v0.t +th.vsseg2h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg2h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 20 -vsseg2h.v v8, (a0) -# CHECK-INST: vsseg2h.v v8, (a0) +th.vsseg2h.v v8, (a0) +# CHECK-INST: th.vsseg2h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 22 -vsseg2w.v v8, (a0), v0.t -# CHECK-INST: vsseg2w.v v8, (a0), v0.t +th.vsseg2w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg2w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 20 -vsseg2w.v v8, (a0) -# CHECK-INST: vsseg2w.v v8, (a0) +th.vsseg2w.v v8, (a0) +# CHECK-INST: th.vsseg2w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 22 -vsseg2e.v v8, (a0), v0.t -# CHECK-INST: vsseg2e.v v8, (a0), v0.t +th.vsseg2e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg2e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0x20] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 20 -vsseg2e.v v8, (a0) -# CHECK-INST: vsseg2e.v v8, (a0) +th.vsseg2e.v v8, (a0) +# CHECK-INST: th.vsseg2e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0x22] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 22 -vlseg2bff.v v8, (a0) -# CHECK-INST: vlseg2bff.v v8, (a0) +th.vlseg2bff.v v8, (a0) +# CHECK-INST: th.vlseg2bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x33] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 33 -vlseg2bff.v v8, (a0), v0.t -# CHECK-INST: vlseg2bff.v v8, (a0), v0.t +th.vlseg2bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x31] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 31 -vlseg2hff.v v8, (a0) -# CHECK-INST: vlseg2hff.v v8, (a0) +th.vlseg2hff.v v8, (a0) +# CHECK-INST: th.vlseg2hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x33] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 33 -vlseg2hff.v v8, (a0), v0.t -# CHECK-INST: vlseg2hff.v v8, (a0), v0.t +th.vlseg2hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x31] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 31 -vlseg2wff.v v8, (a0) -# CHECK-INST: vlseg2wff.v v8, (a0) +th.vlseg2wff.v v8, (a0) +# CHECK-INST: th.vlseg2wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x33] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 33 -vlseg2wff.v v8, (a0), v0.t -# CHECK-INST: vlseg2wff.v v8, (a0), v0.t +th.vlseg2wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x31] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 31 -vlseg2buff.v v8, (a0) -# CHECK-INST: vlseg2buff.v v8, (a0) +th.vlseg2buff.v v8, (a0) +# CHECK-INST: th.vlseg2buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x23] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 23 -vlseg2buff.v v8, (a0), v0.t -# CHECK-INST: vlseg2buff.v v8, (a0), v0.t +th.vlseg2buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x21] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 21 -vlseg2huff.v v8, (a0) -# CHECK-INST: vlseg2huff.v v8, (a0) +th.vlseg2huff.v v8, (a0) +# CHECK-INST: th.vlseg2huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x23] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 23 -vlseg2huff.v v8, (a0), v0.t -# CHECK-INST: vlseg2huff.v v8, (a0), v0.t +th.vlseg2huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x21] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 21 -vlseg2wuff.v v8, (a0) -# CHECK-INST: vlseg2wuff.v v8, (a0) +th.vlseg2wuff.v v8, (a0) +# CHECK-INST: th.vlseg2wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x23] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 23 -vlseg2wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg2wuff.v v8, (a0), v0.t +th.vlseg2wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x21] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 21 -vlseg2eff.v v8, (a0) -# CHECK-INST: vlseg2eff.v v8, (a0) +th.vlseg2eff.v v8, (a0) +# CHECK-INST: th.vlseg2eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x23] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 23 -vlseg2eff.v v8, (a0), v0.t -# CHECK-INST: vlseg2eff.v v8, (a0), v0.t +th.vlseg2eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg2eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x21] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 21 -vlsseg2b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2b.v v8, (a0), a1, v0.t +th.vlsseg2b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x38] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 38 -vlsseg2b.v v8, (a0), a1 -# CHECK-INST: vlsseg2b.v v8, (a0), a1 +th.vlsseg2b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x3a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 3a -vlsseg2h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2h.v v8, (a0), a1, v0.t +th.vlsseg2h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x38] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 38 -vlsseg2h.v v8, (a0), a1 -# CHECK-INST: vlsseg2h.v v8, (a0), a1 +th.vlsseg2h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x3a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 3a -vlsseg2w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2w.v v8, (a0), a1, v0.t +th.vlsseg2w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x38] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 38 -vlsseg2w.v v8, (a0), a1 -# CHECK-INST: vlsseg2w.v v8, (a0), a1 +th.vlsseg2w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x3a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 3a -vlsseg2bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2bu.v v8, (a0), a1, v0.t +th.vlsseg2bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 28 -vlsseg2bu.v v8, (a0), a1 -# CHECK-INST: vlsseg2bu.v v8, (a0), a1 +th.vlsseg2bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 2a -vlsseg2hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2hu.v v8, (a0), a1, v0.t +th.vlsseg2hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 28 -vlsseg2hu.v v8, (a0), a1 -# CHECK-INST: vlsseg2hu.v v8, (a0), a1 +th.vlsseg2hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 2a -vlsseg2wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2wu.v v8, (a0), a1, v0.t +th.vlsseg2wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 28 -vlsseg2wu.v v8, (a0), a1 -# CHECK-INST: vlsseg2wu.v v8, (a0), a1 +th.vlsseg2wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 2a -vlsseg2e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg2e.v v8, (a0), a1, v0.t +th.vlsseg2e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg2e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 28 -vlsseg2e.v v8, (a0), a1 -# CHECK-INST: vlsseg2e.v v8, (a0), a1 +th.vlsseg2e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg2e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 2a -vssseg2b.v v8, (a0), a1 -# CHECK-INST: vssseg2b.v v8, (a0), a1 +th.vssseg2b.v v8, (a0), a1 +# CHECK-INST: th.vssseg2b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 2a -vssseg2b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg2b.v v8, (a0), a1, v0.t +th.vssseg2b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg2b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 28 -vssseg2h.v v8, (a0), a1 -# CHECK-INST: vssseg2h.v v8, (a0), a1 +th.vssseg2h.v v8, (a0), a1 +# CHECK-INST: th.vssseg2h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 2a -vssseg2h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg2h.v v8, (a0), a1, v0.t +th.vssseg2h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg2h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 28 -vssseg2w.v v8, (a0), a1 -# CHECK-INST: vssseg2w.v v8, (a0), a1 +th.vssseg2w.v v8, (a0), a1 +# CHECK-INST: th.vssseg2w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 2a -vssseg2w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg2w.v v8, (a0), a1, v0.t +th.vssseg2w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg2w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 28 -vssseg2e.v v8, (a0), a1 -# CHECK-INST: vssseg2e.v v8, (a0), a1 +th.vssseg2e.v v8, (a0), a1 +# CHECK-INST: th.vssseg2e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0x2a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 2a -vssseg2e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg2e.v v8, (a0), a1, v0.t +th.vssseg2e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg2e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0x28] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 28 -vlxseg2b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2b.v v8, (a0), v4, v0.t +th.vlxseg2b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x3c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 3c -vlxseg2b.v v8, (a0), v4 -# CHECK-INST: vlxseg2b.v v8, (a0), v4 +th.vlxseg2b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x3e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 3e -vlxseg2h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2h.v v8, (a0), v4, v0.t +th.vlxseg2h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x3c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 3c -vlxseg2h.v v8, (a0), v4 -# CHECK-INST: vlxseg2h.v v8, (a0), v4 +th.vlxseg2h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x3e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 3e -vlxseg2w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2w.v v8, (a0), v4, v0.t +th.vlxseg2w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x3c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 3c -vlxseg2w.v v8, (a0), v4 -# CHECK-INST: vlxseg2w.v v8, (a0), v4 +th.vlxseg2w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x3e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 3e -vlxseg2bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2bu.v v8, (a0), v4, v0.t +th.vlxseg2bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 2c -vlxseg2bu.v v8, (a0), v4 -# CHECK-INST: vlxseg2bu.v v8, (a0), v4 +th.vlxseg2bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 2e -vlxseg2hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2hu.v v8, (a0), v4, v0.t +th.vlxseg2hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 2c -vlxseg2hu.v v8, (a0), v4 -# CHECK-INST: vlxseg2hu.v v8, (a0), v4 +th.vlxseg2hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 2e -vlxseg2wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2wu.v v8, (a0), v4, v0.t +th.vlxseg2wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 2c -vlxseg2wu.v v8, (a0), v4 -# CHECK-INST: vlxseg2wu.v v8, (a0), v4 +th.vlxseg2wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 2e -vlxseg2e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg2e.v v8, (a0), v4, v0.t +th.vlxseg2e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg2e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 2c -vlxseg2e.v v8, (a0), v4 -# CHECK-INST: vlxseg2e.v v8, (a0), v4 +th.vlxseg2e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg2e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 2e -vsxseg2b.v v8, (a0), v4 -# CHECK-INST: vsxseg2b.v v8, (a0), v4 +th.vsxseg2b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg2b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 2e -vsxseg2b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg2b.v v8, (a0), v4, v0.t +th.vsxseg2b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg2b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 2c -vsxseg2h.v v8, (a0), v4 -# CHECK-INST: vsxseg2h.v v8, (a0), v4 +th.vsxseg2h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg2h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 2e -vsxseg2h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg2h.v v8, (a0), v4, v0.t +th.vsxseg2h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg2h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 2c -vsxseg2w.v v8, (a0), v4 -# CHECK-INST: vsxseg2w.v v8, (a0), v4 +th.vsxseg2w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg2w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 2e -vsxseg2w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg2w.v v8, (a0), v4, v0.t +th.vsxseg2w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg2w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 2c -vsxseg2e.v v8, (a0), v4 -# CHECK-INST: vsxseg2e.v v8, (a0), v4 +th.vsxseg2e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg2e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0x2e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 2e -vsxseg2e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg2e.v v8, (a0), v4, v0.t +th.vsxseg2e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg2e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0x2c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 2c -vlseg3b.v v8, (a0), v0.t -# CHECK-INST: vlseg3b.v v8, (a0), v0.t +th.vlseg3b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x50] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 50 -vlseg3b.v v8, (a0) -# CHECK-INST: vlseg3b.v v8, (a0) +th.vlseg3b.v v8, (a0) +# CHECK-INST: th.vlseg3b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x52] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 52 -vlseg3h.v v8, (a0), v0.t -# CHECK-INST: vlseg3h.v v8, (a0), v0.t +th.vlseg3h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x50] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 50 -vlseg3h.v v8, (a0) -# CHECK-INST: vlseg3h.v v8, (a0) +th.vlseg3h.v v8, (a0) +# CHECK-INST: th.vlseg3h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x52] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 52 -vlseg3w.v v8, (a0), v0.t -# CHECK-INST: vlseg3w.v v8, (a0), v0.t +th.vlseg3w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x50] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 50 -vlseg3w.v v8, (a0) -# CHECK-INST: vlseg3w.v v8, (a0) +th.vlseg3w.v v8, (a0) +# CHECK-INST: th.vlseg3w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x52] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 52 -vlseg3bu.v v8, (a0), v0.t -# CHECK-INST: vlseg3bu.v v8, (a0), v0.t +th.vlseg3bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 40 -vlseg3bu.v v8, (a0) -# CHECK-INST: vlseg3bu.v v8, (a0) +th.vlseg3bu.v v8, (a0) +# CHECK-INST: th.vlseg3bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 42 -vlseg3hu.v v8, (a0), v0.t -# CHECK-INST: vlseg3hu.v v8, (a0), v0.t +th.vlseg3hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 40 -vlseg3hu.v v8, (a0) -# CHECK-INST: vlseg3hu.v v8, (a0) +th.vlseg3hu.v v8, (a0) +# CHECK-INST: th.vlseg3hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 42 -vlseg3wu.v v8, (a0), v0.t -# CHECK-INST: vlseg3wu.v v8, (a0), v0.t +th.vlseg3wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 40 -vlseg3wu.v v8, (a0) -# CHECK-INST: vlseg3wu.v v8, (a0) +th.vlseg3wu.v v8, (a0) +# CHECK-INST: th.vlseg3wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 42 -vlseg3e.v v8, (a0), v0.t -# CHECK-INST: vlseg3e.v v8, (a0), v0.t +th.vlseg3e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 40 -vlseg3e.v v8, (a0) -# CHECK-INST: vlseg3e.v v8, (a0) +th.vlseg3e.v v8, (a0) +# CHECK-INST: th.vlseg3e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 42 -vsseg3b.v v8, (a0), v0.t -# CHECK-INST: vsseg3b.v v8, (a0), v0.t +th.vsseg3b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg3b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 40 -vsseg3b.v v8, (a0) -# CHECK-INST: vsseg3b.v v8, (a0) +th.vsseg3b.v v8, (a0) +# CHECK-INST: th.vsseg3b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 42 -vsseg3h.v v8, (a0), v0.t -# CHECK-INST: vsseg3h.v v8, (a0), v0.t +th.vsseg3h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg3h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 40 -vsseg3h.v v8, (a0) -# CHECK-INST: vsseg3h.v v8, (a0) +th.vsseg3h.v v8, (a0) +# CHECK-INST: th.vsseg3h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 42 -vsseg3w.v v8, (a0), v0.t -# CHECK-INST: vsseg3w.v v8, (a0), v0.t +th.vsseg3w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg3w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 40 -vsseg3w.v v8, (a0) -# CHECK-INST: vsseg3w.v v8, (a0) +th.vsseg3w.v v8, (a0) +# CHECK-INST: th.vsseg3w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 42 -vsseg3e.v v8, (a0), v0.t -# CHECK-INST: vsseg3e.v v8, (a0), v0.t +th.vsseg3e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg3e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0x40] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 40 -vsseg3e.v v8, (a0) -# CHECK-INST: vsseg3e.v v8, (a0) +th.vsseg3e.v v8, (a0) +# CHECK-INST: th.vsseg3e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0x42] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 42 -vlseg3bff.v v8, (a0) -# CHECK-INST: vlseg3bff.v v8, (a0) +th.vlseg3bff.v v8, (a0) +# CHECK-INST: th.vlseg3bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x53] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 53 -vlseg3bff.v v8, (a0), v0.t -# CHECK-INST: vlseg3bff.v v8, (a0), v0.t +th.vlseg3bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x51] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 51 -vlseg3hff.v v8, (a0) -# CHECK-INST: vlseg3hff.v v8, (a0) +th.vlseg3hff.v v8, (a0) +# CHECK-INST: th.vlseg3hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x53] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 53 -vlseg3hff.v v8, (a0), v0.t -# CHECK-INST: vlseg3hff.v v8, (a0), v0.t +th.vlseg3hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x51] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 51 -vlseg3wff.v v8, (a0) -# CHECK-INST: vlseg3wff.v v8, (a0) +th.vlseg3wff.v v8, (a0) +# CHECK-INST: th.vlseg3wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x53] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 53 -vlseg3wff.v v8, (a0), v0.t -# CHECK-INST: vlseg3wff.v v8, (a0), v0.t +th.vlseg3wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x51] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 51 -vlseg3buff.v v8, (a0) -# CHECK-INST: vlseg3buff.v v8, (a0) +th.vlseg3buff.v v8, (a0) +# CHECK-INST: th.vlseg3buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x43] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 43 -vlseg3buff.v v8, (a0), v0.t -# CHECK-INST: vlseg3buff.v v8, (a0), v0.t +th.vlseg3buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x41] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 41 -vlseg3huff.v v8, (a0) -# CHECK-INST: vlseg3huff.v v8, (a0) +th.vlseg3huff.v v8, (a0) +# CHECK-INST: th.vlseg3huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x43] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 43 -vlseg3huff.v v8, (a0), v0.t -# CHECK-INST: vlseg3huff.v v8, (a0), v0.t +th.vlseg3huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x41] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 41 -vlseg3wuff.v v8, (a0) -# CHECK-INST: vlseg3wuff.v v8, (a0) +th.vlseg3wuff.v v8, (a0) +# CHECK-INST: th.vlseg3wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x43] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 43 -vlseg3wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg3wuff.v v8, (a0), v0.t +th.vlseg3wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x41] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 41 -vlseg3eff.v v8, (a0) -# CHECK-INST: vlseg3eff.v v8, (a0) +th.vlseg3eff.v v8, (a0) +# CHECK-INST: th.vlseg3eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x43] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 43 -vlseg3eff.v v8, (a0), v0.t -# CHECK-INST: vlseg3eff.v v8, (a0), v0.t +th.vlseg3eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg3eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x41] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 41 -vlsseg3b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3b.v v8, (a0), a1, v0.t +th.vlsseg3b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x58] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 58 -vlsseg3b.v v8, (a0), a1 -# CHECK-INST: vlsseg3b.v v8, (a0), a1 +th.vlsseg3b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x5a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 5a -vlsseg3h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3h.v v8, (a0), a1, v0.t +th.vlsseg3h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x58] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 58 -vlsseg3h.v v8, (a0), a1 -# CHECK-INST: vlsseg3h.v v8, (a0), a1 +th.vlsseg3h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x5a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 5a -vlsseg3w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3w.v v8, (a0), a1, v0.t +th.vlsseg3w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x58] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 58 -vlsseg3w.v v8, (a0), a1 -# CHECK-INST: vlsseg3w.v v8, (a0), a1 +th.vlsseg3w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x5a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 5a -vlsseg3bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3bu.v v8, (a0), a1, v0.t +th.vlsseg3bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 48 -vlsseg3bu.v v8, (a0), a1 -# CHECK-INST: vlsseg3bu.v v8, (a0), a1 +th.vlsseg3bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 4a -vlsseg3hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3hu.v v8, (a0), a1, v0.t +th.vlsseg3hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 48 -vlsseg3hu.v v8, (a0), a1 -# CHECK-INST: vlsseg3hu.v v8, (a0), a1 +th.vlsseg3hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 4a -vlsseg3wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3wu.v v8, (a0), a1, v0.t +th.vlsseg3wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 48 -vlsseg3wu.v v8, (a0), a1 -# CHECK-INST: vlsseg3wu.v v8, (a0), a1 +th.vlsseg3wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 4a -vlsseg3e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg3e.v v8, (a0), a1, v0.t +th.vlsseg3e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg3e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 48 -vlsseg3e.v v8, (a0), a1 -# CHECK-INST: vlsseg3e.v v8, (a0), a1 +th.vlsseg3e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg3e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 4a -vssseg3b.v v8, (a0), a1 -# CHECK-INST: vssseg3b.v v8, (a0), a1 +th.vssseg3b.v v8, (a0), a1 +# CHECK-INST: th.vssseg3b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 4a -vssseg3b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg3b.v v8, (a0), a1, v0.t +th.vssseg3b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg3b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 48 -vssseg3h.v v8, (a0), a1 -# CHECK-INST: vssseg3h.v v8, (a0), a1 +th.vssseg3h.v v8, (a0), a1 +# CHECK-INST: th.vssseg3h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 4a -vssseg3h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg3h.v v8, (a0), a1, v0.t +th.vssseg3h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg3h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 48 -vssseg3w.v v8, (a0), a1 -# CHECK-INST: vssseg3w.v v8, (a0), a1 +th.vssseg3w.v v8, (a0), a1 +# CHECK-INST: th.vssseg3w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 4a -vssseg3w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg3w.v v8, (a0), a1, v0.t +th.vssseg3w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg3w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 48 -vssseg3e.v v8, (a0), a1 -# CHECK-INST: vssseg3e.v v8, (a0), a1 +th.vssseg3e.v v8, (a0), a1 +# CHECK-INST: th.vssseg3e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0x4a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 4a -vssseg3e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg3e.v v8, (a0), a1, v0.t +th.vssseg3e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg3e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0x48] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 48 -vlxseg3b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3b.v v8, (a0), v4, v0.t +th.vlxseg3b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x5c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 5c -vlxseg3b.v v8, (a0), v4 -# CHECK-INST: vlxseg3b.v v8, (a0), v4 +th.vlxseg3b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x5e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 5e -vlxseg3h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3h.v v8, (a0), v4, v0.t +th.vlxseg3h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x5c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 5c -vlxseg3h.v v8, (a0), v4 -# CHECK-INST: vlxseg3h.v v8, (a0), v4 +th.vlxseg3h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x5e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 5e -vlxseg3w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3w.v v8, (a0), v4, v0.t +th.vlxseg3w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x5c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 5c -vlxseg3w.v v8, (a0), v4 -# CHECK-INST: vlxseg3w.v v8, (a0), v4 +th.vlxseg3w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x5e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 5e -vlxseg3bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3bu.v v8, (a0), v4, v0.t +th.vlxseg3bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 4c -vlxseg3bu.v v8, (a0), v4 -# CHECK-INST: vlxseg3bu.v v8, (a0), v4 +th.vlxseg3bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 4e -vlxseg3hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3hu.v v8, (a0), v4, v0.t +th.vlxseg3hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 4c -vlxseg3hu.v v8, (a0), v4 -# CHECK-INST: vlxseg3hu.v v8, (a0), v4 +th.vlxseg3hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 4e -vlxseg3wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3wu.v v8, (a0), v4, v0.t +th.vlxseg3wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 4c -vlxseg3wu.v v8, (a0), v4 -# CHECK-INST: vlxseg3wu.v v8, (a0), v4 +th.vlxseg3wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 4e -vlxseg3e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg3e.v v8, (a0), v4, v0.t +th.vlxseg3e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg3e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 4c -vlxseg3e.v v8, (a0), v4 -# CHECK-INST: vlxseg3e.v v8, (a0), v4 +th.vlxseg3e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg3e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 4e -vsxseg3b.v v8, (a0), v4 -# CHECK-INST: vsxseg3b.v v8, (a0), v4 +th.vsxseg3b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg3b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 4e -vsxseg3b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg3b.v v8, (a0), v4, v0.t +th.vsxseg3b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg3b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 4c -vsxseg3h.v v8, (a0), v4 -# CHECK-INST: vsxseg3h.v v8, (a0), v4 +th.vsxseg3h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg3h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 4e -vsxseg3h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg3h.v v8, (a0), v4, v0.t +th.vsxseg3h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg3h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 4c -vsxseg3w.v v8, (a0), v4 -# CHECK-INST: vsxseg3w.v v8, (a0), v4 +th.vsxseg3w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg3w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 4e -vsxseg3w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg3w.v v8, (a0), v4, v0.t +th.vsxseg3w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg3w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 4c -vsxseg3e.v v8, (a0), v4 -# CHECK-INST: vsxseg3e.v v8, (a0), v4 +th.vsxseg3e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg3e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0x4e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 4e -vsxseg3e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg3e.v v8, (a0), v4, v0.t +th.vsxseg3e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg3e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0x4c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 4c -vlseg4b.v v8, (a0), v0.t -# CHECK-INST: vlseg4b.v v8, (a0), v0.t +th.vlseg4b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x70] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 70 -vlseg4b.v v8, (a0) -# CHECK-INST: vlseg4b.v v8, (a0) +th.vlseg4b.v v8, (a0) +# CHECK-INST: th.vlseg4b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x72] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 72 -vlseg4h.v v8, (a0), v0.t -# CHECK-INST: vlseg4h.v v8, (a0), v0.t +th.vlseg4h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x70] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 70 -vlseg4h.v v8, (a0) -# CHECK-INST: vlseg4h.v v8, (a0) +th.vlseg4h.v v8, (a0) +# CHECK-INST: th.vlseg4h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x72] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 72 -vlseg4w.v v8, (a0), v0.t -# CHECK-INST: vlseg4w.v v8, (a0), v0.t +th.vlseg4w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x70] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 70 -vlseg4w.v v8, (a0) -# CHECK-INST: vlseg4w.v v8, (a0) +th.vlseg4w.v v8, (a0) +# CHECK-INST: th.vlseg4w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x72] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 72 -vlseg4bu.v v8, (a0), v0.t -# CHECK-INST: vlseg4bu.v v8, (a0), v0.t +th.vlseg4bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 60 -vlseg4bu.v v8, (a0) -# CHECK-INST: vlseg4bu.v v8, (a0) +th.vlseg4bu.v v8, (a0) +# CHECK-INST: th.vlseg4bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 62 -vlseg4hu.v v8, (a0), v0.t -# CHECK-INST: vlseg4hu.v v8, (a0), v0.t +th.vlseg4hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 60 -vlseg4hu.v v8, (a0) -# CHECK-INST: vlseg4hu.v v8, (a0) +th.vlseg4hu.v v8, (a0) +# CHECK-INST: th.vlseg4hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 62 -vlseg4wu.v v8, (a0), v0.t -# CHECK-INST: vlseg4wu.v v8, (a0), v0.t +th.vlseg4wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 60 -vlseg4wu.v v8, (a0) -# CHECK-INST: vlseg4wu.v v8, (a0) +th.vlseg4wu.v v8, (a0) +# CHECK-INST: th.vlseg4wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 62 -vlseg4e.v v8, (a0), v0.t -# CHECK-INST: vlseg4e.v v8, (a0), v0.t +th.vlseg4e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 60 -vlseg4e.v v8, (a0) -# CHECK-INST: vlseg4e.v v8, (a0) +th.vlseg4e.v v8, (a0) +# CHECK-INST: th.vlseg4e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 62 -vsseg4b.v v8, (a0), v0.t -# CHECK-INST: vsseg4b.v v8, (a0), v0.t +th.vsseg4b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg4b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 60 -vsseg4b.v v8, (a0) -# CHECK-INST: vsseg4b.v v8, (a0) +th.vsseg4b.v v8, (a0) +# CHECK-INST: th.vsseg4b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 62 -vsseg4h.v v8, (a0), v0.t -# CHECK-INST: vsseg4h.v v8, (a0), v0.t +th.vsseg4h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg4h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 60 -vsseg4h.v v8, (a0) -# CHECK-INST: vsseg4h.v v8, (a0) +th.vsseg4h.v v8, (a0) +# CHECK-INST: th.vsseg4h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 62 -vsseg4w.v v8, (a0), v0.t -# CHECK-INST: vsseg4w.v v8, (a0), v0.t +th.vsseg4w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg4w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 60 -vsseg4w.v v8, (a0) -# CHECK-INST: vsseg4w.v v8, (a0) +th.vsseg4w.v v8, (a0) +# CHECK-INST: th.vsseg4w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 62 -vsseg4e.v v8, (a0), v0.t -# CHECK-INST: vsseg4e.v v8, (a0), v0.t +th.vsseg4e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg4e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0x60] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 60 -vsseg4e.v v8, (a0) -# CHECK-INST: vsseg4e.v v8, (a0) +th.vsseg4e.v v8, (a0) +# CHECK-INST: th.vsseg4e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0x62] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 62 -vlseg4bff.v v8, (a0) -# CHECK-INST: vlseg4bff.v v8, (a0) +th.vlseg4bff.v v8, (a0) +# CHECK-INST: th.vlseg4bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x73] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 73 -vlseg4bff.v v8, (a0), v0.t -# CHECK-INST: vlseg4bff.v v8, (a0), v0.t +th.vlseg4bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x71] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 71 -vlseg4hff.v v8, (a0) -# CHECK-INST: vlseg4hff.v v8, (a0) +th.vlseg4hff.v v8, (a0) +# CHECK-INST: th.vlseg4hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x73] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 73 -vlseg4hff.v v8, (a0), v0.t -# CHECK-INST: vlseg4hff.v v8, (a0), v0.t +th.vlseg4hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x71] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 71 -vlseg4wff.v v8, (a0) -# CHECK-INST: vlseg4wff.v v8, (a0) +th.vlseg4wff.v v8, (a0) +# CHECK-INST: th.vlseg4wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x73] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 73 -vlseg4wff.v v8, (a0), v0.t -# CHECK-INST: vlseg4wff.v v8, (a0), v0.t +th.vlseg4wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x71] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 71 -vlseg4buff.v v8, (a0) -# CHECK-INST: vlseg4buff.v v8, (a0) +th.vlseg4buff.v v8, (a0) +# CHECK-INST: th.vlseg4buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x63] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 63 -vlseg4buff.v v8, (a0), v0.t -# CHECK-INST: vlseg4buff.v v8, (a0), v0.t +th.vlseg4buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x61] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 61 -vlseg4huff.v v8, (a0) -# CHECK-INST: vlseg4huff.v v8, (a0) +th.vlseg4huff.v v8, (a0) +# CHECK-INST: th.vlseg4huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x63] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 63 -vlseg4huff.v v8, (a0), v0.t -# CHECK-INST: vlseg4huff.v v8, (a0), v0.t +th.vlseg4huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x61] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 61 -vlseg4wuff.v v8, (a0) -# CHECK-INST: vlseg4wuff.v v8, (a0) +th.vlseg4wuff.v v8, (a0) +# CHECK-INST: th.vlseg4wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x63] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 63 -vlseg4wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg4wuff.v v8, (a0), v0.t +th.vlseg4wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x61] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 61 -vlseg4eff.v v8, (a0) -# CHECK-INST: vlseg4eff.v v8, (a0) +th.vlseg4eff.v v8, (a0) +# CHECK-INST: th.vlseg4eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x63] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 63 -vlseg4eff.v v8, (a0), v0.t -# CHECK-INST: vlseg4eff.v v8, (a0), v0.t +th.vlseg4eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg4eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x61] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 61 -vlsseg4b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4b.v v8, (a0), a1, v0.t +th.vlsseg4b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x78] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 78 -vlsseg4b.v v8, (a0), a1 -# CHECK-INST: vlsseg4b.v v8, (a0), a1 +th.vlsseg4b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x7a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 7a -vlsseg4h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4h.v v8, (a0), a1, v0.t +th.vlsseg4h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x78] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 78 -vlsseg4h.v v8, (a0), a1 -# CHECK-INST: vlsseg4h.v v8, (a0), a1 +th.vlsseg4h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x7a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 7a -vlsseg4w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4w.v v8, (a0), a1, v0.t +th.vlsseg4w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x78] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 78 -vlsseg4w.v v8, (a0), a1 -# CHECK-INST: vlsseg4w.v v8, (a0), a1 +th.vlsseg4w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x7a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 7a -vlsseg4bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4bu.v v8, (a0), a1, v0.t +th.vlsseg4bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 68 -vlsseg4bu.v v8, (a0), a1 -# CHECK-INST: vlsseg4bu.v v8, (a0), a1 +th.vlsseg4bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 6a -vlsseg4hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4hu.v v8, (a0), a1, v0.t +th.vlsseg4hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 68 -vlsseg4hu.v v8, (a0), a1 -# CHECK-INST: vlsseg4hu.v v8, (a0), a1 +th.vlsseg4hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 6a -vlsseg4wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4wu.v v8, (a0), a1, v0.t +th.vlsseg4wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 68 -vlsseg4wu.v v8, (a0), a1 -# CHECK-INST: vlsseg4wu.v v8, (a0), a1 +th.vlsseg4wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 6a -vlsseg4e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg4e.v v8, (a0), a1, v0.t +th.vlsseg4e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg4e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 68 -vlsseg4e.v v8, (a0), a1 -# CHECK-INST: vlsseg4e.v v8, (a0), a1 +th.vlsseg4e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg4e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 6a -vssseg4b.v v8, (a0), a1 -# CHECK-INST: vssseg4b.v v8, (a0), a1 +th.vssseg4b.v v8, (a0), a1 +# CHECK-INST: th.vssseg4b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 6a -vssseg4b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg4b.v v8, (a0), a1, v0.t +th.vssseg4b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg4b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 68 -vssseg4h.v v8, (a0), a1 -# CHECK-INST: vssseg4h.v v8, (a0), a1 +th.vssseg4h.v v8, (a0), a1 +# CHECK-INST: th.vssseg4h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 6a -vssseg4h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg4h.v v8, (a0), a1, v0.t +th.vssseg4h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg4h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 68 -vssseg4w.v v8, (a0), a1 -# CHECK-INST: vssseg4w.v v8, (a0), a1 +th.vssseg4w.v v8, (a0), a1 +# CHECK-INST: th.vssseg4w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 6a -vssseg4w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg4w.v v8, (a0), a1, v0.t +th.vssseg4w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg4w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 68 -vssseg4e.v v8, (a0), a1 -# CHECK-INST: vssseg4e.v v8, (a0), a1 +th.vssseg4e.v v8, (a0), a1 +# CHECK-INST: th.vssseg4e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0x6a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 6a -vssseg4e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg4e.v v8, (a0), a1, v0.t +th.vssseg4e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg4e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0x68] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 68 -vlxseg4b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4b.v v8, (a0), v4, v0.t +th.vlxseg4b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x7c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 7c -vlxseg4b.v v8, (a0), v4 -# CHECK-INST: vlxseg4b.v v8, (a0), v4 +th.vlxseg4b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x7e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 7e -vlxseg4h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4h.v v8, (a0), v4, v0.t +th.vlxseg4h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x7c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 7c -vlxseg4h.v v8, (a0), v4 -# CHECK-INST: vlxseg4h.v v8, (a0), v4 +th.vlxseg4h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x7e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 7e -vlxseg4w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4w.v v8, (a0), v4, v0.t +th.vlxseg4w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x7c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 7c -vlxseg4w.v v8, (a0), v4 -# CHECK-INST: vlxseg4w.v v8, (a0), v4 +th.vlxseg4w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x7e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 7e -vlxseg4bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4bu.v v8, (a0), v4, v0.t +th.vlxseg4bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 6c -vlxseg4bu.v v8, (a0), v4 -# CHECK-INST: vlxseg4bu.v v8, (a0), v4 +th.vlxseg4bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 6e -vlxseg4hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4hu.v v8, (a0), v4, v0.t +th.vlxseg4hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 6c -vlxseg4hu.v v8, (a0), v4 -# CHECK-INST: vlxseg4hu.v v8, (a0), v4 +th.vlxseg4hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 6e -vlxseg4wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4wu.v v8, (a0), v4, v0.t +th.vlxseg4wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 6c -vlxseg4wu.v v8, (a0), v4 -# CHECK-INST: vlxseg4wu.v v8, (a0), v4 +th.vlxseg4wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 6e -vlxseg4e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg4e.v v8, (a0), v4, v0.t +th.vlxseg4e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg4e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 6c -vlxseg4e.v v8, (a0), v4 -# CHECK-INST: vlxseg4e.v v8, (a0), v4 +th.vlxseg4e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg4e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 6e -vsxseg4b.v v8, (a0), v4 -# CHECK-INST: vsxseg4b.v v8, (a0), v4 +th.vsxseg4b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg4b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 6e -vsxseg4b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg4b.v v8, (a0), v4, v0.t +th.vsxseg4b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg4b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 6c -vsxseg4h.v v8, (a0), v4 -# CHECK-INST: vsxseg4h.v v8, (a0), v4 +th.vsxseg4h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg4h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 6e -vsxseg4h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg4h.v v8, (a0), v4, v0.t +th.vsxseg4h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg4h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 6c -vsxseg4w.v v8, (a0), v4 -# CHECK-INST: vsxseg4w.v v8, (a0), v4 +th.vsxseg4w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg4w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 6e -vsxseg4w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg4w.v v8, (a0), v4, v0.t +th.vsxseg4w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg4w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 6c -vsxseg4e.v v8, (a0), v4 -# CHECK-INST: vsxseg4e.v v8, (a0), v4 +th.vsxseg4e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg4e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0x6e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 6e -vsxseg4e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg4e.v v8, (a0), v4, v0.t +th.vsxseg4e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg4e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0x6c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 6c -vlseg5b.v v8, (a0), v0.t -# CHECK-INST: vlseg5b.v v8, (a0), v0.t +th.vlseg5b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x90] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 90 -vlseg5b.v v8, (a0) -# CHECK-INST: vlseg5b.v v8, (a0) +th.vlseg5b.v v8, (a0) +# CHECK-INST: th.vlseg5b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x92] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 92 -vlseg5h.v v8, (a0), v0.t -# CHECK-INST: vlseg5h.v v8, (a0), v0.t +th.vlseg5h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x90] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 90 -vlseg5h.v v8, (a0) -# CHECK-INST: vlseg5h.v v8, (a0) +th.vlseg5h.v v8, (a0) +# CHECK-INST: th.vlseg5h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x92] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 92 -vlseg5w.v v8, (a0), v0.t -# CHECK-INST: vlseg5w.v v8, (a0), v0.t +th.vlseg5w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x90] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 90 -vlseg5w.v v8, (a0) -# CHECK-INST: vlseg5w.v v8, (a0) +th.vlseg5w.v v8, (a0) +# CHECK-INST: th.vlseg5w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x92] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 92 -vlseg5bu.v v8, (a0), v0.t -# CHECK-INST: vlseg5bu.v v8, (a0), v0.t +th.vlseg5bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 80 -vlseg5bu.v v8, (a0) -# CHECK-INST: vlseg5bu.v v8, (a0) +th.vlseg5bu.v v8, (a0) +# CHECK-INST: th.vlseg5bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 82 -vlseg5hu.v v8, (a0), v0.t -# CHECK-INST: vlseg5hu.v v8, (a0), v0.t +th.vlseg5hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 80 -vlseg5hu.v v8, (a0) -# CHECK-INST: vlseg5hu.v v8, (a0) +th.vlseg5hu.v v8, (a0) +# CHECK-INST: th.vlseg5hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 82 -vlseg5wu.v v8, (a0), v0.t -# CHECK-INST: vlseg5wu.v v8, (a0), v0.t +th.vlseg5wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 80 -vlseg5wu.v v8, (a0) -# CHECK-INST: vlseg5wu.v v8, (a0) +th.vlseg5wu.v v8, (a0) +# CHECK-INST: th.vlseg5wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 82 -vlseg5e.v v8, (a0), v0.t -# CHECK-INST: vlseg5e.v v8, (a0), v0.t +th.vlseg5e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 80 -vlseg5e.v v8, (a0) -# CHECK-INST: vlseg5e.v v8, (a0) +th.vlseg5e.v v8, (a0) +# CHECK-INST: th.vlseg5e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 82 -vsseg5b.v v8, (a0), v0.t -# CHECK-INST: vsseg5b.v v8, (a0), v0.t +th.vsseg5b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg5b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 80 -vsseg5b.v v8, (a0) -# CHECK-INST: vsseg5b.v v8, (a0) +th.vsseg5b.v v8, (a0) +# CHECK-INST: th.vsseg5b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 82 -vsseg5h.v v8, (a0), v0.t -# CHECK-INST: vsseg5h.v v8, (a0), v0.t +th.vsseg5h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg5h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 80 -vsseg5h.v v8, (a0) -# CHECK-INST: vsseg5h.v v8, (a0) +th.vsseg5h.v v8, (a0) +# CHECK-INST: th.vsseg5h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 82 -vsseg5w.v v8, (a0), v0.t -# CHECK-INST: vsseg5w.v v8, (a0), v0.t +th.vsseg5w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg5w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 80 -vsseg5w.v v8, (a0) -# CHECK-INST: vsseg5w.v v8, (a0) +th.vsseg5w.v v8, (a0) +# CHECK-INST: th.vsseg5w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 82 -vsseg5e.v v8, (a0), v0.t -# CHECK-INST: vsseg5e.v v8, (a0), v0.t +th.vsseg5e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg5e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0x80] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 80 -vsseg5e.v v8, (a0) -# CHECK-INST: vsseg5e.v v8, (a0) +th.vsseg5e.v v8, (a0) +# CHECK-INST: th.vsseg5e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0x82] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 82 -vlseg5bff.v v8, (a0) -# CHECK-INST: vlseg5bff.v v8, (a0) +th.vlseg5bff.v v8, (a0) +# CHECK-INST: th.vlseg5bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x93] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 93 -vlseg5bff.v v8, (a0), v0.t -# CHECK-INST: vlseg5bff.v v8, (a0), v0.t +th.vlseg5bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x91] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 91 -vlseg5hff.v v8, (a0) -# CHECK-INST: vlseg5hff.v v8, (a0) +th.vlseg5hff.v v8, (a0) +# CHECK-INST: th.vlseg5hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x93] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 93 -vlseg5hff.v v8, (a0), v0.t -# CHECK-INST: vlseg5hff.v v8, (a0), v0.t +th.vlseg5hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x91] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 91 -vlseg5wff.v v8, (a0) -# CHECK-INST: vlseg5wff.v v8, (a0) +th.vlseg5wff.v v8, (a0) +# CHECK-INST: th.vlseg5wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x93] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 93 -vlseg5wff.v v8, (a0), v0.t -# CHECK-INST: vlseg5wff.v v8, (a0), v0.t +th.vlseg5wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x91] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 91 -vlseg5buff.v v8, (a0) -# CHECK-INST: vlseg5buff.v v8, (a0) +th.vlseg5buff.v v8, (a0) +# CHECK-INST: th.vlseg5buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x83] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 83 -vlseg5buff.v v8, (a0), v0.t -# CHECK-INST: vlseg5buff.v v8, (a0), v0.t +th.vlseg5buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x81] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 81 -vlseg5huff.v v8, (a0) -# CHECK-INST: vlseg5huff.v v8, (a0) +th.vlseg5huff.v v8, (a0) +# CHECK-INST: th.vlseg5huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x83] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 83 -vlseg5huff.v v8, (a0), v0.t -# CHECK-INST: vlseg5huff.v v8, (a0), v0.t +th.vlseg5huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x81] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 81 -vlseg5wuff.v v8, (a0) -# CHECK-INST: vlseg5wuff.v v8, (a0) +th.vlseg5wuff.v v8, (a0) +# CHECK-INST: th.vlseg5wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x83] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 83 -vlseg5wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg5wuff.v v8, (a0), v0.t +th.vlseg5wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x81] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 81 -vlseg5eff.v v8, (a0) -# CHECK-INST: vlseg5eff.v v8, (a0) +th.vlseg5eff.v v8, (a0) +# CHECK-INST: th.vlseg5eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x83] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 83 -vlseg5eff.v v8, (a0), v0.t -# CHECK-INST: vlseg5eff.v v8, (a0), v0.t +th.vlseg5eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg5eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x81] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 81 -vlsseg5b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5b.v v8, (a0), a1, v0.t +th.vlsseg5b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x98] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 98 -vlsseg5b.v v8, (a0), a1 -# CHECK-INST: vlsseg5b.v v8, (a0), a1 +th.vlsseg5b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x9a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 9a -vlsseg5h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5h.v v8, (a0), a1, v0.t +th.vlsseg5h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x98] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 98 -vlsseg5h.v v8, (a0), a1 -# CHECK-INST: vlsseg5h.v v8, (a0), a1 +th.vlsseg5h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x9a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 9a -vlsseg5w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5w.v v8, (a0), a1, v0.t +th.vlsseg5w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x98] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 98 -vlsseg5w.v v8, (a0), a1 -# CHECK-INST: vlsseg5w.v v8, (a0), a1 +th.vlsseg5w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x9a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 9a -vlsseg5bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5bu.v v8, (a0), a1, v0.t +th.vlsseg5bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 88 -vlsseg5bu.v v8, (a0), a1 -# CHECK-INST: vlsseg5bu.v v8, (a0), a1 +th.vlsseg5bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 8a -vlsseg5hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5hu.v v8, (a0), a1, v0.t +th.vlsseg5hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 88 -vlsseg5hu.v v8, (a0), a1 -# CHECK-INST: vlsseg5hu.v v8, (a0), a1 +th.vlsseg5hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 8a -vlsseg5wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5wu.v v8, (a0), a1, v0.t +th.vlsseg5wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 88 -vlsseg5wu.v v8, (a0), a1 -# CHECK-INST: vlsseg5wu.v v8, (a0), a1 +th.vlsseg5wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 8a -vlsseg5e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg5e.v v8, (a0), a1, v0.t +th.vlsseg5e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg5e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 88 -vlsseg5e.v v8, (a0), a1 -# CHECK-INST: vlsseg5e.v v8, (a0), a1 +th.vlsseg5e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg5e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 8a -vssseg5b.v v8, (a0), a1 -# CHECK-INST: vssseg5b.v v8, (a0), a1 +th.vssseg5b.v v8, (a0), a1 +# CHECK-INST: th.vssseg5b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 8a -vssseg5b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg5b.v v8, (a0), a1, v0.t +th.vssseg5b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg5b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 88 -vssseg5h.v v8, (a0), a1 -# CHECK-INST: vssseg5h.v v8, (a0), a1 +th.vssseg5h.v v8, (a0), a1 +# CHECK-INST: th.vssseg5h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 8a -vssseg5h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg5h.v v8, (a0), a1, v0.t +th.vssseg5h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg5h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 88 -vssseg5w.v v8, (a0), a1 -# CHECK-INST: vssseg5w.v v8, (a0), a1 +th.vssseg5w.v v8, (a0), a1 +# CHECK-INST: th.vssseg5w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 8a -vssseg5w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg5w.v v8, (a0), a1, v0.t +th.vssseg5w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg5w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 88 -vssseg5e.v v8, (a0), a1 -# CHECK-INST: vssseg5e.v v8, (a0), a1 +th.vssseg5e.v v8, (a0), a1 +# CHECK-INST: th.vssseg5e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0x8a] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 8a -vssseg5e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg5e.v v8, (a0), a1, v0.t +th.vssseg5e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg5e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0x88] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 88 -vlxseg5b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5b.v v8, (a0), v4, v0.t +th.vlxseg5b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x9c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 9c -vlxseg5b.v v8, (a0), v4 -# CHECK-INST: vlxseg5b.v v8, (a0), v4 +th.vlxseg5b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x9e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 9e -vlxseg5h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5h.v v8, (a0), v4, v0.t +th.vlxseg5h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x9c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 9c -vlxseg5h.v v8, (a0), v4 -# CHECK-INST: vlxseg5h.v v8, (a0), v4 +th.vlxseg5h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x9e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 9e -vlxseg5w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5w.v v8, (a0), v4, v0.t +th.vlxseg5w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x9c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 9c -vlxseg5w.v v8, (a0), v4 -# CHECK-INST: vlxseg5w.v v8, (a0), v4 +th.vlxseg5w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x9e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 9e -vlxseg5bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5bu.v v8, (a0), v4, v0.t +th.vlxseg5bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 8c -vlxseg5bu.v v8, (a0), v4 -# CHECK-INST: vlxseg5bu.v v8, (a0), v4 +th.vlxseg5bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 8e -vlxseg5hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5hu.v v8, (a0), v4, v0.t +th.vlxseg5hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 8c -vlxseg5hu.v v8, (a0), v4 -# CHECK-INST: vlxseg5hu.v v8, (a0), v4 +th.vlxseg5hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 8e -vlxseg5wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5wu.v v8, (a0), v4, v0.t +th.vlxseg5wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 8c -vlxseg5wu.v v8, (a0), v4 -# CHECK-INST: vlxseg5wu.v v8, (a0), v4 +th.vlxseg5wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 8e -vlxseg5e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg5e.v v8, (a0), v4, v0.t +th.vlxseg5e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg5e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 8c -vlxseg5e.v v8, (a0), v4 -# CHECK-INST: vlxseg5e.v v8, (a0), v4 +th.vlxseg5e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg5e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 8e -vsxseg5b.v v8, (a0), v4 -# CHECK-INST: vsxseg5b.v v8, (a0), v4 +th.vsxseg5b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg5b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 8e -vsxseg5b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg5b.v v8, (a0), v4, v0.t +th.vsxseg5b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg5b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 8c -vsxseg5h.v v8, (a0), v4 -# CHECK-INST: vsxseg5h.v v8, (a0), v4 +th.vsxseg5h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg5h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 8e -vsxseg5h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg5h.v v8, (a0), v4, v0.t +th.vsxseg5h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg5h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 8c -vsxseg5w.v v8, (a0), v4 -# CHECK-INST: vsxseg5w.v v8, (a0), v4 +th.vsxseg5w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg5w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 8e -vsxseg5w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg5w.v v8, (a0), v4, v0.t +th.vsxseg5w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg5w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 8c -vsxseg5e.v v8, (a0), v4 -# CHECK-INST: vsxseg5e.v v8, (a0), v4 +th.vsxseg5e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg5e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0x8e] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 8e -vsxseg5e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg5e.v v8, (a0), v4, v0.t +th.vsxseg5e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg5e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0x8c] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 8c -vlseg6b.v v8, (a0), v0.t -# CHECK-INST: vlseg6b.v v8, (a0), v0.t +th.vlseg6b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 b0 -vlseg6b.v v8, (a0) -# CHECK-INST: vlseg6b.v v8, (a0) +th.vlseg6b.v v8, (a0) +# CHECK-INST: th.vlseg6b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xb2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 b2 -vlseg6h.v v8, (a0), v0.t -# CHECK-INST: vlseg6h.v v8, (a0), v0.t +th.vlseg6h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 b0 -vlseg6h.v v8, (a0) -# CHECK-INST: vlseg6h.v v8, (a0) +th.vlseg6h.v v8, (a0) +# CHECK-INST: th.vlseg6h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xb2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 b2 -vlseg6w.v v8, (a0), v0.t -# CHECK-INST: vlseg6w.v v8, (a0), v0.t +th.vlseg6w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xb0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 b0 -vlseg6w.v v8, (a0) -# CHECK-INST: vlseg6w.v v8, (a0) +th.vlseg6w.v v8, (a0) +# CHECK-INST: th.vlseg6w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xb2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 b2 -vlseg6bu.v v8, (a0), v0.t -# CHECK-INST: vlseg6bu.v v8, (a0), v0.t +th.vlseg6bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 a0 -vlseg6bu.v v8, (a0) -# CHECK-INST: vlseg6bu.v v8, (a0) +th.vlseg6bu.v v8, (a0) +# CHECK-INST: th.vlseg6bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 a2 -vlseg6hu.v v8, (a0), v0.t -# CHECK-INST: vlseg6hu.v v8, (a0), v0.t +th.vlseg6hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 a0 -vlseg6hu.v v8, (a0) -# CHECK-INST: vlseg6hu.v v8, (a0) +th.vlseg6hu.v v8, (a0) +# CHECK-INST: th.vlseg6hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 a2 -vlseg6wu.v v8, (a0), v0.t -# CHECK-INST: vlseg6wu.v v8, (a0), v0.t +th.vlseg6wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 a0 -vlseg6wu.v v8, (a0) -# CHECK-INST: vlseg6wu.v v8, (a0) +th.vlseg6wu.v v8, (a0) +# CHECK-INST: th.vlseg6wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 a2 -vlseg6e.v v8, (a0), v0.t -# CHECK-INST: vlseg6e.v v8, (a0), v0.t +th.vlseg6e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 a0 -vlseg6e.v v8, (a0) -# CHECK-INST: vlseg6e.v v8, (a0) +th.vlseg6e.v v8, (a0) +# CHECK-INST: th.vlseg6e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 a2 -vsseg6b.v v8, (a0), v0.t -# CHECK-INST: vsseg6b.v v8, (a0), v0.t +th.vsseg6b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg6b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 a0 -vsseg6b.v v8, (a0) -# CHECK-INST: vsseg6b.v v8, (a0) +th.vsseg6b.v v8, (a0) +# CHECK-INST: th.vsseg6b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 a2 -vsseg6h.v v8, (a0), v0.t -# CHECK-INST: vsseg6h.v v8, (a0), v0.t +th.vsseg6h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg6h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 a0 -vsseg6h.v v8, (a0) -# CHECK-INST: vsseg6h.v v8, (a0) +th.vsseg6h.v v8, (a0) +# CHECK-INST: th.vsseg6h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 a2 -vsseg6w.v v8, (a0), v0.t -# CHECK-INST: vsseg6w.v v8, (a0), v0.t +th.vsseg6w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg6w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 a0 -vsseg6w.v v8, (a0) -# CHECK-INST: vsseg6w.v v8, (a0) +th.vsseg6w.v v8, (a0) +# CHECK-INST: th.vsseg6w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 a2 -vsseg6e.v v8, (a0), v0.t -# CHECK-INST: vsseg6e.v v8, (a0), v0.t +th.vsseg6e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg6e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0xa0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 a0 -vsseg6e.v v8, (a0) -# CHECK-INST: vsseg6e.v v8, (a0) +th.vsseg6e.v v8, (a0) +# CHECK-INST: th.vsseg6e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0xa2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 a2 -vlseg6bff.v v8, (a0) -# CHECK-INST: vlseg6bff.v v8, (a0) +th.vlseg6bff.v v8, (a0) +# CHECK-INST: th.vlseg6bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xb3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 b3 -vlseg6bff.v v8, (a0), v0.t -# CHECK-INST: vlseg6bff.v v8, (a0), v0.t +th.vlseg6bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xb1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 b1 -vlseg6hff.v v8, (a0) -# CHECK-INST: vlseg6hff.v v8, (a0) +th.vlseg6hff.v v8, (a0) +# CHECK-INST: th.vlseg6hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xb3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 b3 -vlseg6hff.v v8, (a0), v0.t -# CHECK-INST: vlseg6hff.v v8, (a0), v0.t +th.vlseg6hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xb1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 b1 -vlseg6wff.v v8, (a0) -# CHECK-INST: vlseg6wff.v v8, (a0) +th.vlseg6wff.v v8, (a0) +# CHECK-INST: th.vlseg6wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xb3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 b3 -vlseg6wff.v v8, (a0), v0.t -# CHECK-INST: vlseg6wff.v v8, (a0), v0.t +th.vlseg6wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xb1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 b1 -vlseg6buff.v v8, (a0) -# CHECK-INST: vlseg6buff.v v8, (a0) +th.vlseg6buff.v v8, (a0) +# CHECK-INST: th.vlseg6buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xa3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 a3 -vlseg6buff.v v8, (a0), v0.t -# CHECK-INST: vlseg6buff.v v8, (a0), v0.t +th.vlseg6buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xa1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 a1 -vlseg6huff.v v8, (a0) -# CHECK-INST: vlseg6huff.v v8, (a0) +th.vlseg6huff.v v8, (a0) +# CHECK-INST: th.vlseg6huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xa3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 a3 -vlseg6huff.v v8, (a0), v0.t -# CHECK-INST: vlseg6huff.v v8, (a0), v0.t +th.vlseg6huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xa1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 a1 -vlseg6wuff.v v8, (a0) -# CHECK-INST: vlseg6wuff.v v8, (a0) +th.vlseg6wuff.v v8, (a0) +# CHECK-INST: th.vlseg6wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xa3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 a3 -vlseg6wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg6wuff.v v8, (a0), v0.t +th.vlseg6wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xa1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 a1 -vlseg6eff.v v8, (a0) -# CHECK-INST: vlseg6eff.v v8, (a0) +th.vlseg6eff.v v8, (a0) +# CHECK-INST: th.vlseg6eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xa3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 a3 -vlseg6eff.v v8, (a0), v0.t -# CHECK-INST: vlseg6eff.v v8, (a0), v0.t +th.vlseg6eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg6eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xa1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 a1 -vlsseg6b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6b.v v8, (a0), a1, v0.t +th.vlsseg6b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xb8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 b8 -vlsseg6b.v v8, (a0), a1 -# CHECK-INST: vlsseg6b.v v8, (a0), a1 +th.vlsseg6b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xba] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 ba -vlsseg6h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6h.v v8, (a0), a1, v0.t +th.vlsseg6h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xb8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 b8 -vlsseg6h.v v8, (a0), a1 -# CHECK-INST: vlsseg6h.v v8, (a0), a1 +th.vlsseg6h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xba] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 ba -vlsseg6w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6w.v v8, (a0), a1, v0.t +th.vlsseg6w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xb8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 b8 -vlsseg6w.v v8, (a0), a1 -# CHECK-INST: vlsseg6w.v v8, (a0), a1 +th.vlsseg6w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xba] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 ba -vlsseg6bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6bu.v v8, (a0), a1, v0.t +th.vlsseg6bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 a8 -vlsseg6bu.v v8, (a0), a1 -# CHECK-INST: vlsseg6bu.v v8, (a0), a1 +th.vlsseg6bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 aa -vlsseg6hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6hu.v v8, (a0), a1, v0.t +th.vlsseg6hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 a8 -vlsseg6hu.v v8, (a0), a1 -# CHECK-INST: vlsseg6hu.v v8, (a0), a1 +th.vlsseg6hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 aa -vlsseg6wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6wu.v v8, (a0), a1, v0.t +th.vlsseg6wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 a8 -vlsseg6wu.v v8, (a0), a1 -# CHECK-INST: vlsseg6wu.v v8, (a0), a1 +th.vlsseg6wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 aa -vlsseg6e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg6e.v v8, (a0), a1, v0.t +th.vlsseg6e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg6e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 a8 -vlsseg6e.v v8, (a0), a1 -# CHECK-INST: vlsseg6e.v v8, (a0), a1 +th.vlsseg6e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg6e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 aa -vssseg6b.v v8, (a0), a1 -# CHECK-INST: vssseg6b.v v8, (a0), a1 +th.vssseg6b.v v8, (a0), a1 +# CHECK-INST: th.vssseg6b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 aa -vssseg6b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg6b.v v8, (a0), a1, v0.t +th.vssseg6b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg6b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 a8 -vssseg6h.v v8, (a0), a1 -# CHECK-INST: vssseg6h.v v8, (a0), a1 +th.vssseg6h.v v8, (a0), a1 +# CHECK-INST: th.vssseg6h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 aa -vssseg6h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg6h.v v8, (a0), a1, v0.t +th.vssseg6h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg6h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 a8 -vssseg6w.v v8, (a0), a1 -# CHECK-INST: vssseg6w.v v8, (a0), a1 +th.vssseg6w.v v8, (a0), a1 +# CHECK-INST: th.vssseg6w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 aa -vssseg6w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg6w.v v8, (a0), a1, v0.t +th.vssseg6w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg6w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 a8 -vssseg6e.v v8, (a0), a1 -# CHECK-INST: vssseg6e.v v8, (a0), a1 +th.vssseg6e.v v8, (a0), a1 +# CHECK-INST: th.vssseg6e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0xaa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 aa -vssseg6e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg6e.v v8, (a0), a1, v0.t +th.vssseg6e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg6e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0xa8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 a8 -vlxseg6b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6b.v v8, (a0), v4, v0.t +th.vlxseg6b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xbc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 bc -vlxseg6b.v v8, (a0), v4 -# CHECK-INST: vlxseg6b.v v8, (a0), v4 +th.vlxseg6b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xbe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 be -vlxseg6h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6h.v v8, (a0), v4, v0.t +th.vlxseg6h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xbc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 bc -vlxseg6h.v v8, (a0), v4 -# CHECK-INST: vlxseg6h.v v8, (a0), v4 +th.vlxseg6h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xbe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 be -vlxseg6w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6w.v v8, (a0), v4, v0.t +th.vlxseg6w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xbc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 bc -vlxseg6w.v v8, (a0), v4 -# CHECK-INST: vlxseg6w.v v8, (a0), v4 +th.vlxseg6w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xbe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 be -vlxseg6bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6bu.v v8, (a0), v4, v0.t +th.vlxseg6bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 ac -vlxseg6bu.v v8, (a0), v4 -# CHECK-INST: vlxseg6bu.v v8, (a0), v4 +th.vlxseg6bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 ae -vlxseg6hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6hu.v v8, (a0), v4, v0.t +th.vlxseg6hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 ac -vlxseg6hu.v v8, (a0), v4 -# CHECK-INST: vlxseg6hu.v v8, (a0), v4 +th.vlxseg6hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 ae -vlxseg6wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6wu.v v8, (a0), v4, v0.t +th.vlxseg6wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 ac -vlxseg6wu.v v8, (a0), v4 -# CHECK-INST: vlxseg6wu.v v8, (a0), v4 +th.vlxseg6wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 ae -vlxseg6e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg6e.v v8, (a0), v4, v0.t +th.vlxseg6e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg6e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 ac -vlxseg6e.v v8, (a0), v4 -# CHECK-INST: vlxseg6e.v v8, (a0), v4 +th.vlxseg6e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg6e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 ae -vsxseg6b.v v8, (a0), v4 -# CHECK-INST: vsxseg6b.v v8, (a0), v4 +th.vsxseg6b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg6b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 ae -vsxseg6b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg6b.v v8, (a0), v4, v0.t +th.vsxseg6b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg6b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 ac -vsxseg6h.v v8, (a0), v4 -# CHECK-INST: vsxseg6h.v v8, (a0), v4 +th.vsxseg6h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg6h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 ae -vsxseg6h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg6h.v v8, (a0), v4, v0.t +th.vsxseg6h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg6h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 ac -vsxseg6w.v v8, (a0), v4 -# CHECK-INST: vsxseg6w.v v8, (a0), v4 +th.vsxseg6w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg6w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 ae -vsxseg6w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg6w.v v8, (a0), v4, v0.t +th.vsxseg6w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg6w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 ac -vsxseg6e.v v8, (a0), v4 -# CHECK-INST: vsxseg6e.v v8, (a0), v4 +th.vsxseg6e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg6e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0xae] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 ae -vsxseg6e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg6e.v v8, (a0), v4, v0.t +th.vsxseg6e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg6e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0xac] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 ac -vlseg7b.v v8, (a0), v0.t -# CHECK-INST: vlseg7b.v v8, (a0), v0.t +th.vlseg7b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xd0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 d0 -vlseg7b.v v8, (a0) -# CHECK-INST: vlseg7b.v v8, (a0) +th.vlseg7b.v v8, (a0) +# CHECK-INST: th.vlseg7b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xd2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 d2 -vlseg7h.v v8, (a0), v0.t -# CHECK-INST: vlseg7h.v v8, (a0), v0.t +th.vlseg7h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xd0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 d0 -vlseg7h.v v8, (a0) -# CHECK-INST: vlseg7h.v v8, (a0) +th.vlseg7h.v v8, (a0) +# CHECK-INST: th.vlseg7h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xd2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 d2 -vlseg7w.v v8, (a0), v0.t -# CHECK-INST: vlseg7w.v v8, (a0), v0.t +th.vlseg7w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xd0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 d0 -vlseg7w.v v8, (a0) -# CHECK-INST: vlseg7w.v v8, (a0) +th.vlseg7w.v v8, (a0) +# CHECK-INST: th.vlseg7w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xd2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 d2 -vlseg7bu.v v8, (a0), v0.t -# CHECK-INST: vlseg7bu.v v8, (a0), v0.t +th.vlseg7bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 c0 -vlseg7bu.v v8, (a0) -# CHECK-INST: vlseg7bu.v v8, (a0) +th.vlseg7bu.v v8, (a0) +# CHECK-INST: th.vlseg7bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 c2 -vlseg7hu.v v8, (a0), v0.t -# CHECK-INST: vlseg7hu.v v8, (a0), v0.t +th.vlseg7hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 c0 -vlseg7hu.v v8, (a0) -# CHECK-INST: vlseg7hu.v v8, (a0) +th.vlseg7hu.v v8, (a0) +# CHECK-INST: th.vlseg7hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 c2 -vlseg7wu.v v8, (a0), v0.t -# CHECK-INST: vlseg7wu.v v8, (a0), v0.t +th.vlseg7wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 c0 -vlseg7wu.v v8, (a0) -# CHECK-INST: vlseg7wu.v v8, (a0) +th.vlseg7wu.v v8, (a0) +# CHECK-INST: th.vlseg7wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 c2 -vlseg7e.v v8, (a0), v0.t -# CHECK-INST: vlseg7e.v v8, (a0), v0.t +th.vlseg7e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 c0 -vlseg7e.v v8, (a0) -# CHECK-INST: vlseg7e.v v8, (a0) +th.vlseg7e.v v8, (a0) +# CHECK-INST: th.vlseg7e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 c2 -vsseg7b.v v8, (a0), v0.t -# CHECK-INST: vsseg7b.v v8, (a0), v0.t +th.vsseg7b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg7b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 c0 -vsseg7b.v v8, (a0) -# CHECK-INST: vsseg7b.v v8, (a0) +th.vsseg7b.v v8, (a0) +# CHECK-INST: th.vsseg7b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 c2 -vsseg7h.v v8, (a0), v0.t -# CHECK-INST: vsseg7h.v v8, (a0), v0.t +th.vsseg7h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg7h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 c0 -vsseg7h.v v8, (a0) -# CHECK-INST: vsseg7h.v v8, (a0) +th.vsseg7h.v v8, (a0) +# CHECK-INST: th.vsseg7h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 c2 -vsseg7w.v v8, (a0), v0.t -# CHECK-INST: vsseg7w.v v8, (a0), v0.t +th.vsseg7w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg7w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 c0 -vsseg7w.v v8, (a0) -# CHECK-INST: vsseg7w.v v8, (a0) +th.vsseg7w.v v8, (a0) +# CHECK-INST: th.vsseg7w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 c2 -vsseg7e.v v8, (a0), v0.t -# CHECK-INST: vsseg7e.v v8, (a0), v0.t +th.vsseg7e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg7e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0xc0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 c0 -vsseg7e.v v8, (a0) -# CHECK-INST: vsseg7e.v v8, (a0) +th.vsseg7e.v v8, (a0) +# CHECK-INST: th.vsseg7e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0xc2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 c2 -vlseg7bff.v v8, (a0) -# CHECK-INST: vlseg7bff.v v8, (a0) +th.vlseg7bff.v v8, (a0) +# CHECK-INST: th.vlseg7bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xd3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 d3 -vlseg7bff.v v8, (a0), v0.t -# CHECK-INST: vlseg7bff.v v8, (a0), v0.t +th.vlseg7bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xd1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 d1 -vlseg7hff.v v8, (a0) -# CHECK-INST: vlseg7hff.v v8, (a0) +th.vlseg7hff.v v8, (a0) +# CHECK-INST: th.vlseg7hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xd3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 d3 -vlseg7hff.v v8, (a0), v0.t -# CHECK-INST: vlseg7hff.v v8, (a0), v0.t +th.vlseg7hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xd1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 d1 -vlseg7wff.v v8, (a0) -# CHECK-INST: vlseg7wff.v v8, (a0) +th.vlseg7wff.v v8, (a0) +# CHECK-INST: th.vlseg7wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xd3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 d3 -vlseg7wff.v v8, (a0), v0.t -# CHECK-INST: vlseg7wff.v v8, (a0), v0.t +th.vlseg7wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xd1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 d1 -vlseg7buff.v v8, (a0) -# CHECK-INST: vlseg7buff.v v8, (a0) +th.vlseg7buff.v v8, (a0) +# CHECK-INST: th.vlseg7buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xc3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 c3 -vlseg7buff.v v8, (a0), v0.t -# CHECK-INST: vlseg7buff.v v8, (a0), v0.t +th.vlseg7buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xc1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 c1 -vlseg7huff.v v8, (a0) -# CHECK-INST: vlseg7huff.v v8, (a0) +th.vlseg7huff.v v8, (a0) +# CHECK-INST: th.vlseg7huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xc3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 c3 -vlseg7huff.v v8, (a0), v0.t -# CHECK-INST: vlseg7huff.v v8, (a0), v0.t +th.vlseg7huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xc1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 c1 -vlseg7wuff.v v8, (a0) -# CHECK-INST: vlseg7wuff.v v8, (a0) +th.vlseg7wuff.v v8, (a0) +# CHECK-INST: th.vlseg7wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xc3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 c3 -vlseg7wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg7wuff.v v8, (a0), v0.t +th.vlseg7wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xc1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 c1 -vlseg7eff.v v8, (a0) -# CHECK-INST: vlseg7eff.v v8, (a0) +th.vlseg7eff.v v8, (a0) +# CHECK-INST: th.vlseg7eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xc3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 c3 -vlseg7eff.v v8, (a0), v0.t -# CHECK-INST: vlseg7eff.v v8, (a0), v0.t +th.vlseg7eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg7eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xc1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 c1 -vlsseg7b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7b.v v8, (a0), a1, v0.t +th.vlsseg7b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xd8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 d8 -vlsseg7b.v v8, (a0), a1 -# CHECK-INST: vlsseg7b.v v8, (a0), a1 +th.vlsseg7b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xda] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 da -vlsseg7h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7h.v v8, (a0), a1, v0.t +th.vlsseg7h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xd8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 d8 -vlsseg7h.v v8, (a0), a1 -# CHECK-INST: vlsseg7h.v v8, (a0), a1 +th.vlsseg7h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xda] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 da -vlsseg7w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7w.v v8, (a0), a1, v0.t +th.vlsseg7w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xd8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 d8 -vlsseg7w.v v8, (a0), a1 -# CHECK-INST: vlsseg7w.v v8, (a0), a1 +th.vlsseg7w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xda] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 da -vlsseg7bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7bu.v v8, (a0), a1, v0.t +th.vlsseg7bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 c8 -vlsseg7bu.v v8, (a0), a1 -# CHECK-INST: vlsseg7bu.v v8, (a0), a1 +th.vlsseg7bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 ca -vlsseg7hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7hu.v v8, (a0), a1, v0.t +th.vlsseg7hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 c8 -vlsseg7hu.v v8, (a0), a1 -# CHECK-INST: vlsseg7hu.v v8, (a0), a1 +th.vlsseg7hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 ca -vlsseg7wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7wu.v v8, (a0), a1, v0.t +th.vlsseg7wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 c8 -vlsseg7wu.v v8, (a0), a1 -# CHECK-INST: vlsseg7wu.v v8, (a0), a1 +th.vlsseg7wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 ca -vlsseg7e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg7e.v v8, (a0), a1, v0.t +th.vlsseg7e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg7e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 c8 -vlsseg7e.v v8, (a0), a1 -# CHECK-INST: vlsseg7e.v v8, (a0), a1 +th.vlsseg7e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg7e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 ca -vssseg7b.v v8, (a0), a1 -# CHECK-INST: vssseg7b.v v8, (a0), a1 +th.vssseg7b.v v8, (a0), a1 +# CHECK-INST: th.vssseg7b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 ca -vssseg7b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg7b.v v8, (a0), a1, v0.t +th.vssseg7b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg7b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 c8 -vssseg7h.v v8, (a0), a1 -# CHECK-INST: vssseg7h.v v8, (a0), a1 +th.vssseg7h.v v8, (a0), a1 +# CHECK-INST: th.vssseg7h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 ca -vssseg7h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg7h.v v8, (a0), a1, v0.t +th.vssseg7h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg7h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 c8 -vssseg7w.v v8, (a0), a1 -# CHECK-INST: vssseg7w.v v8, (a0), a1 +th.vssseg7w.v v8, (a0), a1 +# CHECK-INST: th.vssseg7w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 ca -vssseg7w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg7w.v v8, (a0), a1, v0.t +th.vssseg7w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg7w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 c8 -vssseg7e.v v8, (a0), a1 -# CHECK-INST: vssseg7e.v v8, (a0), a1 +th.vssseg7e.v v8, (a0), a1 +# CHECK-INST: th.vssseg7e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0xca] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 ca -vssseg7e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg7e.v v8, (a0), a1, v0.t +th.vssseg7e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg7e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0xc8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 c8 -vlxseg7b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7b.v v8, (a0), v4, v0.t +th.vlxseg7b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xdc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 dc -vlxseg7b.v v8, (a0), v4 -# CHECK-INST: vlxseg7b.v v8, (a0), v4 +th.vlxseg7b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xde] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 de -vlxseg7h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7h.v v8, (a0), v4, v0.t +th.vlxseg7h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xdc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 dc -vlxseg7h.v v8, (a0), v4 -# CHECK-INST: vlxseg7h.v v8, (a0), v4 +th.vlxseg7h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xde] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 de -vlxseg7w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7w.v v8, (a0), v4, v0.t +th.vlxseg7w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xdc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 dc -vlxseg7w.v v8, (a0), v4 -# CHECK-INST: vlxseg7w.v v8, (a0), v4 +th.vlxseg7w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xde] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 de -vlxseg7bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7bu.v v8, (a0), v4, v0.t +th.vlxseg7bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 cc -vlxseg7bu.v v8, (a0), v4 -# CHECK-INST: vlxseg7bu.v v8, (a0), v4 +th.vlxseg7bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 ce -vlxseg7hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7hu.v v8, (a0), v4, v0.t +th.vlxseg7hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 cc -vlxseg7hu.v v8, (a0), v4 -# CHECK-INST: vlxseg7hu.v v8, (a0), v4 +th.vlxseg7hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 ce -vlxseg7wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7wu.v v8, (a0), v4, v0.t +th.vlxseg7wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 cc -vlxseg7wu.v v8, (a0), v4 -# CHECK-INST: vlxseg7wu.v v8, (a0), v4 +th.vlxseg7wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 ce -vlxseg7e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg7e.v v8, (a0), v4, v0.t +th.vlxseg7e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg7e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 cc -vlxseg7e.v v8, (a0), v4 -# CHECK-INST: vlxseg7e.v v8, (a0), v4 +th.vlxseg7e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg7e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 ce -vsxseg7b.v v8, (a0), v4 -# CHECK-INST: vsxseg7b.v v8, (a0), v4 +th.vsxseg7b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg7b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 ce -vsxseg7b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg7b.v v8, (a0), v4, v0.t +th.vsxseg7b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg7b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 cc -vsxseg7h.v v8, (a0), v4 -# CHECK-INST: vsxseg7h.v v8, (a0), v4 +th.vsxseg7h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg7h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 ce -vsxseg7h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg7h.v v8, (a0), v4, v0.t +th.vsxseg7h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg7h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 cc -vsxseg7w.v v8, (a0), v4 -# CHECK-INST: vsxseg7w.v v8, (a0), v4 +th.vsxseg7w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg7w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 ce -vsxseg7w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg7w.v v8, (a0), v4, v0.t +th.vsxseg7w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg7w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 cc -vsxseg7e.v v8, (a0), v4 -# CHECK-INST: vsxseg7e.v v8, (a0), v4 +th.vsxseg7e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg7e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0xce] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 ce -vsxseg7e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg7e.v v8, (a0), v4, v0.t +th.vsxseg7e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg7e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0xcc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 cc -vlseg8b.v v8, (a0), v0.t -# CHECK-INST: vlseg8b.v v8, (a0), v0.t +th.vlseg8b.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8b.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xf0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 f0 -vlseg8b.v v8, (a0) -# CHECK-INST: vlseg8b.v v8, (a0) +th.vlseg8b.v v8, (a0) +# CHECK-INST: th.vlseg8b.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xf2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 f2 -vlseg8h.v v8, (a0), v0.t -# CHECK-INST: vlseg8h.v v8, (a0), v0.t +th.vlseg8h.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8h.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xf0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 f0 -vlseg8h.v v8, (a0) -# CHECK-INST: vlseg8h.v v8, (a0) +th.vlseg8h.v v8, (a0) +# CHECK-INST: th.vlseg8h.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xf2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 f2 -vlseg8w.v v8, (a0), v0.t -# CHECK-INST: vlseg8w.v v8, (a0), v0.t +th.vlseg8w.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8w.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xf0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 f0 -vlseg8w.v v8, (a0) -# CHECK-INST: vlseg8w.v v8, (a0) +th.vlseg8w.v v8, (a0) +# CHECK-INST: th.vlseg8w.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xf2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 f2 -vlseg8bu.v v8, (a0), v0.t -# CHECK-INST: vlseg8bu.v v8, (a0), v0.t +th.vlseg8bu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8bu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 e0 -vlseg8bu.v v8, (a0) -# CHECK-INST: vlseg8bu.v v8, (a0) +th.vlseg8bu.v v8, (a0) +# CHECK-INST: th.vlseg8bu.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 e2 -vlseg8hu.v v8, (a0), v0.t -# CHECK-INST: vlseg8hu.v v8, (a0), v0.t +th.vlseg8hu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8hu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 e0 -vlseg8hu.v v8, (a0) -# CHECK-INST: vlseg8hu.v v8, (a0) +th.vlseg8hu.v v8, (a0) +# CHECK-INST: th.vlseg8hu.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 e2 -vlseg8wu.v v8, (a0), v0.t -# CHECK-INST: vlseg8wu.v v8, (a0), v0.t +th.vlseg8wu.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8wu.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 e0 -vlseg8wu.v v8, (a0) -# CHECK-INST: vlseg8wu.v v8, (a0) +th.vlseg8wu.v v8, (a0) +# CHECK-INST: th.vlseg8wu.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 e2 -vlseg8e.v v8, (a0), v0.t -# CHECK-INST: vlseg8e.v v8, (a0), v0.t +th.vlseg8e.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8e.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 e0 -vlseg8e.v v8, (a0) -# CHECK-INST: vlseg8e.v v8, (a0) +th.vlseg8e.v v8, (a0) +# CHECK-INST: th.vlseg8e.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 e2 -vsseg8b.v v8, (a0), v0.t -# CHECK-INST: vsseg8b.v v8, (a0), v0.t +th.vsseg8b.v v8, (a0), v0.t +# CHECK-INST: th.vsseg8b.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x04,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 e0 -vsseg8b.v v8, (a0) -# CHECK-INST: vsseg8b.v v8, (a0) +th.vsseg8b.v v8, (a0) +# CHECK-INST: th.vsseg8b.v v8, (a0) # CHECK-ENCODING: [0x27,0x04,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 05 e2 -vsseg8h.v v8, (a0), v0.t -# CHECK-INST: vsseg8h.v v8, (a0), v0.t +th.vsseg8h.v v8, (a0), v0.t +# CHECK-INST: th.vsseg8h.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x54,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 e0 -vsseg8h.v v8, (a0) -# CHECK-INST: vsseg8h.v v8, (a0) +th.vsseg8h.v v8, (a0) +# CHECK-INST: th.vsseg8h.v v8, (a0) # CHECK-ENCODING: [0x27,0x54,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 05 e2 -vsseg8w.v v8, (a0), v0.t -# CHECK-INST: vsseg8w.v v8, (a0), v0.t +th.vsseg8w.v v8, (a0), v0.t +# CHECK-INST: th.vsseg8w.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x64,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 e0 -vsseg8w.v v8, (a0) -# CHECK-INST: vsseg8w.v v8, (a0) +th.vsseg8w.v v8, (a0) +# CHECK-INST: th.vsseg8w.v v8, (a0) # CHECK-ENCODING: [0x27,0x64,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 05 e2 -vsseg8e.v v8, (a0), v0.t -# CHECK-INST: vsseg8e.v v8, (a0), v0.t +th.vsseg8e.v v8, (a0), v0.t +# CHECK-INST: th.vsseg8e.v v8, (a0), v0.t # CHECK-ENCODING: [0x27,0x74,0x05,0xe0] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 e0 -vsseg8e.v v8, (a0) -# CHECK-INST: vsseg8e.v v8, (a0) +th.vsseg8e.v v8, (a0) +# CHECK-INST: th.vsseg8e.v v8, (a0) # CHECK-ENCODING: [0x27,0x74,0x05,0xe2] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 05 e2 -vlseg8bff.v v8, (a0) -# CHECK-INST: vlseg8bff.v v8, (a0) +th.vlseg8bff.v v8, (a0) +# CHECK-INST: th.vlseg8bff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xf3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 f3 -vlseg8bff.v v8, (a0), v0.t -# CHECK-INST: vlseg8bff.v v8, (a0), v0.t +th.vlseg8bff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8bff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xf1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 f1 -vlseg8hff.v v8, (a0) -# CHECK-INST: vlseg8hff.v v8, (a0) +th.vlseg8hff.v v8, (a0) +# CHECK-INST: th.vlseg8hff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xf3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 f3 -vlseg8hff.v v8, (a0), v0.t -# CHECK-INST: vlseg8hff.v v8, (a0), v0.t +th.vlseg8hff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8hff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xf1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 f1 -vlseg8wff.v v8, (a0) -# CHECK-INST: vlseg8wff.v v8, (a0) +th.vlseg8wff.v v8, (a0) +# CHECK-INST: th.vlseg8wff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xf3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 f3 -vlseg8wff.v v8, (a0), v0.t -# CHECK-INST: vlseg8wff.v v8, (a0), v0.t +th.vlseg8wff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8wff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xf1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 f1 -vlseg8buff.v v8, (a0) -# CHECK-INST: vlseg8buff.v v8, (a0) +th.vlseg8buff.v v8, (a0) +# CHECK-INST: th.vlseg8buff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xe3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 e3 -vlseg8buff.v v8, (a0), v0.t -# CHECK-INST: vlseg8buff.v v8, (a0), v0.t +th.vlseg8buff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8buff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xe1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 05 e1 -vlseg8huff.v v8, (a0) -# CHECK-INST: vlseg8huff.v v8, (a0) +th.vlseg8huff.v v8, (a0) +# CHECK-INST: th.vlseg8huff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xe3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 e3 -vlseg8huff.v v8, (a0), v0.t -# CHECK-INST: vlseg8huff.v v8, (a0), v0.t +th.vlseg8huff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8huff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xe1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 05 e1 -vlseg8wuff.v v8, (a0) -# CHECK-INST: vlseg8wuff.v v8, (a0) +th.vlseg8wuff.v v8, (a0) +# CHECK-INST: th.vlseg8wuff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xe3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 e3 -vlseg8wuff.v v8, (a0), v0.t -# CHECK-INST: vlseg8wuff.v v8, (a0), v0.t +th.vlseg8wuff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8wuff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xe1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 05 e1 -vlseg8eff.v v8, (a0) -# CHECK-INST: vlseg8eff.v v8, (a0) +th.vlseg8eff.v v8, (a0) +# CHECK-INST: th.vlseg8eff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xe3] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 e3 -vlseg8eff.v v8, (a0), v0.t -# CHECK-INST: vlseg8eff.v v8, (a0), v0.t +th.vlseg8eff.v v8, (a0), v0.t +# CHECK-INST: th.vlseg8eff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xe1] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 05 e1 -vlsseg8b.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8b.v v8, (a0), a1, v0.t +th.vlsseg8b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xf8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 f8 -vlsseg8b.v v8, (a0), a1 -# CHECK-INST: vlsseg8b.v v8, (a0), a1 +th.vlsseg8b.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8b.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xfa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 fa -vlsseg8h.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8h.v v8, (a0), a1, v0.t +th.vlsseg8h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xf8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 f8 -vlsseg8h.v v8, (a0), a1 -# CHECK-INST: vlsseg8h.v v8, (a0), a1 +th.vlsseg8h.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8h.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xfa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 fa -vlsseg8w.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8w.v v8, (a0), a1, v0.t +th.vlsseg8w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xf8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 f8 -vlsseg8w.v v8, (a0), a1 -# CHECK-INST: vlsseg8w.v v8, (a0), a1 +th.vlsseg8w.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8w.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xfa] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 fa -vlsseg8bu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8bu.v v8, (a0), a1, v0.t +th.vlsseg8bu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8bu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 e8 -vlsseg8bu.v v8, (a0), a1 -# CHECK-INST: vlsseg8bu.v v8, (a0), a1 +th.vlsseg8bu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8bu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 b5 ea -vlsseg8hu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8hu.v v8, (a0), a1, v0.t +th.vlsseg8hu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8hu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 e8 -vlsseg8hu.v v8, (a0), a1 -# CHECK-INST: vlsseg8hu.v v8, (a0), a1 +th.vlsseg8hu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8hu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 b5 ea -vlsseg8wu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8wu.v v8, (a0), a1, v0.t +th.vlsseg8wu.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8wu.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 e8 -vlsseg8wu.v v8, (a0), a1 -# CHECK-INST: vlsseg8wu.v v8, (a0), a1 +th.vlsseg8wu.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8wu.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 b5 ea -vlsseg8e.v v8, (a0), a1, v0.t -# CHECK-INST: vlsseg8e.v v8, (a0), a1, v0.t +th.vlsseg8e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vlsseg8e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 e8 -vlsseg8e.v v8, (a0), a1 -# CHECK-INST: vlsseg8e.v v8, (a0), a1 +th.vlsseg8e.v v8, (a0), a1 +# CHECK-INST: th.vlsseg8e.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 b5 ea -vssseg8b.v v8, (a0), a1 -# CHECK-INST: vssseg8b.v v8, (a0), a1 +th.vssseg8b.v v8, (a0), a1 +# CHECK-INST: th.vssseg8b.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x04,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 ea -vssseg8b.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg8b.v v8, (a0), a1, v0.t +th.vssseg8b.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg8b.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x04,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 b5 e8 -vssseg8h.v v8, (a0), a1 -# CHECK-INST: vssseg8h.v v8, (a0), a1 +th.vssseg8h.v v8, (a0), a1 +# CHECK-INST: th.vssseg8h.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x54,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 ea -vssseg8h.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg8h.v v8, (a0), a1, v0.t +th.vssseg8h.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg8h.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x54,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 b5 e8 -vssseg8w.v v8, (a0), a1 -# CHECK-INST: vssseg8w.v v8, (a0), a1 +th.vssseg8w.v v8, (a0), a1 +# CHECK-INST: th.vssseg8w.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x64,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 ea -vssseg8w.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg8w.v v8, (a0), a1, v0.t +th.vssseg8w.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg8w.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x64,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 b5 e8 -vssseg8e.v v8, (a0), a1 -# CHECK-INST: vssseg8e.v v8, (a0), a1 +th.vssseg8e.v v8, (a0), a1 +# CHECK-INST: th.vssseg8e.v v8, (a0), a1 # CHECK-ENCODING: [0x27,0x74,0xb5,0xea] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 ea -vssseg8e.v v8, (a0), a1, v0.t -# CHECK-INST: vssseg8e.v v8, (a0), a1, v0.t +th.vssseg8e.v v8, (a0), a1, v0.t +# CHECK-INST: th.vssseg8e.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x74,0xb5,0xe8] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 b5 e8 -vlxseg8b.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8b.v v8, (a0), v4, v0.t +th.vlxseg8b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xfc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 fc -vlxseg8b.v v8, (a0), v4 -# CHECK-INST: vlxseg8b.v v8, (a0), v4 +th.vlxseg8b.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8b.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xfe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 fe -vlxseg8h.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8h.v v8, (a0), v4, v0.t +th.vlxseg8h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xfc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 fc -vlxseg8h.v v8, (a0), v4 -# CHECK-INST: vlxseg8h.v v8, (a0), v4 +th.vlxseg8h.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8h.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xfe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 fe -vlxseg8w.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8w.v v8, (a0), v4, v0.t +th.vlxseg8w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xfc] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 fc -vlxseg8w.v v8, (a0), v4 -# CHECK-INST: vlxseg8w.v v8, (a0), v4 +th.vlxseg8w.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8w.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xfe] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 fe -vlxseg8bu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8bu.v v8, (a0), v4, v0.t +th.vlxseg8bu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8bu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 ec -vlxseg8bu.v v8, (a0), v4 -# CHECK-INST: vlxseg8bu.v v8, (a0), v4 +th.vlxseg8bu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8bu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 04 45 ee -vlxseg8hu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8hu.v v8, (a0), v4, v0.t +th.vlxseg8hu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8hu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 ec -vlxseg8hu.v v8, (a0), v4 -# CHECK-INST: vlxseg8hu.v v8, (a0), v4 +th.vlxseg8hu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8hu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 54 45 ee -vlxseg8wu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8wu.v v8, (a0), v4, v0.t +th.vlxseg8wu.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8wu.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 ec -vlxseg8wu.v v8, (a0), v4 -# CHECK-INST: vlxseg8wu.v v8, (a0), v4 +th.vlxseg8wu.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8wu.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 64 45 ee -vlxseg8e.v v8, (a0), v4, v0.t -# CHECK-INST: vlxseg8e.v v8, (a0), v4, v0.t +th.vlxseg8e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vlxseg8e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 ec -vlxseg8e.v v8, (a0), v4 -# CHECK-INST: vlxseg8e.v v8, (a0), v4 +th.vlxseg8e.v v8, (a0), v4 +# CHECK-INST: th.vlxseg8e.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 07 74 45 ee -vsxseg8b.v v8, (a0), v4 -# CHECK-INST: vsxseg8b.v v8, (a0), v4 +th.vsxseg8b.v v8, (a0), v4 +# CHECK-INST: th.vsxseg8b.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x04,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 ee -vsxseg8b.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg8b.v v8, (a0), v4, v0.t +th.vsxseg8b.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg8b.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x04,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 04 45 ec -vsxseg8h.v v8, (a0), v4 -# CHECK-INST: vsxseg8h.v v8, (a0), v4 +th.vsxseg8h.v v8, (a0), v4 +# CHECK-INST: th.vsxseg8h.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x54,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 ee -vsxseg8h.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg8h.v v8, (a0), v4, v0.t +th.vsxseg8h.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg8h.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x54,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 54 45 ec -vsxseg8w.v v8, (a0), v4 -# CHECK-INST: vsxseg8w.v v8, (a0), v4 +th.vsxseg8w.v v8, (a0), v4 +# CHECK-INST: th.vsxseg8w.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x64,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 ee -vsxseg8w.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg8w.v v8, (a0), v4, v0.t +th.vsxseg8w.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg8w.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x64,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 64 45 ec -vsxseg8e.v v8, (a0), v4 -# CHECK-INST: vsxseg8e.v v8, (a0), v4 +th.vsxseg8e.v v8, (a0), v4 +# CHECK-INST: th.vsxseg8e.v v8, (a0), v4 # CHECK-ENCODING: [0x27,0x74,0x45,0xee] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 ee -vsxseg8e.v v8, (a0), v4, v0.t -# CHECK-INST: vsxseg8e.v v8, (a0), v4, v0.t +th.vsxseg8e.v v8, (a0), v4, v0.t +# CHECK-INST: th.vsxseg8e.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x74,0x45,0xec] -# CHECK-ERROR: unrecognized instruction mnemonic +# CHECK-ERROR: instruction requires the following: 'xtheadvector' (T-Head Base Vector Instructions), 'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions){{$}} # CHECK-UNKNOWN: 27 74 45 ec diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 290f4932ac041..faec0a8d42f04 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -475,9 +475,9 @@ TEST(ParseArchString, RejectsConflictingExtensions) { "'zcf' is only supported for 'rv32'"); } - for (StringRef Input : {"rv64iv_xtheadv", "rv32iv_xtheadv"}) { + for (StringRef Input : {"rv64iv_xtheadvector", "rv32iv_xtheadvector"}) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'xtheadv' extension is incompatible with " + "'xtheadvector' extension is incompatible with " "'v' or 'zve*' extension"); } }