From 19467ffa58cd8759f983f9ee7c531faaf75b5754 Mon Sep 17 00:00:00 2001
From: Steve Hoover <steve_github@hooverfam.net>
Date: Sun, 4 Feb 2024 01:49:27 -0500
Subject: [PATCH] Slow col.

---
 src/top.sv | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/top.sv b/src/top.sv
index dbf8851..e05f3eb 100644
--- a/src/top.sv
+++ b/src/top.sv
@@ -130,8 +130,8 @@ logic FpgaPins_Fpga_PIPE_ResetFell_n1,
       FpgaPins_Fpga_PIPE_ResetFell_a0;
 
 // For /fpga_pins/fpga|pipe$Seq.
-logic [7:0] FpgaPins_Fpga_PIPE_Seq_n1,
-            FpgaPins_Fpga_PIPE_Seq_a0;
+logic [21:0] FpgaPins_Fpga_PIPE_Seq_n1,
+             FpgaPins_Fpga_PIPE_Seq_a0;
 
 // For /fpga_pins/fpga|pipe$reset.
 logic FpgaPins_Fpga_PIPE_reset_n1,
@@ -183,7 +183,7 @@ logic FpgaPins_Fpga_PIPE_update_a0;
             always_ff @(posedge clk) FpgaPins_Fpga_PIPE_ResetFell_a0 <= FpgaPins_Fpga_PIPE_ResetFell_n1;
 
             // Staging of $Seq.
-            always_ff @(posedge clk) FpgaPins_Fpga_PIPE_Seq_a0[7:0] <= FpgaPins_Fpga_PIPE_Seq_n1[7:0];
+            always_ff @(posedge clk) FpgaPins_Fpga_PIPE_Seq_a0[21:0] <= FpgaPins_Fpga_PIPE_Seq_n1[21:0];
 
             // Staging of $reset.
             always_ff @(posedge clk) FpgaPins_Fpga_PIPE_reset_a0 <= FpgaPins_Fpga_PIPE_reset_n1;
@@ -249,7 +249,7 @@ logic FpgaPins_Fpga_PIPE_update_a0;
                assign \///@-1$LastButton = FpgaPins_Fpga_PIPE_LastButton_n1;
                (* keep *) logic  \///@-1$ResetFell ;
                assign \///@-1$ResetFell = FpgaPins_Fpga_PIPE_ResetFell_n1;
-               (* keep *) logic [7:0] \///@-1$Seq ;
+               (* keep *) logic [21:0] \///@-1$Seq ;
                assign \///@-1$Seq = FpgaPins_Fpga_PIPE_Seq_n1;
                (* keep *) logic  \///@-1$reset ;
                assign \///@-1$reset = FpgaPins_Fpga_PIPE_reset_n1;
@@ -324,10 +324,10 @@ logic FpgaPins_Fpga_PIPE_update_a0;
                      assign uo_out = {FpgaPins_Fpga_PIPE_LastButton_a0, 4'b1 << FpgaPins_Fpga_PIPE_Col_a0};
                      assign FpgaPins_Fpga_PIPE_reset_falls_a0 = ! FpgaPins_Fpga_PIPE_reset_a0 && FpgaPins_Fpga_PIPE_reset_a1;
                      assign FpgaPins_Fpga_PIPE_ResetFell_n1 = FpgaPins_Fpga_PIPE_reset_falls_a0 || FpgaPins_Fpga_PIPE_ResetFell_a0;
-                     assign FpgaPins_Fpga_PIPE_Seq_n1[7:0] =
+                     assign FpgaPins_Fpga_PIPE_Seq_n1[21:0] =
                         FpgaPins_Fpga_PIPE_reset_a0 ? 0 : FpgaPins_Fpga_PIPE_Seq_a0 + 1;
                      assign FpgaPins_Fpga_PIPE_update_a0 = FpgaPins_Fpga_PIPE_Seq_a0 == 0;
-                     assign FpgaPins_Fpga_PIPE_sample_a0 = FpgaPins_Fpga_PIPE_Seq_a0 == ~ 8'b0;
+                     assign FpgaPins_Fpga_PIPE_sample_a0 = FpgaPins_Fpga_PIPE_Seq_a0 == ~ 22'b0;
                      assign FpgaPins_Fpga_PIPE_Col_n1[1:0] =
                         FpgaPins_Fpga_PIPE_reset_a0  ? 2'b0 :
                         FpgaPins_Fpga_PIPE_update_a0 ? FpgaPins_Fpga_PIPE_Col_a0 + 2'b1 :