mealy.vcd

$date
  Wed Aug 26 16:22:45 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module mealy_tb $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var reg 1 # enable $end
$var reg 2 $ o[1:0] $end
$var integer 32 % i $end
$scope module mealy_test $end
$var reg 1 & clk $end
$var reg 1 ' reset $end
$var reg 1 ( enable $end
$var integer 32 ) i $end
$var reg 2 * o[1:0] $end
$var integer 32 + state $end
$var integer 32 , next_state $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
1"
0#
b00 $
b1 %
0&
1'
0(
b1 )
b00 *
b0 +
b1 ,
#10
1!
0"
1#
b0 %
1&
0'
1(
b0 )
b1 +
b10 ,
#20
0!
0&
#30
1!
b10 $
1&
b10 *
b10 +
b100 ,
#40
0!
0&
#50
1!
b01 $
1&
b01 *
b100 +
#60
0!
0&
#70
1!
b00 $
b1 %
1&
b1 )
b00 *
b101 ,
#80
0!
0&
#90
1!
1&
b101 +
b0 ,
#100
0!
0&
#110
1!
1&
b0 +
b1 ,
#120