sys_zelle.vcd

$date
  Thu Sep 03 11:56:22 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module sys_zelle_tb $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var integer 32 # links_in $end
$var integer 32 $ oben_in $end
$scope module sys_zelle_1 $end
$var reg 1 % clk $end
$var reg 1 & reset $end
$var integer 32 ' links_in $end
$var integer 32 ( oben_in $end
$var integer 32 ) unten_out $end
$var integer 32 * rechts_out $end
$var integer 32 + ergebnis_out $end
$var integer 32 , speicher $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
1"
b10000000000000000000000000000000 #
b10000000000000000000000000000000 $
0%
1&
b10000000000000000000000000000000 '
b10000000000000000000000000000000 (
b0 )
b0 *
b0 +
b0 ,
#10
1!
0"
b10 #
b10 $
1%
0&
b10 '
b10 (
b10 )
b10 *
b100 ,
#20
0!
0%
b100 +
#30
1!
1%
b1000 ,
#40
0!
0%
b1000 +
#50