From d2146e4c88ee2b3a1003411151b4ac7150ead1a7 Mon Sep 17 00:00:00 2001 From: Haiwen Xia Date: Wed, 11 Dec 2024 15:28:13 +0800 Subject: [PATCH] riscv:telink: disable retention ramcode proc. - will not proc ramcode in start.s . Signed-off-by: Haiwen Xia --- .github/workflows/chef.yaml | 2 +- .github/workflows/examples-telink.yaml | 2 +- config/telink/chip-module/Kconfig.defaults | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/chef.yaml b/.github/workflows/chef.yaml index 9d97c4e2272750..a673479c22e195 100644 --- a/.github/workflows/chef.yaml +++ b/.github/workflows/chef.yaml @@ -111,7 +111,7 @@ jobs: platform: telink - name: Update Zephyr to specific revision (for developers purpose) shell: bash - run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 6992cc68609189a5eb9d7810416de8610dfccc51" + run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 3108dced67ee46d7b00a0abb3d7155e32c2b7c6f" - name: CI Examples Telink shell: bash run: | diff --git a/.github/workflows/examples-telink.yaml b/.github/workflows/examples-telink.yaml index f94a4ab331b475..1a778dcc2f7d02 100644 --- a/.github/workflows/examples-telink.yaml +++ b/.github/workflows/examples-telink.yaml @@ -58,7 +58,7 @@ jobs: gh-context: ${{ toJson(github) }} - name: Update Zephyr to specific revision (for developers purpose) - run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 6992cc68609189a5eb9d7810416de8610dfccc51" + run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 3108dced67ee46d7b00a0abb3d7155e32c2b7c6f" - name: Build example Telink (B92 retention) Air Quality Sensor App # Run test for master and s07641069 PRs diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults index d118362b3068a1..d36582eafffba4 100644 --- a/config/telink/chip-module/Kconfig.defaults +++ b/config/telink/chip-module/Kconfig.defaults @@ -34,7 +34,7 @@ choice LOG_MODE endchoice choice MATTER_LOG_LEVEL_CHOICE - default MATTER_LOG_LEVEL_WRN if SOC_RISCV_TELINK_TL321X + default MATTER_LOG_LEVEL_DBG if SOC_RISCV_TELINK_TL321X default MATTER_LOG_LEVEL_DBG endchoice @@ -223,7 +223,7 @@ endif if BOARD_TL3218X_RETENTION config SOC_SERIES_RISCV_TELINK_TLX_NON_RETENTION_RAM_CODE - default y if PM + default n if PM config TELINK_TLX_MATTER_RETENTION_LAYOUT default y if PM