Add support for VHDL and SystemVerilog syntax highlinting

[rafaelnp]

Thanks for the nice tool, really useful. I would like to request support for VHDL and SystemVerilog syntax highlingting. It would a nice addition for FPGA/ASIC development workflow.

[keith-hall]

Have you tried any existing syntax definitions to recommend one? https://packagecontrol.io/search/Vhdl
https://github.com/sharkdp/bat#adding-new-syntaxes--language-definitions

[rafaelnp]

Thanks for your reply. No, I was not aware of these links. I will try to implement what is described, and reply my results. Nevertheless, I would be helpful and nice to have this syntax support of out the box. :)

[rafaelnp]

@keith-hall: I did as you suggested, and it worked using the following sublime text packages, in case anyone else wants to use it:

VHDL:

• https://packagecontrol.io/packages/Smart%20VHDL

SystemVerilog:

• https://packagecontrol.io/packages/SystemVerilog

And the list of commands to install them:

mkdir -p "$(bat --config-dir)/syntaxes" ; \
cd "$(bat --config-dir)/syntaxes" ; \
git clone https://github.com/TheClams/SmartVHDL.git ; \
git clone https://github.com/TheClams/SystemVerilog.git ; \
bat cache --build

[goldenwunder]

thanks for the tip and the good instructions - worked a treat for me.

[sharkdp]

Glad that worked. Closing this for now.