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Arty-A7 35 で DDR access 実装 #4

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shin-yamashita opened this issue Jun 12, 2022 · 0 comments

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shin-yamashita commented Jun 12, 2022 •

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Arty-A7 35 の DDR memory を、rv_core から access する。

MIG で ddr3memc (AXI4 interface) 生成。
rv_core の bus に chache unit を接続、AXIでメモリアクセス

shin-yamashita changed the title ~~Arty-A35 で DDR akusesu~~ Arty-A35 で DDR access 実装

shin-yamashita changed the title ~~Arty-A35 で DDR access 実装~~ Arty-A7 35 で DDR access 実装

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