README.md

RISC V

Table of contents:

• Aim
• About the project
• Theory
• Flowchart
• Tech stack
• Getting Started
• Usage
• Screen shot and demo
• Future work
• Troubleshooting
• Contributors
• Mentors
• Acknowlegdements and Resources

Aim:

To build a 32-bit RISC V processor core in logisim.

About the project:

RISC-V(Reduced Instruction Set Architecture) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. This project focuses on making a RISC-V CPU Core using logisim software.

RISC-V is significant because it will allow smaller device manufacturers to build hardware without paying royalties and allow developers and researchers to design and experiment with a proven and freely available instruction set architecture. RISC-V is ideal for a variety of applications from IOTs to Embedded systems such as disks, CPUs, Calculators, SOCs, etc.

Theory:

In a RISC V processor, first the PC (program counter) gives the byte adderess to IMem . IMem (Instruction Memory) is the place where program instructions are stored. IMem gives out the instruction located on address given by PC. This instruction is coded in RISC V ISA. It needs to be decoded in various fields and identified. This job is done by Decode Logic . After the instruction is identified and relevent data is extracted, we access the registers from Register File. Data from respective registers and/or IMM (Imediate value) is sent to ALU to perform computational and logical operations. Result of these operations can modify register values/ can be stored in DMem (Data Memory)/ can be desplayed on 7 segment output display. Control Logic is the chip which monitors all this flow and controls which chip needs to be enabled.

Note: This is the general flow for most of the commands. There are few exceptions like jump instruction where data needs to flow in different manner

For more detailed information follow Project Report

Flowchart:

Tech stack:

• Logisim
• JVM (To run logisim software)
• Makerchip online IDE
• Github
• Python 3

Getting Started

• Download Logisim software from the link given above.
• Download logisim circuit files.
• Download text file of program and initial data.

Usage

To run Fibonacci series:

1. Open final.circ in logisim
2. In main circuit, right click on IMEM chip and select 'View IMEM' from drop down
3. In IMEM circuit, right click on RAM module and load 'Fibo.txt' from IMem folder
4. Back to main circuit, in the top right corner, click on load pin to activate processor
5. Turn on the clock from either the Simulate menu or using ctrl+k
6. To halt the program press ctrl+k
7. To reset the processor, press reset button
8. After reset, the processor is ready to load nest pogram

Screen shot and demo:

32 bit processor running fibonacci series code:

Future work:

• Add more instrcutions and functionality
• Create verilog model

Troubleshooting

• Problem in Logisim installation
  • Check if your system has java installed
• Circuit showing-
  • Red wires: Reset the simulation from Simulate menu/ Check if all connections are correct (You can refer to images of circuits from indevidual folder)
  • Blue wire: Reset the simulation from Simulate menu/ make sure simulation is enabled
  • Gray wire: Check if all connections are correct (You can refer to images of circuits from indevidual folder)

Contributors:

• Premraj Jadhav
• Siddesh Patil
• Siddharth Sankhe

Mentors:

• Ninad Jangle
• Gautam Agrawal

Acknowlegdements and Resources:

• SRA VJTI Eklavya 2020