[RISC-V] Implement On Stack Replacement #1

sirntar · 2023-12-07T13:33:21Z

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sirntar added 30 commits November 28, 2023 14:21

[RISC-V] Set OSR root frames reg for large offset

2803037

[RISC-V] Enable OSR feature in cmake

4eaddc1

[RISC-V] Add config info about QuickJitForLoops

bff6fe5

[RISC-V] Add osr ifdef directives to codegencommon

43b5a49

[RISC-V] Redesign FuncletFrameInfoDsc for OSR

42c1b20

[RISC-V] Correct some assembly comments

c32d8a8

[RISC-V] Rebuild genFuncletProlog for OSR

fbd338a

[RISC-V] Add some documentation in coments

405bdab

[RISC-V] Fix potential issue for 0 calee-save regs

d2fb93b

[RISC-V] Rebuild OSR epilog

b799803

[RISC-V] Rebuild genCaptureFuncletPrologEpilogInfo for OSR

53a6dc1

[RISC-V] Add OSR support in genSetPSPSym

b306acb

[RISC-V] Cosmetic changes in genSetRegToConst

9ad6889

[RISC-V] Add coment to genCodeForCpObj

3ad737d

[RISC-V] Cleanup in genCodeForCompare for OSR

f05be9c

[RISC-V] Improve some SP/FP delta manimulations

1e13920

[RISC-V] Add OSR support to genSetGSSecurityCookie

058aadc

[RISC-V] Implement genPushCalleeSavedRegisters for OSR

4e0823e

[RISC-V] Implement genPopCalleeSavedRegisters for OSR

65324eb

[RISC-V] Update vars for OSR in Compiler

e2d6fd9

[RISC-V] Update gcInfoBlockHdrSave for OSR

05b50f2

[RISC-V] Enable TC_OnStackReplacement

cba3bf6

[RISC-V] Correct compiler OSR vars

9079076

[RISC-V] Fix codegen definition

a940ddd

[RISC-V] Correct spelling of SPtoCallerSPdelta

bf3dca9

[RISC-V] Add missing semicolon

1c002d4

[RISC-V] Fix IsOSR is not a pointer member

99a5d05

[RISC-V] Fix OSR errors

5423fa9

[RISC-V] A little correction and cleanup

1092662

[RISC-V] Add some docs and small optimization changes

d6d8f4c

[RISC-V] Remove space before genCaptureFuncletPrologEpilogInfo

e6116dc

sirntar merged commit 71844c6 into riscv64-osr Dec 7, 2023

sirntar deleted the rv64-osr branch December 7, 2023 13:35

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