From be900de17a93b58841da05ab9097a80b5cbbedfd Mon Sep 17 00:00:00 2001
From: Richard Dymond <rjdymond@gmail.com>
Date: Fri, 9 Feb 2024 17:11:23 -0400
Subject: [PATCH] Make trace.py use IFF1 to determine whether interrupts are
 enabled

---
 skoolkit/trace.py   |  2 +-
 tests/test_trace.py | 38 +++++++++++++++++++-------------------
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/skoolkit/trace.py b/skoolkit/trace.py
index 9133cc30..d90bdc4f 100644
--- a/skoolkit/trace.py
+++ b/skoolkit/trace.py
@@ -175,7 +175,7 @@ def run(snafile, options, config):
         else:
             memory, org = make_snapshot(snafile, options.org)[:2]
     if snapshot:
-        state = {'im': snapshot.im, 'iff': snapshot.iff2, 'tstates': snapshot.tstates}
+        state = {'im': snapshot.im, 'iff': snapshot.iff1, 'tstates': snapshot.tstates}
         border = snapshot.border
         out7ffd = snapshot.out7ffd
         outfffd = snapshot.outfffd
diff --git a/tests/test_trace.py b/tests/test_trace.py
index 27543c3f..f4508d3b 100644
--- a/tests/test_trace.py
+++ b/tests/test_trace.py
@@ -406,7 +406,7 @@ def test_interrupt_mode_0(self):
         stop = 0x8002
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 0, 'tstates': 69884}
+        registers = {'PC': start, 'iff1': 1, 'im': 0, 'tstates': 69884}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -426,7 +426,7 @@ def test_interrupt_mode_1(self):
         stop = 0x8002
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69884}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69884}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -449,7 +449,7 @@ def test_interrupt_mode_2(self):
         stop = 0x7ffd
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 69882}
+        registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 69882}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -470,7 +470,7 @@ def test_interrupt_without_halt(self):
         stop = 0x8003
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69882}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69882}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -493,7 +493,7 @@ def test_interrupt_with_ei(self):
         stop = 0x8004
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69882}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69882}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -517,7 +517,7 @@ def test_interrupt_with_di(self):
         stop = 0x8004
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69882}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69882}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -539,7 +539,7 @@ def test_interrupt_with_dd_prefix(self):
         ram = [0] * 49152
         ram[0x1C00] = ram[0x1C04] = 0xFF # KSTATE0/4
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -562,7 +562,7 @@ def test_interrupt_with_fd_prefix(self):
         ram = [0] * 49152
         ram[0x1C00] = ram[0x1C04] = 0xFF # KSTATE0/4
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -588,7 +588,7 @@ def test_interrupt_with_ddfd_chain(self):
         ram = [0] * 49152
         ram[0x1C00] = ram[0x1C04] = 0xFF # KSTATE0/4
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -612,7 +612,7 @@ def test_interrupt_at_exact_frame_boundary(self):
         stop = 0x8002
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69884}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69884}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -642,7 +642,7 @@ def test_interrupt_with_djnz(self):
         stop = 0x7fff
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69805}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69805}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file} {outfile}')
         self.assertEqual(error, '')
@@ -667,7 +667,7 @@ def test_interrupt_with_ldir(self):
         stop = 0x7fff
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69805}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69805}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file} {outfile}')
         self.assertEqual(error, '')
@@ -692,7 +692,7 @@ def test_interrupt_with_lddr(self):
         stop = 0x7fff
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69805}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69805}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file} {outfile}')
         self.assertEqual(error, '')
@@ -707,7 +707,7 @@ def test_interrupt_mode_1_with_timestamps(self):
         stop = 0x8002
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69884}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69884}
         z80file = self.write_z80_file(None, ram, registers=registers)
         trace_line = 'TraceLine={t} ${pc:04X} {i}'
         output, error = self.run_trace(('-I', trace_line, '-S', str(stop), '-v', z80file))
@@ -732,7 +732,7 @@ def test_interrupt_mode_2_with_timestamps(self):
         stop = 0x7ffd
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 69884}
+        registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 69884}
         z80file = self.write_z80_file(None, ram, registers=registers)
         trace_line = 'TraceLine={t} ${pc:04X} {i}'
         output, error = self.run_trace(('-I', trace_line, '-S', str(stop), '-v', z80file))
@@ -756,7 +756,7 @@ def test_interrupt_routine_executed_twice_while_int_is_active_48k(self):
         stop = 0x7fff
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 69884}
+        registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 69884}
         z80file = self.write_z80_file(None, ram, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -784,7 +784,7 @@ def test_interrupt_routine_executed_twice_while_int_is_active_128k(self):
         stop = 0x7fff
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 70904}
+        registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 70904}
         z80file = self.write_z80_file(None, ram, machine_id=4, registers=registers)
         output, error = self.run_trace(f'-S {stop} -v {z80file}')
         self.assertEqual(error, '')
@@ -928,7 +928,7 @@ def test_option_cmio(self):
         stop = 0x8000
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 14335}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 14335}
         z80file = self.write_z80_file(None, ram, registers=registers)
         trace_line = 'TraceLine={t} ${pc:04X} {i}'
         exp_output = """
@@ -1174,7 +1174,7 @@ def test_option_no_interrupts(self):
         stop = 0x8002
         ram = [0] * 49152
         ram[start - 0x4000:start - 0x4000 + len(data)] = data
-        registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
+        registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
         z80file = self.write_z80_file(None, ram, registers=registers)
         exp_output = dedent("""
             $8000 NOP