diff --git a/axi/axi-stream/rtl/AxiStreamDeMux.vhd b/axi/axi-stream/rtl/AxiStreamDeMux.vhd index 5dd0cd8767..ffa91b057d 100644 --- a/axi/axi-stream/rtl/AxiStreamDeMux.vhd +++ b/axi/axi-stream/rtl/AxiStreamDeMux.vhd @@ -26,6 +26,7 @@ use surf.AxiStreamPkg.all; entity AxiStreamDeMux is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; NUM_MASTERS_G : integer range 1 to 256 := 12; MODE_G : string := "INDEXED"; -- Or "ROUTED" Or "DYNAMIC" @@ -36,10 +37,10 @@ entity AxiStreamDeMux is port ( -- Clock and reset axisClk : in sl; - axisRst : in sl; + axisRst : in sl := not RST_POLARITY_G; -- Dynamic Route Table (only used when MODE_G = "DYNAMIC") dynamicRouteMasks : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000"); - dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000"); + dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000"); -- Slave sAxisMaster : in AxiStreamMasterType; sAxisSlave : out AxiStreamSlaveType; @@ -139,7 +140,7 @@ begin sAxisSlave <= v.slave; -- Reset - if (RST_ASYNC_G = false and axisRst = '1') then + if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -151,14 +152,14 @@ begin end process comb; - GEN_VEC : - for i in (NUM_MASTERS_G-1) downto 0 generate + GEN_VEC : for i in (NUM_MASTERS_G-1) downto 0 generate U_Pipeline : entity surf.AxiStreamPipeline generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - PIPE_STAGES_G => PIPE_STAGES_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PIPE_STAGES_G => PIPE_STAGES_G) port map ( axisClk => axisClk, axisRst => axisRst, @@ -171,7 +172,7 @@ begin seq : process (axisClk, axisRst) is begin - if (RST_ASYNC_G and axisRst = '1') then + if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(axisClk) then r <= rin after TPD_G; diff --git a/axi/axi-stream/rtl/AxiStreamMux.vhd b/axi/axi-stream/rtl/AxiStreamMux.vhd index 7a12f90d5a..12edcf15d1 100644 --- a/axi/axi-stream/rtl/AxiStreamMux.vhd +++ b/axi/axi-stream/rtl/AxiStreamMux.vhd @@ -27,6 +27,7 @@ use surf.AxiStreamPkg.all; entity AxiStreamMux is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; PIPE_STAGES_G : integer range 0 to 16 := 0; NUM_SLAVES_G : integer range 1 to 256 := 4; @@ -66,7 +67,7 @@ entity AxiStreamMux is port ( -- Clock and reset axisClk : in sl; - axisRst : in sl; + axisRst : in sl := not RST_POLARITY_G; -- Slaves disableSel : in slv(NUM_SLAVES_G-1 downto 0) := (others => '0'); rearbitrate : in sl := '0'; @@ -308,7 +309,7 @@ begin sAxisSlaves <= v.slaves; -- Reset - if (RST_ASYNC_G = false and axisRst = '1') then + if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -322,7 +323,7 @@ begin seq : process (axisClk, axisRst) is begin - if (RST_ASYNC_G) and (axisRst = '1') then + if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(axisClk) then r <= rin after TPD_G; @@ -332,9 +333,10 @@ begin -- Optional output pipeline registers to ease timing AxiStreamPipeline_1 : entity surf.AxiStreamPipeline generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - PIPE_STAGES_G => PIPE_STAGES_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PIPE_STAGES_G => PIPE_STAGES_G) port map ( axisClk => axisClk, axisRst => axisRst, diff --git a/axi/axi-stream/rtl/AxiStreamPipeline.vhd b/axi/axi-stream/rtl/AxiStreamPipeline.vhd index 8d706f866b..16d4fb9dbf 100644 --- a/axi/axi-stream/rtl/AxiStreamPipeline.vhd +++ b/axi/axi-stream/rtl/AxiStreamPipeline.vhd @@ -23,13 +23,14 @@ use surf.AxiStreamPkg.all; entity AxiStreamPipeline is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; SIDE_BAND_WIDTH_G : positive := 1; -- General purpose sideband PIPE_STAGES_G : natural := 0); port ( -- Clock and Reset axisClk : in sl; - axisRst : in sl; + axisRst : in sl := not RST_POLARITY_G; -- Slave Port sAxisMaster : in AxiStreamMasterType; sSideBand : in slv(SIDE_BAND_WIDTH_G-1 downto 0) := (others => '0'); @@ -148,7 +149,7 @@ begin mSideBand <= r.mSideBand(PIPE_STAGES_C); -- Synchronous Reset - if (RST_ASYNC_G = false and axisRst = '1') then + if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -159,7 +160,7 @@ begin seq : process (axisClk, axisRst) is begin - if (RST_ASYNC_G and axisRst = '1') then + if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(axisClk) then r <= rin after TPD_G; diff --git a/base/crc/rtl/Crc32.vhd b/base/crc/rtl/Crc32.vhd index 5293cd6ba3..4b9ed09aa8 100644 --- a/base/crc/rtl/Crc32.vhd +++ b/base/crc/rtl/Crc32.vhd @@ -34,13 +34,14 @@ use surf.CrcPkg.all; entity Crc32 is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; BYTE_WIDTH_G : positive := 4; INPUT_REGISTER_G : boolean := true; CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF"; CRC_POLY_G : slv(31 downto 0) := x"04C11DB7"); port ( - crcPwrOnRst : in sl := '0'; + crcPwrOnRst : in sl := not RST_POLARITY_G; crcOut : out slv(31 downto 0); -- CRC output crcRem : out slv(31 downto 0); -- CRC interim remainder crcClk : in sl; -- system clock @@ -146,10 +147,10 @@ begin seq : process (crcClk, crcPwrOnRst) is begin - if (RST_ASYNC_G and crcPwrOnRst = '1') then + if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif (rising_edge(crcClk)) then - if (RST_ASYNC_G = false and crcPwrOnRst = '1') then + if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; else r <= rin after TPD_G; diff --git a/base/crc/rtl/Crc32Parallel.vhd b/base/crc/rtl/Crc32Parallel.vhd index 7222680894..09819969a8 100755 --- a/base/crc/rtl/Crc32Parallel.vhd +++ b/base/crc/rtl/Crc32Parallel.vhd @@ -40,12 +40,13 @@ use surf.CrcPkg.all; entity Crc32Parallel is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; BYTE_WIDTH_G : positive := 4; INPUT_REGISTER_G : boolean := true; CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF"); port ( - crcPwrOnRst : in sl := '0'; + crcPwrOnRst : in sl := not RST_POLARITY_G; crcOut : out slv(31 downto 0); -- CRC output crcRem : out slv(31 downto 0); -- CRC interim remainder crcClk : in sl; -- system clock @@ -188,10 +189,10 @@ begin seq : process (crcClk, crcPwrOnRst) is begin - if (RST_ASYNC_G and crcPwrOnRst = '1') then + if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif (rising_edge(crcClk)) then - if (RST_ASYNC_G = false and crcPwrOnRst = '1') then + if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; else r <= rin after TPD_G; diff --git a/base/general/rtl/Gearbox.vhd b/base/general/rtl/Gearbox.vhd index 933b64c17a..9790420824 100644 --- a/base/general/rtl/Gearbox.vhd +++ b/base/general/rtl/Gearbox.vhd @@ -34,7 +34,7 @@ entity Gearbox is port ( -- Clock and Reset clk : in sl; - rst : in sl; + rst : in sl := not RST_POLARITY_G; -- input side data and flow control slaveData : in slv(SLAVE_WIDTH_G-1 downto 0); slaveValid : in sl := '1'; diff --git a/base/general/rtl/Scrambler.vhd b/base/general/rtl/Scrambler.vhd index 614239cb64..59da5bc5a8 100644 --- a/base/general/rtl/Scrambler.vhd +++ b/base/general/rtl/Scrambler.vhd @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all; entity Scrambler is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; DIRECTION_G : string := "SCRAMBLER"; -- or DESCRAMBLER DATA_WIDTH_G : integer := 64; @@ -34,7 +35,7 @@ entity Scrambler is TAPS_G : IntegerArray := (0 => 39, 1 => 58)); port ( clk : in sl; - rst : in sl; + rst : in sl := not RST_POLARITY_G; inputValid : in sl := '1'; inputReady : out sl; inputData : in slv(DATA_WIDTH_G-1 downto 0); @@ -129,7 +130,7 @@ begin inputReady <= v.inputReady; -- Reset - if (RST_ASYNC_G = false and rst = '1') then + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -150,7 +151,7 @@ begin seq : process (clk, rst) is begin - if (RST_ASYNC_G and rst = '1') then + if (RST_ASYNC_G and rst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(clk) then r <= rin after TPD_G; diff --git a/base/sync/rtl/SynchronizerFifo.vhd b/base/sync/rtl/SynchronizerFifo.vhd index 7b50cff926..87c922a877 100644 --- a/base/sync/rtl/SynchronizerFifo.vhd +++ b/base/sync/rtl/SynchronizerFifo.vhd @@ -22,18 +22,19 @@ use surf.StdRtlPkg.all; entity SynchronizerFifo is generic ( - TPD_G : time := 1 ns; - RST_ASYNC_G : boolean := false; - COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration - MEMORY_TYPE_G : string := "distributed"; - SYNC_STAGES_G : integer range 3 to (2**24) := 3; - PIPE_STAGES_G : natural range 0 to 16 := 0; - DATA_WIDTH_G : integer range 1 to (2**24) := 16; - ADDR_WIDTH_G : integer range 2 to 48 := 4; - INIT_G : slv := "0"); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false; + COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration + MEMORY_TYPE_G : string := "distributed"; + SYNC_STAGES_G : integer range 3 to (2**24) := 3; + PIPE_STAGES_G : natural range 0 to 16 := 0; + DATA_WIDTH_G : integer range 1 to (2**24) := 16; + ADDR_WIDTH_G : integer range 2 to 48 := 4; + INIT_G : slv := "0"); port ( -- Asynchronous Reset - rst : in sl := '0'; + rst : in sl := not RST_POLARITY_G; -- Write Ports (wr_clk domain) wr_clk : in sl; wr_en : in sl := '1'; @@ -58,15 +59,16 @@ begin FifoAsync_1 : entity surf.FifoAsync generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - MEMORY_TYPE_G => MEMORY_TYPE_G, - FWFT_EN_G => true, - SYNC_STAGES_G => SYNC_STAGES_G, - PIPE_STAGES_G => PIPE_STAGES_G, - DATA_WIDTH_G => DATA_WIDTH_G, - ADDR_WIDTH_G => ADDR_WIDTH_G, - INIT_G => INIT_C) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + FWFT_EN_G => true, + SYNC_STAGES_G => SYNC_STAGES_G, + PIPE_STAGES_G => PIPE_STAGES_G, + DATA_WIDTH_G => DATA_WIDTH_G, + ADDR_WIDTH_G => ADDR_WIDTH_G, + INIT_G => INIT_C) port map ( rst => rst, wr_clk => wr_clk, diff --git a/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd b/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd index 8f7912faa6..2b5f9333d7 100644 --- a/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd +++ b/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd @@ -30,6 +30,7 @@ use surf.AxiStreamPacketizer2Pkg.all; entity AxiStreamDepacketizer2 is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; MEMORY_TYPE_G : string := "distributed"; REG_EN_G : boolean := false; @@ -42,7 +43,7 @@ entity AxiStreamDepacketizer2 is port ( -- Clock and Reset axisClk : in sl; - axisRst : in sl; + axisRst : in sl := not RST_POLARITY_G; -- Link Status monitoring and debug interfaces linkGood : in sl; debug : out Packetizer2DebugType; @@ -159,9 +160,10 @@ begin ----------------- U_Input : entity surf.AxiStreamPipeline generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - PIPE_STAGES_G => INPUT_PIPE_STAGES_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G) port map ( axisClk => axisClk, axisRst => axisRst, @@ -186,15 +188,16 @@ begin GEN_SEQ : if (SEQ_CNT_SIZE_G > 0) generate U_DualPortRam_1 : entity surf.DualPortRam generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - MEMORY_TYPE_G => MEMORY_TYPE_G, - REG_EN_G => REG_EN_G, - DOA_REG_G => REG_EN_G, - DOB_REG_G => REG_EN_G, - BYTE_WR_EN_G => false, - DATA_WIDTH_G => RAM_DATA_WIDTH_C, - ADDR_WIDTH_G => ADDR_WIDTH_C) + TPD_G => TPD_G, + RST_ASYNC_G => RST_ASYNC_G, + RST_POLARITY_G => RST_POLARITY_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + REG_EN_G => REG_EN_G, + DOA_REG_G => REG_EN_G, + DOB_REG_G => REG_EN_G, + BYTE_WR_EN_G => false, + DATA_WIDTH_G => RAM_DATA_WIDTH_C, + ADDR_WIDTH_G => ADDR_WIDTH_C) port map ( clka => axisClk, rsta => axisRst, @@ -207,10 +210,10 @@ begin NO_SEQ : if (SEQ_CNT_SIZE_G = 0) generate process (axisClk, axisRst) is begin - if (RST_ASYNC_G and axisRst = '1') then + if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then ramDout <= (others => '0') after TPD_G; elsif (rising_edge(axisClk)) then - if (RST_ASYNC_G = false and axisRst = '1') then + if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then ramDout <= (others => '0') after TPD_G; else ramDout <= ramDin after TPD_G; @@ -228,6 +231,7 @@ begin U_Crc32 : entity surf.Crc32Parallel generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, INPUT_REGISTER_G => false, BYTE_WIDTH_G => 8, @@ -248,6 +252,7 @@ begin U_Crc32 : entity surf.Crc32 generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, INPUT_REGISTER_G => false, BYTE_WIDTH_G => 8, @@ -649,10 +654,10 @@ begin seq : process (axisClk, axisRst) is begin - if (RST_ASYNC_G and axisRst = '1') then + if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif (rising_edge(axisClk)) then - if (RST_ASYNC_G = false and axisRst = '1') then + if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; else r <= rin after TPD_G; @@ -665,9 +670,10 @@ begin ------------------ U_Output : entity surf.AxiStreamPipeline generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) port map ( axisClk => axisClk, axisRst => axisRst, diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd index 73afb8b48d..c16f623c04 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd @@ -27,12 +27,13 @@ use surf.StdRtlPkg.all; entity Pgp3RxGearboxAligner is generic ( - TPD_G : time := 1 ns; - RST_ASYNC_G : boolean := false; - SLIP_WAIT_G : integer := 32); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false; + SLIP_WAIT_G : integer := 32); port ( clk : in sl; - rst : in sl; + rst : in sl := not RST_POLARITY_G; rxHeader : in slv(1 downto 0); rxHeaderValid : in sl; slip : out sl; @@ -119,7 +120,7 @@ begin when others => null; end case; - if (RST_ASYNC_G = false and rst = '1') then + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -132,7 +133,7 @@ begin seq : process (clk, rst) is begin - if (RST_ASYNC_G) and (rst = '1') then + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(clk) then r <= rin after TPD_G; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd index 8a61df5ebd..7be4bfbbad 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd @@ -29,7 +29,9 @@ use surf.AxiStreamPacketizer2Pkg.all; entity Pgp4Rx is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; + SIMULATION_G : boolean := false; -- bypasses elastic buffer NUM_VC_G : integer range 1 to 16 := 4; SKIP_EN_G : boolean := true; -- TRUE for Elastic Buffer LITE_EN_G : boolean := false; -- TRUE: Lite does NOT support SOC/EOC @@ -37,7 +39,7 @@ entity Pgp4Rx is port ( -- User Transmit interface pgpRxClk : in sl; - pgpRxRst : in sl; + pgpRxRst : in sl := not RST_POLARITY_G; pgpRxIn : in Pgp4RxInType := PGP4_RX_IN_INIT_C; pgpRxOut : out Pgp4RxOutType; pgpRxMasters : out AxiStreamMasterArray(NUM_VC_G-1 downto 0); @@ -99,9 +101,10 @@ begin -- Gearbox aligner U_Pgp3RxGearboxAligner_1 : entity surf.Pgp3RxGearboxAligner -- Same RX gearbox aligner as PGPv3 generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - SLIP_WAIT_G => ALIGN_SLIP_WAIT_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SLIP_WAIT_G => ALIGN_SLIP_WAIT_G) port map ( clk => phyRxClk, -- [in] rst => phyRxRst, -- [in] @@ -115,6 +118,7 @@ begin U_Scrambler_1 : entity surf.Scrambler generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, DIRECTION_G => "DESCRAMBLER", DATA_WIDTH_G => 64, @@ -130,12 +134,13 @@ begin outputData => unscrambledData, -- [out] outputSideband => unscrambledHeader); -- [out] - GEN_EB : if (SKIP_EN_G = true) generate + GEN_EB : if (SKIP_EN_G = true and SIMULATION_G = false) generate -- Elastic Buffer U_Pgp4RxEb_1 : entity surf.Pgp4RxEb generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) port map ( phyRxClk => phyRxClk, -- [in] phyRxRst => phyRxRst, -- [in] @@ -152,7 +157,7 @@ begin linkError => linkError, -- [out] status => ebStatus); -- [out] end generate GEN_EB; - NO_EB : if (SKIP_EN_G = false) generate + NO_EB : if (SKIP_EN_G = false or SIMULATION_G = true) generate ebValid <= unscrambledValid; ebHeader <= unscrambledHeader; ebData <= unscrambledData; @@ -161,9 +166,10 @@ begin -- Main RX protocol logic U_Pgp4RxProtocol_1 : entity surf.Pgp4RxProtocol generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - NUM_VC_G => NUM_VC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + NUM_VC_G => NUM_VC_G) port map ( pgpRxClk => pgpRxClk, -- [in] pgpRxRst => pgpRxRst, -- [in] @@ -185,6 +191,7 @@ begin U_AxiStreamDepacketizer2_1 : entity surf.AxiStreamDepacketizer2 generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, MEMORY_TYPE_G => "distributed", CRC_MODE_G => "DATA", @@ -206,13 +213,14 @@ begin -- Demultiplex the depacketized streams U_AxiStreamDeMux_1 : entity surf.AxiStreamDeMux generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - NUM_MASTERS_G => NUM_VC_G, - MODE_G => "INDEXED", - PIPE_STAGES_G => 0, - TDEST_HIGH_G => 7, - TDEST_LOW_G => 0) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + NUM_MASTERS_G => NUM_VC_G, + MODE_G => "INDEXED", + PIPE_STAGES_G => 0, + TDEST_HIGH_G => 7, + TDEST_LOW_G => 0) port map ( axisClk => pgpRxClk, -- [in] axisRst => pgpRxRst, -- [in] diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index 71164c686b..bdea32a4ae 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -25,17 +25,18 @@ use surf.Pgp4Pkg.all; entity Pgp4RxEb is generic ( - TPD_G : time := 1 ns; - RST_ASYNC_G : boolean := false); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false); port ( phyRxClk : in sl; - phyRxRst : in sl; + phyRxRst : in sl := not RST_POLARITY_G; phyRxValid : in sl; phyRxData : in slv(63 downto 0); -- Unscrambled data from the PHY phyRxHeader : in slv(1 downto 0); -- User Transmit interface pgpRxClk : in sl; - pgpRxRst : in sl; + pgpRxRst : in sl := not RST_POLARITY_G; pgpRxValid : out sl; pgpRxData : out slv(63 downto 0); pgpRxHeader : out slv(1 downto 0); @@ -112,7 +113,7 @@ begin end if; -- Reset - if (RST_ASYNC_G = false and phyRxRst = '1') then + if (RST_ASYNC_G = false and phyRxRst = RST_POLARITY_G) then -- Maintain save behavior before the remLinkData update (not reseting fifoIn or fifoWrEn) v.remLinkData := (others => '0'); end if; @@ -124,7 +125,7 @@ begin seq : process (phyRxClk, phyRxRst) is begin - if (RST_ASYNC_G) and (phyRxRst = '1') then + if (RST_ASYNC_G) and (phyRxRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(phyRxClk) then r <= rin after TPD_G; @@ -133,9 +134,10 @@ begin U_remLinkData : entity surf.SynchronizerFifo generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - DATA_WIDTH_G => 48) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_WIDTH_G => 48) port map ( rst => phyRxRst, wr_clk => phyRxClk, @@ -146,13 +148,14 @@ begin U_FifoAsync_1 : entity surf.FifoAsync generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - MEMORY_TYPE_G => "block", - FWFT_EN_G => true, - PIPE_STAGES_G => 0, - DATA_WIDTH_G => 66, - ADDR_WIDTH_G => 9) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MEMORY_TYPE_G => "block", + FWFT_EN_G => true, + PIPE_STAGES_G => 0, + DATA_WIDTH_G => 66, + ADDR_WIDTH_G => 9) port map ( rst => phyRxRst, -- Write Interface diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd index c0f7164bba..58ec9767f0 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd @@ -31,13 +31,14 @@ use surf.Pgp4Pkg.all; entity Pgp4RxProtocol is generic ( - TPD_G : time := 1 ns; - RST_ASYNC_G : boolean := false; - NUM_VC_G : integer range 1 to 16 := 4); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false; + NUM_VC_G : integer range 1 to 16 := 4); port ( -- User Transmit interface pgpRxClk : in sl; - pgpRxRst : in sl; + pgpRxRst : in sl := not RST_POLARITY_G; pgpRxIn : in Pgp4RxInType := PGP4_RX_IN_INIT_C; pgpRxOut : out Pgp4RxOutType; pgpRxMaster : out AxiStreamMasterType; @@ -90,8 +91,9 @@ begin U_phyRxActiveSync : entity surf.SynchronizerEdge generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) port map ( clk => pgpRxClk, rst => pgpRxRst, @@ -278,7 +280,7 @@ begin locRxLinkReady <= r.pgpRxOut.linkReady; -- Reset - if (RST_ASYNC_G = false and pgpRxRst = '1') then + if (RST_ASYNC_G = false and pgpRxRst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -289,7 +291,7 @@ begin seq : process (pgpRxClk, pgpRxRst) is begin - if (RST_ASYNC_G) and (pgpRxRst = '1') then + if (RST_ASYNC_G) and (pgpRxRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(pgpRxClk) then r <= rin after TPD_G; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd index 0a3a179ffe..48ebb9236c 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd @@ -28,6 +28,7 @@ use surf.Pgp4Pkg.all; entity Pgp4TxLite is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; NUM_VC_G : integer range 1 to 16 := 1; SKIP_EN_G : boolean := false; @@ -35,7 +36,7 @@ entity Pgp4TxLite is port ( -- Transmit interface pgpTxClk : in sl; - pgpTxRst : in sl; + pgpTxRst : in sl := not RST_POLARITY_G; pgpTxIn : in Pgp4TxInType := PGP4_TX_IN_INIT_C; pgpTxOut : out Pgp4TxOutType; pgpTxActive : in sl; @@ -82,8 +83,9 @@ begin -- Synchronize remote link and FIFO status to tx clock U_Synchronizer_REM : entity surf.Synchronizer generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) port map ( clk => pgpTxClk, -- [in] rst => pgpTxRst, -- [in] @@ -92,9 +94,10 @@ begin REM_STATUS_SYNC : for i in NUM_VC_G-1 downto 0 generate U_SynchronizerVector_1 : entity surf.SynchronizerVector generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G, - WIDTH_G => 2) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + WIDTH_G => 2) port map ( clk => pgpTxClk, -- [in] rst => pgpTxRst, -- [in] @@ -107,8 +110,9 @@ begin -- Synchronize local rx status U_Synchronizer_LOC : entity surf.Synchronizer generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) port map ( clk => pgpTxClk, -- [in] rst => pgpTxRst, -- [in] @@ -117,8 +121,9 @@ begin LOC_STATUS_SYNC : for i in NUM_VC_G-1 downto 0 generate U_Synchronizer_pause : entity surf.Synchronizer generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) port map ( clk => pgpTxClk, -- [in] rst => pgpTxRst, -- [in] @@ -126,8 +131,9 @@ begin dataOut => syncLocRxFifoCtrl(i).pause); -- [out] U_Synchronizer_overflow : entity surf.SynchronizerOneShot generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) port map ( clk => pgpTxClk, -- [in] rst => pgpTxRst, -- [in] @@ -158,6 +164,7 @@ begin U_AxiStreamMux_1 : entity surf.AxiStreamMux generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, NUM_SLAVES_G => NUM_VC_G, MODE_G => "INDEXED", @@ -189,6 +196,7 @@ begin U_Protocol : entity surf.Pgp4TxLiteProtocol generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, NUM_VC_G => NUM_VC_G, SKIP_EN_G => SKIP_EN_G, @@ -216,6 +224,7 @@ begin U_Scrambler_1 : entity surf.Scrambler generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, DIRECTION_G => "SCRAMBLER", DATA_WIDTH_G => 64, @@ -237,6 +246,7 @@ begin outputSideband(1 downto 0) => phyTxHeader, -- [out] outputSideband(2) => phyTxStart); -- [out] - phyTxActiveL <= not(phyTxActive); + -- not using ite to prevent errors in ASIC synth flow + phyTxActiveL <= not(phyTxActive) when RST_POLARITY_G = '1' else phyTxActive; end architecture rtl; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd index 0f28e10d17..00c6797ddc 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd @@ -32,6 +32,7 @@ use surf.Pgp4Pkg.all; entity Pgp4TxLiteProtocol is generic ( TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; NUM_VC_G : integer range 1 to 16 := 1; SKIP_EN_G : boolean := false; @@ -40,7 +41,7 @@ entity Pgp4TxLiteProtocol is port ( -- User Transmit interface pgpTxClk : in sl; - pgpTxRst : in sl; + pgpTxRst : in sl := not RST_POLARITY_G; pgpTxIn : in Pgp4TxInType := PGP4_TX_IN_INIT_C; pgpTxOut : out Pgp4TxOutType; pgpTxActive : in sl := '1'; @@ -127,6 +128,7 @@ begin U_Crc32 : entity surf.Crc32Parallel generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, INPUT_REGISTER_G => false, BYTE_WIDTH_G => 8, @@ -453,7 +455,7 @@ begin end loop; -- Reset - if (RST_ASYNC_G = false and pgpTxRst = '1') then + if (RST_ASYNC_G = false and pgpTxRst = RST_POLARITY_G) then v := REG_INIT_C; end if; @@ -464,7 +466,7 @@ begin seq : process (pgpTxClk, pgpTxRst) is begin - if (RST_ASYNC_G) and (pgpTxRst = '1') then + if (RST_ASYNC_G) and (pgpTxRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; elsif rising_edge(pgpTxClk) then r <= rin after TPD_G; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd index 2eb515de10..7cd5267ae2 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd @@ -24,12 +24,13 @@ use surf.Pgp4Pkg.all; entity Pgp4TxLiteWrapper is generic ( - TPD_G : time := 1 ns; - RST_ASYNC_G : boolean := false); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false); port ( -- Clock and Reset clk : in sl; - rst : in sl; -- Active HIGH reset + rst : in sl := not RST_POLARITY_G; -- 64-bit Input Framing Interface txValid : in sl; -- tValid txReady : out sl; -- tReady @@ -71,8 +72,9 @@ begin U_Pgp4TxLite : entity surf.Pgp4TxLite generic map ( TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, - NUM_VC_G => 1, -- Only 1 VC per PGPv4 link + NUM_VC_G => 1, -- Only 1 VC per PGPv4 link SKIP_EN_G => false, -- No skips (assumes clock source synchronous system) FLOW_CTRL_EN_G => false) -- no pause flow control from PGPv4.RX side port map ( @@ -97,6 +99,7 @@ begin phyTxData => phyTxData(63 downto 0), phyTxHeader => phyTxData(65 downto 64)); - rstL <= not(rst); + -- not using ite to prevent errors in ASIC synth flow + rstL <= not(rst) when RST_POLARITY_G = '1' else rst; end architecture mapping;