From 74c8236215ec1c3c3101ab627119233da47cdfbc Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 11 Jul 2024 10:12:57 -0700 Subject: [PATCH] Update DmaXvcWrapper.vhd's generic from AXIS_CLK_FREQ_G to XVC_CLK_FREQ_G ### Description - AXIS_CLK_FREQ_G is misleading name because generic is associated with the xvcClk (not axisClk) at surf.UdpDebugBridgeWrapper - Renaming this generic to XVC_CLK_FREQ_G --- protocols/xvc-udp/rtl/DmaXvcWrapper.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd b/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd index 2f00b291c5..8117b90a16 100644 --- a/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd +++ b/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd @@ -27,7 +27,7 @@ entity DmaXvcWrapper is generic ( TPD_G : time := 1 ns; COMMON_CLOCK_G : boolean := false; - AXIS_CLK_FREQ_G : real := 156.25e6; + XVC_CLK_FREQ_G : real := 156.25e6; FIFO_INT_PIPE_STAGES_G : natural range 0 to 16 := 0; -- Internal FIFO setting FIFO_PIPE_STAGES_G : natural range 0 to 16 := 1; OB_FIFO_SLAVE_READY_EN_G : boolean := true; @@ -67,7 +67,7 @@ begin U_XVC : entity surf.UdpDebugBridgeWrapper generic map ( TPD_G => TPD_G, - AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) + AXIS_CLK_FREQ_G => XVC_CLK_FREQ_G) port map ( -- Clock and Reset clk => xvcClk,