From 9c6aee9d9c0a240ffdc0726d7dc13350faafbb8a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 10 Jul 2024 17:41:52 -0700 Subject: [PATCH] depreciating VLAN support in ethernet/EthMacCore because never tested and never used --- ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd | 25 +- ethernet/EthMacCore/rtl/EthMacRx.vhd | 76 ++---- ethernet/EthMacCore/rtl/EthMacRxCsum.vhd | 170 ++++-------- ethernet/EthMacCore/rtl/EthMacRxFifo.vhd | 96 ++----- ethernet/EthMacCore/rtl/EthMacRxPause.vhd | 111 ++------ ethernet/EthMacCore/rtl/EthMacTop.vhd | 198 +++++--------- ethernet/EthMacCore/rtl/EthMacTx.vhd | 73 +----- ethernet/EthMacCore/rtl/EthMacTxCsum.vhd | 286 ++++++--------------- ethernet/EthMacCore/rtl/EthMacTxFifo.vhd | 83 +----- ethernet/EthMacCore/rtl/EthMacTxPause.vhd | 76 +----- 10 files changed, 314 insertions(+), 880 deletions(-) mode change 100755 => 100644 ethernet/EthMacCore/rtl/EthMacRxCsum.vhd diff --git a/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd b/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd index c6d3de548e..ced8f0353d 100644 --- a/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd +++ b/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd @@ -17,17 +17,14 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; entity EthMacFlowCtrl is generic ( - TPD_G : time := 1 ns; - BYP_EN_G : boolean := false; - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive range 1 to 8 := 1); + TPD_G : time := 1 ns; + BYP_EN_G : boolean := false); port ( -- Clock and Reset ethClk : in sl; @@ -35,7 +32,6 @@ entity EthMacFlowCtrl is -- Inputs primCtrl : in AxiStreamCtrlType; bypCtrl : in AxiStreamCtrlType; - vlanCtrl : in AxiStreamCtrlArray(VLAN_SIZE_G-1 downto 0); -- Output flowCtrl : out AxiStreamCtrlType); end EthMacFlowCtrl; @@ -56,7 +52,7 @@ architecture rtl of EthMacFlowCtrl is begin - comb : process (bypCtrl, ethRst, primCtrl, r, vlanCtrl) is + comb : process (bypCtrl, ethRst, primCtrl, r) is variable v : RegType; variable i : natural; begin @@ -80,21 +76,6 @@ begin end if; end if; - -- Check if VLAN interface is enabled - if (VLAN_EN_G) then - -- Loop through the channels - for i in (VLAN_SIZE_G-1) downto 0 loop - -- Sample the VLAN pause - if (vlanCtrl(i).pause = '1') then - v.flowCtrl.pause := '1'; - end if; - -- Sample the VLAN overflow - if (vlanCtrl(i).overflow = '1') then - v.flowCtrl.overflow := '1'; - end if; - end loop; - end if; - -- Reset if (ethRst = '1') then v := REG_INIT_C; diff --git a/ethernet/EthMacCore/rtl/EthMacRx.vhd b/ethernet/EthMacCore/rtl/EthMacRx.vhd index d4d799cf95..f1f5485903 100644 --- a/ethernet/EthMacCore/rtl/EthMacRx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRx.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.AxiStreamPkg.all; use surf.StdRtlPkg.all; @@ -26,21 +25,17 @@ use surf.EthMacPkg.all; entity EthMacRx is generic ( -- Simulation Generics - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; -- MAC Configurations - PAUSE_EN_G : boolean := true; - PHY_TYPE_G : string := "XGMII"; - JUMBO_G : boolean := true; - -- Non-VLAN Configurations - FILT_EN_G : boolean := false; - BYP_EN_G : boolean := false; - BYP_ETH_TYPE_G : slv(15 downto 0) := x"0000"; - -- VLAN Configurations - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive range 1 to 8 := 1; - VLAN_VID_G : Slv12Array := (0 => x"001"); - -- Internal RAM sythesis mode - SYNTH_MODE_G : string := "inferred"); + PAUSE_EN_G : boolean := true; + PHY_TYPE_G : string := "XGMII"; + JUMBO_G : boolean := true; + -- Misc. Configurations + FILT_EN_G : boolean := false; + BYP_EN_G : boolean := false; + BYP_ETH_TYPE_G : slv(15 downto 0) := x"0000"; + -- Internal RAM synthesis mode + SYNTH_MODE_G : string := "inferred"); port ( -- Clock and Reset ethClkEn : in sl; @@ -52,9 +47,6 @@ entity EthMacRx is -- Bypass Interface mBypMaster : out AxiStreamMasterType; mBypCtrl : in AxiStreamCtrlType; - -- VLAN Interfaces - mVlanMasters : out AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - mVlanCtrl : in AxiStreamCtrlArray(VLAN_SIZE_G-1 downto 0); -- XLGMII PHY Interface xlgmiiRxd : in slv(127 downto 0); xlgmiiRxc : in slv(15 downto 0); @@ -79,7 +71,6 @@ architecture mapping of EthMacRx is signal macIbMaster : AxiStreamMasterType; signal pauseMaster : AxiStreamMasterType; - signal pauseMasters : AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); signal csumMaster : AxiStreamMasterType; signal bypassMaster : AxiStreamMasterType; @@ -120,11 +111,8 @@ begin ------------------ U_Pause : entity surf.EthMacRxPause generic map ( - TPD_G => TPD_G, - PAUSE_EN_G => PAUSE_EN_G, - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_VID_G => VLAN_VID_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -133,19 +121,17 @@ begin sAxisMaster => macIbMaster, -- Outgoing data mAxisMaster => pauseMaster, - mAxisMasters => pauseMasters, -- Pause Values rxPauseReq => rxPauseReq, rxPauseValue => rxPauseValue); - ------------------------------ - -- RX Non-VLAN Checksum Module - ------------------------------ + --------------------- + -- RX Checksum Module + --------------------- U_Csum : entity surf.EthMacRxCsum generic map ( TPD_G => TPD_G, - JUMBO_G => JUMBO_G, - VLAN_G => false) + JUMBO_G => JUMBO_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -158,36 +144,6 @@ begin sAxisMaster => pauseMaster, mAxisMaster => csumMaster); - -------------------------- - -- RX VLAN Checksum Module - -------------------------- - GEN_VLAN : if (VLAN_EN_G = true) generate - GEN_VEC : - for i in (VLAN_SIZE_G-1) downto 0 generate - U_Csum : entity surf.EthMacRxCsum - generic map ( - TPD_G => TPD_G, - JUMBO_G => JUMBO_G, - VLAN_G => true) - port map ( - -- Clock and Reset - ethClk => ethClk, - ethRst => ethRst, - -- Configurations - ipCsumEn => '1', - tcpCsumEn => '1', - udpCsumEn => '1', - -- Outbound data to MAC - sAxisMaster => pauseMasters(i), - mAxisMaster => mVlanMasters(i)); - end generate GEN_VEC; - end generate; - - BYPASS_VLAN : if (VLAN_EN_G = false) generate - -- Terminate Unused buses - mVlanMasters <= (others => AXI_STREAM_MASTER_INIT_C); - end generate; - ------------------- -- RX Bypass Module ------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd old mode 100755 new mode 100644 index e9e1c0e124..c4374cd0b9 --- a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd @@ -18,7 +18,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; @@ -27,8 +26,7 @@ use surf.EthMacPkg.all; entity EthMacRxCsum is generic ( TPD_G : time := 1 ns; - JUMBO_G : boolean := true; - VLAN_G : boolean := false); + JUMBO_G : boolean := true); port ( -- Clock and Reset ethClk : in sl; @@ -193,19 +191,16 @@ begin v.mAxisMaster := sAxisMaster; -- Check for no EOF if (sAxisMaster.tLast = '0') then - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Check for EtherType = IPV4 = 0x0800 - if (sAxisMaster.tData(111 downto 96) = IPV4_TYPE_C) then - -- Set the flag - v.ipv4Det(0) := '1'; - end if; - -- Fill in the IPv4 header checksum - v.ipv4Hdr(0) := sAxisMaster.tData(119 downto 112); -- IPVersion + Header length - v.ipv4Hdr(1) := sAxisMaster.tData(127 downto 120); -- DSCP and ECN + -- Check for EtherType = IPV4 = 0x0800 + if (sAxisMaster.tData(111 downto 96) = IPV4_TYPE_C) then + -- Set the flag + v.ipv4Det(0) := '1'; end if; + -- Fill in the IPv4 header checksum + v.ipv4Hdr(0) := sAxisMaster.tData(119 downto 112); -- IPVersion + Header length + v.ipv4Hdr(1) := sAxisMaster.tData(127 downto 120); -- DSCP and ECN -- Next state - v.state := IPV4_HDR0_S; + v.state := IPV4_HDR0_S; end if; end if; ---------------------------------------------------------------------- @@ -221,53 +216,27 @@ begin -- Next state v.state := IDLE_S; else - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Fill in the IPv4 header checksum - v.ipv4Hdr(2) := sAxisMaster.tData(7 downto 0); -- IPV4_Length(15 downto 8) - v.ipv4Hdr(3) := sAxisMaster.tData(15 downto 8); -- IPV4_Length(7 downto 0) - v.ipv4Hdr(4) := sAxisMaster.tData(23 downto 16); -- IPV4_ID(15 downto 8) - v.ipv4Hdr(5) := sAxisMaster.tData(31 downto 24); -- IPV4_ID(7 downto 0) - v.ipv4Hdr(6) := sAxisMaster.tData(39 downto 32); -- Flags(2 downto 0) and Fragment Offsets(12 downto 8) - v.ipv4Hdr(7) := sAxisMaster.tData(47 downto 40); -- Fragment Offsets(7 downto 0) - v.ipv4Hdr(8) := sAxisMaster.tData(55 downto 48); -- Time-To-Live - v.ipv4Hdr(9) := sAxisMaster.tData(63 downto 56); -- Protocol - v.ipv4Hdr(10) := sAxisMaster.tData(71 downto 64); -- IPV4_Checksum(15 downto 8) - v.ipv4Hdr(11) := sAxisMaster.tData(79 downto 72); -- IPV4_Checksum(7 downto 0) - v.ipv4Hdr(12) := sAxisMaster.tData(87 downto 80); -- Source IP Address - v.ipv4Hdr(13) := sAxisMaster.tData(95 downto 88); -- Source IP Address - v.ipv4Hdr(14) := sAxisMaster.tData(103 downto 96); -- Source IP Address - v.ipv4Hdr(15) := sAxisMaster.tData(111 downto 104); -- Source IP Address - v.ipv4Hdr(16) := sAxisMaster.tData(119 downto 112); -- Destination IP Address - v.ipv4Hdr(17) := sAxisMaster.tData(127 downto 120); -- Destination IP Address - -- Fill in the TCP/UDP checksum - v.tData(63 downto 0) := sAxisMaster.tData(127 downto 80) & sAxisMaster.tData(63 downto 56) & x"00"; - v.tKeep(7 downto 0) := (others => '1'); - else - -- Check for EtherType = IPV4 = 0x0800 - if (sAxisMaster.tData(15 downto 0) = IPV4_TYPE_C) then - -- Set the flag - v.ipv4Det(0) := '1'; - end if; - -- Fill in the IPv4 header checksum - v.ipv4Hdr(0) := sAxisMaster.tData(23 downto 16); -- IPVersion + Header length - v.ipv4Hdr(1) := sAxisMaster.tData(31 downto 24); -- DSCP and ECN - v.ipv4Hdr(2) := sAxisMaster.tData(39 downto 32); -- IPV4_Length(15 downto 8) - v.ipv4Hdr(3) := sAxisMaster.tData(47 downto 40); -- IPV4_Length(7 downto 0) - v.ipv4Hdr(4) := sAxisMaster.tData(55 downto 48); -- IPV4_ID(15 downto 8) - v.ipv4Hdr(5) := sAxisMaster.tData(63 downto 56); -- IPV4_ID(7 downto 0) - v.ipv4Hdr(6) := sAxisMaster.tData(71 downto 64); -- Flags(2 downto 0) and Fragment Offsets(12 downto 8) - v.ipv4Hdr(7) := sAxisMaster.tData(79 downto 72); -- Fragment Offsets(7 downto 0) - v.ipv4Hdr(8) := sAxisMaster.tData(87 downto 80); -- Time-To-Live - v.ipv4Hdr(9) := sAxisMaster.tData(95 downto 88); -- Protocol - v.ipv4Hdr(10) := sAxisMaster.tData(103 downto 96); -- IPV4_Checksum(15 downto 8) - v.ipv4Hdr(11) := sAxisMaster.tData(111 downto 104); -- IPV4_Checksum(7 downto 0) - v.ipv4Hdr(12) := sAxisMaster.tData(119 downto 112); -- Source IP Address - v.ipv4Hdr(13) := sAxisMaster.tData(127 downto 120); -- Source IP Address - -- Fill in the TCP/UDP checksum - v.tData(31 downto 0) := sAxisMaster.tData(127 downto 112) & sAxisMaster.tData(95 downto 88) & x"00"; - v.tKeep(3 downto 0) := (others => '1'); - end if; + -- Fill in the IPv4 header checksum + v.ipv4Hdr(2) := sAxisMaster.tData(7 downto 0); -- IPV4_Length(15 downto 8) + v.ipv4Hdr(3) := sAxisMaster.tData(15 downto 8); -- IPV4_Length(7 downto 0) + v.ipv4Hdr(4) := sAxisMaster.tData(23 downto 16); -- IPV4_ID(15 downto 8) + v.ipv4Hdr(5) := sAxisMaster.tData(31 downto 24); -- IPV4_ID(7 downto 0) + v.ipv4Hdr(6) := sAxisMaster.tData(39 downto 32); -- Flags(2 downto 0) and Fragment Offsets(12 downto 8) + v.ipv4Hdr(7) := sAxisMaster.tData(47 downto 40); -- Fragment Offsets(7 downto 0) + v.ipv4Hdr(8) := sAxisMaster.tData(55 downto 48); -- Time-To-Live + v.ipv4Hdr(9) := sAxisMaster.tData(63 downto 56); -- Protocol + v.ipv4Hdr(10) := sAxisMaster.tData(71 downto 64); -- IPV4_Checksum(15 downto 8) + v.ipv4Hdr(11) := sAxisMaster.tData(79 downto 72); -- IPV4_Checksum(7 downto 0) + v.ipv4Hdr(12) := sAxisMaster.tData(87 downto 80); -- Source IP Address + v.ipv4Hdr(13) := sAxisMaster.tData(95 downto 88); -- Source IP Address + v.ipv4Hdr(14) := sAxisMaster.tData(103 downto 96); -- Source IP Address + v.ipv4Hdr(15) := sAxisMaster.tData(111 downto 104); -- Source IP Address + v.ipv4Hdr(16) := sAxisMaster.tData(119 downto 112); -- Destination IP Address + v.ipv4Hdr(17) := sAxisMaster.tData(127 downto 120); -- Destination IP Address + -- Fill in the TCP/UDP checksum + v.tData(63 downto 0) := sAxisMaster.tData(127 downto 80) & sAxisMaster.tData(63 downto 56) & x"00"; + v.tKeep(7 downto 0) := (others => '1'); + -- Latch the IPv4 length value v.ipv4Len(0)(15 downto 8) := v.ipv4Hdr(2); v.ipv4Len(0)(7 downto 0) := v.ipv4Hdr(3); @@ -297,46 +266,22 @@ begin -- Fill in the TCP/UDP checksum v.tKeep := sAxisMaster.tKeep(15 downto 0); v.tData := sAxisMaster.tData(127 downto 0); - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Fill in the IPv4 header checksum - v.ipv4Hdr(18) := sAxisMaster.tData(7 downto 0); -- Destination IP Address - v.ipv4Hdr(19) := sAxisMaster.tData(15 downto 8); -- Destination IP Address - -- Check for UDP data with inbound checksum - if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then - -- Mask off inbound UDP checksum - v.tData := sAxisMaster.tData(127 downto 80) & x"0000" & sAxisMaster.tData(63 downto 0); - -- Latch the inbound UDP checksum - v.protCsum(0)(15 downto 8) := sAxisMaster.tData(71 downto 64); - v.protCsum(0)(7 downto 0) := sAxisMaster.tData(79 downto 72); - -- Latch the inbound UDP length - v.protLen(0)(15 downto 8) := sAxisMaster.tData(55 downto 48); - v.protLen(0)(7 downto 0) := sAxisMaster.tData(63 downto 56); - end if; - -- Track the number of bytes (include IPv4 header offset from previous state) - v.byteCnt := getTKeep(sAxisMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) + 18; - else - -- Fill in the IPv4 header checksum - v.ipv4Hdr(14) := sAxisMaster.tData(7 downto 0); -- Source IP Address - v.ipv4Hdr(15) := sAxisMaster.tData(15 downto 8); -- Source IP Address - v.ipv4Hdr(16) := sAxisMaster.tData(23 downto 16); -- Destination IP Address - v.ipv4Hdr(17) := sAxisMaster.tData(31 downto 24); -- Destination IP Address - v.ipv4Hdr(18) := sAxisMaster.tData(39 downto 32); -- Destination IP Address - v.ipv4Hdr(19) := sAxisMaster.tData(47 downto 40); -- Destination IP Address - -- Check for UDP data with inbound checksum - if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then - -- Mask off inbound UDP checksum - v.tData := sAxisMaster.tData(127 downto 112) & x"0000" & sAxisMaster.tData(95 downto 0); - -- Latch the inbound UDP checksum - v.protCsum(0)(15 downto 8) := sAxisMaster.tData(103 downto 96); - v.protCsum(0)(7 downto 0) := sAxisMaster.tData(111 downto 104); - -- Latch the inbound UDP length - v.protLen(0)(15 downto 8) := sAxisMaster.tData(87 downto 80); - v.protLen(0)(7 downto 0) := sAxisMaster.tData(95 downto 88); - end if; - -- Track the number of bytes (include IPv4 header offset from previous state) - v.byteCnt := getTKeep(sAxisMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) + 14; + -- Fill in the IPv4 header checksum + v.ipv4Hdr(18) := sAxisMaster.tData(7 downto 0); -- Destination IP Address + v.ipv4Hdr(19) := sAxisMaster.tData(15 downto 8); -- Destination IP Address + -- Check for UDP data with inbound checksum + if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then + -- Mask off inbound UDP checksum + v.tData := sAxisMaster.tData(127 downto 80) & x"0000" & sAxisMaster.tData(63 downto 0); + -- Latch the inbound UDP checksum + v.protCsum(0)(15 downto 8) := sAxisMaster.tData(71 downto 64); + v.protCsum(0)(7 downto 0) := sAxisMaster.tData(79 downto 72); + -- Latch the inbound UDP length + v.protLen(0)(15 downto 8) := sAxisMaster.tData(55 downto 48); + v.protLen(0)(7 downto 0) := sAxisMaster.tData(63 downto 56); end if; + -- Track the number of bytes (include IPv4 header offset from previous state) + v.byteCnt := getTKeep(sAxisMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) + 18; -- Check for EOF if (sAxisMaster.tLast = '1') then -- Next state @@ -358,23 +303,14 @@ begin -- Check for TCP data with inbound checksum if (r.ipv4Det(0) = '1') and (r.tcpDet(0) = '1') and (r.tcpFlag = '0') then -- Set the flag - v.tcpFlag := '1'; + v.tcpFlag := '1'; -- Calculate TCP length from IPv4 length - v.protLen(0) := r.ipv4Len(0) - 20; - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Mask off inbound TCP checksum - v.tData := sAxisMaster.tData(127 downto 32) & x"0000" & sAxisMaster.tData(15 downto 0); - -- Latch the inbound TCP checksum - v.protCsum(0)(15 downto 8) := sAxisMaster.tData(23 downto 16); - v.protCsum(0)(7 downto 0) := sAxisMaster.tData(31 downto 24); - else - -- Mask off inbound TCP checksum - v.tData := sAxisMaster.tData(127 downto 64) & x"0000" & sAxisMaster.tData(47 downto 0); - -- Latch the inbound TCP checksum - v.protCsum(0)(15 downto 8) := sAxisMaster.tData(55 downto 48); - v.protCsum(0)(7 downto 0) := sAxisMaster.tData(63 downto 56); - end if; + v.protLen(0) := r.ipv4Len(0) - 20; + -- Mask off inbound TCP checksum + v.tData := sAxisMaster.tData(127 downto 32) & x"0000" & sAxisMaster.tData(15 downto 0); + -- Latch the inbound TCP checksum + v.protCsum(0)(15 downto 8) := sAxisMaster.tData(23 downto 16); + v.protCsum(0)(7 downto 0) := sAxisMaster.tData(31 downto 24); end if; -- Track the number of bytes v.byteCnt := r.byteCnt + getTKeep(sAxisMaster.tKeep, INT_EMAC_AXIS_CONFIG_C); @@ -390,7 +326,7 @@ begin v.state := BLOWOFF_S; else -- Next state - v.state := IDLE_S; + v.state := IDLE_S; -- Flush the AXIS pipeline v.pipeFlush := '1'; end if; diff --git a/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd b/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd index 2137135184..5fae072ff2 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; @@ -36,40 +35,29 @@ entity EthMacRxFifo is PRIM_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C; BYP_EN_G : boolean := false; BYP_COMMON_CLK_G : boolean := false; - BYP_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C; - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive := 1; - VLAN_COMMON_CLK_G : boolean := false; - VLAN_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C); + BYP_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C); port ( -- Clock and Reset - sClk : in sl; - sRst : in sl; + sClk : in sl; + sRst : in sl; -- Status/Config (sClk domain) - phyReady : in sl; - rxFifoDrop : out sl; - pauseThresh : in slv(15 downto 0); + phyReady : in sl; + rxFifoDrop : out sl; + pauseThresh : in slv(15 downto 0); -- Primary Interface - mPrimClk : in sl; - mPrimRst : in sl; - sPrimMaster : in AxiStreamMasterType; - sPrimCtrl : out AxiStreamCtrlType; - mPrimMaster : out AxiStreamMasterType; - mPrimSlave : in AxiStreamSlaveType; + mPrimClk : in sl; + mPrimRst : in sl; + sPrimMaster : in AxiStreamMasterType; + sPrimCtrl : out AxiStreamCtrlType; + mPrimMaster : out AxiStreamMasterType; + mPrimSlave : in AxiStreamSlaveType; -- Bypass interface - mBypClk : in sl; - mBypRst : in sl; - sBypMaster : in AxiStreamMasterType; - sBypCtrl : out AxiStreamCtrlType; - mBypMaster : out AxiStreamMasterType; - mBypSlave : in AxiStreamSlaveType; - -- VLAN Interfaces - mVlanClk : in sl; - mVlanRst : in sl; - sVlanMasters : in AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - sVlanCtrl : out AxiStreamCtrlArray(VLAN_SIZE_G-1 downto 0); - mVlanMasters : out AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - mVlanSlaves : in AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0)); + mBypClk : in sl; + mBypRst : in sl; + sBypMaster : in AxiStreamMasterType; + sBypCtrl : out AxiStreamCtrlType; + mBypMaster : out AxiStreamMasterType; + mBypSlave : in AxiStreamSlaveType); end EthMacRxFifo; architecture rtl of EthMacRxFifo is @@ -89,9 +77,8 @@ architecture rtl of EthMacRxFifo is signal r : RegType := REG_INIT_C; signal rin : RegType; - signal primDrop : sl := '0'; - signal bypDrop : sl := '0'; - signal vlanDrops : slv(VLAN_SIZE_G-1 downto 0) := (others => '0'); + signal primDrop : sl := '0'; + signal bypDrop : sl := '0'; -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; @@ -163,46 +150,7 @@ begin mAxisSlave => mBypSlave); end generate; - VLAN_DISABLED : if (VLAN_EN_G = false) generate - sVlanCtrl <= (others => AXI_STREAM_CTRL_UNUSED_C); - mVlanMasters <= (others => AXI_STREAM_MASTER_INIT_C); - end generate; - - VLAN_ENABLED : if (VLAN_EN_G = true) generate - GEN_VEC : for i in (VLAN_SIZE_G-1) downto 0 generate - U_Fifo : entity surf.SsiFifo - generic map ( - -- General Configurations - TPD_G => TPD_G, - INT_PIPE_STAGES_G => INT_PIPE_STAGES_G, - PIPE_STAGES_G => PIPE_STAGES_G, - SLAVE_READY_EN_G => false, - VALID_THOLD_G => VALID_THOLD_C, - -- FIFO configurations - SYNTH_MODE_G => SYNTH_MODE_G, - MEMORY_TYPE_G => MEMORY_TYPE_G, - GEN_SYNC_FIFO_G => PRIM_COMMON_CLK_G, - FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, - FIFO_FIXED_THRESH_G => false, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => INT_EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => VLAN_CONFIG_G) - port map ( - sAxisClk => sClk, - sAxisRst => sRst, - sAxisMaster => sVlanMasters(i), - sAxisCtrl => sVlanCtrl(i), - sAxisDropFrame => vlanDrops(i), - fifoPauseThresh => r.fifoPauseThresh, - mAxisClk => mVlanClk, - mAxisRst => mVlanRst, - mAxisMaster => mVlanMasters(i), - mAxisSlave => mVlanSlaves(i)); - end generate GEN_VEC; - end generate; - - comb : process (bypDrop, pauseThresh, phyReady, primDrop, r, sRst, - vlanDrops) is + comb : process (bypDrop, pauseThresh, phyReady, primDrop, r, sRst) is variable v : RegType; variable drop : sl; begin @@ -210,7 +158,7 @@ begin v := r; -- OR-ing drop flags together - v.rxFifoDrop := primDrop or bypDrop or uOr(vlanDrops); + v.rxFifoDrop := primDrop or bypDrop; -- Check the programmable threshold if pauseThresh >= (2**FIFO_ADDR_WIDTH_G)-1 then diff --git a/ethernet/EthMacCore/rtl/EthMacRxPause.vhd b/ethernet/EthMacCore/rtl/EthMacRxPause.vhd index 640dec6920..7262e1965c 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxPause.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxPause.vhd @@ -19,7 +19,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.AxiStreamPkg.all; use surf.StdRtlPkg.all; @@ -27,11 +26,8 @@ use surf.EthMacPkg.all; entity EthMacRxPause is generic ( - TPD_G : time := 1 ns; - PAUSE_EN_G : boolean := true; - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive range 1 to 8 := 1; - VLAN_VID_G : Slv12Array := (0 => x"001")); + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true); port ( -- Clock and Reset ethClk : in sl; @@ -40,7 +36,6 @@ entity EthMacRxPause is sAxisMaster : in AxiStreamMasterType; -- Outgoing data mAxisMaster : out AxiStreamMasterType; - mAxisMasters : out AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); -- Pause Values rxPauseReq : out sl; rxPauseValue : out slv(15 downto 0)); @@ -52,25 +47,20 @@ architecture rtl of EthMacRxPause is IDLE_S, PAUSE_S, DUMP_S, - PASS_S, - VLAN_S); + PASS_S); type RegType is record - idx : natural range 0 to VLAN_SIZE_G-1; - pauseEn : sl; - pauseValue : slv(15 downto 0); - mAxisMaster : AxiStreamMasterType; - mAxisMasters : AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - state : StateType; + pauseEn : sl; + pauseValue : slv(15 downto 0); + mAxisMaster : AxiStreamMasterType; + state : StateType; end record RegType; constant REG_INIT_C : RegType := ( - idx => 0, - pauseEn => '0', - pauseValue => (others => '0'), - mAxisMaster => AXI_STREAM_MASTER_INIT_C, - mAxisMasters => (others => AXI_STREAM_MASTER_INIT_C), - state => IDLE_S); + pauseEn => '0', + pauseValue => (others => '0'), + mAxisMaster => AXI_STREAM_MASTER_INIT_C, + state => IDLE_S); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -80,13 +70,11 @@ architecture rtl of EthMacRxPause is begin - U_RxPauseGen : if ((PAUSE_EN_G = true) or (VLAN_EN_G = true)) generate + U_RxPauseGen : if (PAUSE_EN_G = true) generate comb : process (ethRst, r, sAxisMaster) is - variable v : RegType; - variable i : natural; - variable vidDet : boolean; - variable vid : slv(11 downto 0); + variable v : RegType; + variable i : natural; begin -- Latch the current value v := r; @@ -94,14 +82,6 @@ begin -- Reset flags v.pauseEn := '0'; v.mAxisMaster.tValid := '0'; - for i in (VLAN_SIZE_G-1) downto 0 loop - v.mAxisMasters(i).tValid := '0'; - end loop; - - -- Update the variable - vidDet := false; - vid(11 downto 8) := sAxisMaster.tData(115 downto 112); - vid(7 downto 0) := sAxisMaster.tData(127 downto 120); -- State Machine case r.state is @@ -110,56 +90,28 @@ begin -- Check for data if (sAxisMaster.tValid = '1') then -- Check for pause frame - if (PAUSE_EN_G = true) and - (sAxisMaster.tData(47 downto 0) = x"01_00_00_C2_80_01") and -- DST MAC (Pause MAC Address) - (sAxisMaster.tData(127 downto 96) = x"01_00_08_88") then -- Mac Type, Mac OpCode + if (sAxisMaster.tData(47 downto 0) = x"01_00_00_C2_80_01") and -- DST MAC (Pause MAC Address) + (sAxisMaster.tData(127 downto 96) = x"01_00_08_88") then -- Mac Type, Mac OpCode -- Check for no EOF if (sAxisMaster.tLast = '0') then -- Next State v.state := PAUSE_S; end if; else - if (VLAN_EN_G = false) then - -- Move the data - v.mAxisMaster := sAxisMaster; - -- Check for no EOF - if (sAxisMaster.tLast = '0') then - -- Next State - v.state := PASS_S; - end if; - else - -- Check for VLAN - if (sAxisMaster.tData(111 downto 96) = VLAN_TYPE_C) then - for i in (VLAN_SIZE_G-1) downto 0 loop - if (vidDet = false) and (vid = VLAN_VID_G(i)) then - vidDet := true; - v.idx := i; - -- Move the data - v.mAxisMasters(i) := sAxisMaster; - -- Check for no EOF - if (sAxisMaster.tLast = '0') then - -- Next State - v.state := VLAN_S; - end if; - end if; - end loop; - else - -- Move the data - v.mAxisMaster := sAxisMaster; - -- Check for no EOF - if (sAxisMaster.tLast = '0') then - -- Next State - v.state := PASS_S; - end if; - end if; + -- Move the data + v.mAxisMaster := sAxisMaster; + -- Check for no EOF + if (sAxisMaster.tLast = '0') then + -- Next State + v.state := PASS_S; end if; end if; end if; ---------------------------------------------------------------------- when PAUSE_S => - -------------------------------------------------------------------------------------------------------------------- - -- Refer to https://hasanmansur1.files.wordpress.com/2012/12/ethernet-flow-control-pause-frame-framing-structure.png - -------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------- + -- Refer to https://hasanmansur1.files.wordpress.com/2012/12/ethernet-flow-control-pause-frame-framing-structure.png + -------------------------------------------------------------------------------------------------------------------- -- Check for data if (sAxisMaster.tValid = '1') then -- Latch the pause data @@ -194,15 +146,6 @@ begin -- Next State v.state := IDLE_S; end if; - ---------------------------------------------------------------------- - when VLAN_S => - -- Move the data - v.mAxisMasters(r.idx) := sAxisMaster; - -- Check for a valid EOF - if (sAxisMaster.tValid = '1') and (sAxisMaster.tLast = '1') then - -- Next State - v.state := IDLE_S; - end if; ---------------------------------------------------------------------- end case; @@ -216,7 +159,6 @@ begin -- Outputs mAxisMaster <= r.mAxisMaster; - mAxisMasters <= r.mAxisMasters; rxPauseReq <= r.pauseEn; rxPauseValue <= r.pauseValue; @@ -231,9 +173,8 @@ begin end generate; - U_BypRxPause : if ((PAUSE_EN_G = false) and (VLAN_EN_G = false)) generate + U_BypRxPause : if (PAUSE_EN_G = false) generate mAxisMaster <= sAxisMaster; - mAxisMasters <= (others => AXI_STREAM_MASTER_INIT_C); rxPauseReq <= '0'; rxPauseValue <= (others => '0'); end generate; diff --git a/ethernet/EthMacCore/rtl/EthMacTop.vhd b/ethernet/EthMacCore/rtl/EthMacTop.vhd index ea86bfd9c2..3a87fc95c6 100644 --- a/ethernet/EthMacCore/rtl/EthMacTop.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTop.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.AxiStreamPkg.all; use surf.StdRtlPkg.all; @@ -39,67 +38,54 @@ entity EthMacTop is FIFO_ADDR_WIDTH_G : positive := 11; SYNTH_MODE_G : string := "inferred"; MEMORY_TYPE_G : string := "block"; - -- Non-VLAN Configurations + -- Misc. Configurations FILT_EN_G : boolean := false; PRIM_COMMON_CLK_G : boolean := false; PRIM_CONFIG_G : AxiStreamConfigType := EMAC_AXIS_CONFIG_C; BYP_EN_G : boolean := false; BYP_ETH_TYPE_G : slv(15 downto 0) := x"0000"; BYP_COMMON_CLK_G : boolean := false; - BYP_CONFIG_G : AxiStreamConfigType := EMAC_AXIS_CONFIG_C; - -- VLAN Configurations - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive range 1 to 8 := 1; - VLAN_VID_G : Slv12Array := (0 => x"001"); - VLAN_COMMON_CLK_G : boolean := false; - VLAN_CONFIG_G : AxiStreamConfigType := EMAC_AXIS_CONFIG_C); + BYP_CONFIG_G : AxiStreamConfigType := EMAC_AXIS_CONFIG_C); port ( -- Core Clock and Reset - ethClkEn : in sl := '1'; - ethClk : in sl; - ethRst : in sl; + ethClkEn : in sl := '1'; + ethClk : in sl; + ethRst : in sl; -- Primary Interface - primClk : in sl; - primRst : in sl; - ibMacPrimMaster : in AxiStreamMasterType; - ibMacPrimSlave : out AxiStreamSlaveType; - obMacPrimMaster : out AxiStreamMasterType; - obMacPrimSlave : in AxiStreamSlaveType; + primClk : in sl; + primRst : in sl; + ibMacPrimMaster : in AxiStreamMasterType; + ibMacPrimSlave : out AxiStreamSlaveType; + obMacPrimMaster : out AxiStreamMasterType; + obMacPrimSlave : in AxiStreamSlaveType; -- Bypass interface - bypClk : in sl := '0'; - bypRst : in sl := '0'; - ibMacBypMaster : in AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - ibMacBypSlave : out AxiStreamSlaveType; - obMacBypMaster : out AxiStreamMasterType; - obMacBypSlave : in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - -- VLAN Interfaces - vlanClk : in sl := '0'; - vlanRst : in sl := '0'; - ibMacVlanMasters : in AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - ibMacVlanSlaves : out AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0); - obMacVlanMasters : out AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - obMacVlanSlaves : in AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + bypClk : in sl := '0'; + bypRst : in sl := '0'; + ibMacBypMaster : in AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + ibMacBypSlave : out AxiStreamSlaveType; + obMacBypMaster : out AxiStreamMasterType; + obMacBypSlave : in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; -- XLGMII PHY Interface - xlgmiiRxd : in slv(127 downto 0) := (others => '0'); - xlgmiiRxc : in slv(15 downto 0) := (others => '0'); - xlgmiiTxd : out slv(127 downto 0); - xlgmiiTxc : out slv(15 downto 0); + xlgmiiRxd : in slv(127 downto 0) := (others => '0'); + xlgmiiRxc : in slv(15 downto 0) := (others => '0'); + xlgmiiTxd : out slv(127 downto 0); + xlgmiiTxc : out slv(15 downto 0); -- XGMII PHY Interface - xgmiiRxd : in slv(63 downto 0) := (others => '0'); - xgmiiRxc : in slv(7 downto 0) := (others => '0'); - xgmiiTxd : out slv(63 downto 0); - xgmiiTxc : out slv(7 downto 0); + xgmiiRxd : in slv(63 downto 0) := (others => '0'); + xgmiiRxc : in slv(7 downto 0) := (others => '0'); + xgmiiTxd : out slv(63 downto 0); + xgmiiTxc : out slv(7 downto 0); -- GMII PHY Interface - gmiiRxDv : in sl := '0'; - gmiiRxEr : in sl := '0'; - gmiiRxd : in slv(7 downto 0) := (others => '0'); - gmiiTxEn : out sl; - gmiiTxEr : out sl; - gmiiTxd : out slv(7 downto 0); + gmiiRxDv : in sl := '0'; + gmiiRxEr : in sl := '0'; + gmiiRxd : in slv(7 downto 0) := (others => '0'); + gmiiTxEn : out sl; + gmiiTxEr : out sl; + gmiiTxd : out slv(7 downto 0); -- Configuration and status - phyReady : in sl; - ethConfig : in EthMacConfigType; - ethStatus : out EthMacStatusType); + phyReady : in sl; + ethConfig : in EthMacConfigType; + ethStatus : out EthMacStatusType); end EthMacTop; architecture mapping of EthMacTop is @@ -114,11 +100,6 @@ architecture mapping of EthMacTop is signal mBypMaster : AxiStreamMasterType; signal mBypCtrl : AxiStreamCtrlType; - signal sVlanMasters : AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - signal sVlanSlaves : AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0); - signal mVlanMasters : AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - signal mVlanCtrl : AxiStreamCtrlArray(VLAN_SIZE_G-1 downto 0); - signal rxPauseReq : sl; signal rxPauseValue : slv(15 downto 0); signal flowCtrl : AxiStreamCtrlType; @@ -144,36 +125,25 @@ begin BYP_EN_G => BYP_EN_G, BYP_COMMON_CLK_G => BYP_COMMON_CLK_G, BYP_CONFIG_G => BYP_CONFIG_G, - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_COMMON_CLK_G => VLAN_COMMON_CLK_G, - VLAN_CONFIG_G => VLAN_CONFIG_G, SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Master Clock and Reset - mClk => ethClk, - mRst => ethRst, + mClk => ethClk, + mRst => ethRst, -- Primary Interface - sPrimClk => primClk, - sPrimRst => primRst, - sPrimMaster => ibMacPrimMaster, - sPrimSlave => ibMacPrimSlave, - mPrimMaster => sPrimMaster, - mPrimSlave => sPrimSlave, + sPrimClk => primClk, + sPrimRst => primRst, + sPrimMaster => ibMacPrimMaster, + sPrimSlave => ibMacPrimSlave, + mPrimMaster => sPrimMaster, + mPrimSlave => sPrimSlave, -- Bypass interface - sBypClk => bypClk, - sBypRst => bypRst, - sBypMaster => ibMacBypMaster, - sBypSlave => ibMacBypSlave, - mBypMaster => sBypMaster, - mBypSlave => sBypSlave, - -- VLAN Interfaces - sVlanClk => vlanClk, - sVlanRst => vlanRst, - sVlanMasters => ibMacVlanMasters, - sVlanSlaves => ibMacVlanSlaves, - mVlanMasters => sVlanMasters, - mVlanSlaves => sVlanSlaves); + sBypClk => bypClk, + sBypRst => bypRst, + sBypMaster => ibMacBypMaster, + sBypSlave => ibMacBypSlave, + mBypMaster => sBypMaster, + mBypSlave => sBypSlave); ------------ -- TX Module @@ -188,12 +158,8 @@ begin PHY_TYPE_G => PHY_TYPE_G, DROP_ERR_PKT_G => DROP_ERR_PKT_G, JUMBO_G => JUMBO_G, - -- Non-VLAN Configurations + -- Misc. Configurations BYP_EN_G => BYP_EN_G, - -- VLAN Configurations - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_VID_G => VLAN_VID_G, -- RAM sythesis Mode SYNTH_MODE_G => SYNTH_MODE_G) port map ( @@ -207,9 +173,6 @@ begin -- Bypass interface sBypMaster => sBypMaster, sBypSlave => sBypSlave, - -- VLAN Interfaces - sVlanMasters => sVlanMasters, - sVlanSlaves => sVlanSlaves, -- XLGMII PHY Interface xlgmiiTxd => xlgmiiTxd, xlgmiiTxc => xlgmiiTxc, @@ -237,10 +200,8 @@ begin --------------------- U_FlowCtrl : entity surf.EthMacFlowCtrl generic map ( - TPD_G => TPD_G, - BYP_EN_G => BYP_EN_G, - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G) + TPD_G => TPD_G, + BYP_EN_G => BYP_EN_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -248,7 +209,6 @@ begin -- Inputs primCtrl => mPrimCtrl, bypCtrl => mBypCtrl, - vlanCtrl => mVlanCtrl, -- Output flowCtrl => flowCtrl); @@ -263,14 +223,10 @@ begin PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => PHY_TYPE_G, JUMBO_G => JUMBO_G, - -- Non-VLAN Configurations + -- Misc. Configurations FILT_EN_G => FILT_EN_G, BYP_EN_G => BYP_EN_G, BYP_ETH_TYPE_G => BYP_ETH_TYPE_G, - -- VLAN Configurations - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_VID_G => VLAN_VID_G, -- RAM Synthesis mode SYNTH_MODE_G => SYNTH_MODE_G) port map ( @@ -284,9 +240,6 @@ begin -- Bypass Interface mBypMaster => mBypMaster, mBypCtrl => mBypCtrl, - -- VLAN Interfaces - mVlanMasters => mVlanMasters, - mVlanCtrl => mVlanCtrl, -- XLGMII PHY Interface xlgmiiRxd => xlgmiiRxd, xlgmiiRxc => xlgmiiRxc, @@ -322,39 +275,28 @@ begin PRIM_CONFIG_G => PRIM_CONFIG_G, BYP_EN_G => BYP_EN_G, BYP_COMMON_CLK_G => BYP_COMMON_CLK_G, - BYP_CONFIG_G => BYP_CONFIG_G, - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_COMMON_CLK_G => VLAN_COMMON_CLK_G, - VLAN_CONFIG_G => VLAN_CONFIG_G) + BYP_CONFIG_G => BYP_CONFIG_G) port map ( -- Slave Clock and Reset - sClk => ethClk, - sRst => ethRst, + sClk => ethClk, + sRst => ethRst, -- Status/Config (sClk domain) - phyReady => phyReady, - rxFifoDrop => ethStatus.rxFifoDropCnt, - pauseThresh => ethConfig.pauseThresh, + phyReady => phyReady, + rxFifoDrop => ethStatus.rxFifoDropCnt, + pauseThresh => ethConfig.pauseThresh, -- Primary Interface - mPrimClk => primClk, - mPrimRst => primRst, - sPrimMaster => mPrimMaster, - sPrimCtrl => mPrimCtrl, - mPrimMaster => obMacPrimMaster, - mPrimSlave => obMacPrimSlave, + mPrimClk => primClk, + mPrimRst => primRst, + sPrimMaster => mPrimMaster, + sPrimCtrl => mPrimCtrl, + mPrimMaster => obMacPrimMaster, + mPrimSlave => obMacPrimSlave, -- Bypass interface - mBypClk => bypClk, - mBypRst => bypRst, - sBypMaster => mBypMaster, - sBypCtrl => mBypCtrl, - mBypMaster => obMacBypMaster, - mBypSlave => obMacBypSlave, - -- VLAN Interfaces - mVlanClk => vlanClk, - mVlanRst => vlanRst, - sVlanMasters => mVlanMasters, - sVlanCtrl => mVlanCtrl, - mVlanMasters => obMacVlanMasters, - mVlanSlaves => obMacVlanSlaves); + mBypClk => bypClk, + mBypRst => bypRst, + sBypMaster => mBypMaster, + sBypCtrl => mBypCtrl, + mBypMaster => obMacBypMaster, + mBypSlave => obMacBypSlave); end mapping; diff --git a/ethernet/EthMacCore/rtl/EthMacTx.vhd b/ethernet/EthMacCore/rtl/EthMacTx.vhd index 27cd40a8c4..2a916fc320 100644 --- a/ethernet/EthMacCore/rtl/EthMacTx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTx.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.AxiStreamPkg.all; use surf.StdRtlPkg.all; @@ -33,12 +32,8 @@ entity EthMacTx is PHY_TYPE_G : string := "XGMII"; DROP_ERR_PKT_G : boolean := true; JUMBO_G : boolean := true; - -- Non-VLAN Configurations + -- Misc. Configurations BYP_EN_G : boolean := false; - -- VLAN Configurations - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive range 1 to 8 := 1; - VLAN_VID_G : Slv12Array := (0 => x"001"); -- RAM Synthesis mode SYNTH_MODE_G : string := "inferred"); port ( @@ -52,9 +47,6 @@ entity EthMacTx is -- Bypass interface sBypMaster : in AxiStreamMasterType; sBypSlave : out AxiStreamSlaveType; - -- VLAN Interfaces - sVlanMasters : in AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - sVlanSlaves : out AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0); -- XLGMII PHY Interface xlgmiiTxd : out slv(127 downto 0); xlgmiiTxc : out slv(15 downto 0); @@ -82,12 +74,12 @@ architecture mapping of EthMacTx is signal bypassMaster : AxiStreamMasterType; signal bypassSlave : AxiStreamSlaveType; - signal csumMaster : AxiStreamMasterType; - signal csumSlave : AxiStreamSlaveType; - signal csumMasters : AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - signal csumSlaves : AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0); - signal macObMaster : AxiStreamMasterType; - signal macObSlave : AxiStreamSlaveType; + + signal csumMaster : AxiStreamMasterType; + signal csumSlave : AxiStreamSlaveType; + + signal macObMaster : AxiStreamMasterType; + signal macObSlave : AxiStreamSlaveType; begin @@ -112,16 +104,14 @@ begin mAxisMaster => bypassMaster, mAxisSlave => bypassSlave); - ------------------------------ - -- TX Non-VLAN Checksum Module - ------------------------------ + --------------------- + -- TX Checksum Module + --------------------- U_Csum : entity surf.EthMacTxCsum generic map ( TPD_G => TPD_G, DROP_ERR_PKT_G => DROP_ERR_PKT_G, - JUMBO_G => JUMBO_G, - VLAN_G => false, - VID_G => x"001") + JUMBO_G => JUMBO_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -136,41 +126,6 @@ begin mAxisMaster => csumMaster, mAxisSlave => csumSlave); - -------------------------- - -- TX VLAN Checksum Module - -------------------------- - GEN_VLAN : if (VLAN_EN_G = true) generate - GEN_VEC : - for i in (VLAN_SIZE_G-1) downto 0 generate - U_Csum : entity surf.EthMacTxCsum - generic map ( - TPD_G => TPD_G, - DROP_ERR_PKT_G => DROP_ERR_PKT_G, - JUMBO_G => JUMBO_G, - VLAN_G => true, - VID_G => VLAN_VID_G(i)) - port map ( - -- Clock and Reset - ethClk => ethClk, - ethRst => ethRst, - -- Configurations - ipCsumEn => '1', - tcpCsumEn => '1', - udpCsumEn => '1', - -- Outbound data to MAC - sAxisMaster => sVlanMasters(i), - sAxisSlave => sVlanSlaves(i), - mAxisMaster => csumMasters(i), - mAxisSlave => csumSlaves(i)); - end generate GEN_VEC; - end generate; - - BYPASS_VLAN : if (VLAN_EN_G = false) generate - -- Terminate Unused buses - sVlanSlaves <= (others => AXI_STREAM_SLAVE_FORCE_C); - csumMasters <= (others => AXI_STREAM_MASTER_INIT_C); - end generate; - ------------------ -- TX Pause Module ------------------ @@ -178,9 +133,7 @@ begin generic map ( TPD_G => TPD_G, PAUSE_EN_G => PAUSE_EN_G, - PAUSE_512BITS_G => PAUSE_512BITS_G, - VLAN_EN_G => VLAN_EN_G, - VLAN_SIZE_G => VLAN_SIZE_G) + PAUSE_512BITS_G => PAUSE_512BITS_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -188,8 +141,6 @@ begin -- Incoming data from client sAxisMaster => csumMaster, sAxisSlave => csumSlave, - sAxisMasters => csumMasters, - sAxisSlaves => csumSlaves, -- Outgoing data to MAC mAxisMaster => macObMaster, mAxisSlave => macObSlave, diff --git a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd index 4ad511ad5b..97a56349d0 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd @@ -18,7 +18,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; @@ -26,12 +25,10 @@ use surf.EthMacPkg.all; entity EthMacTxCsum is generic ( - TPD_G : time := 1 ns; - DROP_ERR_PKT_G : boolean := true; - JUMBO_G : boolean := true; - VLAN_G : boolean := false; - VID_G : slv(11 downto 0) := x"001"; - SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs + TPD_G : time := 1 ns; + DROP_ERR_PKT_G : boolean := true; + JUMBO_G : boolean := true; + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Clock and Reset ethClk : in sl; @@ -249,24 +246,16 @@ begin -- Write the transaction data v.tranWr := '1'; else - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Check for EtherType = IPV4 = 0x0800 - if (rxMaster.tData(111 downto 96) = IPV4_TYPE_C) then - -- Set the flag - v.ipv4Det(0) := '1'; - end if; - -- Fill in the IPv4 header checksum - v.ipv4Hdr(0) := rxMaster.tData(119 downto 112); -- IPVersion + Header length - v.ipv4Hdr(1) := rxMaster.tData(127 downto 120); -- DSCP and ECN - else - -- Add the IEEE 802.1Q header - v.sMaster.tData(111 downto 96) := VLAN_TYPE_C; - v.sMaster.tData(119 downto 112) := x"0" & VID_G(11 downto 8); - v.sMaster.tData(127 downto 120) := VID_G(7 downto 0); + -- Check for EtherType = IPV4 = 0x0800 + if (rxMaster.tData(111 downto 96) = IPV4_TYPE_C) then + -- Set the flag + v.ipv4Det(0) := '1'; end if; + -- Fill in the IPv4 header checksum + v.ipv4Hdr(0) := rxMaster.tData(119 downto 112); -- IPVersion + Header length + v.ipv4Hdr(1) := rxMaster.tData(127 downto 120); -- DSCP and ECN -- Next state - v.state := IPV4_HDR0_S; + v.state := IPV4_HDR0_S; end if; end if; ---------------------------------------------------------------------- @@ -292,45 +281,22 @@ begin -- Next state v.state := IDLE_S; else - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Fill in the IPv4 header checksum - v.ipv4Hdr(4) := rxMaster.tData(23 downto 16); -- IPV4_ID(15 downto 8) - v.ipv4Hdr(5) := rxMaster.tData(31 downto 24); -- IPV4_ID(7 downto 0) - v.ipv4Hdr(6) := rxMaster.tData(39 downto 32); -- Flags(2 downto 0) and Fragment Offsets(12 downto 8) - v.ipv4Hdr(7) := rxMaster.tData(47 downto 40); -- Fragment Offsets(7 downto 0) - v.ipv4Hdr(8) := rxMaster.tData(55 downto 48); -- Time-To-Live - v.ipv4Hdr(9) := rxMaster.tData(63 downto 56); -- Protocol - v.ipv4Hdr(12) := rxMaster.tData(87 downto 80); -- Source IP Address - v.ipv4Hdr(13) := rxMaster.tData(95 downto 88); -- Source IP Address - v.ipv4Hdr(14) := rxMaster.tData(103 downto 96); -- Source IP Address - v.ipv4Hdr(15) := rxMaster.tData(111 downto 104); -- Source IP Address - v.ipv4Hdr(16) := rxMaster.tData(119 downto 112); -- Destination IP Address - v.ipv4Hdr(17) := rxMaster.tData(127 downto 120); -- Destination IP Address - -- Fill in the TCP/UDP checksum - v.tData(63 downto 0) := rxMaster.tData(127 downto 80) & rxMaster.tData(63 downto 56) & x"00"; - v.tKeep(7 downto 0) := (others => '1'); - else - -- Check for EtherType = IPV4 = 0x0800 - if (rxMaster.tData(15 downto 0) = IPV4_TYPE_C) then - -- Set the flag - v.ipv4Det(0) := '1'; - end if; - -- Fill in the IPv4 header checksum - v.ipv4Hdr(0) := rxMaster.tData(23 downto 16); -- IPVersion + Header length - v.ipv4Hdr(1) := rxMaster.tData(31 downto 24); -- DSCP and ECN - v.ipv4Hdr(4) := rxMaster.tData(55 downto 48); -- IPV4_ID(15 downto 8) - v.ipv4Hdr(5) := rxMaster.tData(63 downto 56); -- IPV4_ID(7 downto 0) - v.ipv4Hdr(6) := rxMaster.tData(71 downto 64); -- Flags(2 downto 0) and Fragment Offsets(12 downto 8) - v.ipv4Hdr(7) := rxMaster.tData(79 downto 72); -- Fragment Offsets(7 downto 0) - v.ipv4Hdr(8) := rxMaster.tData(87 downto 80); -- Time-To-Live - v.ipv4Hdr(9) := rxMaster.tData(95 downto 88); -- Protocol - v.ipv4Hdr(12) := rxMaster.tData(119 downto 112); -- Source IP Address - v.ipv4Hdr(13) := rxMaster.tData(127 downto 120); -- Source IP Address - -- Fill in the TCP/UDP checksum - v.tData(31 downto 0) := rxMaster.tData(127 downto 112) & rxMaster.tData(95 downto 88) & x"00"; - v.tKeep(3 downto 0) := (others => '1'); - end if; + -- Fill in the IPv4 header checksum + v.ipv4Hdr(4) := rxMaster.tData(23 downto 16); -- IPV4_ID(15 downto 8) + v.ipv4Hdr(5) := rxMaster.tData(31 downto 24); -- IPV4_ID(7 downto 0) + v.ipv4Hdr(6) := rxMaster.tData(39 downto 32); -- Flags(2 downto 0) and Fragment Offsets(12 downto 8) + v.ipv4Hdr(7) := rxMaster.tData(47 downto 40); -- Fragment Offsets(7 downto 0) + v.ipv4Hdr(8) := rxMaster.tData(55 downto 48); -- Time-To-Live + v.ipv4Hdr(9) := rxMaster.tData(63 downto 56); -- Protocol + v.ipv4Hdr(12) := rxMaster.tData(87 downto 80); -- Source IP Address + v.ipv4Hdr(13) := rxMaster.tData(95 downto 88); -- Source IP Address + v.ipv4Hdr(14) := rxMaster.tData(103 downto 96); -- Source IP Address + v.ipv4Hdr(15) := rxMaster.tData(111 downto 104); -- Source IP Address + v.ipv4Hdr(16) := rxMaster.tData(119 downto 112); -- Destination IP Address + v.ipv4Hdr(17) := rxMaster.tData(127 downto 120); -- Destination IP Address + -- Fill in the TCP/UDP checksum + v.tData(63 downto 0) := rxMaster.tData(127 downto 80) & rxMaster.tData(63 downto 56) & x"00"; + v.tKeep(7 downto 0) := (others => '1'); -- Check for UDP protocol if (v.ipv4Hdr(9) = UDP_C) then v.udpDet(0) := '1'; @@ -354,36 +320,17 @@ begin -- Fill in the TCP/UDP checksum v.tKeep := rxMaster.tKeep(15 downto 0); v.tData := rxMaster.tData(127 downto 0); - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Fill in the IPv4 header checksum - v.ipv4Hdr(18) := rxMaster.tData(7 downto 0); -- Destination IP Address - v.ipv4Hdr(19) := rxMaster.tData(15 downto 8); -- Destination IP Address - -- Check for UDP data with inbound length/checksum - if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then - -- Mask off inbound UDP length/checksum - v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0); - end if; - -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2; - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2; - else - -- Fill in the IPv4 header checksum - v.ipv4Hdr(14) := rxMaster.tData(7 downto 0); -- Source IP Address - v.ipv4Hdr(15) := rxMaster.tData(15 downto 8); -- Source IP Address - v.ipv4Hdr(16) := rxMaster.tData(23 downto 16); -- Destination IP Address - v.ipv4Hdr(17) := rxMaster.tData(31 downto 24); -- Destination IP Address - v.ipv4Hdr(18) := rxMaster.tData(39 downto 32); -- Destination IP Address - v.ipv4Hdr(19) := rxMaster.tData(47 downto 40); -- Destination IP Address - -- Check for UDP data with inbound length/checksum - if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then - -- Mask off inbound UDP length/checksum - v.tData := rxMaster.tData(127 downto 112) & x"00000000" & rxMaster.tData(79 downto 0); - end if; - -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 6; - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 6; + -- Fill in the IPv4 header checksum + v.ipv4Hdr(18) := rxMaster.tData(7 downto 0); -- Destination IP Address + v.ipv4Hdr(19) := rxMaster.tData(15 downto 8); -- Destination IP Address + -- Check for UDP data with inbound length/checksum + if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then + -- Mask off inbound UDP length/checksum + v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0); end if; + -- Track the number of bytes + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2; + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2; -- Check for EOF if (rxMaster.tLast = '1') then -- Save the EOFE value @@ -412,14 +359,8 @@ begin if (r.ipv4Det(0) = '1') and (r.tcpDet(0) = '1') and (r.tcpFlag = '0') then -- Set the flag v.tcpFlag := '1'; - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Mask off inbound TCP checksum - v.tData := rxMaster.tData(127 downto 32) & x"0000" & rxMaster.tData(15 downto 0); - else - -- Mask off inbound TCP checksum - v.tData := rxMaster.tData(127 downto 64) & x"0000" & rxMaster.tData(47 downto 0); - end if; + -- Mask off inbound TCP checksum + v.tData := rxMaster.tData(127 downto 32) & x"0000" & rxMaster.tData(15 downto 0); end if; -- Track the number of bytes v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C); @@ -483,117 +424,58 @@ begin end if; -- Check for IPv4 checksum/length insertion if (ipv4Det = '1') and (r.mvCnt = 1) then - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Check if firmware checksum enabled - if (ipCsumEn = '1') then - -- Overwrite the data field - v.txMaster.tData(7 downto 0) := ipv4Len(15 downto 8); - v.txMaster.tData(15 downto 8) := ipv4Len(7 downto 0); - v.txMaster.tData(71 downto 64) := ipv4Csum(15 downto 8); - v.txMaster.tData(79 downto 72) := ipv4Csum(7 downto 0); - end if; - -- Check for mismatch between firmware/software IPv4 length - if (ipv4Len(15 downto 8) /= mMaster.tData(7 downto 0)) or (ipv4Len(7 downto 0) /= mMaster.tData(15 downto 8)) then - -- Set the flag - v.dbg(0) := '1'; - end if; - -- Check for mismatch between firmware/software IPv4 checksum - if (ipv4Csum(15 downto 8) /= mMaster.tData(71 downto 64)) or (ipv4Csum(7 downto 0) /= mMaster.tData(79 downto 72)) then - -- Set the flag - v.dbg(1) := '1'; - end if; - else - -- Check if firmware checksum enabled - if (ipCsumEn = '1') then - -- Overwrite the data field - v.txMaster.tData(39 downto 32) := ipv4Len(15 downto 8); - v.txMaster.tData(47 downto 40) := ipv4Len(7 downto 0); - v.txMaster.tData(103 downto 96) := ipv4Csum(15 downto 8); - v.txMaster.tData(111 downto 104) := ipv4Csum(7 downto 0); - end if; - -- Check for mismatch between firmware/software IPv4 length - if (ipv4Len(15 downto 8) /= mMaster.tData(39 downto 32)) or (ipv4Len(7 downto 0) /= mMaster.tData(47 downto 40)) then - -- Set the flag - v.dbg(0) := '1'; - end if; - -- Check for mismatch between firmware/software IPv4 checksum - if (ipv4Csum(15 downto 8) /= mMaster.tData(103 downto 96)) or (ipv4Csum(7 downto 0) /= mMaster.tData(111 downto 104)) then - -- Set the flag - v.dbg(1) := '1'; - end if; + -- Check if firmware checksum enabled + if (ipCsumEn = '1') then + -- Overwrite the data field + v.txMaster.tData(7 downto 0) := ipv4Len(15 downto 8); + v.txMaster.tData(15 downto 8) := ipv4Len(7 downto 0); + v.txMaster.tData(71 downto 64) := ipv4Csum(15 downto 8); + v.txMaster.tData(79 downto 72) := ipv4Csum(7 downto 0); + end if; + -- Check for mismatch between firmware/software IPv4 length + if (ipv4Len(15 downto 8) /= mMaster.tData(7 downto 0)) or (ipv4Len(7 downto 0) /= mMaster.tData(15 downto 8)) then + -- Set the flag + v.dbg(0) := '1'; + end if; + -- Check for mismatch between firmware/software IPv4 checksum + if (ipv4Csum(15 downto 8) /= mMaster.tData(71 downto 64)) or (ipv4Csum(7 downto 0) /= mMaster.tData(79 downto 72)) then + -- Set the flag + v.dbg(1) := '1'; end if; end if; -- Check for UDP checksum/length insertion and no fragmentation if (ipv4Det = '1') and (udpDet = '1') and (fragDet = '0') and (r.mvCnt = 2) then - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Check if firmware checksum enabled - if (udpCsumEn = '1') then - -- Overwrite the data field - v.txMaster.tData(55 downto 48) := protLen(15 downto 8); - v.txMaster.tData(63 downto 56) := protLen(7 downto 0); - v.txMaster.tData(71 downto 64) := protCsum(15 downto 8); - v.txMaster.tData(79 downto 72) := protCsum(7 downto 0); - end if; - -- Check for mismatch between firmware/software UDP length - if (protLen(15 downto 8) /= mMaster.tData(55 downto 48)) or (protLen(7 downto 0) /= mMaster.tData(63 downto 56)) then - -- Set the flag - v.dbg(2) := '1'; - end if; - -- Check for mismatch between firmware/software UDP checksum - if (protCsum(15 downto 8) /= mMaster.tData(71 downto 64)) or (protCsum(7 downto 0) /= mMaster.tData(79 downto 72)) then - -- Set the flag - v.dbg(3) := '1'; - end if; - else - -- Check if firmware checksum enabled - if (udpCsumEn = '1') then - -- Overwrite the data field - v.txMaster.tData(87 downto 80) := protLen(15 downto 8); - v.txMaster.tData(95 downto 88) := protLen(7 downto 0); - v.txMaster.tData(103 downto 96) := protCsum(15 downto 8); - v.txMaster.tData(111 downto 104) := protCsum(7 downto 0); - end if; - -- Check for mismatch between firmware/software UDP length - if (protLen(15 downto 8) /= mMaster.tData(87 downto 80)) or (protLen(7 downto 0) /= mMaster.tData(95 downto 88)) then - -- Set the flag - v.dbg(2) := '1'; - end if; - -- Check for mismatch between firmware/software UDP checksum - if (protCsum(15 downto 8) /= mMaster.tData(103 downto 96)) or (protCsum(7 downto 0) /= mMaster.tData(111 downto 104)) then - -- Set the flag - v.dbg(3) := '1'; - end if; + -- Check if firmware checksum enabled + if (udpCsumEn = '1') then + -- Overwrite the data field + v.txMaster.tData(55 downto 48) := protLen(15 downto 8); + v.txMaster.tData(63 downto 56) := protLen(7 downto 0); + v.txMaster.tData(71 downto 64) := protCsum(15 downto 8); + v.txMaster.tData(79 downto 72) := protCsum(7 downto 0); + end if; + -- Check for mismatch between firmware/software UDP length + if (protLen(15 downto 8) /= mMaster.tData(55 downto 48)) or (protLen(7 downto 0) /= mMaster.tData(63 downto 56)) then + -- Set the flag + v.dbg(2) := '1'; + end if; + -- Check for mismatch between firmware/software UDP checksum + if (protCsum(15 downto 8) /= mMaster.tData(71 downto 64)) or (protCsum(7 downto 0) /= mMaster.tData(79 downto 72)) then + -- Set the flag + v.dbg(3) := '1'; end if; end if; -- Check for TCP checksum insertion and no fragmentation if (ipv4Det = '1') and (tcpDet = '1') and (fragDet = '0') and (r.mvCnt = 3) then - -- Check if NON-VLAN - if (VLAN_G = false) then - -- Check if firmware checksum enabled - if (tcpCsumEn = '1') then - -- Overwrite the data field - v.txMaster.tData(23 downto 16) := protCsum(15 downto 8); - v.txMaster.tData(31 downto 24) := protCsum(7 downto 0); - end if; - -- Check for mismatch between firmware/software TCP checksum - if (protCsum(15 downto 8) /= mMaster.tData(23 downto 16)) or (protCsum(7 downto 0) /= mMaster.tData(31 downto 24)) then - -- Set the flag - v.dbg(4) := '1'; - end if; - else - -- Check if firmware checksum enabled - if (tcpCsumEn = '1') then - -- Overwrite the data field - v.txMaster.tData(55 downto 48) := protCsum(15 downto 8); - v.txMaster.tData(63 downto 56) := protCsum(7 downto 0); - end if; - -- Check for mismatch between firmware/software TCP checksum - if (protCsum(15 downto 8) /= mMaster.tData(55 downto 48)) or (protCsum(7 downto 0) /= mMaster.tData(63 downto 56)) then - -- Set the flag - v.dbg(4) := '1'; - end if; + -- Check if firmware checksum enabled + if (tcpCsumEn = '1') then + -- Overwrite the data field + v.txMaster.tData(23 downto 16) := protCsum(15 downto 8); + v.txMaster.tData(31 downto 24) := protCsum(7 downto 0); + end if; + -- Check for mismatch between firmware/software TCP checksum + if (protCsum(15 downto 8) /= mMaster.tData(23 downto 16)) or (protCsum(7 downto 0) /= mMaster.tData(31 downto 24)) then + -- Set the flag + v.dbg(4) := '1'; end if; end if; -- Check for tLast diff --git a/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd b/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd index d893aab7ae..47cb0f2a7a 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd @@ -15,7 +15,6 @@ library ieee; use ieee.std_logic_1164.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; @@ -29,36 +28,25 @@ entity EthMacTxFifo is BYP_EN_G : boolean := false; BYP_COMMON_CLK_G : boolean := false; BYP_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C; - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive := 1; - VLAN_COMMON_CLK_G : boolean := false; - VLAN_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C; SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Master Clock and Reset - mClk : in sl; - mRst : in sl; + mClk : in sl; + mRst : in sl; -- Primary Interface - sPrimClk : in sl; - sPrimRst : in sl; - sPrimMaster : in AxiStreamMasterType; - sPrimSlave : out AxiStreamSlaveType; - mPrimMaster : out AxiStreamMasterType; - mPrimSlave : in AxiStreamSlaveType; + sPrimClk : in sl; + sPrimRst : in sl; + sPrimMaster : in AxiStreamMasterType; + sPrimSlave : out AxiStreamSlaveType; + mPrimMaster : out AxiStreamMasterType; + mPrimSlave : in AxiStreamSlaveType; -- Bypass interface - sBypClk : in sl; - sBypRst : in sl; - sBypMaster : in AxiStreamMasterType; - sBypSlave : out AxiStreamSlaveType; - mBypMaster : out AxiStreamMasterType; - mBypSlave : in AxiStreamSlaveType; - -- VLAN Interfaces - sVlanClk : in sl; - sVlanRst : in sl; - sVlanMasters : in AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - sVlanSlaves : out AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0); - mVlanMasters : out AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - mVlanSlaves : in AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0)); + sBypClk : in sl; + sBypRst : in sl; + sBypMaster : in AxiStreamMasterType; + sBypSlave : out AxiStreamSlaveType; + mBypMaster : out AxiStreamMasterType; + mBypSlave : in AxiStreamSlaveType); end EthMacTxFifo; architecture mapping of EthMacTxFifo is @@ -142,47 +130,4 @@ begin end generate; - VLAN_DISABLED : if (VLAN_EN_G = false) generate - sVlanSlaves <= (others => AXI_STREAM_SLAVE_FORCE_C); - mVlanMasters <= (others => AXI_STREAM_MASTER_INIT_C); - end generate; - - VLAN_ENABLED : if (VLAN_EN_G = true) generate - VLAN_FIFO_BYPASS : if ((VLAN_COMMON_CLK_G = true) and (VLAN_CONFIG_G = INT_EMAC_AXIS_CONFIG_C)) generate - mVlanMasters <= sVlanMasters; - sVlanSlaves <= mVlanSlaves; - end generate; - - VLAN_FIFO : if ((VLAN_COMMON_CLK_G = false) or (VLAN_CONFIG_G /= INT_EMAC_AXIS_CONFIG_C)) generate - GEN_VEC : for i in (VLAN_SIZE_G-1) downto 0 generate - U_Fifo : entity surf.AxiStreamFifoV2 - generic map ( - -- General Configurations - TPD_G => TPD_G, - INT_PIPE_STAGES_G => 0, - PIPE_STAGES_G => 1, - SLAVE_READY_EN_G => true, - VALID_THOLD_G => 1, - -- FIFO configurations - SYNTH_MODE_G => SYNTH_MODE_G, - MEMORY_TYPE_G => "distributed", - GEN_SYNC_FIFO_G => VLAN_COMMON_CLK_G, - CASCADE_SIZE_G => 1, - FIFO_ADDR_WIDTH_G => 4, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => VLAN_CONFIG_G, - MASTER_AXI_CONFIG_G => INT_EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => sVlanClk, - sAxisRst => sVlanRst, - sAxisMaster => sVlanMasters(i), - sAxisSlave => sVlanSlaves(i), - mAxisClk => mClk, - mAxisRst => mRst, - mAxisMaster => mVlanMasters(i), - mAxisSlave => mVlanSlaves(i)); - end generate GEN_VEC; - end generate; - end generate; - end mapping; diff --git a/ethernet/EthMacCore/rtl/EthMacTxPause.vhd b/ethernet/EthMacCore/rtl/EthMacTxPause.vhd index 915cd3b1ee..a007c4d1d7 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxPause.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxPause.vhd @@ -19,7 +19,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.AxiStreamPkg.all; use surf.StdRtlPkg.all; @@ -29,9 +28,7 @@ entity EthMacTxPause is generic ( TPD_G : time := 1 ns; PAUSE_EN_G : boolean := true; - PAUSE_512BITS_G : natural range 1 to 1024 := 8; - VLAN_EN_G : boolean := false; - VLAN_SIZE_G : positive range 1 to 8 := 1); + PAUSE_512BITS_G : natural range 1 to 1024 := 8); port ( -- Clock and Reset ethClk : in sl; @@ -39,8 +36,6 @@ entity EthMacTxPause is -- Incoming data from client sAxisMaster : in AxiStreamMasterType; sAxisSlave : out AxiStreamSlaveType; - sAxisMasters : in AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0); - sAxisSlaves : out AxiStreamSlaveArray(VLAN_SIZE_G-1 downto 0); -- Outgoing data to MAC mAxisMaster : out AxiStreamMasterType; mAxisSlave : in AxiStreamSlaveType; @@ -60,7 +55,6 @@ end EthMacTxPause; architecture rtl of EthMacTxPause is constant CNT_BITS_C : integer := bitSize(PAUSE_512BITS_G-1); - constant SIZE_C : natural := ite(VLAN_EN_G, (VLAN_SIZE_G+1), 1); type StateType is ( IDLE_S, @@ -75,7 +69,7 @@ architecture rtl of EthMacTxPause is remPreCnt : slv(CNT_BITS_C-1 downto 0); pauseTx : sl; mAxisMaster : AxiStreamMasterType; - rxSlave : AxiStreamSlaveType; + sAxisSlave : AxiStreamSlaveType; state : StateType; end record RegType; @@ -87,71 +81,29 @@ architecture rtl of EthMacTxPause is remPreCnt => (others => '0'), pauseTx => '0', mAxisMaster => AXI_STREAM_MASTER_INIT_C, - rxSlave => AXI_STREAM_SLAVE_INIT_C, + sAxisSlave => AXI_STREAM_SLAVE_INIT_C, state => IDLE_S); signal r : RegType := REG_INIT_C; signal rin : RegType; - signal rxMasters : AxiStreamMasterArray(SIZE_C-1 downto 0); - signal rxSlaves : AxiStreamSlaveArray(SIZE_C-1 downto 0); - - signal rxMaster : AxiStreamMasterType; - signal rxSlave : AxiStreamSlaveType; - -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "true"; begin - rxMasters(0) <= sAxisMaster; - sAxisSlave <= rxSlaves(0); - - U_NoVlanGen : if (VLAN_EN_G = false) generate - - rxMaster <= rxMasters(0); - rxSlaves(0) <= rxSlave; - sAxisSlaves <= (others => AXI_STREAM_SLAVE_FORCE_C); - - end generate; - - U_VlanGen : if (VLAN_EN_G = true) generate - - GEN_VEC : - for i in (VLAN_SIZE_G-1) downto 0 generate - rxMasters(i+1) <= sAxisMasters(i); - sAxisSlaves(i) <= rxSlaves(i+1); - end generate GEN_VEC; - - U_AxiStreamMux : entity surf.AxiStreamMux - generic map ( - TPD_G => TPD_G, - NUM_SLAVES_G => SIZE_C) - port map ( - -- Clock and reset - axisClk => ethClk, - axisRst => ethRst, - -- Slaves - sAxisMasters => rxMasters, - sAxisSlaves => rxSlaves, - -- Master - mAxisMaster => rxMaster, - mAxisSlave => rxSlave); - - end generate; - U_TxPauseGen : if (PAUSE_EN_G = true) generate comb : process (clientPause, ethRst, mAxisSlave, pauseEnable, pauseTime, - phyReady, r, rxMaster, rxPauseReq, rxPauseValue) is + phyReady, r, rxPauseReq, rxPauseValue, sAxisMaster) is variable v : RegType; begin -- Latch the current value v := r; -- Reset the flags - v.pauseTx := '0'; - v.rxSlave := AXI_STREAM_SLAVE_INIT_C; + v.pauseTx := '0'; + v.sAxisSlave := AXI_STREAM_SLAVE_INIT_C; if (mAxisSlave.tReady = '1') then v.mAxisMaster.tValid := '0'; end if; @@ -184,7 +136,7 @@ begin -- Next state v.state := PAUSE_S; -- Transmit required and not paused by received pause count - elsif (rxMaster.tValid = '1') and (r.locPauseCnt = 0) then + elsif (sAxisMaster.tValid = '1') and (r.locPauseCnt = 0) then -- Next state v.state := PASS_S; end if; @@ -240,13 +192,13 @@ begin ---------------------------------------------------------------------- when PASS_S => -- Check if ready to move data - if (v.mAxisMaster.tValid = '0') and (rxMaster.tValid = '1') then + if (v.mAxisMaster.tValid = '0') and (sAxisMaster.tValid = '1') then -- Accept the data - v.rxSlave.tReady := '1'; + v.sAxisSlave.tReady := '1'; -- Move the data - v.mAxisMaster := rxMaster; + v.mAxisMaster := sAxisMaster; -- Check for EOF - if (rxMaster.tLast = '1') then + if (sAxisMaster.tLast = '1') then -- Next state v.state := IDLE_S; end if; @@ -255,7 +207,7 @@ begin end case; -- Combinatorial outputs before the reset - rxSlave <= v.rxSlave; + sAxisSlave <= v.sAxisSlave; -- Reset if (ethRst = '1') then @@ -281,8 +233,8 @@ begin end generate; U_BypTxPause : if (PAUSE_EN_G = false) generate - mAxisMaster <= rxMaster; - rxSlave <= mAxisSlave; + mAxisMaster <= sAxisMaster; + sAxisSlave <= mAxisSlave; pauseTx <= '0'; end generate;