From a6012a435c2d638c489410c72cb27d270fd15866 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 11 Jul 2024 12:17:56 -0700 Subject: [PATCH] bug fix when using ultrascale+ FPGAs --- protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd b/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd index 78defb56d1..39e48f835f 100644 --- a/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd +++ b/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd @@ -42,8 +42,8 @@ end UdpDebugBridgeWrapper; architecture rtl of UdpDebugBridgeWrapper is component UdpDebugBridge is - generic ( - AXIS_CLK_FREQ_G : real); +-- generic ( +-- AXIS_CLK_FREQ_G : real); port ( axisClk : in std_logic; axisRst : in std_logic; @@ -81,6 +81,10 @@ architecture rtl of UdpDebugBridgeWrapper is begin + assert (AXIS_CLK_FREQ_G = 156.25E+6) + report "AXIS_CLK_FREQ_G: Must be 156.25E+6" + severity error; + ---------------------------- -- 'XVC' Server @2542 (modified protocol to work over UDP) ---------------------------- @@ -115,8 +119,8 @@ begin end process P_SOF_SPLICE; U_XvcServer : component UdpDebugBridge - generic map ( - AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) +-- generic map ( +-- AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) port map ( axisClk => clk, axisRst => rst,