diff --git a/protocols/pgp/shared/PgpXvcWrapper.vhd b/protocols/pgp/shared/PgpXvcWrapper.vhd new file mode 100644 index 0000000000..2b4a8e54a5 --- /dev/null +++ b/protocols/pgp/shared/PgpXvcWrapper.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: XVC Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity PgpXvcWrapper is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + AXIS_CLK_FREQ_G : real := 156.25e6; + PHY_AXI_CONFIG_G : AxiStreamConfigType); + port ( + -- Clock and Reset (xvcClk domain) + xvcClk : in sl; + xvcRst : in sl; + -- Clock and Reset (pgpClk domain) + pgpClk : in sl; + pgpRst : in sl; + -- PGP Interface (pgpClk domain) + rxlinkReady : in sl; + txlinkReady : in sl; + -- TX FIFO (pgpClk domain) + pgpTxSlave : in AxiStreamSlaveType; + pgpTxMaster : out AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + -- RX FIFO (pgpClk domain) + pgpRxMaster : in AxiStreamMasterType; + pgpRxCtrl : out AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C); +end PgpXvcWrapper; + +architecture rtl of PgpXvcWrapper is + + signal ibXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); + signal ibXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal obXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); + signal obXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + GEN_REAL : if (SIMULATION_G = false) generate + + ----------------------------------------------------------------- + -- Xilinx Virtual Cable (XVC) + -- https://www.xilinx.com/products/intellectual-property/xvc.html + ----------------------------------------------------------------- + U_XVC : entity surf.UdpDebugBridgeWrapper + generic map ( + TPD_G => TPD_G, + AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) + port map ( + -- Clock and Reset + clk => xvcClk, + rst => xvcRst, + -- UDP XVC Interface + obServerMaster => ibXvcMaster, + obServerSlave => ibXvcSlave, + ibServerMaster => obXvcMaster, + ibServerSlave => obXvcSlave); + + U_VC_RX : entity surf.PgpRxVcFifo + generic map ( + TPD_G => TPD_G, + PHY_AXI_CONFIG_G => PHY_AXI_CONFIG_G, + APP_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) + port map ( + -- PGP Interface (pgpClk domain) + pgpClk => pgpClk, + pgpRst => pgpRst, + rxlinkReady => rxlinkReady, + pgpRxMaster => pgpRxMaster, + pgpRxCtrl => pgpRxCtrl, + pgpRxSlave => pgpRxSlave, + -- AXIS Interface (axisClk domain) + axisClk => xvcClk, + axisRst => xvcRst, + axisMaster => ibXvcMaster, + axisSlave => ibXvcSlave); + + U_VC_TX : entity surf.PgpTxVcFifo + generic map ( + TPD_G => TPD_G, + APP_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, + PHY_AXI_CONFIG_G => PHY_AXI_CONFIG_G) + port map ( + -- AXIS Interface (axisClk domain) + axisClk => xvcClk, + axisRst => xvcRst, + axisMaster => obXvcMaster, + axisSlave => obXvcSlave, + -- PGP Interface (pgpClk domain) + pgpClk => pgpClk, + pgpRst => pgpRst, + rxlinkReady => rxlinkReady, + txlinkReady => txlinkReady, + pgpTxMaster => pgpTxMaster, + pgpTxSlave => pgpTxSlave); + + end generate GEN_REAL; + +end rtl; diff --git a/protocols/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd b/protocols/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd index 8a3df7465d..8ceb5da408 100644 --- a/protocols/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd +++ b/protocols/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd @@ -25,6 +25,8 @@ use surf.AxiStreamPkg.all; use surf.UdpDebugBridgePkg.all; entity UdpDebugBridge is + generic ( + AXIS_CLK_FREQ_G : real := 156.25e6); port ( axisClk : in sl; axisRst : in sl; @@ -38,11 +40,14 @@ entity UdpDebugBridge is end entity UdpDebugBridge; architecture UdpDebugBridgeImpl of UdpDebugBridge is + + constant XVC_TCLK_DIV2_C : positive := positive( ieee.math_real.round( AXIS_CLK_FREQ_G/XVC_TCLK_FREQ_C/2.0 ) ); + begin U_AxisJtagDebugBridge : entity surf.AxisJtagDebugBridge(AxisJtagDebugBridgeImpl) generic map ( - AXIS_FREQ_G => XVC_ACLK_FREQ_C, + AXIS_FREQ_G => AXIS_CLK_FREQ_G, CLK_DIV2_G => XVC_TCLK_DIV2_C, AXIS_WIDTH_G => XVC_AXIS_WIDTH_C, MEM_DEPTH_G => XVC_MEM_DEPTH_C, diff --git a/protocols/xvc-udp/dcp/core/UdpDebugBridgePkg.vhd b/protocols/xvc-udp/dcp/core/UdpDebugBridgePkg.vhd index 91a52e245f..b5e0457ad3 100644 --- a/protocols/xvc-udp/dcp/core/UdpDebugBridgePkg.vhd +++ b/protocols/xvc-udp/dcp/core/UdpDebugBridgePkg.vhd @@ -37,8 +37,6 @@ package UdpDebugBridgePkg is constant XVC_MEM_SIZE_C : natural := 1450/2; -- non-jumbo MTU; mem must hold max. reply = max request/2 constant XVC_TCLK_FREQ_C : real := 15.0E+6; - constant XVC_ACLK_FREQ_C : real := 156.25E+6; - constant XVC_TCLK_DIV2_C : positive := positive( ieee.math_real.round( XVC_ACLK_FREQ_C/XVC_TCLK_FREQ_C/2.0 ) ); constant XVC_AXIS_WIDTH_C : positive range 4 to 16 := EMAC_AXIS_CONFIG_C.TDATA_BYTES_C; constant XVC_MEM_DEPTH_C : natural range 0 to 65535 := XVC_MEM_SIZE_C/XVC_AXIS_WIDTH_C; diff --git a/protocols/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd b/protocols/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd index 4c7808a2e2..7863d22d1c 100644 --- a/protocols/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd +++ b/protocols/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd @@ -25,6 +25,8 @@ use surf.AxiStreamPkg.all; use surf.UdpDebugBridgePkg.all; entity UdpDebugBridge is + generic ( + AXIS_CLK_FREQ_G : real := 156.25e6); port ( axisClk : in sl; axisRst : in sl; @@ -38,11 +40,14 @@ entity UdpDebugBridge is end entity UdpDebugBridge; architecture UdpDebugBridgeImpl of UdpDebugBridge is + + constant XVC_TCLK_DIV2_C : positive := positive( ieee.math_real.round( AXIS_CLK_FREQ_G/XVC_TCLK_FREQ_C/2.0 ) ); + begin U_AxisJtagDebugBridge : entity surf.AxisJtagDebugBridge(AxisJtagDebugBridgeStub) generic map ( - AXIS_FREQ_G => XVC_ACLK_FREQ_C, + AXIS_FREQ_G => AXIS_CLK_FREQ_C, CLK_DIV2_G => XVC_TCLK_DIV2_C, AXIS_WIDTH_G => XVC_AXIS_WIDTH_C, MEM_DEPTH_G => XVC_MEM_DEPTH_C, diff --git a/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd b/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd new file mode 100644 index 0000000000..2f00b291c5 --- /dev/null +++ b/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd @@ -0,0 +1,136 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: XVC Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity DmaXvcWrapper is + generic ( + TPD_G : time := 1 ns; + COMMON_CLOCK_G : boolean := false; + AXIS_CLK_FREQ_G : real := 156.25e6; + FIFO_INT_PIPE_STAGES_G : natural range 0 to 16 := 0; -- Internal FIFO setting + FIFO_PIPE_STAGES_G : natural range 0 to 16 := 1; + OB_FIFO_SLAVE_READY_EN_G : boolean := true; + FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9; + FIFO_SYNTH_MODE_G : string := "inferred"; + FIFO_MEMORY_TYPE_G : string := "block"; + AXIS_CONFIG_G : AxiStreamConfigType); + port ( + -- Clock and Reset (xvcClk domain) + xvcClk : in sl; + xvcRst : in sl; + -- Clock and Reset (axisClk domain) + axisClk : in sl; + axisRst : in sl; + -- OB FIFO (axisClk domain) + obFifoMaster : in AxiStreamMasterType; + obFifoSlave : out AxiStreamSlaveType; + obFifoCtrl : out AxiStreamCtrlType; + -- IB FIFO (axisClk domain) + ibFifoSlave : in AxiStreamSlaveType; + ibFifoMaster : out AxiStreamMasterType); +end DmaXvcWrapper; + +architecture rtl of DmaXvcWrapper is + + signal ibXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); + signal ibXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal obXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); + signal obXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + ----------------------------------------------------------------- + -- Xilinx Virtual Cable (XVC) + -- https://www.xilinx.com/products/intellectual-property/xvc.html + ----------------------------------------------------------------- + U_XVC : entity surf.UdpDebugBridgeWrapper + generic map ( + TPD_G => TPD_G, + AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) + port map ( + -- Clock and Reset + clk => xvcClk, + rst => xvcRst, + -- UDP XVC Interface + obServerMaster => obXvcMaster, + obServerSlave => obXvcSlave, + ibServerMaster => ibXvcMaster, + ibServerSlave => ibXvcSlave); + + U_OB_FIFO : entity surf.AxiStreamFifoV2 + generic map ( + -- General Configurations + TPD_G => TPD_G, + -- FIFO configurations + INT_PIPE_STAGES_G => FIFO_INT_PIPE_STAGES_G, + PIPE_STAGES_G => FIFO_PIPE_STAGES_G, + SLAVE_READY_EN_G => OB_FIFO_SLAVE_READY_EN_G, + GEN_SYNC_FIFO_G => COMMON_CLOCK_G, + MEMORY_TYPE_G => FIFO_MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + SYNTH_MODE_G => FIFO_SYNTH_MODE_G, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => AXIS_CONFIG_G, + MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) + port map ( + -- Slave Port + sAxisClk => axisClk, + sAxisRst => axisRst, + sAxisMaster => obFifoMaster, + sAxisSlave => obFifoSlave, + sAxisCtrl => obFifoCtrl, + -- Master Port + mAxisClk => xvcClk, + mAxisRst => xvcRst, + mAxisMaster => obXvcMaster, + mAxisSlave => obXvcSlave); + + U_IB_FIFO : entity surf.AxiStreamFifoV2 + generic map ( + -- General Configurations + TPD_G => TPD_G, + -- FIFO configurations + INT_PIPE_STAGES_G => FIFO_INT_PIPE_STAGES_G, + PIPE_STAGES_G => FIFO_PIPE_STAGES_G, + SLAVE_READY_EN_G => OB_FIFO_SLAVE_READY_EN_G, + GEN_SYNC_FIFO_G => COMMON_CLOCK_G, + MEMORY_TYPE_G => FIFO_MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + SYNTH_MODE_G => FIFO_SYNTH_MODE_G, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => AXIS_CONFIG_G) + port map ( + -- Slave Port + sAxisClk => xvcClk, + sAxisRst => xvcRst, + sAxisMaster => ibXvcMaster, + sAxisSlave => ibXvcSlave, + -- Master Port + mAxisClk => axisClk, + mAxisRst => axisRst, + mAxisMaster => ibFifoMaster, + mAxisSlave => ibFifoSlave); + +end rtl; diff --git a/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd b/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd index d7b87e300a..78defb56d1 100644 --- a/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd +++ b/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd @@ -26,7 +26,8 @@ use surf.EthMacPkg.all; entity UdpDebugBridgeWrapper is generic ( - TPD_G : time := 1 ns); + TPD_G : time := 1 ns; + AXIS_CLK_FREQ_G : real := 156.25e6); port ( -- Clock and Reset clk : in sl; @@ -41,6 +42,8 @@ end UdpDebugBridgeWrapper; architecture rtl of UdpDebugBridgeWrapper is component UdpDebugBridge is + generic ( + AXIS_CLK_FREQ_G : real); port ( axisClk : in std_logic; axisRst : in std_logic; @@ -112,6 +115,8 @@ begin end process P_SOF_SPLICE; U_XvcServer : component UdpDebugBridge + generic map ( + AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) port map ( axisClk => clk, axisRst => rst,