-
Notifications
You must be signed in to change notification settings - Fork 0
/
top_digital_tb.vhd
227 lines (211 loc) · 5.03 KB
/
top_digital_tb.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:01:30 11/30/2016
-- Design Name:
-- Module Name: C:/Documents and Settings/alumno/Mis documentos/VHDL2/VHDL2/top_digital_tb.vhd
-- Project Name: VHDL2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top_digital
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library STD;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
ENTITY top_digital_tb IS
END top_digital_tb;
ARCHITECTURE behavior OF top_digital_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_digital
PORT(
clk : IN std_logic;
Rst : IN std_logic;
Up0 : IN std_logic;
Down0 : IN std_logic;
Up1 : IN std_logic;
Down1 : IN std_logic;
sw : IN std_logic_vector(5 downto 0);
DOUT : IN std_logic;
Disp0 : OUT std_logic;
Disp1 : OUT std_logic;
Disp2 : OUT std_logic;
Disp3 : OUT std_logic;
Seg7 : OUT std_logic_vector(6 downto 0);
CS0 : OUT std_logic;
CS1 : OUT std_logic;
SCLK : OUT std_logic;
DIN : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal pulsadores : std_logic_vector(3 downto 0);
signal sw : std_logic_vector(5 downto 0) := (others => '0');
signal DOUT : std_logic := '0';
--Outputs
signal Disp0 : std_logic;
signal Disp1 : std_logic;
signal Disp2 : std_logic;
signal Disp3 : std_logic;
signal Seg7 : std_logic_vector(6 downto 0);
signal CS0 : std_logic;
signal CS1 : std_logic;
signal SCLK : std_logic;
signal DIN : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
-- constant Rst_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_digital PORT MAP (
clk => clk,
Rst => Rst,
Up0 => pulsadores(0),
Down0 => pulsadores(1),
Up1 => pulsadores(2),
Down1 => pulsadores(3),
sw => sw,
DOUT => DOUT,
Disp0 => Disp0,
Disp1 => Disp1,
Disp2 => Disp2,
Disp3 => Disp3,
Seg7 => Seg7,
CS0 => CS0,
CS1 => CS1,
SCLK => SCLK,
DIN => DIN
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- start_ADC process
pulsadores_process :process
begin
pulsadores <= "0000";
wait for 125us;
pulsadores <= "0100";
wait for 125us;
pulsadores <= "0000";
wait for 100ms;
pulsadores <= "0001";
wait for 125us;
pulsadores <= "0000";
wait for 100ms;
pulsadores <= "0000";
end process;
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
sw <= "001011";
rst<='1';
wait for 500 ns;
rst <='0';
wait for 143 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait for 2 us;
DOUT <='1';
wait for 2 us;
DOUT <='0';
wait;
end process;
END;