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While we try to make improvements and fixes to the VPI as we can I doubt we would change it in a way that breaks existing code. anytime soon. |
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I have a VPI module that acts as a bridge between VVP running a simulation and a larger simulation that contains it. That means that it acts very like a testbench written inside the VPI module. It is intended to be rather general, so contains no information about the Verilog source code.
To make that work, early on it must scan the ports of the top-level module and set up the means to send inputs and capture outputs. From the standard docs, the way to do that seems to be to call vpiHandle(vpiLowConn, port) to get access to the internal variable that represents the value on the port. Then force values or set callbacks on it.
But vpiLowConn is not implemented. Instead, I have this code, that works so far.
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My question, for anyone still reading: is this the best way to do it? If so, can it be expected to continue to work in future releases?
Thanks,
Giles
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