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It seems like memory model writers always use the most arcane features of verilog, and this issue seems to be related to a force/release of a wire. Commenting line 2024 (force DQ1 = 1'bX;) in N25Q128A11E_VG12/code/N25Qxxx.v makes it work. Haven't dug deep enough into the LRM to figure out if this is a issue with Icarus or if the model should be changed.
The text was updated successfully, but these errors were encountered:
I'm trying to simulate a Micron Flash memory model (https://www.micron.com/~/media/documents/products/sim-model/nor-flash/serial/bfm/n25q/n25q128a_micronxip_hold_18v_vg11,-d-,tar.gz). It works fine in ModelSim and Riviera Pro, but fails in Icarus (tried latest git head), as I only get 'x' on the MISO line (DQ1)
It seems like memory model writers always use the most arcane features of verilog, and this issue seems to be related to a force/release of a wire. Commenting line 2024 (
force DQ1 = 1'bX;
) inN25Q128A11E_VG12/code/N25Qxxx.v
makes it work. Haven't dug deep enough into the LRM to figure out if this is a issue with Icarus or if the model should be changed.The text was updated successfully, but these errors were encountered: