From ead4465279e13e19b24f4d78b372d4fad146a6ee Mon Sep 17 00:00:00 2001
From: Stafford Horne <shorne@gmail.com>
Date: Tue, 2 Apr 2019 14:06:01 +0900
Subject: [PATCH] or1k: fix up docs for new operations

---
 gcc/config/or1k/or1k.opt |  8 ++++++--
 gcc/doc/invoke.texi      | 15 +++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
index eb41f79785bde..9a7e1c8bae76e 100644
--- a/gcc/config/or1k/or1k.opt
+++ b/gcc/config/or1k/or1k.opt
@@ -29,14 +29,18 @@ mhard-mul
 Target RejectNegative InverseMask(SOFT_MUL).
 Use hardware multiply instructions, use -msoft-mul for emulation.
 
+msoft-float
+Target RejectNegative InverseMask(HARD_FLOAT)
+Use gcc provided software routines for floating point operations.
+
 mhard-float
-Target Mask(HARD_FLOAT)
+Target RejectNegative Mask(HARD_FLOAT)
 Use hardware floating point instructions.
 
 mdouble-float
 Target Mask(DOUBLE_FLOAT)
 Allows generation of binaries which support 64-bit doubles on 32-bit systems by
-soring doubles in register pairs.
+storing doubles in register pairs.
 
 mcmov
 Target RejectNegative Mask(CMOV)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1787967d75329..af06821c352a3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1028,6 +1028,7 @@ Objective-C and Objective-C++ Dialects}.
 @emph{OpenRISC Options}
 @gccoptlist{-mboard=@var{name}  -mnewlib  -mhard-mul  -mhard-div @gol
 -msoft-mul  -msoft-div @gol
+-msoft-float  -mhard-float  -mdouble-float @gol
 -mcmov  -mror  -msext  -msfimm  -mshftimm}
 
 @emph{PDP-11 Options}
@@ -23557,6 +23558,20 @@ default.
 Generate code for hardware which supports multiply instructions.  This is the
 default.
 
+@item -msoft-float
+@opindex msoft-float
+Generate code which uses library calls for floating point operations.  This is
+the default.
+
+@item -mhard-float
+@opindex mhard-float
+Generate code for hardware which supports floating point instructions.
+
+@item -mdouble-float
+@opindex mdouble-float
+Generate code for hardware which supports 64-bit floating point operations
+on 32-bit OpenRISC targets.
+
 @item -mcmov
 @opindex mcmov
 Generate code for hardware which supports the conditional move (@code{l.cmov})