-
Notifications
You must be signed in to change notification settings - Fork 1.2k
/
gdb-server.c
1896 lines (1527 loc) · 66.5 KB
/
gdb-server.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2011 Peter Zotov <whitequark@whitequark.org>
* Use of this source code is governed by a BSD-style license that can be found in the LICENSE file.
*/
#include <ctype.h>
#include <getopt.h>
#include <signal.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/types.h>
#if defined(_MSC_VER)
#include <stdbool.h>
#define __attribute__(x)
#endif
#if defined(_WIN32)
#include <win32_socket.h>
#else
#include <unistd.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#endif
#include <stlink.h>
#include <helper.h>
#include <logging.h>
#include "gdb-remote.h"
#include "gdb-server.h"
#include "semihosting.h"
#define FLASH_BASE 0x08000000
// Semihosting doesn't have a short option, we define a value to identify it
#define SEMIHOSTING_OPTION 128
#define SERIAL_OPTION 127
// always update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize
#define FLASH_PAGE (sl->flash_pgsz)
static stlink_t *connected_stlink = NULL;
static bool semihosting = false;
static bool serial_specified = false;
static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0};
#if defined(_WIN32)
#define close_socket win32_close_socket
#define IS_SOCK_VALID(__sock) ((__sock) != INVALID_SOCKET)
#else
#define close_socket close
#define SOCKET int
#define IS_SOCK_VALID(__sock) ((__sock) > 0)
#endif
static const char hex[] = "0123456789abcdef";
static const char* current_memory_map = NULL;
typedef struct _st_state_t {
// things from command line, bleh
int logging_level;
int listen_port;
int persistent;
enum connect_type connect_mode;
int freq;
} st_state_t;
int serve(stlink_t *sl, st_state_t *st);
char* make_memory_map(stlink_t *sl);
static void init_cache(stlink_t *sl);
static void _cleanup() {
if (connected_stlink) {
// Switch back to mass storage mode before closing
stlink_run(connected_stlink);
stlink_exit_debug_mode(connected_stlink);
stlink_close(connected_stlink);
}
}
static void cleanup(int signum) {
printf("Receive signal %i. Exiting...\n", signum);
_cleanup();
exit(1);
(void)signum;
}
#if defined(_WIN32)
BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) {
printf("Receive signal %i. Exiting...\r\n", (int)fdwCtrlType);
_cleanup();
return FALSE;
}
#endif
static stlink_t* do_connect(st_state_t *st) {
stlink_t *sl = NULL;
if (serial_specified) {
sl = stlink_open_usb(st->logging_level, st->connect_mode, serialnumber, st->freq);
} else {
sl = stlink_open_usb(st->logging_level, st->connect_mode, NULL, st->freq);
}
return(sl);
}
int parse_options(int argc, char** argv, st_state_t *st) {
static struct option long_options[] = {
{"help", no_argument, NULL, 'h'},
{"verbose", optional_argument, NULL, 'v'},
{"listen_port", required_argument, NULL, 'p'},
{"multi", optional_argument, NULL, 'm'},
{"no-reset", optional_argument, NULL, 'n'},
{"hot-plug", optional_argument, NULL, 'n'},
{"freq", optional_argument, NULL, 'F'},
{"version", no_argument, NULL, 'V'},
{"semihosting", no_argument, NULL, SEMIHOSTING_OPTION},
{"serial", required_argument, NULL, SERIAL_OPTION},
{0, 0, 0, 0},
};
const char * help_str = "%s - usage:\n\n"
" -h, --help\t\tPrint this help\n"
" -V, --version\t\tPrint the version\n"
" -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n"
" -v, --verbose\t\tSpecify generally verbose logging\n"
" -p 4242, --listen_port=1234\n"
"\t\t\tSet the gdb server listen port. "
"(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n"
" -m, --multi\n"
"\t\t\tSet gdb server to extended mode.\n"
"\t\t\tst-util will continue listening for connections after disconnect.\n"
" -n, --no-reset, --hot-plug\n"
"\t\t\tDo not reset board on connection.\n"
" -F 1800K, --freq=1M\n"
"\t\t\tSet the frequency of the SWD/JTAG interface.\n"
" --semihosting\n"
"\t\t\tEnable semihosting support.\n"
" --serial <serial>\n"
"\t\t\tUse a specific serial number.\n"
"\n"
"The STLINK device to use can be specified in the environment\n"
"variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.\n"
"\n"
;
int option_index = 0;
int c;
int q;
while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1)
switch (c) {
case 0:
break;
case 'h':
printf(help_str, argv[0]);
exit(EXIT_SUCCESS);
break;
case 'v':
if (optarg) {
st->logging_level = atoi(optarg);
} else {
st->logging_level = DEBUG_LOGGING_LEVEL;
}
break;
case 'p':
sscanf(optarg, "%i", &q);
if (q < 0) {
fprintf(stderr, "Can't use a negative port to listen on: %d\n", q);
exit(EXIT_FAILURE);
}
st->listen_port = q;
break;
case 'm':
st->persistent = 1;
break;
case 'n':
st->connect_mode = CONNECT_HOT_PLUG;
break;
case 'F':
st->freq = arg_parse_freq(optarg);
if (st->freq < 0) {
fprintf(stderr, "Can't parse a frequency: %s\n", optarg);
exit(EXIT_FAILURE);
}
break;
case 'V':
printf("v%s\n", STLINK_VERSION);
exit(EXIT_SUCCESS);
case SEMIHOSTING_OPTION:
semihosting = true;
break;
case SERIAL_OPTION:
printf("use serial %s\n", optarg);
memcpy(serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE);
serial_specified = true;
break;
}
if (optind < argc) {
printf("non-option ARGV-elements: ");
while (optind < argc) { printf("%s ", argv[optind++]); }
printf("\n");
}
return(0);
}
int main(int argc, char** argv) {
stlink_t *sl = NULL;
st_state_t state;
memset(&state, 0, sizeof(state));
// set defaults ...
state.logging_level = DEFAULT_LOGGING_LEVEL;
state.listen_port = DEFAULT_GDB_LISTEN_PORT;
state.connect_mode = CONNECT_NORMAL; // by default, reset board
parse_options(argc, argv, &state);
printf("st-util\n");
sl = do_connect(&state);
if (sl == NULL) { return(1); }
if (sl->chip_id == STLINK_CHIPID_UNKNOWN) {
ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id);
return(1);
}
connected_stlink = sl;
#if defined(_WIN32)
SetConsoleCtrlHandler((PHANDLER_ROUTINE) CtrlHandler, TRUE);
#else
signal(SIGINT, &cleanup);
signal(SIGTERM, &cleanup);
signal(SIGSEGV, &cleanup);
#endif
if (state.connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); }
DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id);
sl->verbose = 0;
current_memory_map = make_memory_map(sl);
#if defined(_WIN32)
WSADATA wsadata;
if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; }
#endif
init_cache(sl);
do { // don't go beserk if serve() returns with error
if (serve(sl, &state)) { usleep (1 * 1000); }
sl = connected_stlink; // in case serve() changed the connection
stlink_run(sl); // continue
} while (state.persistent);
#if defined(_WIN32)
winsock_error:
WSACleanup();
#endif
// switch back to mass storage mode before closing
stlink_exit_debug_mode(sl);
stlink_close(sl);
return(0);
}
static const char* const target_description =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target version=\"1.0\">"
" <architecture>arm</architecture>"
" <feature name=\"org.gnu.gdb.arm.m-profile\">"
" <reg name=\"r0\" bitsize=\"32\"/>"
" <reg name=\"r1\" bitsize=\"32\"/>"
" <reg name=\"r2\" bitsize=\"32\"/>"
" <reg name=\"r3\" bitsize=\"32\"/>"
" <reg name=\"r4\" bitsize=\"32\"/>"
" <reg name=\"r5\" bitsize=\"32\"/>"
" <reg name=\"r6\" bitsize=\"32\"/>"
" <reg name=\"r7\" bitsize=\"32\"/>"
" <reg name=\"r8\" bitsize=\"32\"/>"
" <reg name=\"r9\" bitsize=\"32\"/>"
" <reg name=\"r10\" bitsize=\"32\"/>"
" <reg name=\"r11\" bitsize=\"32\"/>"
" <reg name=\"r12\" bitsize=\"32\"/>"
" <reg name=\"sp\" bitsize=\"32\" type=\"data_ptr\"/>"
" <reg name=\"lr\" bitsize=\"32\"/>"
" <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\"/>"
" <reg name=\"xpsr\" bitsize=\"32\" regnum=\"25\"/>"
" <reg name=\"msp\" bitsize=\"32\" regnum=\"26\" type=\"data_ptr\" group=\"general\" />"
" <reg name=\"psp\" bitsize=\"32\" regnum=\"27\" type=\"data_ptr\" group=\"general\" />"
" <reg name=\"control\" bitsize=\"8\" regnum=\"28\" type=\"int\" group=\"general\" />"
" <reg name=\"faultmask\" bitsize=\"8\" regnum=\"29\" type=\"int\" group=\"general\" />"
" <reg name=\"basepri\" bitsize=\"8\" regnum=\"30\" type=\"int\" group=\"general\" />"
" <reg name=\"primask\" bitsize=\"8\" regnum=\"31\" type=\"int\" group=\"general\" />"
" <reg name=\"s0\" bitsize=\"32\" regnum=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s1\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s2\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s3\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s4\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s5\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s6\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s7\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s8\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s9\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s10\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s11\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s12\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s13\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s14\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s15\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s16\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s17\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s18\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s19\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s20\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s21\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s22\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s23\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s24\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s25\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s26\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s27\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s28\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s29\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s30\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"s31\" bitsize=\"32\" type=\"float\" group=\"float\" />"
" <reg name=\"fpscr\" bitsize=\"32\" type=\"int\" group=\"float\" />"
" </feature>"
"</target>";
static const char* const memory_map_template_F4 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x20000\"/>" // sram
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" // Sectors 0..3
" <property name=\"blocksize\">0x4000</property>" // 16kB
" </memory>"
" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" // Sector 4
" <property name=\"blocksize\">0x10000</property>" // 64kB
" </memory>"
" <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" // Sectors 5..11
" <property name=\"blocksize\">0x20000</property>" // 128kB
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_F4_HD =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x40000\"/>" // sram
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x10000000\"/>" // fmc bank 1 (nor/psram/sram)
" <memory type=\"ram\" start=\"0x70000000\" length=\"0x20000000\"/>" // fmc bank 2 & 3 (nand flash)
" <memory type=\"ram\" start=\"0x90000000\" length=\"0x10000000\"/>" // fmc bank 4 (pc card)
" <memory type=\"ram\" start=\"0xC0000000\" length=\"0x20000000\"/>" // fmc sdram bank 1 & 2
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" // Sectors 0..3
" <property name=\"blocksize\">0x4000</property>" // 16kB
" </memory>"
" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" // Sector 4
" <property name=\"blocksize\">0x10000</property>" // 64kB
" </memory>"
" <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" // Sectors 5..11
" <property name=\"blocksize\">0x20000</property>" // 128kB
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_F2 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" // Sectors 0..3
" <property name=\"blocksize\">0x4000</property>" // 16kB
" </memory>"
" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" // Sector 4
" <property name=\"blocksize\">0x10000</property>" // 64kB
" </memory>"
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x%x\">" // Sectors 5..
" <property name=\"blocksize\">0x20000</property>" // 128kB
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x%08x\" length=\"0x%x\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_L4 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x8000\"/>" // SRAM2 (32kB)
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x18000\"/>" // SRAM1 (96kB)
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
" <property name=\"blocksize\">0x800</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7000\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x10\"/>" // option byte area
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_L496 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // SRAM2 (64kB)
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x50000\"/>" // SRAM1 + aliased SRAM2 (256 + 64 = 320kB)
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
" <property name=\"blocksize\">0x800</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7000\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x10\"/>" // option byte area
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram 8kB
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
" <property name=\"blocksize\">0x%x</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x%08x\" length=\"0x%x\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_F7 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"ram\" start=\"0x00000000\" length=\"0x4000\"/>" // ITCM ram 16kB
" <memory type=\"rom\" start=\"0x00200000\" length=\"0x100000\"/>" // ITCM flash
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // Sectors 0..3
" <property name=\"blocksize\">0x8000</property>" // 32kB
" </memory>"
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x20000\">" // Sector 4
" <property name=\"blocksize\">0x20000</property>" // 128kB
" </memory>"
" <memory type=\"flash\" start=\"0x08040000\" length=\"0xC0000\">" // Sectors 5..7
" <property name=\"blocksize\">0x40000</property>" // 128kB
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x00100000\" length=\"0xEDC0\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x20\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_H7 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x10000\"/>" // ITCMRAM 64kB
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x20000\"/>" // DTCMRAM 128kB
" <memory type=\"ram\" start=\"0x24000000\" length=\"0x80000\"/>" // RAM D1 512kB
" <memory type=\"ram\" start=\"0x30000000\" length=\"0x48000\"/>" // RAM D2 288kB
" <memory type=\"ram\" start=\"0x38000000\" length=\"0x10000\"/>" // RAM D3 64kB
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
" <property name=\"blocksize\">0x%x</property>"
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x1ff00000\" length=\"0x20000\"/>" // bootrom
"</memory-map>";
static const char* const memory_map_template_F4_DE =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x80000\"/>" // code = sram, bootrom or flash; flash is bigger
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x18000\"/>" // sram
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" // Sectors 0..3
" <property name=\"blocksize\">0x4000</property>" // 16kB
" </memory>"
" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" // Sector 4
" <property name=\"blocksize\">0x10000</property>" // 64kB
" </memory>"
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x60000\">" // Sectors 5..7
" <property name=\"blocksize\">0x20000</property>" // 128kB
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x210\"/>" // otp
" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
"</memory-map>";
char* make_memory_map(stlink_t *sl) {
// this will be freed in serve()
const size_t sz = 4096;
char* map = malloc(sz);
map[0] = '\0';
if (sl->chip_id == STLINK_CHIPID_STM32_F4 ||
sl->chip_id == STLINK_CHIPID_STM32_F446 ||
sl->chip_id == STLINK_CHIPID_STM32_F411RE) {
strcpy(map, memory_map_template_F4);
} else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) {
strcpy(map, memory_map_template_F4_DE);
} else if (sl->core_id == STM32F7_CORE_ID) {
snprintf(map, sz, memory_map_template_F7,
(unsigned int)sl->sram_size);
} else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) {
snprintf(map, sz, memory_map_template_H7,
(unsigned int)sl->flash_size,
(unsigned int)sl->flash_pgsz);
} else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) {
strcpy(map, memory_map_template_F4_HD);
} else if (sl->chip_id == STLINK_CHIPID_STM32_F2) {
snprintf(map, sz, memory_map_template_F2,
(unsigned int)sl->flash_size,
(unsigned int)sl->sram_size,
(unsigned int)sl->flash_size - 0x20000,
(unsigned int)sl->sys_base,
(unsigned int)sl->sys_size);
} else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
(sl->chip_id == STLINK_CHIPID_STM32_L43X) ||
(sl->chip_id == STLINK_CHIPID_STM32_L46X)) {
snprintf(map, sz, memory_map_template_L4,
(unsigned int)sl->flash_size,
(unsigned int)sl->flash_size);
} else if (sl->chip_id == STLINK_CHIPID_STM32_L496X) {
snprintf(map, sz, memory_map_template_L496,
(unsigned int)sl->flash_size,
(unsigned int)sl->flash_size);
} else {
snprintf(map, sz, memory_map_template,
(unsigned int)sl->flash_size,
(unsigned int)sl->sram_size,
(unsigned int)sl->flash_size,
(unsigned int)sl->flash_pgsz,
(unsigned int)sl->sys_base,
(unsigned int)sl->sys_size);
}
return(map);
}
#define DATA_WATCH_NUM 4
enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 };
struct code_hw_watchpoint {
stm32_addr_t addr;
uint8_t mask;
enum watchfun fun;
};
static struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
static void init_data_watchpoints(stlink_t *sl) {
uint32_t data;
DLOG("init watchpoints\n");
// set TRCENA in debug command to turn on DWT unit
stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data);
data |= STLINK_REG_CM3_DEMCR_TRCENA;
stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data);
// make sure all watchpoints are cleared
for (int i = 0; i < DATA_WATCH_NUM; i++) {
data_watches[i].fun = WATCHDISABLED;
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0);
}
}
static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) {
int i = 0;
uint32_t mask, dummy;
// computer mask
// find a free watchpoint
// configure
mask = -1;
i = len;
while (i) {
i >>= 1;
mask++;
}
if ((mask != (uint32_t)-1) && (mask < 16)) {
for (i = 0; i < DATA_WATCH_NUM; i++)
// is this an empty slot ?
if (data_watches[i].fun == WATCHDISABLED) {
DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len);
data_watches[i].fun = wf;
data_watches[i].addr = addr;
data_watches[i].mask = mask;
// insert comparator address
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_COMPn(i), addr);
// insert mask
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_MASKn(i), mask);
// insert function
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), wf);
// just to make sure the matched bit is clear !
stlink_read_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), &dummy);
return(0);
}
}
DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len);
return(-1);
}
static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) {
int i;
for (i = 0; i < DATA_WATCH_NUM; i++) {
if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) {
DLOG("delete watchpoint %d addr %x\n", i, addr);
data_watches[i].fun = WATCHDISABLED;
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0);
return(0);
}
}
DLOG("failure: delete watchpoint addr %x\n", addr);
return(-1);
}
static int code_break_num;
static int code_lit_num;
static int code_break_rev;
#define CODE_BREAK_NUM_MAX 15
#define CODE_BREAK_LOW 0x01
#define CODE_BREAK_HIGH 0x02
#define CODE_BREAK_REMAP 0x04
#define CODE_BREAK_REV_V1 0x00
#define CODE_BREAK_REV_V2 0x01
struct code_hw_breakpoint {
stm32_addr_t addr;
int type;
};
static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
static void init_code_breakpoints(stlink_t *sl) {
unsigned int val;
memset(sl->q_buf, 0, 4);
stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */);
stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val);
code_break_num = ((val >> 4) & 0xf);
code_lit_num = ((val >> 8) & 0xf);
code_break_rev = ((val >> 28) & 0xf);
ILOG("Found %i hw breakpoint registers\n", code_break_num);
stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &val);
if (((val>>4) & 0xFFF) == 0xC27) {
// Cortex-M7 can have locked to write FP_* registers
// IHI0029D, p. 48, Lock Access Register
stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY);
}
for (int i = 0; i < code_break_num; i++) {
code_breaks[i].type = 0;
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0);
}
}
static int has_breakpoint(stm32_addr_t addr) {
for (int i = 0; i < code_break_num; i++)
if (code_breaks[i].addr == addr) { return(1); }
return(0);
}
static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
uint32_t mask;
int type;
stm32_addr_t fpb_addr;
if (addr & 1) {
ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
return(-1);
}
if (code_break_rev == CODE_BREAK_REV_V1) {
type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
fpb_addr = addr & 0x1FFFFFFC;
} else {
type = CODE_BREAK_REMAP;
fpb_addr = addr;
}
int id = -1;
for (int i = 0; i < code_break_num; i++)
if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) {
id = i;
break;
}
if (id == -1) {
if (set)
return(-1); // free slot not found
else
return(0); // breakpoint is already removed
}
struct code_hw_breakpoint* bp = &code_breaks[id];
bp->addr = fpb_addr;
if (set)
bp->type |= type;
else
bp->type &= ~type;
// DDI0403E, p. 759, FP_COMPn register description
mask = ((bp->type&0x03) << 30) | bp->addr | 1;
if (bp->type == 0) {
DLOG("clearing hw break %d\n", id);
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), 0);
} else {
DLOG("setting hw break %d at %08x (%d)\n", id, bp->addr, bp->type);
DLOG("reg %08x \n", mask);
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), mask);
}
return(0);
}
struct flash_block {
stm32_addr_t addr;
unsigned length;
uint8_t* data;
struct flash_block* next;
};
static struct flash_block* flash_root;
static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) {
if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) {
ELOG("flash_add_block: incorrect bounds\n");
return(-1);
}
stlink_calculate_pagesize(sl, addr);
if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) {
ELOG("flash_add_block: unaligned block\n");
return(-1);
}
struct flash_block* new = malloc(sizeof(struct flash_block));
new->next = flash_root;
new->addr = addr;
new->length = length;
new->data = malloc(length);
memset(new->data, stlink_get_erased_pattern(sl), length);
flash_root = new;
return(0);
}
static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) {
unsigned int fit_blocks = 0, fit_length = 0;
for (struct flash_block* fb = flash_root; fb; fb = fb->next) {
/*
* Block: ------X------Y--------
* Data: a-----b
* a--b
* a-----------b
* Block intersects with data, if:
* a < Y && b > x
*/
unsigned X = fb->addr, Y = fb->addr + fb->length;
unsigned a = addr, b = addr + length;
if (a < Y && b > X) {
// from start of the block
unsigned start = (a > X ? a : X) - X;
unsigned end = (b > Y ? Y : b) - X;
memcpy(fb->data + start, data, end - start);
fit_blocks++;
fit_length += end - start;
}
}
if (fit_blocks == 0) {
ELOG("Unfit data block %08x -> %04x\n", addr, length);
return(-1);
}
if (fit_length != length) {
WLOG("data block %08x -> %04x truncated to %04x\n", addr, length, fit_length);
WLOG("(this is not an error, just a GDB glitch)\n");
}
return(0);
}
static int flash_go(stlink_t *sl) {
int error = -1;
int ret;
flash_loader_t fl;
// some kinds of clock settings do not allow writing to flash.
stlink_reset(sl);
stlink_force_debug(sl);
// delay to ensure that STM32 HSI clock and others have started up fully
usleep(10000);
for (struct flash_block* fb = flash_root; fb; fb = fb->next) {
ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length);
for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) {
// update FLASH_PAGE
stlink_calculate_pagesize(sl, page);
ILOG("flash_erase: page %08x\n", page);
ret = stlink_erase_flash_page(sl, page);
if (ret) { goto error; }
}
}
ret = stlink_flashloader_start(sl, &fl);
if (ret) { goto error; }
for (struct flash_block* fb = flash_root; fb; fb = fb->next) {
ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) {
unsigned length = fb->length - (page - fb->addr);
// update FLASH_PAGE
stlink_calculate_pagesize(sl, page);
ILOG("flash_do: page %08x\n", page);
unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length;
ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len);
if (ret) { goto error; }
}
}
stlink_flashloader_stop(sl);
stlink_soft_reset(sl, 1 /* halt on reset */);
error = 0;
error:
for (struct flash_block* fb = flash_root, *next; fb; fb = next) {
next = fb->next;
free(fb->data);
free(fb);
}
flash_root = NULL;
return(error);
}
struct cache_level_desc {
unsigned int nsets;
unsigned int nways;
unsigned int log2_nways;
unsigned int width;
};
struct cache_desc_t {
unsigned used;
// minimal line size in bytes
unsigned int dminline;
unsigned int iminline;
// last level of unification (uniprocessor)
unsigned int louu;
struct cache_level_desc icache[7];
struct cache_level_desc dcache[7];
};
static struct cache_desc_t cache_desc;
// return the smallest R so that V <= (1 << R); not performance critical
static unsigned ceil_log2(unsigned v) {
unsigned res;
for (res = 0; (1U << res) < v; res++);
return(res);
}
static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) {
unsigned int ccsidr;
unsigned int log2_nsets;
stlink_read_debug32(sl, STLINK_REG_CM7_CCSIDR, &ccsidr);
desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
desc->log2_nways = ceil_log2 (desc->nways);
log2_nsets = ceil_log2 (desc->nsets);
desc->width = 4 + (ccsidr & 7) + log2_nsets;
ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n",
ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width);
}
static void init_cache (stlink_t *sl) {
unsigned int clidr;
unsigned int ccr;
unsigned int ctr;
int i;
// Check have cache
stlink_read_debug32(sl, STLINK_REG_CM7_CTR, &ctr);
if ((ctr >> 29) != 0x04) {
cache_desc.used = 0;
return;
} else
cache_desc.used = 1;
cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
cache_desc.iminline = 4 << (ctr & 0x0f);
stlink_read_debug32(sl, STLINK_REG_CM7_CLIDR, &clidr);
cache_desc.louu = (clidr >> 27) & 7;
stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr);
ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n",
clidr, ccr & STLINK_REG_CM7_CCR_IC ? "on" : "off", ccr & STLINK_REG_CM7_CCR_DC ? "on" : "off");
ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n",
(clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7);
ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr,
cache_desc.dminline, cache_desc.iminline);
for (i = 0; i < 7; i++) {