diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
index 0e09d989f..7cf5b4881 100644
--- a/include/stlink/chipid.h
+++ b/include/stlink/chipid.h
@@ -62,8 +62,9 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_F303_HIGH        = 0x446,
 	STLINK_CHIPID_STM32_L0_CAT5          = 0x447,
 	STLINK_CHIPID_STM32_F0_CAN           = 0x448,
-	STLINK_CHIPID_STM32_F7               = 0x449,
+	STLINK_CHIPID_STM32_F7               = 0x449,	/* This ID is found on the NucleoF746ZG board */
 	STLINK_CHIPID_STM32_F7XXXX           = 0x451,
+	STLINK_CHIPID_STM32_F72XXX           = 0x452,	/* This ID is found on the NucleoF722ZE board */
 	STLINK_CHIPID_STM32_L011             = 0x457,
 	STLINK_CHIPID_STM32_F410             = 0x458,
 	STLINK_CHIPID_STM32_F413             = 0x463
diff --git a/src/chipid.c b/src/chipid.c
index b81ff3544..7cf83218d 100644
--- a/src/chipid.c
+++ b/src/chipid.c
@@ -24,6 +24,17 @@ static const struct stlink_chipid_params devices[] = {
             .bootrom_base = 0x00100000,        // "System memory" starting address from DS Fig 18
             .bootrom_size = 0xEDC0             // "System memory" byte size in hex from DS Fig 18
         },
+        {
+            //RM0431 and DS document was used to find these paramaters
+            .chip_id = STLINK_CHIPID_STM32_F72XXX,
+            .description = "F72 device",
+            .flash_type = STLINK_FLASH_TYPE_F4,
+            .flash_size_reg = 0x1ff07a22,      // section 35.2
+            .flash_pagesize = 0x800,           // No flash pages
+            .sram_size = 0x40000,              // "SRAM" byte size in hex from DS Fig 24
+            .bootrom_base = 0x00100000,        // "System memory" starting address from DS Fig 24
+            .bootrom_size = 0xEDC0             // "System memory" byte size in hex from DS Fig 24
+        },
         { // table 2, PM0063
             .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM,
             .description = "F1 Medium-density device",