diff --git a/src/common.c b/src/common.c index 354075d8d..1457d640c 100644 --- a/src/common.c +++ b/src/common.c @@ -449,7 +449,7 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STLINK_CHIPID_STM32_L1_MD: case STLINK_CHIPID_STM32_L1_MD_PLUS: case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: - return (STM32L1_FLASH_REGS_ADDR); + return (STM32L_FLASH_REGS_ADDR); default: WLOG("Flash base use default L0 address\n"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 2f5ff1143..653c7bcec 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -503,7 +503,7 @@ static const char* const memory_map_template_H7 = " " // bootrom ""; -static const char* const memory_map_template_H72X3X = +static const char* const memory_map_template_H72x3x = "" "" @@ -583,8 +583,8 @@ char* make_memory_map(stlink_t *sl) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H72X) { - snprintf(map, sz, memory_map_template_H72X3X, + } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { + snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); } else {