From a70c994964d420dbb3684861ad8ee7c6b3c69382 Mon Sep 17 00:00:00 2001
From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com>
Date: Wed, 29 May 2024 22:48:25 +0200
Subject: [PATCH] Fixed flash_pagesize for STM32H7A chips

(Closes #1369)
---
 config/chips/H7Ax_H7Bx.chip   | 2 +-
 src/stlink-lib/common_flash.c | 4 ++--
 src/stlink-lib/flash_loader.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip
index 0f66d2c77..a0817b77d 100644
--- a/config/chips/H7Ax_H7Bx.chip
+++ b/config/chips/H7Ax_H7Bx.chip
@@ -5,7 +5,7 @@ ref_manual_id 0455
 chip_id 0x480                // STM32_CHIPID_H7Ax
 flash_type H7
 flash_size_reg 0x08fff80c
-flash_pagesize 0x2000        // 8 KB
+flash_pagesize 0x20000       // 128 KB
 sram_size 0x20000            // 128 KB "DTCM"
 bootrom_base 0x1ff00000
 bootrom_size 0x20000         // 128 KB
diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c
index 0446abdf4..d7f6a6e99 100644
--- a/src/stlink-lib/common_flash.c
+++ b/src/stlink-lib/common_flash.c
@@ -1250,9 +1250,9 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) {
 
     if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STM32_CHIPID_H7Ax) {
       // set parallelism
-      write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_1);
+      write_flash_cr_psiz(sl, 3 /* 64 bit */, BANK_1);
       if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
-        write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2);
+        write_flash_cr_psiz(sl, 3 /* 64 bit */, BANK_2);
       }
     }
 
diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c
index 34033a0f8..f3a400713 100644
--- a/src/stlink-lib/flash_loader.c
+++ b/src/stlink-lib/flash_loader.c
@@ -713,9 +713,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) {
     }
     if (sl->chip_id != STM32_CHIPID_H7Ax) {
       // set parallelism
-      write_flash_cr_psiz(sl, 3 /* 64bit */, BANK_1);
+      write_flash_cr_psiz(sl, 3 /* 64 bit */, BANK_1);
       if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
-        write_flash_cr_psiz(sl, 3 /* 64bit */, BANK_2);
+        write_flash_cr_psiz(sl, 3 /* 64 bit */, BANK_2);
       }
     }
   } else {