diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index eed78e4e2..ea7fdb9e2 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F03x +# Chip-ID file for STM32F03x device # -chip_id 0x444 -description F03x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1000 +dev_type STM32F03x +ref_manual_id 0091 +chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1000 // 4 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 1f2a2043e..3e702585b 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F04x +# Chip-ID file for STM32F04x device # -chip_id 0x445 -description F04x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1800 +dev_type STM32F04x +ref_manual_id 0091 +chip_id 0x445 // STLINK_CHIPID_STM32_F04 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1800 // 6 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index 787adb6bf..1a4f61386 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F05x +# Chip-ID file for STM32F05x device # -chip_id 0x440 -description F05x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 +dev_type STM32F05x +ref_manual_id 0091 +chip_id 0x440 // STLINK_CHIPID_STM32_F0 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index e893a5457..2a577b7b4 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F07x +# Chip-ID file for STM32F07x device # -chip_id 0x448 -description F07x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x4000 +dev_type STM32F07x +ref_manual_id 0091 +chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x4000 // 16 KB bootrom_base 0x1fffc800 -bootrom_size 0x3000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x3000 // 12 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 267a2612f..9f419893e 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F09x +# Chip-ID file for STM32F09x device # -chip_id 0x442 -description F09x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32F09x +ref_manual_id 0091 +chip_id 0x442 // STLINK_CHIPID_STM32_F09x +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 6282bc2ee..4c8bb0b8d 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,15 +1,15 @@ -# Chip-ID file for STM32F1xx CL device +# Chip-ID file for STM32F1xx Connectivity Line device # -dev_type STM32F1xx Connectivity Line device +dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fffb000 -bootrom_size 0x4800 +bootrom_size 0x4800 // 18 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 72ad9fa75..18757029a 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx high density device # -dev_type F1xx high density device +dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 8a3682755..8a8f5867d 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1 low density device # -dev_type STM32F1xx low density device +dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x2800 +flash_pagesize 0x400 // 1 KB +sram_size 0x2800 // 10 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index f3da99493..be492f54a 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx medium density device # -dev_type STM32F1xx medium density device +dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x5000 -bootrom_base 0x1ffff000 // Section 2.3.3 "Embedded Flash memory" -bootrom_size 0x800 +flash_pagesize 0x400 // 1 KB +sram_size 0x5000 // 20 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index f46945a94..f5ca6b023 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx high density Value Line device # -dev_type STM32F1xx Value Line high density device +dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x8000 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 2bff05b82..e79668c70 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STMF1xx Value Line medium & low density device # -dev_type STM32F1xx Value Line medium & low density device +dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x2000 // 0x1000 for low density devices +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 90264ce0f..d7d8cf2b7 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx XL density device # -dev_type STM32F1xx XL density device +dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD -flash_type 2 // STLINK_FLASH_TYPE_F1_XL +chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +flash_type 2 // STLINK_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x18000 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB bootrom_base 0x1fffe000 -bootrom_size 0x1800 +bootrom_size 0x1800 // 6 KB option_base 0x0 option_size 0x0 flags swo diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index ce2e9e698..67c225af5 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -1,14 +1,14 @@ -# Chip-ID file for STM32F2xx device (STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx) +# Chip-ID file for STM32F2xx device # -dev_type STM32F2xx device +dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STLINK_CHIPID_STM32_F2 flash_type 3 // STLINK_FLASH_TYPE_F4 flash_size_reg 0x1fff7a22 -flash_pagesize 0x20000 -sram_size 0x20000 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE -option_size 0x4 // 4 +option_size 0x4 // 4 B flags swo diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index 429c836b4..ee71dfe90 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F301/F302/F318 +# Chip-ID file for STM32F3xx device (F301x6/8, F302x6x8, F318x8) # -chip_id 0x439 -description F301/F302/F318 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F301_F302_F318 +ref_manual_id 0365 // also RM0366 +chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index ffd1491ff..64d0651f2 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F302/F303/F358 +# Chip-ID file for STM32F3xx device (F302xBxC, F303xB/C, F358) # -chip_id 0x422 -description F302/F303/F358 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F302_F303_358 +ref_manual_id 0365 // also RM0316 +chip_id 0x422 // STLINK_CHIPID_STM32_F3 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip new file mode 100644 index 000000000..eaf36b74c --- /dev/null +++ b/config/chips/F302_F303_F398_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F3xx high density device (F302xD/E, F303xD/E, F398xE) +# +dev_type STM32F302_F303_F398_HD +ref_manual_id 0365 // also RM0316 (Rev 5) +chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fffd800 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 5df2a9bbb..2ecdbfb71 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F303/F328/F334 +# Chip-ID file for STM32F3xx device (F303x6/8, F328, F334) # -chip_id 0x438 -description F303/F328/F334 -flash_type 1 -flash_pagesize 0x800 -sram_size 0x3000 +dev_type STM32F303_F328_F334 +ref_manual_id 0364 // also RM0316 +chip_id 0x438 // STLINK_CHIPID_STM32_F334 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip deleted file mode 100644 index 748c27cbc..000000000 --- a/config/chips/F303_high_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F303 high density -# -chip_id 0x446 -description F303 high density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 92201657d..1bd7ac421 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F37x +# Chip-ID file for STM32F37x device # -chip_id 0x432 -description F37x -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F37x +ref_manual_id 0313 +chip_id 0x432 // STLINK_CHIPID_STM32_F37x +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F401xB_C.chip b/config/chips/F401xB_C.chip deleted file mode 100644 index 09e998dba..000000000 --- a/config/chips/F401xB_C.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xB/C -# -chip_id 0x423 -description F401xB/C -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x10000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip new file mode 100644 index 000000000..fc93c2f1a --- /dev/null +++ b/config/chips/F401xB_xC.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xB/xC device +# +dev_type STM32F401xB_xC +ref_manual_id 0368 +chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F401xD_E.chip b/config/chips/F401xD_E.chip deleted file mode 100644 index 5b70d7d86..000000000 --- a/config/chips/F401xD_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xD/E -# -chip_id 0x433 -description F401xD/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x18000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip new file mode 100644 index 000000000..e31d5eace --- /dev/null +++ b/config/chips/F401xD_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xD/xE device +# +dev_type STM32F401xD_xE +ref_manual_id 0368 +chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x18000 // 96 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F410.chip b/config/chips/F410.chip index ae199d9c4..a8a7fbad0 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F410 +# Chip-ID file for STM32F410 device # -chip_id 0x458 -description F410 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x8000 +dev_type STM32F410 +ref_manual_id 0401 +chip_id 0x458 // STLINK_CHIPID_STM32_F410 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F411xC_E.chip b/config/chips/F411xC_E.chip deleted file mode 100644 index d344489c5..000000000 --- a/config/chips/F411xC_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F411xC/E -# -chip_id 0x431 -description F411xC/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip new file mode 100644 index 000000000..cf2cbd2c1 --- /dev/null +++ b/config/chips/F411xC_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F411xC/xE device +# +dev_type STM32F411xC_xE +ref_manual_id 0383 +chip_id 0x431 // STLINK_CHIPID_STM32_F411xx +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 3212a340c..4c866a3c5 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F412 +# Chip-ID file for STM32F412 device # -chip_id 0x441 -description F412 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F412 +ref_manual_id 0402 +chip_id 0x441 // STLINK_CHIPID_STM32_F412 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 647775eeb..81ca585f6 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F413/F423 +# Chip-ID file for STM32F413 / STM32F423 device # -chip_id 0x463 -description F413/F423 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x50000 +dev_type STM32F413_F423 +ref_manual_id 0430 // RM0430 (Rev 2) +chip_id 0x463 // STLINK_CHIPID_STM32_F413 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x50000 // 320 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 3184d0d4f..2ec8fb8e8 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F42x/F43x +# Chip-ID file for STM32F42x / STM32F43x device # -chip_id 0x419 -description F42x/F43x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F42x_F43x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 86cee6a56..8cebe358e 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F446 +# Chip-ID file for STM32F446 device # -chip_id 0x421 -description F446 -flash_type 3 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32F446 +ref_manual_id 0390 +chip_id 0x421 // STLINK_CHIPID_STM32_F446 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index ee5f6a5a7..2e4055f2c 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F46x/F47x +# Chip-ID file for STM32F46x / STM32F47x device # -chip_id 0x434 -description F46x/F47x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F46x_F47x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index b19e4a5b3..9313c8ae1 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F4x5/F4x7 +# Chip-ID file for STM32F4x5 / STM32F4x7 device # -chip_id 0x413 -description F4x5/F4x7 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x30000 +dev_type STM32F4x5_F4x7 +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x413 // STLINK_CHIPID_STM32_F4 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x30000 // 192 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x40023c14 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 2836040ac..37dcd1234 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F72x/F73x +# Chip-ID file for STM32F72x / STM32F73x device # -chip_id 0x452 -description F72x/F73x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32F72x_F73x +ref_manual_id 0431 +chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1ff07a22 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 0604b299d..96cc95217 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F74x/F75x +# Chip-ID file for STM32F74x / STM32F75x device # -chip_id 0x449 -description F74x/F75x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x50000 +dev_type STM32F74x_F75x +ref_manual_id 0385 +chip_id 0x449 // STLINK_CHIPID_STM32_F7 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x50000 // 320 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index 304c99191..a93aba2be 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F76x/F77x +# Chip-ID file for STM32F76x / STM32F77x device # -chip_id 0x451 -description F76x/F77x -flash_type 4 -flash_pagesize 0x800 -sram_size 0x80000 +dev_type STM32F76x_F77x +ref_manual_id 0410 +chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx +flash_type 4 // STLINK_FLASH_TYPE_F7 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x80000 // 512 KB bootrom_base 0x200000 -bootrom_size 0xedc0 -option_base 0x1fff0000 -option_size 0x20 -flags dualbank swo - +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE /* Used for reading back option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 */ +option_size 0x20 // 32 B +flags swo dualbank diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index 7c5a00c58..a21a9898f 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G03x/G04x +# Chip-ID file for STM32G030 / STM32G031 / STM32G041 device # -chip_id 0x466 -description G03x/G04x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x2000 +dev_type STM32G03x_G04x +ref_manual_id 0444 // also RM454 +chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 -bootrom_size 0x2000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x2000 // 8 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 45295ec6e..89af0825c 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G05x/G06x +# Chip-ID file for STM32G05x / STM32G06x device # -chip_id 0x456 -description G05x/G06x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G05x_G06x +ref_manual_id 0444 +chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 7bddcd82c..c54de398f 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G07x/G08x +# Chip-ID file for STM32G07x / STM32G08x device # -chip_id 0x460 -description G07x/G08x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G07x_G08x +ref_manual_id 0444 +chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 98e503569..d8e0eb042 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G0Bx/G0Cx +# Chip-ID file for STM32G0Bx / STM32G0Cx device # -chip_id 0x467 -description G0Bx/G0Cx -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G0Bx_G0Cx +ref_manual_id 0444 +chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags dualbank - diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 033f1dd80..455d65b8c 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G43x/G44x +# Chip-ID file for STM32G43x / STM32G44x device # -chip_id 0x468 -description G43x/G44x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32G43x_G44x +ref_manual_id 0440 +chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index fa331650f..250905c68 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G47x/G48x +# Chip-ID file for STM32G47x / STM32G48x device # -chip_id 0x469 -description G47x/G48x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x20000 +dev_type STM32G47x_G48x +ref_manual_id 0440 +chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 -flags dualbank swo - +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B +flags swo dualbank diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index b764572db..9702541a8 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G49x/G4Ax +# Chip-ID file for STM32G49x / STM32G4Ax device # -chip_id 0x479 -description G49x/G4Ax -flash_type 8 -flash_pagesize 0x800 -sram_size 0x1c000 +dev_type STM32G49x_G4Ax +ref_manual_id 0440 +chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1c000 // 112 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index df20037d3..183c7d197 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H72x/H73x +# Chip-ID file for STM32H72x / STM32H73x device # -chip_id 0x483 -description H72x/H73x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H72x_H73x +ref_manual_id 0468 +chip_id 0x483 // STLINK_CHIPID_STM32_H72x +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B flags swo - diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 7a4bc86e3..2e543b197 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H74x/H75x +# Chip-ID file for STM32H74x / STM32H75x device # -chip_id 0x450 -description H74x/H75x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H74x_H75x +ref_manual_id 0433 +chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */ +flags swo dualbank diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b9202bd1a..b5fe72119 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H7Ax/H7Bx +# Chip-ID file for STM32H7Ax / STM32H7Bx device # -chip_id 0x480 -description H7Ax/H7Bx -flash_type 10 -flash_pagesize 0x2000 -sram_size 0x20000 +dev_type STM32H7Ax_H7Bx +ref_manual_id 0455 +chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B +flags swo dualbank diff --git a/config/chips/L01x_L02x.chip b/config/chips/L01x_L02x.chip deleted file mode 100644 index c3d2074b9..000000000 --- a/config/chips/L01x_L02x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L01x/L02x -# -chip_id 0x457 -description L01x/L02x -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff00000 -bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 -flags none - diff --git a/config/chips/L0xx_Cat_2.chip b/config/chips/L0xx_Cat_2.chip deleted file mode 100644 index 47183b8ef..000000000 --- a/config/chips/L0xx_Cat_2.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.2 -# -chip_id 0x425 -description L0xx Cat.2 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_3.chip b/config/chips/L0xx_Cat_3.chip deleted file mode 100644 index 6d9fcc105..000000000 --- a/config/chips/L0xx_Cat_3.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.3 -# -chip_id 0x417 -description L0xx Cat.3 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_5.chip b/config/chips/L0xx_Cat_5.chip deleted file mode 100644 index 545c1c2ef..000000000 --- a/config/chips/L0xx_Cat_5.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.5 -# -chip_id 0x447 -description L0xx Cat.5 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x5000 -bootrom_base 0x1ff0000 -bootrom_size 0x2000 -option_base 0x1ff80000 -option_size 0x14 -flags dualbank - diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip new file mode 100644 index 000000000..1dd8a1acb --- /dev/null +++ b/config/chips/L0xxx_Cat_1.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.1) device (L010x3 / L010x4 / L011x / L021x) +# +dev_type STM32L0xxx_Cat_1 +ref_manual_id 0451 // also RM0377 +chip_id 0x457 // STLINK_CHIPID_STM32_L011 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip new file mode 100644 index 000000000..58d6439ba --- /dev/null +++ b/config/chips/L0xxx_Cat_2.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.2) device (L010x6 / L031x / L041x) +# +dev_type STM32L0xxx_Cat_2 +ref_manual_id 0451 // also RM0377 +chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip new file mode 100644 index 000000000..406c1a037 --- /dev/null +++ b/config/chips/L0xxx_Cat_3.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.3) device (L010x8 / L051x / L053x / L063x) +# +dev_type STM32L0xxx_Cat_3 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x417 // STLINK_CHIPID_STM32_L0 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip new file mode 100644 index 000000000..1a0c387a7 --- /dev/null +++ b/config/chips/L0xxx_Cat_5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.5) device (L010xB / L071x / L081x / L073x / L083x) +# +dev_type STM32L0xxx_Cat_5 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x5000 // 20 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags dualbank diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip new file mode 100644 index 000000000..ce268148b --- /dev/null +++ b/config/chips/L5x5.chip @@ -0,0 +1,15 @@ +# Chip-ID file for STM32L5x2 device +# +dev_type STM32L5x2 +ref_manual_id 0438 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip new file mode 100644 index 000000000..177359cc3 --- /dev/null +++ b/config/chips/U5x5.chip @@ -0,0 +1,15 @@ +# Chip-ID file for STM32U5x5 device +# +dev_type STM32U5x5 +ref_manual_id 0456 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0xc4800 // 786 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip new file mode 100644 index 000000000..ba5fee778 --- /dev/null +++ b/config/chips/WBx0_WBx5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WBx0 / STM32WBx5 device +# +dev_type STM32WBx0_WBx5 +ref_manual_id 0434 // also RM0471 +chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff8000 +option_size 0x80 // 128 B +flags swo diff --git a/config/chips/WBx5_WBx0.chip b/config/chips/WBx5_WBx0.chip deleted file mode 100644 index 5bd2501e6..000000000 --- a/config/chips/WBx5_WBx0.chip +++ /dev/null @@ -1,14 +0,0 @@ -# Chip-ID file for STM32WBx0 device (STM32WB55xx, STM32WB35xx, STM32WB50CG, STM32WB30CE) -# -dev_type STM32WBx0 device -ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STLINK_CHIPID_STM32_WB55 -flash_type 9 // STLINK_FLASH_TYPE_WB -flash_size_reg 0x1fff75e0 -flash_pagesize 0x1000 // 4k -sram_size 0x40000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo diff --git a/config/chips/WLEx.chip b/config/chips/WLx5.chip similarity index 54% rename from config/chips/WLEx.chip rename to config/chips/WLx5.chip index e9b6248f6..2dc9ce648 100644 --- a/config/chips/WLEx.chip +++ b/config/chips/WLx5.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32WLEx device # -dev_type STM32WLEx device +dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STLINK_CHIPID_STM32_WLE flash_type 9 // STLINK_FLASH_TYPE_WB flash_size_reg 0x1fff75e0 -flash_pagesize 0x800 // 2k -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 +bootrom_size 0x7000 // 28 KB +option_base 0x1fffc000 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 8f3772e53..1b74f22fa 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,6 +1,6 @@ # Chip-ID file for unknown device # -dev_type unknown device +dev_type unknown ref_manual_id 0000 chip_id 0x0 // STLINK_CHIPID_UNKNOWN flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN diff --git a/inc/stm32.h b/inc/stm32.h index 21da2f563..15e0ff147 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -16,19 +16,24 @@ /* Constant STM32 memory map figures */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_FLASH_BASE ((uint32_t)0x08000000) + #define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) + #define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) -#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) + #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) + #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3dd82a1b2..213d43f8c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -28,8 +28,8 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_size_reg %x\n", dev->flash_size_reg); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); @@ -42,8 +42,8 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) { return p1->chip_id == p2->chip_id && - p1->description && p2->description && - strcmp(p1->description, p2->description) == 0 && + p1->dev_type && p2->dev_type && + strcmp(p1->dev_type, p2->dev_type) == 0 && p1->flash_type == p2->flash_type && p1->flash_size_reg == p2->flash_size_reg && p1->flash_pagesize == p2->flash_pagesize && @@ -205,8 +205,8 @@ void dump_chips (void) { fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); fprintf(fp, "sram_size %x\n", ts->sram_size); fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index bc6491ad4..b86b13289 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -6,123 +6,6 @@ // config/chips/*.chip file. static struct stlink_chipid_params devices[] = { - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .dev_type = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .dev_type = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .dev_type = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .dev_type = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .dev_type = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .dev_type = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .dev_type = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .dev_type = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .dev_type = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, { // STM32L100/L15x/L16x Cat.1 // RM0038 @@ -191,130 +74,137 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .dev_type = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .dev_type = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xB/C, STM32F358, STM32F302xBxC - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .dev_type = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .dev_type = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .dev_type = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .dev_type = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .dev_type = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .dev_type = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, +// ######################################################################## +// ######################################################################## +// ######################################################################## { - // STM32F09x + // STM32F03x // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .dev_type = "F09x", + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, + .dev_type = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, }, @@ -333,19 +223,165 @@ static struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // STM32F03x + // STM32F05x // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .dev_type = "F03x", + .chip_id = STLINK_CHIPID_STM32_F0, + .dev_type = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, }, + { + // STM32F07x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .dev_type = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F09x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F09x, + .dev_type = "F09x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F1xx low- and medium-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, + .dev_type = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, + .dev_type = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_LD, + .dev_type = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx medium-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_MD, + .dev_type = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_HD, + .dev_type = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx XL-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_XLD, + .dev_type = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx connectivity devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .dev_type = "F1xx CL", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) + .chip_id = STLINK_CHIPID_STM32_F2, + .dev_type = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, { // STM32F301x6/8, STM32F302x6x8, STM32F318x8 // RM0366, RM0365 @@ -362,50 +398,37 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .dev_type = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, + // STM32F302xBxC, STM32F303xB/C, STM32F358 + // RM0316, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3, + .dev_type = "F302/F303/F358", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .dev_type = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, + // STM32F302xD/E, STM32F303xD/E, STM32F398xE, + // RM0316 (rev 5), RM0365 + .chip_id = STLINK_CHIPID_STM32_F303_HD, + .dev_type = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .dev_type = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F334, STM32F303x6/8, STM32F328 + // STM32F303x6/8, STM32F328, STM32F334 // RM0364, RM0316 .chip_id = STLINK_CHIPID_STM32_F334, .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) @@ -420,149 +443,192 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xD/E, STM32F398xE, STM32F302xD/E - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .dev_type = "F303 high density", + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 + .chip_id = STLINK_CHIPID_STM32_F37x, + .dev_type = "F37x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .dev_type = "F401xB/C", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .dev_type = "F401xD/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + // STM32F410 + // RM0401 + .chip_id = STLINK_CHIPID_STM32_F410, + .dev_type = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + .chip_id = STLINK_CHIPID_STM32_F411xx, + .dev_type = "F411xC/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base + // STM32F412 + // RM0402 + .chip_id = STLINK_CHIPID_STM32_F412, + .dev_type = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, + // STM32F413/F423 + // RM0430 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F413, + .dev_type = "F413/F423", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F42x/F43x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .dev_type = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F446x family + // RM0390 + .chip_id = STLINK_CHIPID_STM32_F446, + .dev_type = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, + // STM32F46x/F47x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .dev_type = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F4x5/F4x7 + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4, + .dev_type = "F4x5/F4x7", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + // STM32F72x/F73x + // RM0431 + .chip_id = STLINK_CHIPID_STM32_F72xxx, + .dev_type = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F74x/F75x + // RM0385, DS10916 + .chip_id = STLINK_CHIPID_STM32_F7, + .dev_type = "F74x/F75x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .dev_type = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, + // STM32F76x/F77x + // RM0410 + .chip_id = STLINK_CHIPID_STM32_F76xxx, + .dev_type = "F76x/F77x", + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ + .option_size = 0x20, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32G030/031/041 @@ -579,10 +645,10 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, }, { - // STM32G071/081 + // STM32G051/G061 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .dev_type = "G07x/G08x", + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .dev_type = "G05x/G06x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -593,10 +659,10 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, }, { - // STM32G0B1/G0C1 + // STM32G071/081 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .dev_type = "G0Bx/G0Cx", + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .dev_type = "G07x/G08x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -605,13 +671,12 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, }, { - // STM32G051/G061 + // STM32G0B1/G0C1 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .dev_type = "G05x/G06x", + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .dev_type = "G0Bx/G0Cx", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -620,6 +685,7 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32G431/441 @@ -675,20 +741,6 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .dev_type = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, { // STM32H7A3/7B3 // RM0455 @@ -720,125 +772,74 @@ static struct stlink_chipid_params devices[] = { .option_size = 44, .flags = CHIP_F_HAS_SWO_TRACING, }, - - - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .dev_type = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .dev_type = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .dev_type = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .dev_type = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74xxx, + .dev_type = "H74x/H75x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .dev_type = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0xx Category 1 + // RM0451, RM0377 + .chip_id = STLINK_CHIPID_STM32_L011, + .dev_type = "L01x/L02x", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000, }, { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .dev_type = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0x Category 2 + // RM0367, RM0377 + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .dev_type = "L0xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, }, { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .dev_type = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0, + .dev_type = "L0xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, }, { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .dev_type = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0x Category 5 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .dev_type = "L0xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE