From 3e04a937f088ee2e0b3fa05cf73c73d5b5448048 Mon Sep 17 00:00:00 2001
From: Michal Sroczynski <msroczyn@gmail.com>
Date: Mon, 26 Apr 2021 07:54:00 +0200
Subject: [PATCH] enable stm32g030

---
 src/common.c            |  1 +
 src/st-flash/flash.c    |  2 +-
 src/stlink-lib/chipid.c | 13 +++++++++++++
 src/stlink-lib/chipid.h |  1 +
 src/stlink-lib/usb.c    |  5 ++++-
 5 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/common.c b/src/common.c
index 20d71df..71852a3 100644
--- a/src/common.c
+++ b/src/common.c
@@ -3708,6 +3708,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) {
         return stlink_read_option_bytes_f7(sl, option_byte);
     case STLINK_CHIPID_STM32_G0_CAT1:
     case STLINK_CHIPID_STM32_G0_CAT2:
+    case STLINK_CHIPID_STM32_G0_CAT3:
     case STLINK_CHIPID_STM32_G4_CAT2:
     case STLINK_CHIPID_STM32_G4_CAT3:
         return stlink_read_option_bytes_Gx(sl, option_byte);
diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c
index d8bd877..9b0e83b 100644
--- a/src/st-flash/flash.c
+++ b/src/st-flash/flash.c
@@ -127,7 +127,7 @@ int main(int ac, char** av) {
     }
 
     // core must be halted to use RAM based flashloaders
-    if (stlink_force_debug(sl)) {
+    if (stlink_step(sl)) {
         printf("Failed to halt the core\n");
         goto on_error;
     }
diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c
index d136384..d055851 100644
--- a/src/stlink-lib/chipid.c
+++ b/src/stlink-lib/chipid.c
@@ -596,6 +596,19 @@ static const struct stlink_chipid_params devices[] = {
         .option_base = STM32_G0_OPTION_BYTES_BASE,
         .option_size = 4,
     },
+    {
+        // STM32G030/031/041 (from RM0454 & RM0444)
+        .chip_id = STLINK_CHIPID_STM32_G0_CAT3,
+        .description = "G030/G031/G041 with error",
+        .flash_type = STLINK_FLASH_TYPE_G0,
+        .flash_size_reg = 0x1FFF75E0,          // Section 38.2
+        .flash_pagesize = 0x800,               // 2k (sec 3.2)
+        .sram_size = 0x2000,                   // 8k (sec 2.3)
+        .bootrom_base = 0x1fff0000,
+        .bootrom_size = 0x2000,                // 8k (sec 2.2.2 table 3)
+        .option_base = STM32_G0_OPTION_BYTES_BASE,
+        .option_size = 4,
+    },
     {
         // STM32G071/081 (from RM0444)
         .chip_id = STLINK_CHIPID_STM32_G0_CAT2,
diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h
index 1573b18..924f314 100644
--- a/src/stlink-lib/chipid.h
+++ b/src/stlink-lib/chipid.h
@@ -61,6 +61,7 @@ enum stlink_stm32_chipids {
     STLINK_CHIPID_STM32_G0_CAT2          = 0x460, /* G070/G071/081 */
     STLINK_CHIPID_STM32_F413             = 0x463,
     STLINK_CHIPID_STM32_G0_CAT1          = 0x466, /* G030/G031/041 */
+    STLINK_CHIPID_STM32_G0_CAT3          = 0xe5c, //e5c
     STLINK_CHIPID_STM32_G4_CAT2          = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */
     STLINK_CHIPID_STM32_G4_CAT3          = 0x469,
     STLINK_CHIPID_STM32_L4RX             = 0x470, /* ID found on the STM32L4R9I-DISCO board */
diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c
index db11968..61b20d5 100644
--- a/src/stlink-lib/usb.c
+++ b/src/stlink-lib/usb.c
@@ -1322,8 +1322,11 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL
         stlink_jtag_reset(sl, 0);
 
         if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); }
+        else stlink_enter_swd_mode(sl);
 
-        stlink_force_debug(sl);
+        stlink_step(sl);
+        fprintf(stderr, "about to EXIT reset in 2s!\n");
+        sleep(2);
         stlink_jtag_reset(sl, 1);
         usleep(10000);
     }
-- 
2.21.3