From 4189f25d1027929ce4555d9c5de5c4f2a62a700f Mon Sep 17 00:00:00 2001 From: Michal Sroczynski Date: Sun, 25 Apr 2021 19:49:40 +0200 Subject: [PATCH] add stm32g030 2 --- src/common.c | 12 ++++++++---- src/st-flash/flash.c | 2 +- src/stlink-lib/chipid.c | 13 +++++++++++++ src/stlink-lib/chipid.h | 1 + 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/common.c b/src/common.c index 4541aa3..369e76c 100644 --- a/src/common.c +++ b/src/common.c @@ -1500,7 +1500,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { ELOG("Can not connect to target. Please use \'connect under reset\' and " "try again\n"); - return -1; +// return -1; } /* @@ -4314,6 +4314,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_bytes_f7(sl, option_byte); case STLINK_CHIPID_STM32_G0_CAT1: case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G0_CAT3: case STLINK_CHIPID_STM32_G4_CAT2: case STLINK_CHIPID_STM32_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); @@ -4737,8 +4738,11 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); - } - stlink_force_debug(sl); + } else + stlink_enter_swd_mode(sl); + + stlink_step(sl); + fprintf(stderr, "about to EXIT reset in 2s!\n"); // clear S_RESET_ST in DHCSR register stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); @@ -4750,7 +4754,7 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { dhcsr = 0; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); + WLOG("NRST is not Connected\n"); } // addition soft reset for halt before the first instruction diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ede0f11..272c0a0 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -99,7 +99,7 @@ int main(int ac, char** av) { } // core must be halted to use RAM based flashloaders - if (stlink_force_debug(sl)) { + if (stlink_step(sl)) { printf("Failed to halt the core\n"); goto on_error; } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 187a6d9..6272ffb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -634,6 +634,19 @@ static const struct stlink_chipid_params devices[] = { .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, + { + // STM32G030/031/041 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .description = "G030/G031/G041 with error", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, { // STM32G071/081 (from RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT2, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e78..d27af5d 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -61,6 +61,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0xe5c, //e5c STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ -- 2.21.3