diff --git a/include/stlink.h b/include/stlink.h
index c93086219..d1bf4815c 100644
--- a/include/stlink.h
+++ b/include/stlink.h
@@ -51,6 +51,7 @@ extern "C" {
     /* cortex core ids */
     // TODO clean this up...
 #define STM32VL_CORE_ID 0x1ba01477
+#define STM32F7_CORE_ID 0x5ba02477
 
     // Constant STM32 memory map figures
 #define STM32_FLASH_BASE 0x08000000
diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
index a5012e38f..72094a733 100644
--- a/include/stlink/chipid.h
+++ b/include/stlink/chipid.h
@@ -52,6 +52,7 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_L0_CAT5          = 0x447,
 	STLINK_CHIPID_STM32_F0_CAN           = 0x448,
 	STLINK_CHIPID_STM32_F7               = 0x449,
+	STLINK_CHIPID_STM32_F7XXXX           = 0x451,
 	STLINK_CHIPID_STM32_F410             = 0x458
 };
 
diff --git a/src/chipid.c b/src/chipid.c
index c3f1a9278..546e2384e 100644
--- a/src/chipid.c
+++ b/src/chipid.c
@@ -2,6 +2,17 @@
 #include "stlink/chipid.h"
 
 static const struct stlink_chipid_params devices[] = {
+        {
+            //RM0410 document was used to find these paramaters
+            .chip_id = STLINK_CHIPID_STM32_F7XXXX,
+            .description = "F76xxx device",
+            .flash_type = STLINK_FLASH_TYPE_F4,
+            .flash_size_reg = 0x1ff0f442,      // section 45.2
+            .flash_pagesize = 0x800,           // No flash pages
+            .sram_size = 0x5C000,              // "SRAM" byte size in hex from 
+            .bootrom_base = 0x00200000,        //! "System memory" starting address from 
+            .bootrom_size = 0xEDC0             //! @todo "System memory" byte size in hex from 
+        },
         {
             //RM0385 and DS10916 document was used to find these paramaters
             .chip_id = STLINK_CHIPID_STM32_F7,
diff --git a/src/flash_loader.c b/src/flash_loader.c
index 6ea324485..eee961808 100644
--- a/src/flash_loader.c
+++ b/src/flash_loader.c
@@ -202,7 +202,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
             || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */
         loader_code = loader_code_stm32l;
         loader_size = sizeof(loader_code_stm32l);
-    } else if (sl->core_id == STM32VL_CORE_ID 
+    } else if (sl->core_id == STM32VL_CORE_ID
             || sl->chip_id == STLINK_CHIPID_STM32_F3
             || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL
             || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH
@@ -231,7 +231,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
             loader_code = loader_code_stm32f4_lv;
             loader_size = sizeof(loader_code_stm32f4_lv);
         }
-    } else if (sl->chip_id == STLINK_CHIPID_STM32_F7){
+    } else if (sl->core_id == STM32F7_CORE_ID ||
+               sl->chip_id == STLINK_CHIPID_STM32_F7 ||
+               sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) {
         loader_code = loader_code_stm32f7;
         loader_size = sizeof(loader_code_stm32f7);
     } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) {
@@ -241,7 +243,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
         loader_code = loader_code_stm32l4;
         loader_size = sizeof(loader_code_stm32l4);
     } else {
-        ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
+        ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id);
         return -1;
     }