From 110532d92ad2064ed7634ad960ed80828b7846d4 Mon Sep 17 00:00:00 2001 From: Jonas Date: Sun, 26 Mar 2023 14:39:12 +0200 Subject: [PATCH 1/4] Initial test of using OpenDrain for output pins of spi using stm32l0x1 --- src/spi.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/spi.rs b/src/spi.rs index 9a0ec65..e1ddc8a 100755 --- a/src/spi.rs +++ b/src/spi.rs @@ -13,7 +13,7 @@ use crate::dma::{self, Buffer}; use crate::gpio::gpioa::*; use crate::gpio::gpiob::*; -use crate::gpio::{AltMode, Analog}; +use crate::gpio::{AltMode, Analog, OpenDrain, Output}; use crate::hal; use crate::pac::SPI1; #[cfg(any( @@ -164,6 +164,7 @@ pins! { SCK: [ [NoSck, None], [PA5, AltMode::AF0], + [PA5>, AltMode::AF0], [PB3, AltMode::AF0] ] MISO: [ @@ -175,6 +176,7 @@ pins! { MOSI: [ [NoMosi, None], [PA7, AltMode::AF0], + [PA7>, AltMode::AF0], [PA12, AltMode::AF0], [PB5, AltMode::AF0] ] From 4387ee3ef985891234f51873523e9fd1b520c87c Mon Sep 17 00:00:00 2001 From: Jonas Date: Sun, 26 Mar 2023 15:42:58 +0200 Subject: [PATCH 2/4] Allow use of output pin modes PushPull and OpenDrain for SPI outputs --- src/spi.rs | 36 +++++++++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/src/spi.rs b/src/spi.rs index e1ddc8a..7b3dd9f 100755 --- a/src/spi.rs +++ b/src/spi.rs @@ -13,7 +13,7 @@ use crate::dma::{self, Buffer}; use crate::gpio::gpioa::*; use crate::gpio::gpiob::*; -use crate::gpio::{AltMode, Analog, OpenDrain, Output}; +use crate::gpio::{AltMode, Analog, OpenDrain, Output, PushPull}; use crate::hal; use crate::pac::SPI1; #[cfg(any( @@ -119,8 +119,12 @@ pins! { SPI1: SCK: [ [NoSck, None], + [PA5, AltMode::AF0], + [PA5>, AltMode::AF0], + [PA5>, AltMode::AF0], [PB3, AltMode::AF0], - [PA5, AltMode::AF0] + [PB3>, AltMode::AF0], + [PB3>, AltMode::AF0] ] MISO: [ [NoMiso, None], @@ -131,8 +135,14 @@ pins! { MOSI: [ [NoMosi, None], [PA7, AltMode::AF0], + [PA7>, AltMode::AF0], + [PA7>, AltMode::AF0], [PA12, AltMode::AF0], - [PB5, AltMode::AF0] + [PA12>, AltMode::AF0], + [PA12>, AltMode::AF0], + [PB5, AltMode::AF0], + [PB5>, AltMode::AF0], + [PB5>, AltMode::AF0] ] } @@ -146,7 +156,9 @@ pins! { SPI2: SCK: [ [NoSck, None], - [PB13, AltMode::AF0] + [PB13, AltMode::AF0], + [PB13>, AltMode::AF0], + [PB13>, AltMode::AF0] ] MISO: [ [NoMiso, None], @@ -154,7 +166,9 @@ pins! { ] MOSI: [ [NoMosi, None], - [PB15, AltMode::AF0] + [PB15, AltMode::AF0], + [PB15>, AltMode::AF0], + [PB15>, AltMode::AF0] ] } @@ -165,7 +179,10 @@ pins! { [NoSck, None], [PA5, AltMode::AF0], [PA5>, AltMode::AF0], - [PB3, AltMode::AF0] + [PA5>, AltMode::AF0], + [PB3, AltMode::AF0], + [PB3>, AltMode::AF0], + [PB3>, AltMode::AF0] ] MISO: [ [NoMiso, None], @@ -177,8 +194,13 @@ pins! { [NoMosi, None], [PA7, AltMode::AF0], [PA7>, AltMode::AF0], + [PA7>, AltMode::AF0], [PA12, AltMode::AF0], - [PB5, AltMode::AF0] + [PA12>, AltMode::AF0], + [PA12>, AltMode::AF0], + [PB5, AltMode::AF0], + [PB5>, AltMode::AF0], + [PB5>, AltMode::AF0] ] } From c7895b55861067698eda246dd1c09223aed59b75 Mon Sep 17 00:00:00 2001 From: Jonas Date: Thu, 30 Mar 2023 22:41:07 +0200 Subject: [PATCH 3/4] SPI output pin modes changelog --- CHANGELOG.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index d1da5b7..e170055 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -13,6 +13,7 @@ forget to update the links at the bottom of the changelog as well.--> ### Additions +- SPI: Allow output pins of mode `PushPull` and `OpenDrain` ([#226]) - Enable TIM2 outputs on `PA5`, `PA15`, `PB3` for all devices in the L0 family (previously only 0x2 and 0x3) ([#224]) - Enable SPI2 on subset of stm32l0x1 devices ([#221]) @@ -186,6 +187,7 @@ _Not yet tracked in this changelog._ +[#226]: https://github.com/stm32-rs/stm32l0xx-hal/pull/226 [#224]: https://github.com/stm32-rs/stm32l0xx-hal/pull/224 [#221]: https://github.com/stm32-rs/stm32l0xx-hal/pull/221 [#220]: https://github.com/stm32-rs/stm32l0xx-hal/pull/218 From 9b63fccefdd13d3441a88ee817b19bb7bc9bd54a Mon Sep 17 00:00:00 2001 From: Jonas Date: Thu, 30 Mar 2023 23:10:24 +0200 Subject: [PATCH 4/4] Clippy fix for rcc MSIRange Default impl --- src/rcc.rs | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/rcc.rs b/src/rcc.rs index 1a8af53..a20d364 100755 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -22,7 +22,7 @@ pub enum ClockSrc { /// /// These ranges control the frequency of the MSI. Internally, these ranges map /// to the `MSIRANGE` bits in the `RCC_ICSCR` register. -#[derive(Clone, Copy)] +#[derive(Clone, Copy, Default)] pub enum MSIRange { /// Around 65.536 kHz Range0 = 0, @@ -35,17 +35,12 @@ pub enum MSIRange { /// Around 1.048 MHz Range4 = 4, /// Around 2.097 MHz (reset value) + #[default] Range5 = 5, /// Around 4.194 MHz Range6 = 6, } -impl Default for MSIRange { - fn default() -> MSIRange { - MSIRange::Range5 - } -} - /// HSI16 divider #[derive(Clone, Copy)] pub enum HSI16Div {