From 113ef68823505338da4509eefa130c7f74b26e02 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 23 Jul 2024 15:48:07 +0200 Subject: [PATCH] system(H5) update STM32H5xx HAL Drivers to v1.3.0 Included in STM32CubeH5 FW v1.3.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 13 +- .../Inc/stm32h5xx_hal_exti.h | 3 +- .../Inc/stm32h5xx_hal_fdcan.h | 4 +- .../Inc/stm32h5xx_hal_flash_ex.h | 11 +- .../Inc/stm32h5xx_hal_gpio_ex.h | 131 ++- .../Inc/stm32h5xx_hal_hash.h | 10 +- .../Inc/stm32h5xx_hal_i3c.h | 28 +- .../Inc/stm32h5xx_hal_nand.h | 2 +- .../Inc/stm32h5xx_hal_pcd_ex.h | 1 - .../Inc/stm32h5xx_hal_rcc.h | 1029 +++++++++++------ .../Inc/stm32h5xx_hal_rcc_ex.h | 23 +- .../Inc/stm32h5xx_hal_sdram.h | 2 +- .../Inc/stm32h5xx_hal_tim.h | 21 +- .../Inc/stm32h5xx_hal_tim_ex.h | 213 +++- .../Inc/stm32h5xx_hal_uart.h | 5 +- .../Inc/stm32h5xx_hal_usart.h | 3 +- .../Inc/stm32h5xx_hal_xspi.h | 15 +- .../Inc/stm32h5xx_ll_bus.h | 21 +- .../Inc/stm32h5xx_ll_exti.h | 53 +- .../Inc/stm32h5xx_ll_fmc.h | 61 +- .../Inc/stm32h5xx_ll_gpio.h | 5 +- .../Inc/stm32h5xx_ll_rcc.h | 13 +- .../Inc/stm32h5xx_ll_rng.h | 39 + .../Inc/stm32h5xx_ll_rtc.h | 4 +- .../Inc/stm32h5xx_ll_system.h | 26 +- .../Inc/stm32h5xx_ll_tim.h | 463 ++++++-- .../Inc/stm32h5xx_ll_ucpd.h | 12 +- .../Inc/stm32h5xx_util_i3c.h | 4 +- .../STM32H5xx_HAL_Driver/Release_Notes.html | 71 +- .../STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c | 4 +- .../Src/stm32h5xx_hal_hash.c | 43 +- .../Src/stm32h5xx_hal_hcd.c | 36 +- .../Src/stm32h5xx_hal_i3c.c | 230 +++- .../Src/stm32h5xx_hal_nand.c | 2 +- .../Src/stm32h5xx_hal_pcd.c | 6 +- .../Src/stm32h5xx_hal_pcd_ex.c | 2 - .../Src/stm32h5xx_hal_pwr.c | 9 +- .../Src/stm32h5xx_hal_rcc_ex.c | 109 +- .../Src/stm32h5xx_hal_rng.c | 13 +- .../Src/stm32h5xx_hal_sdram.c | 5 +- .../Src/stm32h5xx_hal_sram.c | 3 + .../Src/stm32h5xx_hal_tim.c | 12 +- .../Src/stm32h5xx_hal_tim_ex.c | 154 ++- .../Src/stm32h5xx_hal_uart.c | 95 ++ .../Src/stm32h5xx_hal_uart_ex.c | 18 +- .../Src/stm32h5xx_hal_usart.c | 69 +- .../Src/stm32h5xx_hal_usart_ex.c | 2 +- .../Src/stm32h5xx_hal_xspi.c | 17 +- .../Src/stm32h5xx_ll_exti.c | 14 +- .../Src/stm32h5xx_ll_fmc.c | 22 +- .../Src/stm32h5xx_ll_gpio.c | 19 +- .../Src/stm32h5xx_ll_opamp.c | 2 - .../Src/stm32h5xx_ll_rcc.c | 4 + .../Src/stm32h5xx_ll_ucpd.c | 2 +- .../Src/stm32h5xx_ll_usb.c | 33 +- .../Src/stm32h5xx_ll_utils.c | 110 +- .../Src/stm32h5xx_util_i3c.c | 32 +- .../{mini-st.css => mini-st_2020.css} | 0 .../{st_logo.png => st_logo_2020.png} | Bin .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 60 files changed, 2446 insertions(+), 909 deletions(-) rename system/Drivers/STM32H5xx_HAL_Driver/_htmresc/{mini-st.css => mini-st_2020.css} (100%) rename system/Drivers/STM32H5xx_HAL_Driver/_htmresc/{st_logo.png => st_logo_2020.png} (100%) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index d10f6f6f89..5c2adb67f4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -1817,7 +1817,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -2731,6 +2731,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3665,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3916,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h index f08c45ee75..142f89fe02 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h @@ -186,9 +186,10 @@ typedef struct #define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19U) #endif /* EXTI_IMR2_IM57 */ #if defined(EXTI_IMR2_IM58) +#if defined(I3C2) #define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1AU) +#endif /* I3C2 */ #endif /* EXTI_IMR2_IM58 */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h index 204a38bc02..0b3a6db2fd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h index 6968de725b..f94a3721ba 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h @@ -632,13 +632,12 @@ byte configuration */ /** @defgroup FLASH_Programming_Delay FLASH Programming Delay * @{ */ -#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or +#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 84 MHz or below */ -#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz - and 185 MHz */ -#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz - and 225 MHz */ -#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ +#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 84 MHz + and 168 MHz */ +#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 168 MHz + and 250 MHz */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h index 10fe04f3d7..090c89914d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h @@ -56,6 +56,12 @@ extern "C" { #define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ #define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ #define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ +#if defined(DMA2D) +#define GPIO_AF0_DMA2D ((uint8_t)0x00) /* DMA2D Alternate Function mapping */ +#endif /* DMA2D */ +#if defined(GFXTIM) +#define GPIO_AF0_GFXTIM ((uint8_t)0x00) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 1 selection @@ -68,9 +74,12 @@ extern "C" { #if defined(TIM17) #define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ #endif /* TIM17 */ -#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) +#if !defined(STM32H503xx) #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ +#endif /* STM32H503xx */ +#if defined(ADF1) +#define GPIO_AF1_ADF1 ((uint8_t)0x01) /* ADF1 Alternate Function mapping */ +#endif /* ADF1 */ /** * @brief AF 2 selection @@ -100,6 +109,11 @@ extern "C" { #if defined(TIM15) #define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ #endif /* TIM15 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ + /** * @brief AF 3 selection */ @@ -115,12 +129,22 @@ extern "C" { #if defined(OCTOSPI1) #define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ #endif /* OCTOSPI1 */ -#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) +#if !defined(STM32H503xx) #define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ -#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ +#endif /* STM32H503xx */ #if defined(TIM8) #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #endif /* TIM8 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF3_COMP1 ((uint8_t)0x03) /* COMP1 Alternate Function mapping */ +#define GPIO_AF3_COMP2 ((uint8_t)0x03) /* COMP2 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(ADF1) +#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ +#endif /* ADF1 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ /** * @brief AF 4 selection @@ -128,10 +152,14 @@ extern "C" { #if defined(CEC) #define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ #endif /* CEC */ +#if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx) #if defined(DCMI) #define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ -#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ #endif /* DCMI */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(PSSI) +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #if defined(I2C3) @@ -153,6 +181,15 @@ extern "C" { #if defined(STM32H503xx) #define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ #endif /* STM32H503xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF4_SAI1 ((uint8_t)0x04) /* SAI1 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(MDF1) +#define GPIO_AF4_MDF1 ((uint8_t)0x04) /* MDF1 Alternate Function mapping */ +#endif /* MDF1 */ +#if defined(ADF1) +#define GPIO_AF4_ADF1 ((uint8_t)0x04) /* ADF1 Alternate Function mapping */ +#endif /* ADF1 */ /** * @brief AF 5 selection @@ -160,10 +197,10 @@ extern "C" { #if defined(CEC) #define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ #endif /* CEC */ -#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) +#if !defined(STM32H503xx) #define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ -#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ +#endif /* STM32H503xx */ #define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ @@ -176,6 +213,14 @@ extern "C" { #if defined(SPI6) #define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ #endif /* SPI6 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF5_I3C2 ((uint8_t)0x05) /* I3C2 Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ +#define GPIO_AF5_AUDIOCLK ((uint8_t)0x05) /* AUDIOCLK Alternate Function mapping */ +#define GPIO_AF5_USART2 ((uint8_t)0x05) /* USART2 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ /** * @brief AF 6 selection @@ -212,6 +257,12 @@ extern "C" { #if defined(UCPD1) #define GPIO_AF6_UCPD1 ((uint8_t)0x06) /* UCPD1 Alternate Function mapping */ #endif /* UCPD1 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_ETH ((uint8_t)0x06) /* ETH Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_USART12 ((uint8_t)0x06) /* USART12 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ /** * @brief AF 7 selection @@ -230,9 +281,11 @@ extern "C" { #if defined(UART8) #define GPIO_AF7_UART8 ((uint8_t)0x07) /* UART8 Alternate Function mapping */ #endif /* UART8 */ +#if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx) #if defined(UART12) #define GPIO_AF7_UART12 ((uint8_t)0x07) /* UART12 Alternate Function mapping */ #endif /* UART12 */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ @@ -245,7 +298,9 @@ extern "C" { #if defined(USART11) #define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */ #endif /* USART11 */ - +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF7_ETH ((uint8_t)0x07) /* ETH Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ /** * @brief AF 8 selection */ @@ -273,6 +328,18 @@ extern "C" { #if defined(UART8) #define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ #endif /* UART8 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF8_ETH ((uint8_t)0x08) /* ETH Alternate Function mapping */ +#define GPIO_AF8_FMC ((uint8_t)0x08) /* FMC Alternate Function mapping */ +#define GPIO_AF8_I3C2 ((uint8_t)0x08) /* I3C2 Alternate Function mapping */ +#define GPIO_AF8_OCTOSPI1 ((uint8_t)0x08) /* OCTOSPI1 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(OCTOSPI2) +#define GPIO_AF8_OCTOSPI2 ((uint8_t)0x08) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#if defined(MDF1) +#define GPIO_AF8_MDF1 ((uint8_t)0x08) /* MDF1 Alternate Function mapping */ +#endif /* MDF1 */ /** * @brief AF 9 selection @@ -304,6 +371,12 @@ extern "C" { #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ #define GPIO_AF9_I3C2 ((uint8_t)0x09) /* I3C2 Alternate Function mapping */ #endif /* STM32H533xx || STM32H523xx */ +#if defined(OCTOSPI2) +#define GPIO_AF9_OCTOSPI2 ((uint8_t)0x09) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#if defined(FDCAN3) +#define GPIO_AF9_FDCAN3 ((uint8_t)0x09) /* FDCAN3 Alternate Function mapping */ +#endif /* FDCAN3 */ /** * @brief AF 10 selection @@ -334,7 +407,24 @@ extern "C" { #if defined(TIM8) #define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ #endif /* TIM8 */ +#if defined(USB_DRD_FS) #define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ +#endif /* USB_DRD_FS */ +#if defined(LCD) +#define GPIO_AF10_LCD ((uint8_t)0x0A) /* LCD Alternate Function mapping */ +#endif /* LCD */ +#if defined(ETH) +#define GPIO_AF10_ETH ((uint8_t)0x0A) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(OCTOSPI2) +#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#if defined(USB_OTG_FS) +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* USB OTG FS Alternate Function mapping */ +#endif /* USB_OTG_FS */ +#if defined(USB_OTG_HS) +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* USB OTG HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ /** * @brief AF 11 selection @@ -369,6 +459,9 @@ extern "C" { #define GPIO_AF11_SPI2 ((uint8_t)0x0B) /* SPI2 Alternate Function mapping */ #define GPIO_AF11_USART2 ((uint8_t)0x0B) /* USART2 Alternate Function mapping */ #endif /* STM32H503xx */ +#if defined(LCD) +#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ +#endif /* LCD */ /** * @brief AF 12 selection @@ -383,6 +476,9 @@ extern "C" { #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ #define GPIO_AF12_SPI1 ((uint8_t)0x0C) /* SPI1 Alternate Function mapping */ #endif /* STM32H503xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF12_ETH ((uint8_t)0x0C) /* ETH Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ /** * @brief AF 13 selection @@ -401,6 +497,12 @@ extern "C" { #define GPIO_AF13_USART2 ((uint8_t)0x0D) /* USART2 Alternate Function mapping */ #define GPIO_AF13_USART3 ((uint8_t)0x0D) /* USART3 Alternate Function mapping */ #endif /* STM32H503xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF13_LPTIM6 ((uint8_t)0x0D) /* LPTIM6 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(LCD) +#define GPIO_AF13_LCD ((uint8_t)0x0D) /* LCD Alternate Function mapping */ +#endif /* LCD */ /** * @brief AF 14 selection @@ -433,6 +535,13 @@ extern "C" { #if (defined(STM32H533xx) || defined(STM32H523xx)) #define GPIO_AF14_USART6 ((uint8_t)0x0E) /* USART6 Alternate Function mapping */ #endif /* STM32H533xx || STM32H523xx */ +#if defined(LCD) +#define GPIO_AF14_LCD ((uint8_t)0x0E) /* LCD Alternate Function mapping */ +#endif /* LCD */ +#if defined(PLAY1) +#define GPIO_AF14_PLAY1_IN ((uint8_t)0x0E) /* PLAY1_IN Alternate Function mapping */ +#define GPIO_AF14_PLAY1_OUT ((uint8_t)0x0E) /* PLAY1_OUT Alternate Function mapping */ +#endif /* PLAY1 */ /** * @brief AF 15 selection @@ -463,10 +572,12 @@ extern "C" { /* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ #if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ - defined(STM32H523xx) || defined(STM32H503xx) + defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \ + defined(STM32H5E5xx) || defined(STM32H5E4xx) #define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) #endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ - defined(STM32H523xx) || defined(STM32H503xx)) */ + defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \ + defined(STM32H5E5xx) || defined(STM32H5E4xx)*/ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h index 0f96eae809..277c4d9520 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h @@ -298,11 +298,13 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @retval The new state of __FLAG__ (SET or RESET). */ -#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \ - (((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\ - (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) ) +#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \ + ((((__HANDLE__)->Instance->CR & (__FLAG__)) == \ + (__FLAG__)) ? SET : RESET) : \ + ((((__HANDLE__)->Instance->SR & (__FLAG__)) == \ + (__FLAG__)) ? SET : RESET) ) /** @brief Clear the specified HASH flag. * @param __HANDLE__ specifies the HASH handle. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h index a1265e942d..cf2b9f0863 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h @@ -968,6 +968,26 @@ typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, * @} */ +/** @defgroup I3C_PATTERN_CONFIGURATION I3C PATTERN CONFIGURATION + * @{ + */ +#define HAL_I3C_TARGET_RESET_PATTERN 0x00000001U /*!< Target reset pattern */ +#define HAL_I3C_HDR_EXIT_PATTERN 0x00000002U /*!< HDR exit pattern */ +/** + * @} + */ + +/** @defgroup I3C_RESET_PATTERN RESET PATTERN + * @{ + */ +#define HAL_I3C_RESET_PATTERN_DISABLE 0x00000000U +/*!< Standard STOP condition emitted at the end of a frame */ +#define HAL_I3C_RESET_PATTERN_ENABLE I3C_CFGR_RSTPTRN +/*!< Reset pattern is inserted before the STOP condition of any emitted frame */ +/** + * @} + */ + /** * @} */ @@ -1129,6 +1149,8 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint8_t nbFrame, uint32_t option); +HAL_StatusTypeDef HAL_I3C_Ctrl_SetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t resetPattern); +HAL_StatusTypeDef HAL_I3C_Ctrl_GetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t *pResetPattern); /** * @} */ @@ -1208,6 +1230,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, uint8_t devAddress, uint32_t trials, uint32_t timeout); +/* Controller arbitration APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout); + /** * @} */ @@ -1342,7 +1367,8 @@ HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, #define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD) #define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) - +#define IS_I3C_RESET_PATTERN(__RSTPTRN__) (((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_ENABLE) || \ + ((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_DISABLE)) /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h index 8f3fc4e219..4f56a9fb4c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h index a92987f089..eb75ab685d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h index 23ed1016d8..3a73efd8e5 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h @@ -773,13 +773,13 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -790,64 +790,64 @@ typedef struct } while(0) #if defined(ETH) -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_ETHTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_ETHTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_ETHRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_ETHRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ + UNUSED(tmpreg); \ + } while(0) #endif /*ETH*/ -#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(DCACHE1) -#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* DCACHE1 */ -#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) @@ -984,13 +984,13 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(DCMI) #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ @@ -1016,12 +1016,12 @@ typedef struct #if defined(HASH) #define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ @@ -1043,30 +1043,30 @@ typedef struct #endif /* PKA */ #if defined(SAES) -#define __HAL_RCC_SAES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SAES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* SAES */ -#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(SRAM3_BASE) -#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* SRAM3_BASE */ #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) @@ -1149,50 +1149,84 @@ typedef struct } while(0) #endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ + #if defined(SDMMC1) -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* SDMMC1 */ #if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* SDMMC2 */ #if defined(FMC_BASE) -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* FMC_BASE */ #if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ + #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) #endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) +#endif /* OTFDEC2 */ + #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) #endif /* SDMMC1 */ @@ -1209,6 +1243,13 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) #endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) +#endif /* OCTOSPIM */ /** * @} */ @@ -1275,34 +1316,34 @@ typedef struct } while(0) #if defined(TIM12) -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* TIM12 */ #if defined(TIM13) -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* TIM13 */ #if defined(TIM14) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* TIM14 */ #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ @@ -1314,13 +1355,13 @@ typedef struct } while(0) #if defined(OPAMP1) -#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* OPAMP1 */ #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ @@ -1349,177 +1390,177 @@ typedef struct } while(0) #endif /* COMP1 */ -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(UART4) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* UART5 */ -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_I3C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_I3C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(USART6) -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* USART6 */ #if defined(USART10) -#define __HAL_RCC_USART10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* USART10 */ #if defined(USART11) -#define __HAL_RCC_USART11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* USART11 */ #if defined(CEC) -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* CEC */ #if defined(UART7) -#define __HAL_RCC_UART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* UART7 */ #if defined(UART8) -#define __HAL_RCC_UART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* UART8 */ #if defined(UART9) -#define __HAL_RCC_UART9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* UART9 */ #if defined(UART12) -#define __HAL_RCC_UART12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_UART12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* UART12 */ -#define __HAL_RCC_DTS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(UCPD1) #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ @@ -1673,42 +1714,42 @@ typedef struct } while(0) #endif /* TIM8 */ -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(TIM15) -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* TIM15 */ #if defined(TIM16) -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* TIM16 */ #if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* TIM17 */ #if defined(SPI4) @@ -1751,13 +1792,35 @@ typedef struct } while(0) #endif /* SAI2 */ -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ - UNUSED(tmpreg); \ - } while(0) +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /*USB_DRD_FS*/ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /*LTDC*/ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /*GFXTIM*/ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1797,8 +1860,17 @@ typedef struct #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) #endif /* SAI2 */ +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) +#endif /* USB_DRD_FS */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) +#endif /* GFXTIM */ /** * @} */ @@ -1932,6 +2004,24 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (PLAY1) +#define __HAL_RCC_PLAY1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PLAY1APB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* PLAY1 */ + #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) #if defined(SPI5) @@ -1976,6 +2066,10 @@ typedef struct #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) +#if defined (PLAY1) +#define __HAL_RCC_PLAY1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) +#define __HAL_RCC_PLAY1APB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) +#endif /* PLAY1 */ /** * @} */ @@ -2102,41 +2196,41 @@ typedef struct #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) -#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) +#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) -#define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U) +#define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U) -#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U) +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) #if defined(CORDIC) -#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) #endif /* CORDIC */ #if defined(FMAC) -#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) #endif /* FMAC */ -#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) +#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) #if defined(ETH) -#define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U) -#define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U) +#define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U) -#define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U) +#define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U) #endif /*ETH*/ -#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U) +#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U) -#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U) +#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U) #if defined(DCACHE1) -#define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) +#define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) #endif /* DCACHE1 */ -#define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) +#define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) /** * @} */ @@ -2278,9 +2372,9 @@ typedef struct #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) #endif /* OTFDEC1 */ -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) -#endif /* OCTOSPI1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) != 0U) +#endif /* OTFDEC2 */ #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) @@ -2294,27 +2388,50 @@ typedef struct #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) != 0U) #endif /* FMC_BASE */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) != 0U) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) != 0U) +#endif /* OCTOSPIM */ #if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) #endif /* OTFDEC1 */ -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) -#endif /* OCTOSPI1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) == 0U) +#endif /* OTFDEC2 */ #if defined(SDMMC1) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) #endif /* SDMMC1 */ #if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == 0U) #endif /* SDMMC2 */ #if defined(FMC_BASE) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U) #endif /* FMC_BASE */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) == 0U) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) == 0U) +#endif /* OCTOSPIM */ + /** * @} */ @@ -2589,48 +2706,67 @@ typedef struct #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) #endif /* SAI2 */ +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) +#endif /* USB_DRD_FS */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) +#endif /* LTDC */ +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) +#endif /* GFXTIM */ -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) #if defined(TIM15) -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) #endif /* TIM15 */ #if defined(TIM16) -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) #endif /* TIM16 */ #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) #endif /* TIM17 */ #if defined(SPI4) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) #endif /* SPI4 */ #if defined(SPI6) -#define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U) #endif /* SPI6 */ #if defined(SAI1) -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) #endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) #endif /* SAI2 */ +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) +#endif /* USB_DRD_FS */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) +#endif /* GFXTIM */ /** * @} */ @@ -2687,6 +2823,10 @@ typedef struct #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) != 0U) +#define __HAL_RCC_PLAY1APB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) != 0U) +#endif /* PLAY1 */ #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) @@ -2732,6 +2872,11 @@ typedef struct #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) == 0U) +#define __HAL_RCC_PLAY1APB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) == 0U) +#endif /* PLAY1 */ + /** * @} */ @@ -2787,7 +2932,7 @@ typedef struct #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) #if defined(ETH) -#define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) +#define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) #endif /* ETH */ #define __HAL_RCC_GTZC1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) @@ -2800,11 +2945,11 @@ typedef struct #define __HAL_RCC_GPDMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) #if defined(CORDIC) -#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) +#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) #endif /* CORDIC */ #if defined(FMAC) -#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) +#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) #endif /* FMAC */ #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) @@ -2864,23 +3009,26 @@ typedef struct #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) #endif /* HASH */ -#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #if defined(PKA) -#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) #endif /* PKA */ #if defined(SAES) -#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ +#if defined(RCC_AHB2RSTR_OTGHSPHYRST) +#define __HAL_RCC_OTGPHY_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) +#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) @@ -2920,23 +3068,27 @@ typedef struct #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) #endif /* HASH */ -#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #if defined(PKA) -#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) #endif /* PKA */ #if defined(SAES) -#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ +#if defined(RCC_AHB2RSTR_OTGHSPHYRST) +#define __HAL_RCC_OTGPHY_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) +#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ + /** * @} */ @@ -2955,11 +3107,11 @@ typedef struct #endif /* OTFDEC1 */ #if defined(SDMMC1) -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) #endif /* SDMMC1 */ #if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) +#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) #endif /* SDMMC2 */ #if defined(FMC_BASE) @@ -2970,6 +3122,17 @@ typedef struct #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) #endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) +#endif /* OTFDEC2 */ #if defined(FMC_BASE) #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) @@ -2995,6 +3158,18 @@ typedef struct #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) #endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) +#endif /* OTFDEC2 */ + /** * @} */ @@ -3027,19 +3202,19 @@ typedef struct #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) #if defined(TIM12) -#define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) #endif /* TIM12 */ #if defined(TIM13) -#define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) #endif /* TIM13 */ #if defined(TIM14) -#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) #endif /* TIM14 */ #if defined(OPAMP1) -#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) +#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) #endif /* OPAMP1 */ #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) @@ -3148,7 +3323,7 @@ typedef struct #endif /* TIM14 */ #if defined(OPAMP1) -#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) +#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) #endif /* OPAMP1 */ #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) @@ -3271,8 +3446,17 @@ typedef struct #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) #endif /* SAI2 */ -#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) @@ -3314,7 +3498,17 @@ typedef struct #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) #endif /* SAI2 */ -#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ /** * @} @@ -3367,6 +3561,11 @@ typedef struct #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) +#define __HAL_RCC_PLAY1POR_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) +#endif /* PLAY1 */ + #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) #if defined(SPI5) @@ -3409,6 +3608,10 @@ typedef struct #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) +#define __HAL_RCC_PLAY1POR_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) +#endif /* PLAY1 */ /** * @} */ @@ -3444,6 +3647,10 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) + +#if defined(RCC_AHB1LPENR_ETHCKLPEN) +#define __HAL_RCC_ETHINTERN_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) +#endif /* RCC_AHB1LPENR_ETHCKLPEN */ #endif /* ETH */ #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) @@ -3483,6 +3690,10 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) + +#if defined(RCC_AHB1LPENR_ETHCKLPEN) +#define __HAL_RCC_ETHINTERN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) +#endif /* RCC_AHB1LPENR_ETHCKLPEN */ #endif /* ETH */ #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) @@ -3543,6 +3754,10 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ #endif /* DCMI */ +#if defined(RCC_AHB2LPENR_OTGPHYLPEN) +#define __HAL_RCC_OTGPHY_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN); +#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ + #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); #endif /* AES */ @@ -3602,6 +3817,10 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ #endif /* DCMI */ +#if defined(RCC_AHB2LPENR_OTGPHYLPEN) +#define __HAL_RCC_OTGPHY_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN) +#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ + #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); #endif /* AES */ @@ -3638,6 +3857,10 @@ typedef struct #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) #endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) +#endif /* OTFDEC2 */ + #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) #endif /* SDMMC1*/ @@ -3654,10 +3877,22 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) #endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) +#endif /* OCTOSPIM */ + #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) #endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) +#endif /* OTFDEC2 */ + #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) #endif /* SDMMC1*/ @@ -3674,6 +3909,14 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) #endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) +#endif /* OCTOSPIM */ + /** * @} */ @@ -3829,7 +4072,7 @@ typedef struct #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) #if defined(COMP1) -#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) +#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) #endif /* COMP1 */ #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) @@ -3882,7 +4125,7 @@ typedef struct #endif /* UART9 */ #if defined(UART12) -#define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) +#define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) #endif /* UART12 */ #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) @@ -3943,8 +4186,17 @@ typedef struct #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) #endif /* SAI2 */ -#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTIMLPEN) +#endif /* GFXTIM */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) +#endif /* USB_DRD_FS */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) @@ -3984,7 +4236,18 @@ typedef struct #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) #endif /* SAI2 */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTMLPEN) +#endif /* GFXTIM */ + +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) +#endif /* USB_DRD_FS */ /** * @} @@ -4040,6 +4303,9 @@ typedef struct #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) +#endif /* PLAY1 */ #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) @@ -4085,6 +4351,9 @@ typedef struct #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) +#endif /* PLAY1 */ /** * @} */ @@ -5047,10 +5316,16 @@ typedef struct ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ ((DIV) == RCC_MCODIV_15)) -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) +#else +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) +#endif /* STM32H5E5xx || STM32H5E4xx || !STM32H5F5xx || STM32H5F4xx */ #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h index 4a7f1aaba0..e9d7b77b39 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h @@ -346,12 +346,13 @@ typedef struct This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ #endif /* CEC */ +#if defined(USB_DRD_FS) uint32_t UsbClockSelection; /*!< Specifies USB clock source. This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif /* USB_DRD_FS */ uint32_t TimPresSelection; /*!< Specifies TIM Clock Prescalers Selection. This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ - } RCC_PeriphCLKInitTypeDef; #if defined(CRS) @@ -507,7 +508,9 @@ typedef struct #if defined(CEC) #define RCC_PERIPHCLK_CEC ((uint64_t)0x800000000U) #endif /* CEC */ +#if defined(USB_DRD_FS) #define RCC_PERIPHCLK_USB ((uint64_t)0x1000000000U) +#endif /* USB_DRD_FS */ #if defined(LPTIM3) #define RCC_PERIPHCLK_LPTIM3 ((uint64_t)0x2000000000U) #endif /* LPTIM3 */ @@ -528,7 +531,6 @@ typedef struct #if defined(I3C2) #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) #endif /* I3C2 */ - /** * @} */ @@ -1209,6 +1211,7 @@ typedef struct */ #endif /* CEC */ +#if defined(USB_DRD_FS) /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source * @{ */ @@ -1222,6 +1225,7 @@ typedef struct /** * @} */ +#endif /* USB_DRD_FS */ /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection * @{ @@ -2361,9 +2365,13 @@ typedef struct * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock + * @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*) * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock + * * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. */ #define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL, (uint32_t)(__I3C2_CLKSOURCE__)) @@ -2371,8 +2379,11 @@ typedef struct /** @brief Macro to get the I3C2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock + * @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*) * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock + * + * (*) : Not available for all stm32h5xxxx family lines. */ #define __HAL_RCC_GET_I3C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL))) #endif /* I3C2 */ @@ -2921,6 +2932,7 @@ typedef struct #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CECSEL))) #endif /* CEC */ +#if defined(USB_DRD_FS) /** @brief Macro to configure the USB clock (USBCLK). * @param __USBCLKSource__ specifies the USB clock source. * This parameter can be one of the following values: @@ -2946,6 +2958,7 @@ typedef struct * (**) : For stm32h503xx family line. */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_USBSEL))) +#endif /* USB_DRD_FS */ /** @brief Macro to configure the Timers clocks prescalers * @param __PRESC__ specifies the Timers clocks prescalers selection @@ -3465,12 +3478,12 @@ typedef struct #if defined(RCC_CR_PLL3ON) #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ - ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \ ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) #else #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ - ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) #endif /* PLL3 */ #endif /* I3C2 */ @@ -3685,6 +3698,7 @@ typedef struct ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) #endif /* SPI6 */ +#if defined(USB_DRD_FS) #if defined(RCC_CR_PLL3ON) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ @@ -3696,6 +3710,7 @@ typedef struct ((__SOURCE__) == RCC_USBCLKSOURCE_PLL2Q) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) #endif /* RCC_CR_PLL3ON */ +#endif /* USB_DRD_FS */ #if defined(CEC) #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h index a3d9094206..62305aba3a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h @@ -212,7 +212,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); * @{ */ /* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h index 9aca3c85fb..ebd8b4d2cf 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h @@ -470,9 +470,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ -#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ -#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ +#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#if defined(COMP1) && defined(COMP2) +#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1848,9 +1851,15 @@ mode. /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) +#if defined(COMP1) && defined(COMP2) +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#endif /* COMP1 && COMP2 */ #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h index ca46864e66..70a501b5e4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h @@ -106,76 +106,119 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ +#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ #if defined(COMP1) -#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ #endif /* COMP1 */ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#if defined(COMP1) +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP1 */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ +#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ #if defined(COMP1) -#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ #endif /* COMP1 */ -#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ +#if defined(COMP2) +#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP2 */ +#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ #if defined(SAI1) -#define TIM_TIM2_ETR_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ -#define TIM_TIM2_ETR_SAI1_FSB (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 */ +#define TIM_TIM2_ETR_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 */ #endif /* SAI1 */ -#define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM3 ETR */ +#define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM3 ETR */ #if defined(TIM4) -#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM4 ETR */ +#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM4 ETR */ #endif /* TIM4 */ #if defined(TIM5) -#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM5 ETR */ +#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined(USB_DRD_FS) -#define TIM_TIM2_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USB SOF */ +#define TIM_TIM2_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USB SOF */ +#elif defined(USB_OTG_HS) +#define TIM_TIM2_ETR_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to USBHS OTG SOF */ +#define TIM_TIM2_ETR_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USBFS OTG SOF */ #endif /* USB_DRD_FS */ #if defined(ETH_NS) -#define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to ETH PPS */ +#define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(PLAY1) +#define TIM_TIM2_ETR_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< TIM2_ETR is connected to PLAY1 output 0 */ +#endif /* PLAY1 */ -#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ +#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ #if defined(COMP1) -#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ +#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ #endif /* COMP1 */ -#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ +#if defined(COMP2) +#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ +#endif /* COMP2 */ +#if defined(ADC2) +#define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM3_ETR_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC2 AWD3 */ +#endif /* ADC2 */ +#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ #if defined(TIM4) -#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to TIM4 ETR */ +#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to TIM4 ETR */ #endif /* TIM4 */ #if defined(TIM5) -#define TIM_TIM3_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM5 ETR */ +#define TIM_TIM3_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined(ETH_NS) -#define TIM_TIM3_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< TIM3_ETR is connected to ETH PPS */ +#define TIM_TIM3_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< TIM3_ETR is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(PLAY1) +#define TIM_TIM3_ETR_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< TIM3_ETR is connected to PLAY1 output 0 */ +#endif /* PLAY1 */ #if defined(TIM4) -#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ -#define TIM_TIM4_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM2 ETR */ -#define TIM_TIM4_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM3 ETR */ -#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */ +#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ +#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#define TIM_TIM4_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM2 ETR */ +#define TIM_TIM4_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM3 ETR */ +#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */ #endif /* TIM4 */ #if defined(TIM5) -#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ -#define TIM_TIM5_ETR_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 */ -#define TIM_TIM5_ETR_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 */ -#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */ -#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */ -#define TIM_TIM5_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM4 ETR */ +#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ +#define TIM_TIM5_ETR_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 */ +#define TIM_TIM5_ETR_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */ +#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */ +#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */ +#define TIM_TIM5_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM4 ETR */ #if defined(USB_DRD_FS) -#define TIM_TIM5_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USB SOF */ +#define TIM_TIM5_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USB SOF */ +#elif defined(USB_OTG_HS) +#define TIM_TIM5_ETR_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM5_ETR is connected to USBHS OTG SOF */ +#define TIM_TIM5_ETR_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USBFS OTG SOF */ #endif /* USB_DRD_FS */ #endif /* TIM5 */ #if defined(TIM8) -#define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */ -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */ +#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#if defined(ADC3) +#define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ +#endif /* ADC3 */ #endif /* TIM8 */ /** * @} @@ -197,6 +240,15 @@ typedef struct #if defined(COMP1) #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ #endif /* COMP1 */ +#if defined(COMP2) +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#endif /* COMP2 */ +#if defined(PLAY1) +#define TIM_BREAKINPUTSOURCE_PLAY1 0x00000008U /*!< The PLAY1 output is connected to the break input (only for BKIN) */ +#endif /* PLAY1 */ +#if defined(MDF1) +#define TIM_BREAKINPUTSOURCE_MDF1 0x00000100U /*!< The Digital filter break output is connected to the break input */ +#endif /* MDF1 */ /** * @} */ @@ -223,9 +275,12 @@ typedef struct * @{ */ #define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ -#if defined(COMP1) +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP1 OUT */ +#define TIM_TIM1_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1_TI1 is connected to COMP2 OUT */ +#elif defined(COMP1) #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ -#endif /* COMP1 */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM1_TI2_GPIO 0x00000000UL /*!< TIM1_TI2 is connected to GPIO */ #define TIM_TIM1_TI3_GPIO 0x00000000UL /*!< TIM1_TI3 is connected to GPIO */ #define TIM_TIM1_TI4_GPIO 0x00000000UL /*!< TIM1_TI4 is connected to GPIO */ @@ -240,6 +295,11 @@ typedef struct #if defined(ETH_NS) #define TIM_TIM2_TI1_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP1 output */ +#define TIM_TIM2_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to COMP2 output */ +#define TIM_TIM2_TI1_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to PLAY1 output 3 */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ #if defined(STM32H503xx) #define TIM_TIM2_TI2_HSI_1024 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to HSI_1024 */ @@ -247,11 +307,15 @@ typedef struct #define TIM_TIM2_TI2_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */ #define TIM_TIM2_TI2_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */ #endif /* STM32H503xx */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 output */ +#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_TI3_GPIO 0x00000000UL /*!< TIM2_TI3 is connected to GPIO */ #define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ -#if defined(COMP1) +#if defined(STM32H503xx) #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 */ -#endif /* COMP1 */ +#endif /* STM32H503xx */ #define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ #if defined(STM32H503xx) @@ -263,17 +327,30 @@ typedef struct #if defined(ETH_NS) #define TIM_TIM3_TI1_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP1 output */ +#define TIM_TIM3_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to COMP2 output */ +#define TIM_TIM3_TI1_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to PLAY1 output 3 */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ #if defined(STM32H503xx) #define TIM_TIM3_TI2_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */ #define TIM_TIM3_TI2_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */ #define TIM_TIM3_TI2_HSI_1024 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM3_TI2 is connected to HSI 1024 */ #endif /* STM32H503xx */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 output */ +#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM3_TI3_GPIO 0x00000000UL /*!< TIM3_TI3 is connected to GPIO */ #define TIM_TIM3_TI4_GPIO 0x00000000UL /*!< TIM3_TI4 is connected to GPIO */ #if defined(TIM4) #define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP1 output */ +#define TIM_TIM4_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */ #define TIM_TIM4_TI3_GPIO 0x00000000UL /*!< TIM4_TI3 is connected to GPIO */ #define TIM_TIM4_TI4_GPIO 0x00000000UL /*!< TIM4_TI4 is connected to GPIO */ @@ -281,6 +358,10 @@ typedef struct #if defined(TIM5) #define TIM_TIM5_TI1_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to COMP1 output */ +#define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM5_TI2_GPIO 0x00000000UL /*!< TIM5_TI2 is connected to GPIO */ #define TIM_TIM5_TI3_GPIO 0x00000000UL /*!< TIM5_TI3 is connected to GPIO */ #define TIM_TIM5_TI4_GPIO 0x00000000UL /*!< TIM5_TI4 is connected to GPIO */ @@ -288,6 +369,10 @@ typedef struct #if defined(TIM8) #define TIM_TIM8_TI1_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP1 output */ +#define TIM_TIM8_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM8_TI2_GPIO 0x00000000UL /*!< TIM8_TI2 is connected to GPIO */ #define TIM_TIM8_TI3_GPIO 0x00000000UL /*!< TIM8_TI3 is connected to GPIO */ #define TIM_TIM8_TI4_GPIO 0x00000000UL /*!< TIM8_TI4 is connected to GPIO */ @@ -295,16 +380,38 @@ typedef struct #if defined(TIM12) #define TIM_TIM12_TI1_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM12_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM12_TI1 is connected to COMP1 output */ +#define TIM_TIM12_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM12_TI1_HSI_1024 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to HSI 1024 */ #define TIM_TIM12_TI1_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */ +#define TIM_TIM12_TI2_GPIO 0x00000000UL /*!< TIM12_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM12_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM12_TI2 is connected to COMP2 output */ +#endif /* COMP2 */ #endif /* TIM12 */ #if defined(TIM13) #define TIM_TIM13_TI1_GPIO 0x00000000UL /*!< TIM13_TI1 is connected to GPIO */ +#if defined(I3C1) +#define TIM_TIM13_TI1_I3C1_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM13_TI1 is connected to I3C1 IBI ACK */ +#endif /* I3C1 */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM13_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM13_TI1 is connected to COMP1 output */ +#define TIM_TIM13_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM13_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #endif /* TIM13 */ #if defined(TIM14) #define TIM_TIM14_TI1_GPIO 0x00000000UL /*!< TIM14_TI1 is connected to GPIO */ +#if defined(I3C2) +#define TIM_TIM14_TI1_I3C2_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM14_TI1 is connected to I3C2 IBI ACK */ +#endif /* I3C1 */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM14_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM14_TI1 is connected to COMP1 output */ +#define TIM_TIM14_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM14_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #endif /* TIM14 */ #if defined(TIM15) @@ -315,10 +422,18 @@ typedef struct #define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */ #define TIM_TIM15_TI1_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to CSI 128*/ #define TIM_TIM15_TI1_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM15_TI1 is connected to COMP1 output */ +#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ #define TIM_TIM15_TI2_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */ #define TIM_TIM15_TI2_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */ #define TIM_TIM15_TI2_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM15_TI2_COMP1 TIM_TISEL_TI2SEL_2 /*!< TIM15_TI2 is connected to COMP1 output */ +#define TIM_TIM15_TI2_COMP2 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #endif /* TIM15 */ #if defined(TIM16) @@ -326,12 +441,20 @@ typedef struct #define TIM_TIM16_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */ #define TIM_TIM16_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */ #define TIM_TIM16_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM16_TI1_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to COMP1 output */ +#define TIM_TIM16_TI1_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #endif /* TIM16 */ #if defined(TIM17) #define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ #define TIM_TIM17_TI1_HSE_1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to HSE 1MHZ */ #define TIM_TIM17_TI1_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM17_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to COMP1 output */ +#define TIM_TIM17_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #endif /* TIM17 */ /** * @} @@ -513,12 +636,18 @@ typedef struct #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) -#if defined(COMP1) +#if defined(COMP1) && defined(COMP2) +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_PLAY1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) +#elif defined(COMP1) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1)) #else #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) -#endif /* COMP1 */ +#endif /* COMP1 && COMP2 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h index f3cada0ed2..df476df8ad 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h @@ -1243,7 +1243,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1258,8 +1258,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h index d1721e25f0..889ee2dd65 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h @@ -710,8 +710,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h index e4f1f3fc9e..3bb5f15564 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_xspi.h @@ -824,12 +824,12 @@ typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup XSPI_Exported_Functions +/** @addtogroup XSPI_Exported_Functions XSPI Exported Functions * @{ */ /* Initialization/de-initialization functions ********************************/ -/** @addtogroup XSPI_Exported_Functions_Group1 +/** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); @@ -842,7 +842,7 @@ void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); */ /* IO operation functions *****************************************************/ -/** @addtogroup XSPI_Exported_Functions_Group2 +/** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* XSPI IRQ handler function */ @@ -858,11 +858,11 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_Hyper uint32_t Timeout); /* XSPI indirect mode functions */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); /* XSPI status flag polling mode functions */ @@ -903,7 +903,7 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL */ /* Peripheral Control and State functions ************************************/ -/** @addtogroup XSPI_Exported_Functions_Group3 +/** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions * @{ */ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); @@ -1048,7 +1048,6 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) - #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h index 97871a6f29..3973a6c567 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h @@ -111,6 +111,9 @@ extern "C" { #define LL_AHB1_GRP1_PERIPH_ETHTX RCC_AHB1ENR_ETHTXEN #define LL_AHB1_GRP1_PERIPH_ETHRX RCC_AHB1ENR_ETHRXEN #endif /* ETH */ +#if defined(RCC_AHB1ENR_ETHCKEN) +#define LL_AHB1_GRP1_PERIPH_ETHINTERN RCC_AHB1ENR_ETHCKEN +#endif /* RCC_AHB1ENR_ETHCKEN */ #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_TZSC1EN @@ -173,7 +176,6 @@ extern "C" { #if defined(SRAM3_BASE) #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR_SRAM3EN #endif /* SRAM3_BASE */ - /** * @} */ @@ -328,7 +330,9 @@ extern "C" { #if defined(SAI2) #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN #endif /* SAI2 */ +#if defined(USB_DRD_FS) #define LL_APB2_GRP1_PERIPH_USB RCC_APB2ENR_USBEN +#endif /* USB_DRD_FS */ /** * @} */ @@ -617,7 +621,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR ETHRXEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TZSC1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR BKPRAMEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DCACHE1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DCACHE1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL @@ -716,7 +720,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_EnableClockSleep\n * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_EnableClockSleep\n * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n - * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_EnableClockSleep\n * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL @@ -1334,7 +1338,6 @@ __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 * @retval None */ __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) @@ -2233,6 +2236,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2321,6 +2325,7 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB + * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -2512,7 +2517,6 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2554,7 +2558,6 @@ __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2592,7 +2595,6 @@ __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2628,7 +2630,6 @@ __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2663,7 +2664,6 @@ __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2700,7 +2700,6 @@ __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2743,7 +2742,6 @@ __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) @@ -2781,7 +2779,6 @@ __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs) * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h index 339d86dcb0..5adeee312f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h @@ -193,7 +193,22 @@ typedef struct #if defined(EXTI_IMR2_IM58) #define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ #endif /* EXTI_IMR2_IM58 */ -#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< ALL Extended line */ +#if defined(EXTI_IMR2_IM59) +#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ +#endif /* EXTI_IMR2_IM59 */ +#if defined(EXTI_IMR2_IM60) +#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ +#endif /* EXTI_IMR2_IM60 */ +#if defined(EXTI_IMR2_IM61) +#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ +#endif /* EXTI_IMR2_IM61 */ +#if defined(EXTI_IMR2_IM62) +#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ +#endif /* EXTI_IMR2_IM62 */ +#if defined(EXTI_IMR2_IM63) +#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ +#endif /* EXTI_IMR2_IM63 */ +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< ALL Extended lines */ #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ @@ -494,6 +509,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -502,7 +518,6 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) CLEAR_BIT(EXTI->IMR2, ExtiLine); } - /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 * @note The reset value for the direct or internal lines (see RM) @@ -584,6 +599,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -677,6 +693,7 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -761,6 +778,7 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -845,6 +863,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -909,6 +928,7 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @note Please check each device line mapping for EXTI Line availability @@ -968,8 +988,11 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1013,8 +1036,11 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1023,7 +1049,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); } - /** * @} */ @@ -1082,6 +1107,7 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1090,7 +1116,6 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) SET_BIT(EXTI->FTSR2, ExtiLine); } - /** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must be @@ -1139,6 +1164,8 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1147,7 +1174,6 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) CLEAR_BIT(EXTI->FTSR2, ExtiLine); } - /** * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 @@ -1184,6 +1210,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1192,7 +1219,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); } - /** * @} */ @@ -1247,6 +1273,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1255,7 +1282,6 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) SET_BIT(EXTI->SWIER2, ExtiLine); } - /** * @} */ @@ -1304,6 +1330,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1352,6 +1379,7 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ @@ -1400,6 +1428,7 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1408,7 +1437,6 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine) WRITE_REG(EXTI->FPR2, ExtiLine); } - /** * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 * @note This bit is set when the Rising edge event arrives on the interrupt @@ -1449,6 +1477,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1497,6 +1526,7 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ @@ -1545,6 +1575,7 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 + * * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1588,6 +1619,8 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * @arg @ref LL_EXTI_EXTI_PORTK (*) * * (*) value not defined in all devices * @param Line This parameter can be one of the following values: @@ -1660,6 +1693,8 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * @arg @ref LL_EXTI_EXTI_PORTK (*) * * (*) value not defined in all devices */ @@ -2074,7 +2109,7 @@ __STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Privilege attribute for Lines in range 32 to 63 - * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_EnablePrivilege_32_63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_DisablePrivilege_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h index 233859af52..121258f9e2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h @@ -213,74 +213,75 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE */ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ + @note: This parameter is common to all NSBank. */ } FMC_NORSRAM_InitTypeDef; /** @@ -329,7 +330,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ @@ -1137,11 +1138,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -1169,11 +1170,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1184,7 +1185,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -1202,9 +1203,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1216,7 +1217,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h index 72db31d699..a5c0c6020b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h @@ -32,7 +32,7 @@ extern "C" { */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) /** @defgroup GPIO_LL GPIO * @{ @@ -1169,7 +1169,8 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ + defined (GPIOK) */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h index 56c7fad086..ee4a74ccc1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h @@ -912,6 +912,7 @@ typedef struct * @} */ +#if defined(USB_DRD_FS) /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection * @{ */ @@ -924,6 +925,7 @@ typedef struct /** * @} */ +#endif /* USB_DRD_FS */ /** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCDAC clock source selection * @{ @@ -1124,6 +1126,7 @@ typedef struct * @} */ +#if defined(USB_DRD_FS) /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source * @{ */ @@ -1131,6 +1134,7 @@ typedef struct /** * @} */ +#endif /* USB_DRD_FS */ /** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source * @{ @@ -2807,7 +2811,6 @@ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n * CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource * @param I3CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*) * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI @@ -3003,6 +3006,7 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, RNGxSource); } +#if defined(USB_DRD_FS) /** * @brief Configure USB clock source * @rmtoll CCIPR4 USBSEL LL_RCC_SetUSBClockSource @@ -3019,6 +3023,7 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, USBxSource); } +#endif /* USB_DRD_FS */ /** * @brief Configure ADCx kernel clock source @@ -3728,7 +3733,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) /** * @brief Get SDMMCx kernel clock source * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_GetSDMMCClockSource - * CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource + * rmtoll CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource * @param SDMMCx This parameter can be one of the following values: * @arg @ref LL_RCC_SDMMC1_CLKSOURCE * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) @@ -3762,6 +3767,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) return (uint32_t)(READ_BIT(RCC->CCIPR5, RNGx)); } +#if defined(USB_DRD_FS) /** * @brief Get USB clock source * @rmtoll CCIPR4 USBSEL LL_RCC_GetUSBClockSource @@ -3779,6 +3785,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { return (uint32_t)(READ_BIT(RCC->CCIPR4, USBx)); } +#endif /* USB_DRD_FS */ /** * @brief Get ADCDACx kernel clock source @@ -6037,7 +6044,9 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); #endif /* SDMMC1 */ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#if defined(USB_DRD_FS) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_DRD_FS */ uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource); uint32_t LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource); #if defined(OCTOSPI1) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h index 600b92d56e..eaa79df907 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h @@ -674,6 +674,9 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ WRITE_REG(RNGx->HTCR, HTCFG); } @@ -691,6 +694,42 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** * @} */ +#if defined(RNG_NSCR_NIST_VALUE) + +/** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control + * @{ + */ + +/** + * @brief Set RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_SetNoiseConfig + * @param RNGx RNG Instance + * @param NOISECFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) +{ + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ + WRITE_REG(RNGx->NSCR, NOISECFG); +} + +/** + * @brief Get RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_GetNoiseConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) +{ + + return (uint32_t)READ_REG(RNGx->NSCR); +} + +/** + * @} + */ + +#endif /* defined(RNG_NSCR_NIST_VALUE) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h index 2f31329834..5984bb4e99 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h @@ -3507,7 +3507,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32 /** * @brief Enable backup register erase after internal tamper event detection * @rmtoll TAMP_CR3 ITAMP1NOER LL_RTC_TAMPER_ITAMP_EnableEraseBKP - * TAMP_CR3 ITAMP2NOER... LL_RTC_TAMPER_ITAMP_EnableEraseBKP + * @rmtoll TAMP_CR3 ITAMP2NOER LL_RTC_TAMPER_ITAMP_EnableEraseBKP * @param RTCx RTC Instance * @param InternalTamper This parameter can be a combination of the following values: * @arg @ref RTC_LL_EC_ITAMPER_NOERASE @@ -3523,7 +3523,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_EnableEraseBKP(const RTC_TypeDef *RTCx, /** * @brief Disable backup register erase after internal tamper event detection * @rmtoll TAMP_CR3 ITAMP1NOER LL_RTC_TAMPER_ITAMP_DisableEraseBKP - * TAMP_CR3 ITAMP2NOER... LL_RTC_TAMPER_ITAMP_DisableEraseBKP + * @rmtoll TAMP_CR3 ITAMP2NOER LL_RTC_TAMPER_ITAMP_DisableEraseBKP * @param RTCx RTC Instance * @param InternalTamper This parameter can be a combination of the following values: * @arg @ref RTC_LL_EC_ITAMPER_NOERASE diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h index fce911fa32..e8e2c44d21 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h @@ -213,8 +213,6 @@ extern "C" { #define LL_SBS_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */ #define LL_SBS_FPU_SEC SBS_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */ #define LL_SBS_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */ -#define LL_SBS_SMPS_SEC SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS configuration secure-only access */ -#define LL_SBS_SMPS_NSEC 0U /*!< SMPS configuration secure/non-secure access */ /** * @} */ @@ -822,7 +820,6 @@ __STATIC_INLINE uint32_t LL_SBS_GetAuthDbgSec(void) { return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos); } - #endif /* SBS_DBGCR_DBG_AUTH_SEC */ /** @@ -976,7 +973,6 @@ __STATIC_INLINE uint32_t LL_SBS_GetSecureLock(void) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /** * @brief Configure Secure mode * @note Only available from secure state when system implements security (TZEN=1) @@ -1010,7 +1006,6 @@ __STATIC_INLINE uint32_t LL_SBS_GetConfigSecure(void) { return (uint32_t)(READ_BIT(SBS->SECCFGR, LL_SBS_CLOCK_SEC | LL_SBS_CLASSB_SEC | LL_SBS_FPU_SEC)); } - #endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */ /** @@ -1027,7 +1022,7 @@ __STATIC_INLINE uint32_t LL_SBS_GetConfigSecure(void) /** * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD - * @rmtoll CCVALR PCV1 LL_SBS_GetPMOSVddCompensationValue + * @rmtoll CCVALR APSRC1 LL_SBS_GetPMOSVddCompensationValue * @retval Returned value is the PMOS compensation cell */ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationValue(void) @@ -1037,7 +1032,7 @@ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationValue(void) /** * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD - * @rmtoll CCVALR NCV1 LL_SBS_GetNMOSVddCompensationValue + * @rmtoll CCVALR ANSRC1 LL_SBS_GetNMOSVddCompensationValue * @retval Returned value is the NMOS compensation cell */ __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationValue(void) @@ -1047,7 +1042,7 @@ __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationValue(void) /** * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 - * @rmtoll CCVALR PCV2 LL_SBS_GetPMOSVddIO2CompensationValue + * @rmtoll CCVALR APSRC2 LL_SBS_GetPMOSVddIO2CompensationValue * @retval Returned value is the PMOS compensation cell */ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIO2CompensationValue(void) @@ -1057,7 +1052,7 @@ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIO2CompensationValue(void) /** * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 - * @rmtoll CCVALR NCV2 LL_SBS_GetNMOSVddIO2CompensationValue + * @rmtoll CCVALR ANSRC2 LL_SBS_GetNMOSVddIO2CompensationValue * @retval Returned value is the NMOS compensation cell */ __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIO2CompensationValue(void) @@ -1067,7 +1062,7 @@ __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIO2CompensationValue(void) /** * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD - * @rmtoll CCSWCR PCC1 LL_SBS_SetPMOSVddCompensationCode + * @rmtoll CCSWCR SW_APSRC1 LL_SBS_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the * SBS_CCCSR is set @@ -1080,7 +1075,7 @@ __STATIC_INLINE void LL_SBS_SetPMOSVddCompensationCode(uint32_t PMOSCode) /** * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD - * @rmtoll CCSWCR PCC1 LL_SBS_GetPMOSVddCompensationCode + * @rmtoll CCSWCR SW_APSRC1 LL_SBS_GetPMOSVddCompensationCode * @retval Returned value is the PMOS compensation cell */ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationCode(void) @@ -1090,7 +1085,7 @@ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationCode(void) /** * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO - * @rmtoll CCSWCR PCC2 LL_SBS_SetPMOSVddIOCompensationCode + * @rmtoll CCSWCR SW_APSRC2 LL_SBS_SetPMOSVddIOCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS2 bit of the * SBS_CCCSR is set @@ -1101,10 +1096,9 @@ __STATIC_INLINE void LL_SBS_SetPMOSVddIOCompensationCode(uint32_t PMOSCode) MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2, PMOSCode << SBS_CCSWCR_SW_APSRC2_Pos); } - /** * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO - * @rmtoll CCSWCR PCC2 LL_SBS_GetPMOSVddIOCompensationCode + * @rmtoll CCSWCR SW_APSRC2 LL_SBS_GetPMOSVddIOCompensationCode * @retval Returned value is the PMOS compensation */ __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIOCompensationCode(void) @@ -1239,7 +1233,7 @@ __STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddCMPCR(void) /** * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO - * @rmtoll CCCSR RDY1 LL_SBS_IsActiveFlag_VddIOCMPCR + * @rmtoll CCCSR RDY2 LL_SBS_IsActiveFlag_VddIOCMPCR * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddIOCMPCR(void) @@ -1816,4 +1810,4 @@ __STATIC_INLINE uint32_t LL_SBS_GetEraseAfterResetStatus(void) } #endif -#endif /* STM32h5xx_LL_SYSTEM_H */ +#endif /* STM32H5xx_LL_SYSTEM_H */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h index eb74d71439..5518f44143 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h @@ -161,6 +161,8 @@ static const uint8_t SHIFT_TAB_OISx[] = @endcond */ +#define OCREF_CLEAR_SELECT_POS (28U) +#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ /** * @} */ @@ -1043,7 +1045,10 @@ typedef struct #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #if defined(COMP1) #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ -#endif /* COMP1*/ +#endif /* COMP1 */ +#if defined(COMP2) +#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP2 */ #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */ #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC1 analog watchdog 2 */ #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */ @@ -1057,7 +1062,10 @@ typedef struct #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #if defined(COMP1) #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ -#endif /* COMP1*/ +#endif /* COMP1 */ +#if defined(COMP2) +#define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP2 */ #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ #if defined(SAI1) #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to SAI1_FSA */ @@ -1072,10 +1080,16 @@ typedef struct #endif /* TIM5 */ #if defined(USB_DRD_FS) #define LL_TIM_TIM2_ETRSOURCE_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to USB SOF */ +#elif defined(USB_OTG_HS) +#define LL_TIM_TIM2_ETRSOURCE_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR is connected to USBHS OTG SOF */ +#define LL_TIM_TIM2_ETRSOURCE_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR is connected to USBFS OTG SOF */ #endif /* USB_DRD_FS */ #if defined(ETH_NS) #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(PLAY1) +#define LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< ETR input is connected to PLAY1 output 0 */ +#endif /* PLAY1 */ /** * @} */ @@ -1086,7 +1100,15 @@ typedef struct #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #if defined(COMP1) #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ -#endif /* COMP1*/ +#endif /* COMP1 */ +#if defined(COMP2) +#define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP2 */ +#if defined(ADC2) +#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */ +#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC2 analog watchdog 2 */ +#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */ +#endif /* ADC2 */ #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ #if defined(TIM4) #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */ @@ -1097,6 +1119,9 @@ typedef struct #if defined(ETH_NS) #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(PLAY1) +#define LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< ETR input is connected to PLAY1 output 0 */ +#endif /* PLAY1 */ /** * @} */ @@ -1105,10 +1130,14 @@ typedef struct /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4 * @{ */ -#define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ -#define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ -#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ -#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ +#define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ +#define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ +#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ +#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ /** * @} */ @@ -1121,11 +1150,18 @@ typedef struct #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to SAI2_FSA */ #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to SAI2_FSB */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM5_ETRSOURCE_COMP1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP1_OUT */ +#define LL_TIM_TIM5_ETRSOURCE_COMP2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */ #define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */ #if defined(USB_DRD_FS) #define LL_TIM_TIM5_ETRSOURCE_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to USB SOF */ +#elif defined(USB_OTG_HS) +#define LL_TIM_TIM5_ETRSOURCE_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR is connected to USBHS OTG SOF */ +#define LL_TIM_TIM5_ETRSOURCE_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR is connected to USBFS OTG SOF */ #endif /* USB_DRD_FS */ /** * @} @@ -1137,9 +1173,18 @@ typedef struct * @{ */ #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ -#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC4 analog watchdog 2 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC2 analog watchdog 2 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */ +#if defined(ADC3) +#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 1 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 3 */ +#endif /* ADC3 */ /** * @} */ @@ -1243,6 +1288,15 @@ typedef struct #if defined(COMP1) #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */ #endif /* COMP1 */ +#if defined(COMP2) +#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */ +#endif /* COMP2 */ +#if defined(PLAY1) +#define LL_TIM_BKIN_SOURCE_PLAY1 TIM1_AF1_BKCMP3E /*!< internal signal: PLAY1 output */ +#endif /* PLAY1 */ +#if defined(MDF1) +#define LL_TIM_BKIN_SOURCE_MDF1 TIM1_AF1_BKDF1BK0E /*!< internal signal: Digital filter break output */ +#endif /* MDF1 */ /** * @} */ @@ -1366,10 +1420,13 @@ typedef struct /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap * @{ */ -#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL -#if defined(COMP1) -#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 -#endif /* COMP1 */ +#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM1_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1_TI1 is connected to COMP2 output */ +#elif defined(COMP1) +#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1377,16 +1434,21 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap * @{ */ -#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ +#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ #if defined(STM32H503xx) -#define LL_TIM_TIM2_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to LSI */ -#define LL_TIM_TIM2_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to LSE */ -#define LL_TIM_TIM2_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to RTC */ +#define LL_TIM_TIM2_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to LSI */ +#define LL_TIM_TIM2_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to LSE */ +#define LL_TIM_TIM2_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to RTC */ #define LL_TIM_TIM2_TI1_RMP_TIM3_TI1 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to TIM3 TI1 */ #endif /* STM32H503xx */ #if defined(ETH_NS) -#define LL_TIM_TIM2_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH_ PPS */ +#define LL_TIM_TIM2_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM2_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to COMP2 output */ +#define LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to PLAY1 output 3 */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1394,13 +1456,17 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 External Input Ch2 Remap * @{ */ -#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ +#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ #if defined(STM32H503xx) #define LL_TIM_TIM2_TI2_RMP_HSI_1024 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to HSI_1024 */ -#define LL_TIM_TIM2_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to CSI_128 */ -#define LL_TIM_TIM2_TI2_RMP_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */ -#define LL_TIM_TIM2_TI2_RMP_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */ +#define LL_TIM_TIM2_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to CSI_128 */ +#define LL_TIM_TIM2_TI2_RMP_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */ +#define LL_TIM_TIM2_TI2_RMP_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */ #endif /* STM32H503xx */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 output */ +#define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1409,9 +1475,9 @@ typedef struct * @{ */ #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ -#if defined(COMP1) -#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI2 is connected to COMP1 */ -#endif /* COMP1 */ +#if defined(STM32H503xx) +#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 output */ +#endif /* STM32H503xx */ /** * @} */ @@ -1419,16 +1485,21 @@ typedef struct /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap * @{ */ -#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ +#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ #if defined(STM32H503xx) -#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 */ -#define LL_TIM_TIM3_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to MCO1 */ -#define LL_TIM_TIM3_TI1_RMP_TIM2_TI1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to TIM2 TI1 */ -#define LL_TIM_TIM3_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to HSE 1MHZ */ +#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM3_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to MCO1 */ +#define LL_TIM_TIM3_TI1_RMP_TIM2_TI1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to TIM2 TI1 */ +#define LL_TIM_TIM3_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to HSE 1MHZ */ #endif /* STM32H503xx */ #if defined(ETH_NS) -#define LL_TIM_TIM3_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */ +#define LL_TIM_TIM3_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to ETH PPS */ #endif /* ETH_NS */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to COMP2 output */ +#define LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to PLAY1 output 3 */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1436,39 +1507,138 @@ typedef struct /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap * @{ */ -#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ +#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ #if defined(STM32H503xx) -#define LL_TIM_TIM3_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */ -#define LL_TIM_TIM3_TI2_RMP_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */ +#define LL_TIM_TIM3_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */ +#define LL_TIM_TIM3_TI2_RMP_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */ #define LL_TIM_TIM3_TI2_RMP_HSI_1024 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM3_TI2 is connected to HSI 1024 */ #endif /* STM32H503xx */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 output */ +#define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ + +#if defined(TIM4) +/** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 External Input Ch1 Remap + * @{ + */ +#define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM4_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ +#endif /* TIM4 */ + +#if defined(TIM5) +/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 External Input Ch1 Remap + * @{ + */ +#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ +#endif /* TIM5 */ + +#if defined(TIM8) +/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap + * @{ + */ +#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ +#endif /* TIM8 */ #if defined(TIM12) /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 External Input Ch1 Remap * @{ */ -#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */ +#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM12_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM12_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM12_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define LL_TIM_TIM12_TI1_RMP_HSI_1024 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to HSI 1024 */ -#define LL_TIM_TIM12_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */ +#define LL_TIM_TIM12_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_TIM12_TI2_RMP TIM12 External Input Ch2 Remap + * @{ + */ +#define LL_TIM_TIM12_TI2_RMP_GPIO 0x00000000UL /*!< TIM12_TI2 is connected to GPIO */ +#if defined(COMP2) +#define LL_TIM_TIM12_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM12_TI2 is connected to COMP2 output */ +#endif /* COMP2 */ /** * @} */ #endif /* TIM12 */ +#if defined(TIM13) +/** @defgroup TIM_LL_EC_TIM13_TI1_RMP TIM13 External Input Ch1 Remap + * @{ + */ +#define LL_TIM_TIM13_TI1_RMP_GPIO 0x00000000UL /*!< TIM13_TI1 is connected to GPIO */ +#if defined(I3C1) +#define LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM13_TI1 is connected to I3C1 IBI ACK */ +#endif /* I3C1 */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM13_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM13_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM13_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM13_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ +#endif /* TIM13 */ + +#if defined(TIM14) +/** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 External Input Ch1 Remap + * @{ + */ +#define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000UL /*!< TIM14_TI1 is connected to GPIO */ +#if defined(I3C2) +#define LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM14_TI1 is connected to I3C2 IBI ACK */ +#endif /* I3C1 */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM14_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM14_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM14_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM14_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ +#endif /* TIM14 */ + #if defined(TIM15) /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap * @{ */ -#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ -#define LL_TIM_TIM15_TI1_RMP_TIM2 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 */ -#define LL_TIM_TIM15_TI1_RMP_TIM3 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 */ -#define LL_TIM_TIM15_TI1_RMP_TIM4 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 */ -#define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */ +#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ +#define LL_TIM_TIM15_TI1_RMP_TIM2 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 */ +#define LL_TIM_TIM15_TI1_RMP_TIM3 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 */ +#define LL_TIM_TIM15_TI1_RMP_TIM4 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 */ +#define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */ #define LL_TIM_TIM15_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to CSI 128*/ -#define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */ +#define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM15_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1476,10 +1646,14 @@ typedef struct /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap * @{ */ -#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ -#define LL_TIM_TIM15_TI2_RMP_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */ -#define LL_TIM_TIM15_TI2_RMP_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */ -#define LL_TIM_TIM15_TI2_RMP_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */ +#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ +#define LL_TIM_TIM15_TI2_RMP_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */ +#define LL_TIM_TIM15_TI2_RMP_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */ +#define LL_TIM_TIM15_TI2_RMP_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM15_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_2 /*!< TIM15_TI2 is connected to COMP1 output */ +#define LL_TIM_TIM15_TI2_RMP_COMP2 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1490,9 +1664,13 @@ typedef struct * @{ */ #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ -#define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */ -#define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */ -#define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */ +#define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */ +#define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */ +#define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM16_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM16_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1502,9 +1680,13 @@ typedef struct /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap * @{ */ -#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ +#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ #define LL_TIM_TIM17_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to HSE 1MHZ */ -#define LL_TIM_TIM17_TI1_RMP_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */ +#define LL_TIM_TIM17_TI1_RMP_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM17_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to COMP1 output */ +#define LL_TIM_TIM17_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1513,8 +1695,11 @@ typedef struct /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection * @{ */ -#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */ -#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ +#define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */ +#define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -3933,6 +4118,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 @@ -3941,6 +4127,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (*) @@ -3948,21 +4135,30 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_USB_SOF (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_USBHS_SOF (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_USBFS_SOF (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS (*) - + * @arg @ref LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0 (*) * * TIM3: any combination of ETR_RMP where * * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0 (*) * * TIM4: any combination of ETR_RMP where (**) * * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR @@ -3972,18 +4168,27 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB + * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR * @arg @ref LL_TIM_TIM5_ETRSOURCE_USB_SOF (*) + * @arg @ref LL_TIM_TIM5_ETRSOURCE_USBHS_SOF (*) + * @arg @ref LL_TIM_TIM5_ETRSOURCE_USBFS_SOF (*) * * TIM8: any combination of ETR_RMP where (**) * * . . ETR_RMP can be one of the following values * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*) + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*) + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*) * * (*) Value not defined in all devices. \n * (**) Timer instance not available on all devices. \n @@ -4357,15 +4562,24 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n + * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n * AF2 BK2INE LL_TIM_EnableBreakInputSource\n * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n + * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_PLAY1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_MDF1 (*) * * (*) Value not defined in all devices. * @retval None @@ -4382,15 +4596,24 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n + * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n * AF2 BK2INE LL_TIM_DisableBreakInputSource\n * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource\n + * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_PLAY1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_MDF1 (*) * * (*) Value not defined in all devices. * @retval None @@ -4407,15 +4630,21 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_PLAY1 (*) * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_POLARITY_LOW * @arg @ref LL_TIM_BKIN_POLARITY_HIGH @@ -4858,17 +5087,16 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM12_TISEL TI2SEL LL_TIM_SetRemap\n * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM17_TISEL TI1SEL LL_TIM_SetRemap * * @param TIMx Timer instance * @param Remap Remap param depends on the TIMx. Description available only @@ -4879,69 +5107,78 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * * TIM1: one of the following values: * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO - * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*) - * @arg LL_TIM_TIM1_TI2_RMP_GPIO: TIM1 TI2 is connected to GPIO - * @arg LL_TIM_TIM1_TI3_RMP_GPIO: TIM1 TI3 is connected to GPIO - * @arg LL_TIM_TIM1_TI4_RMP_GPIO: TIM1 TI4 is connected to GPIO + * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*) * * TIM2: one of the following values: * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO - * @arg LL_TIM_TIM2_TI1_RMP_LSI: TIM2 TI1 is connected to LSI (*) - * @arg LL_TIM_TIM2_TI1_RMP_LSE: TIM2 TI1 is connected to LSE (*) - * @arg LL_TIM_TIM2_TI1_RMP_RTC: TIM2 TI1 is connected to RTC (*) - * @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1: TIM2 TI1 is connected to TIM3 TI1 (*) - * @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS: TIM2 TI1 is connected to ETH PPS (*) + * @arg LL_TIM_TIM2_TI1_RMP_LSI: TIM2 TI1 is connected to LSI (*) + * @arg LL_TIM_TIM2_TI1_RMP_LSE: TIM2 TI1 is connected to LSE (*) + * @arg LL_TIM_TIM2_TI1_RMP_RTC: TIM2 TI1 is connected to RTC (*) + * @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1: TIM2 TI1 is connected to TIM3 TI1 (*) + * @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS: TIM2 TI1 is connected to ETH PPS (*) + * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output (*) + * @arg LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3: TIM2 TI1 is connected to PLAY1 output 3 (*) * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO - * @arg LL_TIM_TIM2_TI2_RMP_HSI_1024: TIM2 TI2 is connected to HSI 1024 (*) - * @arg LL_TIM_TIM2_TI2_RMP_CSI_128: TIM2 TI2 is connected to CSI 128 (*) - * @arg LL_TIM_TIM2_TI2_RMP_MCO2: TIM2 TI2 is connected to MCO2 (*) - * @arg LL_TIM_TIM2_TI2_RMP_MCO1: TIM2 TI2 is connected to MCO1 (*) - * @arg LL_TIM_TIM2_TI3_RMP_GPIO: TIM2 TI3 is connected to GPIO + * @arg LL_TIM_TIM2_TI2_RMP_HSI_1024: TIM2 TI2 is connected to HSI 1024 (*) + * @arg LL_TIM_TIM2_TI2_RMP_CSI_128: TIM2 TI2 is connected to CSI 128 (*) + * @arg LL_TIM_TIM2_TI2_RMP_MCO2: TIM2 TI2 is connected to MCO2 (*) + * @arg LL_TIM_TIM2_TI2_RMP_MCO1: TIM2 TI2 is connected to MCO1 (*) + * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI2 is connected to COMP1 output (*) + * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI2 is connected to COMP2 output (*) * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO - * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 (*) + * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 (*) * * TIM3: one of the following values: * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO - * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*) - * @arg LL_TIM_TIM3_TI1_RMP_MCO1: TIM3 TI1 is connected to MCO1 (*) - * @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1: TIM3 TI1 is connected to TIM2 TI1 (*) - * @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ: TIM3 TI1 is connected to HSE_1MHZ (*) - * @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS: TIM3 TI1 is connected to ETH PPS (*) + * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*) + * @arg LL_TIM_TIM3_TI1_RMP_MCO1: TIM3 TI1 is connected to MCO1 (*) + * @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1: TIM3 TI1 is connected to TIM2 TI1 (*) + * @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ: TIM3 TI1 is connected to HSE_1MHZ (*) + * @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS: TIM3 TI1 is connected to ETH PPS (*) + * @arg LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3: TIM3 TI1 is connected to PLAY1 output 3 (*) * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO - * @arg LL_TIM_TIM3_TI2_RMP_CSI_128: TIM3 TI2 is connected to CSI_128 (*) - * @arg LL_TIM_TIM3_TI2_RMP_MCO2: TIM3 TI2 is connected to MCO2 (*) - * @arg LL_TIM_TIM3_TI2_RMP_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*) - * @arg LL_TIM_TIM3_TI3_RMP_GPIO: TIM3 TI3 is connected to GPIO - * @arg LL_TIM_TIM3_TI4_RMP_GPIO: TIM3 TI4 is connected to GPIO + * @arg LL_TIM_TIM3_TI2_RMP_CSI_128: TIM3 TI2 is connected to CSI_128 (*) + * @arg LL_TIM_TIM3_TI2_RMP_MCO2: TIM3 TI2 is connected to MCO2 (*) + * @arg LL_TIM_TIM3_TI2_RMP_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*) + * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*) + * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*) * * TIM4: one of the following values: (**) * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO - * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO - * @arg LL_TIM_TIM4_TI3_RMP_GPIO: TIM4 TI3 is connected to GPIO - * @arg LL_TIM_TIM4_TI4_RMP_GPIO: TIM4 TI4 is connected to GPIO + * @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output (*) * * TIM5: one of the following values: (**) * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO - * @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO - * @arg LL_TIM_TIM5_TI3_RMP_GPIO: TIM5 TI3 is connected to GPIO - * @arg LL_TIM_TIM5_TI4_RMP_GPIO: TIM5 TI4 is connected to GPIO + * @arg LL_TIM_TIM5_TI1_RMP_COMP1: TIM5 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM5_TI1_RMP_COMP2: TIM5 TI1 is connected to COMP2 output (*) * * TIM8: one of the following values: (**) * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO - * @arg LL_TIM_TIM8_TI2_RMP_GPIO: TIM8 TI2 is connected to GPIO - * @arg LL_TIM_TIM8_TI3_RMP_GPIO: TIM8 TI3 is connected to GPIO - * @arg LL_TIM_TIM8_TI4_RMP_GPIO: TIM8 TI4 is connected to GPIO + * @arg LL_TIM_TIM8_TI1_RMP_COMP1: TIM8 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output (*) * * TIM12: one of the following values: (**) * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO - * @arg LL_TIM_TIM12_TI1_RMP_HSI_1024: TIM12 TI1 is connected to GPIO - * @arg LL_TIM_TIM12_TI1_RMP_CSI_128: TIM12 TI1 is connected to GPIO + * @arg LL_TIM_TIM12_TI1_RMP_COMP1: TIM12 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM12_TI1_RMP_COMP2: TIM12 TI1 is connected to COMP2 output (*) + * @arg LL_TIM_TIM12_TI1_RMP_HSI_1024: TIM12 TI1 is connected to HSI 1024 + * @arg LL_TIM_TIM12_TI1_RMP_CSI_128: TIM12 TI1 is connected to CSI 128 * * TIM13: one of the following values: (**) * @arg LL_TIM_TIM13_TI1_RMP_GPIO: TIM13 TI1 is connected to GPIO + * @arg LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK: TIM13 TI1 is connected to I3C1 IBI ACK (*) + * @arg LL_TIM_TIM13_TI1_RMP_COMP1: TIM13 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM13_TI1_RMP_COMP2: TIM13 TI1 is connected to COMP2 output (*) * * TIM14: one of the following values: (**) * @arg LL_TIM_TIM14_TI1_RMP_GPIO: TIM14 TI1 is connected to GPIO + * @arg LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK: TIM14 TI1 is connected to I3C2 IBI ACK (*) + * @arg LL_TIM_TIM14_TI1_RMP_COMP1: TIM14 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM14_TI1_RMP_COMP2: TIM14 TI1 is connected to COMP2 output (*) * * TIM15: one of the following values: (**) * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO @@ -4951,21 +5188,29 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE * @arg LL_TIM_TIM15_TI1_RMP_CSI_128: TIM15 TI1 is connected to CSI/128 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2 + * @arg LL_TIM_TIM15_TI1_RMP_COMP1: TIM15 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM15_TI1_RMP_COMP2: TIM15 TI1 is connected to COMP2 output (*) * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI1 is connected to GPIO * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI1 is connected to TIM2 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI1 is connected to TIM3 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI1 is connected to TIM4 + * @arg LL_TIM_TIM15_TI2_RMP_COMP1: TIM15 TI2 is connected to COMP1 output (*) + * @arg LL_TIM_TIM15_TI2_RMP_COMP2: TIM15 TI2 is connected to COMP2 output (*) * * TIM16: one of the following values: (**) - * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO - * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI - * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE - * @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP: TIM16 TI1 is connected to RTC_WKUP + * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO + * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI + * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE + * @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP: TIM16 TI1 is connected to RTC_WKUP + * @arg LL_TIM_TIM16_TI1_RMP_COMP1: TIM16 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM16_TI1_RMP_COMP2: TIM16 TI1 is connected to COMP2 output (*) * * TIM17: one of the following values: (**) - * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO - * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ - * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1 + * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO + * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ + * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1 + * @arg LL_TIM_TIM17_TI1_RMP_COMP1: TIM17 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM17_TI1_RMP_COMP2: TIM17 TI1 is connected to COMP2 output (*) * * (*) Value not defined in all devices. \n * (**) Timer instance not available on all devices. \n @@ -5025,15 +5270,21 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledRTCPRE(const TIM_TypeDef *TIMx) * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT * @note This function can only be used in Output compare and PWM modes. * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource * @param TIMx Timer instance * @param OCRefClearInputSource This parameter can be one of the following values: - * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR * @arg @ref LL_TIM_OCREF_CLR_INT_ETR + * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*) + * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*) + * + * (*) Value not defined in all devices. \n * @retval None */ __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) { - MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); + MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, + ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos); + MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource); } /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h index 1338c3aa13..70f3038036 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_ucpd.h @@ -869,7 +869,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1034,7 +1034,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1523,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset interrupt * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1855,7 +1855,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h index aec9c62184..2cd97d7ff2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h @@ -37,11 +37,11 @@ extern "C" { * @{ */ -/** @addtogroup I3C +/** @defgroup UTILITY_I3C I3C Utility * @{ */ /* Exported types ----------------------------------------------------------------------------------------------------*/ -/** @defgroup I3C_Exported_Types I3C Exported Types +/** @defgroup I3C_UTIL_Exported_Types I3C Utility Exported Types * @{ */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html index 6dd7eea432..0a95394326 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html @@ -11,7 +11,7 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} - + @@ -24,7 +24,7 @@

Release Notes for STM32CubeH5 HAL and LL drivers

Copyright ©  2023 STMicroelectronics

- +

Purpose

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

@@ -40,10 +40,55 @@

Purpose

Update History

- +

Main Changes

    +
  • Maintenance release V1.3.0 of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx / STM32H523xx/ STM32H533xx devices
    • +
  • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and Coverity compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
    • +

  • General updates to fix known defects and implementation enhancements

    +
      +
    • HAL drivers : +
        +
      • HAL I3C driver: +
          +
        • Add HAL_I3C_TARGET_RESET_PATTERN, HAL_I3C_HDR_EXIT_PATTERN, HAL_I3C_RESET_PATTERN_DISABLE, HAL_I3C_RESET_PATTERN_ENABLE and IS_I3C_RESET_PATTERN defines
          • +
        • Add HAL_I3C_Ctrl_SetConfigResetPattern, HAL_I3C_Ctrl_GetConfigResetPattern and HAL_I3C_Ctrl_GenerateArbitration functions
          • +
        • +
      • +
    • LL drivers : +
        +
      • LL RNG driver: +
          +
        • Add LL_RNG_SetNoiseConfig and LL_RNG_GetNoiseConfig functions
          • +
        • +
      • LL SYSTEM driver: +
          +
        • Remove LL_SBS_SMPS_SEC and LL_SBS_SMPS_NSEC defines
          • +
        • +
      • LL TIM driver: +
          +
        • Remove irrelevant LL_TIM_OCREF_CLR_INT_OCREF_CLR and TIM_CLEARINPUTSOURCE_OCREFCLR constants
          • +
        • +
      • +
    • +
+

Note: HAL/LL Backward compatibility ensured by legacy defines.

+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • No compatibility break
    • +
+
+
+
+ +
+

Main Changes

+

  • First offiicial release of HAL and LL drivers to support STM32H533xx and STM32H523xx devices

    • HAL drivers : @@ -151,7 +196,7 @@

      Main Changes

      • Add HSE divider control capability for TIM17 (Ticket 164073).
      • Remove irrelevant state management in DMA callbacks (Ticket 167896).
        • -
      • Fix typo in some macros (ASYMMETRIC instead of ASSYMETRIC) (Ticket 165438).
        • +
      • Fix typo in some macros (ASYMMETRIC instead of ASYMMETRIC) (Ticket 165438).
      • Add USB related ETR defines.
    • HAL UART driver: @@ -206,17 +251,17 @@

      Main Changes

    • LL TIM driver:
      • Add HSE divider control capability for TIM17 (Ticket 164073).
        • -
      • Fix typo in some macros (ASYMMETRIC instead of ASSYMETRIC) (Ticket 165438).
        • +
      • Fix typo in some macros (ASYMMETRIC instead of ASYMMETRIC) (Ticket 165438).

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -225,7 +270,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Maintenance Release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices

      @@ -297,11 +342,11 @@

      Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -310,15 +355,15 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Not Applicable
diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c index 8d80e46101..42780e8e8a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -48,10 +48,10 @@ /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** - * @brief STM32H5xx HAL Driver version number 1.2.0 + * @brief STM32H5xx HAL Driver version number 1.3.0 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c index 21aea51096..d96e47c510 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c @@ -3116,43 +3116,20 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, { uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if (Status == RESET) + while (__HAL_HASH_GET_FLAG(hhash, Flag) == Status) { - while (__HAL_HASH_GET_FLAG(hhash, Flag) == RESET) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Set State to Ready to be able to restart later on */ - hhash->State = HAL_HASH_STATE_READY; - hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - return HAL_ERROR; - } - } - } - } - else - { - while (__HAL_HASH_GET_FLAG(hhash, Flag) != RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Set State to Ready to be able to restart later on */ - hhash->State = HAL_HASH_STATE_READY; - hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hhash); + /* Set State to Ready to be able to restart later on */ + hhash->State = HAL_HASH_STATE_READY; + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); - return HAL_ERROR; - } + return HAL_ERROR; } } } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c index 8c5e0d6ba9..ab74378f59 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c @@ -1913,8 +1913,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) { - hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; } else { @@ -1927,10 +1927,10 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U; } } - /* manage NACK Response */ + /* Manage NACK Response */ else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) { @@ -1944,7 +1944,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); } } - /* manage STALL Response */ + /* Manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) { (void)HAL_HCD_HC_Halt(hhcd, ch_num); @@ -2033,7 +2033,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Handle Isochronous channel */ if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) { - /* correct transaction */ + /* Correct transaction */ if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) { /* Double buffer isochronous out */ @@ -2042,7 +2042,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); } #if (USE_USB_DOUBLE_BUFFER == 1U) - else /* double buffer isochronous out */ + else /* Double buffer isochronous out */ { /* Odd Transaction */ if ((ch_reg & USB_CH_DTOG_TX) != 0U) @@ -2091,14 +2091,20 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_len = 0U; } + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + } + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { - /* manage multiple Xfer */ + /* Manage multiple Xfer */ hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; - /* start a new transfer */ + /* Start a new transfer */ (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else @@ -2107,12 +2113,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - - if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) - { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; - } } } /* Check NACK Response */ @@ -2127,7 +2127,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); - /*clear NAK status*/ + /* Clear NAK status */ WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; /* Update channel register Value */ @@ -2218,13 +2218,13 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /* Host Port State */ hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ + /* Clear all allocated virtual channel */ HAL_HCD_ClearPhyChannel(hhcd); /* Reset the PMA current pointer */ (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 Pma allocation state */ + /* Reset Ep0 Pma allocation state */ hhcd->ep0_PmaAllocState = 0U; /* Disconnection Callback */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c index 63add3cb59..13dffa2fdf 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c @@ -134,6 +134,18 @@ (#) To check if I2C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() + (#) To send a message header {S + 0x7E + W + STOP}, use the function HAL_I3C_Ctrl_GenerateArbitration(). + (#) To insert a target reset pattern before the STOP of a transmitted frame containing a RSTACT CCC command, + the application must enable the reset pattern configuration using HAL_I3C_Ctrl_SetConfigResetPattern() + before calling HAL_I3C_Ctrl_TransmitCCC() or HAL_I3C_Ctrl_ReceiveCCC() interfaces. + + To have a standard STOP emitted at the end of a frame containing a RSTACT CCC command, the application must + disable the reset pattern configuration using HAL_I3C_Ctrl_SetConfigResetPattern() before calling + HAL_I3C_Ctrl_TransmitCCC() or HAL_I3C_Ctrl_ReceiveCCC() interfaces. + + Use HAL_I3C_Ctrl_SetConfigResetPattern() function to configure the insertion of the reset pattern at + the end of a Frame, and HAL_I3C_Ctrl_GetConfigResetPattern() to retrieve reset pattern configuration. + (#) For I3C IO operations, three operation modes are available within this driver : *** Polling mode IO operation *** @@ -1652,6 +1664,10 @@ void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rul (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a transfer descriptor which contained different buffer pointers and their associated size through I3C_XferTypeDef. This function must be called before initiate any communication transfer. + (+) Call the function HAL_I3C_Ctrl_SetConfigResetPattern() to configure the insertion of the reset pattern + at the end of a Frame. + (+) Call the function HAL_I3C_Ctrl_GetConfigResetPattern() to get the current reset pattern configuration + [..] (@) Users must call all above functions after I3C initialization. @@ -2222,6 +2238,110 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, return status; } +/** + * @brief Set the configuration of the inserted reset pattern at the end of a Frame. + * @note When the transfer descriptor contains multiple frames with RESTART option, the reset pattern at the end of + * RSTACT CCC frame is not possible. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param resetPattern : [IN] Specifies the reset pattern configuration. + * It can be a value of @ref I3C_RESET_PATTERN + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_SetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t resetPattern) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + assert_param(IS_I3C_RESET_PATTERN(resetPattern)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + hi3c->State = HAL_I3C_STATE_BUSY; + + if (resetPattern == HAL_I3C_RESET_PATTERN_ENABLE) + { + LL_I3C_EnableResetPattern(hi3c->Instance); + } + else + { + LL_I3C_DisableResetPattern(hi3c->Instance); + } + + /* At the end of process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Get the configuration of the inserted reset pattern at the end of a Frame. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param pResetPattern : [OUT] Pointer to the current reset pattern configuration. + * It can be a value of @ref I3C_RESET_PATTERN + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_GetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t *pResetPattern) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + /* Check on user parameters */ + else if (pResetPattern == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check if the reset pattern configuration is enabled */ + if (LL_I3C_IsEnabledResetPattern(hi3c->Instance) == 1U) + { + *pResetPattern = HAL_I3C_RESET_PATTERN_ENABLE; + } + else + { + *pResetPattern = HAL_I3C_RESET_PATTERN_DISABLE; + } + } + + return status; +} + /** * @} */ @@ -2596,6 +2716,8 @@ HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTyp during the Dynamic Address Assignment processus. (+) Call the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() to check if I3C target device is ready. (+) Call the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() to check if I2C target device is ready. + (+) Call the function HAL_I3C_Ctrl_GenerateArbitration to send arbitration + (message header {S + 0x7E + W + STOP}) in polling mode (+) Those functions are called only when mode is Controller. @@ -3082,7 +3204,6 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, } else { - /* Check the instance and the mode parameters */ assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); @@ -3265,7 +3386,6 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, } else { - /* Check the instance and the mode parameters */ assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); @@ -5232,6 +5352,109 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, return status; } + +/** + * @brief Controller generates arbitration (message header {S/Sr + 0x7E addr + W}) in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + __IO uint32_t exit_condition; + uint32_t tickstart; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Disable exit pattern */ + LL_I3C_DisableExitPattern(hi3c->Instance); + /* Disable reset pattern */ + LL_I3C_DisableResetPattern(hi3c->Instance); + + /* Write message control register */ + WRITE_REG(hi3c->Instance->CR, LL_I3C_CONTROLLER_MTYPE_HEADER | LL_I3C_GENERATE_STOP); + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + + tickstart = HAL_GetTick(); + + while (exit_condition == 0U) + { + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + /* Update I3C error code */ + hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } + + if (status == HAL_OK) + { + /* Check if the FCF flag has been set */ + if (__HAL_I3C_GET_FLAG(hi3c, I3C_EVR_FCF) == SET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + else + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + } + + /* At the end of Rx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + /** * @} */ @@ -6659,6 +6882,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, const uint8_t * (+) Call the function HAL_I3C_GetState() to get the I3C handle state. (+) Call the function HAL_I3C_GetMode() to get the I3C handle mode. (+) Call the function HAL_I3C_GetError() to get the error code. + (+) Call the function HAL_I3C_Get_ENTDAA_Payload_Info() to get BCR, DCR and PID information after ENTDAA. @endverbatim * @{ @@ -8728,7 +8952,7 @@ static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint uint32_t current_tx_index = 0U; uint32_t global_tx_size = 0U; uint32_t global_rx_size = 0U; - uint32_t nb_tx_frame = 0U; + uint32_t nb_tx_frame = 0U; uint32_t direction; for (uint32_t descr_index = 0U; descr_index < counter; descr_index++) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c index 41fba182a4..f16b0fde46 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c @@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c index b040a96e1a..67bcd95c1f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c @@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -2227,13 +2227,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c index e9e7bc0cbe..8edff61212 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c @@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c index 669efbc1e8..d714293178 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c @@ -392,10 +392,11 @@ void HAL_PWR_EnterSTANDBYMode(void) /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif /* __CC_ARM */ + /* Wait For all memory accesses to complete before continuing */ + __DSB(); + + /* Ensure that the processor pipeline is flushed */ + __ISB(); /* Wait For Interrupt Request */ __WFI(); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c index ee5954a180..6eb5ad771b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c @@ -114,7 +114,6 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*) * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*) * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*) @@ -1147,7 +1146,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe switch (pPeriphClkInit->I3c2ClockSelection) { - case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK1 is used as clock source for I3C2*/ + case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I3C2*/ /* I3C2 clock source config set later after clock selection check */ break; @@ -1172,7 +1171,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Set the source of I3C2 clock*/ @@ -2373,6 +2371,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe } } +#if defined(USB_DRD_FS) /*------------------------------ USB Configuration -------------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { @@ -2423,6 +2422,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe } } +#endif /* USB_DRD_FS */ #if defined(CEC) /*-------------------------- CEC clock source configuration ----------------*/ @@ -2441,7 +2441,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe return status; } - /** * @brief Get the pPeriphClkInit according to the internal RCC configuration registers. * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that @@ -2449,7 +2448,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6, * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1, - * SAI2, USB,), PLL2 and PLL3. + * SAI2, USB, PLAY1), PLL2 and PLL3. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) @@ -2460,8 +2459,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_USB; + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER; +#if defined(USB_DRD_FS) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif /* USB_DRD_FS */ #if defined(UART4) pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART4; #endif /* UART4 */ @@ -2742,8 +2744,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) pPeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); #endif /* CEC */ +#if defined(USB_DRD_FS) /* Get the USB clock source ------------------------------------------------*/ pPeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* USB_DRD_FS */ /* Get the TIM Prescaler configuration -------------------------------------*/ if ((RCC->CFGR1 & RCC_CFGR1_TIMPRE) == 0U) @@ -2754,6 +2758,61 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED; } + +#if defined(PLAY1) + /* Get the PLAY1 clock source ------------------------------------------------*/ + pPeriphClkInit->PLAY1ClockSelection = __HAL_RCC_GET_PLAY1_SOURCE(); +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) + /* Get the USB_OTG_FS clock source ------------------------------------------------*/ + pPeriphClkInit->OtgfsClockSelection = __HAL_RCC_GET_OTGFS_SOURCE(); +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) + /* Get the USB_OTG_HS clock source ------------------------------------------------*/ + pPeriphClkInit->OtghsClockSelection = __HAL_RCC_GET_OTGHS_SOURCE(); +#endif /* USB_OTG_HS */ + +#if defined(OCTOSPI2) + /* Get the OSPI2 clock source -----------------------------------------------*/ + pPeriphClkInit->Ospi2ClockSelection = __HAL_RCC_GET_OSPI2_SOURCE(); +#endif /* OCTOSPI2 */ + +#if defined(LTDC) + /* Get the LTDC clock source ------------------------------------------------*/ + pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* LTDC */ + +#if defined(ADF1) + /* Get the ADF1 clock source ------------------------------------------------*/ + pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); +#endif /* ADF1 */ + +#if defined(MDF1) + /* Get the MDF1 clock source ------------------------------------------------*/ + pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) + /* Get the ETH clock source ------------------------------------------------*/ + pPeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE(); +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) + /* Get the ETHPTP clock source ------------------------------------------------*/ + pPeriphClkInit->EthptpClockSelection = __HAL_RCC_GET_ETHPTP_SOURCE(); +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHT1SCLKSEL) + /* Get the ETHT1S clock source ------------------------------------------------*/ + pPeriphClkInit->Etht1sClockSelection = __HAL_RCC_GET_ETHT1S_SOURCE(); +#endif /* RCC_CCIPR5_ETHT1SCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) + /* Get the ETHREF clock source ------------------------------------------------*/ + pPeriphClkInit->EthrefClockSelection = __HAL_RCC_GET_ETHREF_SOURCE(); +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ } /** @@ -3184,7 +3243,6 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks) * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*) * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*) * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*) @@ -4185,7 +4243,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) case RCC_PERIPHCLK_I3C2: /* Get the current I3C2 source */ srcclk = __HAL_RCC_GET_I3C2_SOURCE(); - if (srcclk == RCC_I3C2CLKSOURCE_PCLK3) { frequency = HAL_RCC_GetPCLK3Freq(); @@ -4207,6 +4264,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); } +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ /* Clock not enabled for I3C2 */ else { @@ -5204,6 +5267,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) } break; +#if defined(USB_DRD_FS) case RCC_PERIPHCLK_USB: /* Get the current USB kernel source */ srcclk = __HAL_RCC_GET_USB_SOURCE(); @@ -5243,9 +5307,36 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) default: frequency = 0U; break; +#endif /* USB_DRD_FS */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) + case RCC_PERIPHCLK_ETH: + + /* Get the current ETH kernel source */ + srcclk = __HAL_RCC_GET_ETH_SOURCE(); + switch (srcclk) + { + case RCC_ETHCLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_ETHCLKSOURCE_HSE: + { + frequency = HSE_VALUE; + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* RCC_CCIPR4_ETHCLKSEL */ } } - return (frequency); } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c index d29d91044b..caecaa7c5c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c @@ -199,6 +199,17 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE); +#endif /* defined(RNG_CR_NIST_VALUE) */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* defined(RNG_HTCR_NIST_VALUE) */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* defined(RNG_NSCR_NIST_VALUE) */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -238,7 +249,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c index 9cb1ef54a6..e69c7da910 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c @@ -1333,7 +1333,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) * the configuration information for SDRAM module. * @retval HAL state */ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram) { return hsdram->State; } @@ -1356,6 +1356,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) */ static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1378,6 +1379,7 @@ static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1400,6 +1402,7 @@ static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c index ea761f2d5b..9190ff38d9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c @@ -1162,6 +1162,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1184,6 +1185,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1206,6 +1208,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c index 664122b9e4..768cd42122 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c @@ -5581,12 +5581,22 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); break; } - case TIM_CLEARINPUTSOURCE_OCREFCLR: + +#if defined(COMP1) && defined(COMP2) + case TIM_CLEARINPUTSOURCE_COMP1: + case TIM_CLEARINPUTSOURCE_COMP2: { + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_COMP_CLEARINPUT_INSTANCE(htim->Instance)); + /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* Set the clear input source */ + MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); break; } +#endif /* COMP1 && COMP2 */ case TIM_CLEARINPUTSOURCE_ETR: { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c index 0a8426cba4..6101eb3769 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c @@ -2340,52 +2340,73 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @param htim TIM handle. * @param Remap specifies the TIM remapping source. * For TIM1, the parameter can take one of the following values: - * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO - * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output (*) - * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output (*) + * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output (*) + * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 * * For TIM2, the parameter can take one of the following values: * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO - * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output (*) + * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output (*) + * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output (*) * @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE - * @arg TIM_TIM2_ETR_SAI1_FSA TIM2 ETR is connected to SAI1 FSA (*) - * @arg TIM_TIM2_ETR_SAI1_FSB TIM2 ETR is connected to SAI1 FSB (*) + * @arg TIM_TIM2_ETR_SAI1_FSA TIM2 ETR is connected to SAI1 FSA (*) + * @arg TIM_TIM2_ETR_SAI1_FSB TIM2 ETR is connected to SAI1 FSB (*) * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin (*) - * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*) - * @arg TIM_TIM2_ETR_USB_SOF TIM2_ETR is connected to USB SOF (*) - * @arg TIM_TIM2_ETR_ETH_PPS TIM2 ETR is connected to ETH PPS (*) + * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin (*) + * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*) + * @arg TIM_TIM2_ETR_USB_SOF TIM2 ETR is connected to USB SOF (*) + * @arg TIM_TIM2_ETR_USBHS_SOF TIM2 ETR is connected to USBHS OTG SOF (*) + * @arg TIM_TIM2_ETR_USBFS_SOF TIM2 ETR is connected to USBFS OTG SOF (*) + * @arg TIM_TIM2_ETR_ETH_PPS TIM2 ETR is connected to ETH PPS (*) + * @arg TIM_TIM2_ETR_PLAY1_OUT0 TIM2 ETR is connected to PLAY1 output 0 (*) * * For TIM3, the parameter can take one of the following values: * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO - * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output (*) + * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output (*) + * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output (*) + * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1 (*) + * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2 (*) + * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3 (*) * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin - * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin (*) - * @arg TIM_TIM3_ETR_TIM5_ETR TIM3 ETR is connected to TIM5 ETR pin (*) - * @arg TIM_TIM3_ETR_ETH_PPS TIM3 ETR is connected to ETH PPS (*) + * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin (*) + * @arg TIM_TIM3_ETR_TIM5_ETR TIM3 ETR is connected to TIM5 ETR pin (*) + * @arg TIM_TIM3_ETR_ETH_PPS TIM3 ETR is connected to ETH PPS (*) + * @arg TIM_TIM3_ETR_PLAY1_OUT0 TIM3 ETR is connected to PLAY1 output 0 (*) * * For TIM4, the parameter can take one of the following values: (**) - * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO - * @arg TIM_TIM4_ETR_TIM2_ETR TIM4 ETR is connected to TIM2 ETR pin - * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin + * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO + * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output (*) + * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output (*) + * @arg TIM_TIM4_ETR_TIM2_ETR TIM4 ETR is connected to TIM2 ETR pin + * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin + * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin * * For TIM5, the parameter can take one of the following values: (**) - * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO - * @arg TIM_TIM5_ETR_SAI2_FSA TIM5 ETR is connected to SAI2 FSA - * @arg TIM_TIM5_ETR_SAI2_FSB TIM5 ETR is connected to SAI2 FSB - * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin - * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM5_ETR_TIM4_ETR TIM5 ETR is connected to TIM4 ETR pin - * @arg TIM_TIM5_ETR_USB_SOF TIM5_ETR is connected to USB SOF (*) + * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO + * @arg TIM_TIM5_ETR_SAI2_FSA TIM5 ETR is connected to SAI2 FSA + * @arg TIM_TIM5_ETR_SAI2_FSB TIM5 ETR is connected to SAI2 FSB + * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*) + * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*) + * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin + * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin + * @arg TIM_TIM5_ETR_TIM4_ETR TIM5 ETR is connected to TIM4 ETR pin + * @arg TIM_TIM5_ETR_USB_SOF TIM5 ETR is connected to USB SOF (*) + * @arg TIM_TIM5_ETR_USBHS_SOF TIM5 ETR is connected to USBHS OTG SOF (*) + * @arg TIM_TIM5_ETR_USBFS_SOF TIM5 ETR is connected to USBFS OTG SOF (*) * * For TIM8, the parameter can take one of the following values: (**) * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO + * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output (*) + * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output (*) * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3 + * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*) + * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*) + * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*) * * (*) Value not defined in all devices. * (**) Timer instance not available on all devices. \n @@ -2418,69 +2439,96 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: * For TIM1, the parameter is one of the following values: * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output (*) * @arg TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO * @arg TIM_TIM1_TI3_GPIO: TIM1 TI3 is connected to GPIO * @arg TIM_TIM1_TI4_GPIO: TIM1 TI4 is connected to GPIO * * For TIM2, the parameter is one of the following values: * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO - * @arg TIM_TIM2_TI1_LSI: TIM2 TI1 is connected to LSI (*) - * @arg TIM_TIM2_TI1_LSE: TIM2 TI1 is connected to LSE (*) - * @arg TIM_TIM2_TI1_ETH_PPS TIM2 TI1 is connected to ETH PPS (*) - * @arg TIM_TIM2_TI1_RTC_WKUP: TIM2 TI2 is connected to RTC_WKUP (*) - * @arg TIM_TIM2_TI1_TIM3_TI1: TIM2 TI2 is connected to TIM3_TI1 (*) + * @arg TIM_TIM2_TI1_LSI: TIM2 TI1 is connected to LSI (*) + * @arg TIM_TIM2_TI1_LSE: TIM2 TI1 is connected to LSE (*) + * @arg TIM_TIM2_TI1_RTC_WKUP: TIM2 TI2 is connected to RTC_WKUP (*) + * @arg TIM_TIM2_TI1_TIM3_TI1: TIM2 TI2 is connected to TIM3_TI1 (*) + * @arg TIM_TIM2_TI1_ETH_PPS TIM2 TI1 is connected to ETH PPS (*) + * @arg TIM_TIM2_TI1_COMP1 TIM2 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI1_COMP2 TIM2 TI1 is connected to COMP2 output (*) + * @arg TIM_TIM2_TI1_PLAY1_OUT3 TIM2 TI1 is connected to PLAY1 output 3 (*) * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO - * @arg TIM_TIM2_TI2_HSI_1024: TIM2 TI2 is connected to HSI/1024 (*) - * @arg TIM_TIM2_TI2_CSI_128: TIM2 TI2 is connected to CSI/128 (*) - * @arg TIM_TIM2_TI2_MCO2: TIM2 TI2 is connected to MCO1 (*) - * @arg TIM_TIM2_TI2_MCO1: TIM2 TI2 is connected to MCO1 (*) + * @arg TIM_TIM2_TI2_HSI_1024: TIM2 TI2 is connected to HSI/1024 (*) + * @arg TIM_TIM2_TI2_CSI_128: TIM2 TI2 is connected to CSI/128 (*) + * @arg TIM_TIM2_TI2_MCO2: TIM2 TI2 is connected to MCO2 (*) + * @arg TIM_TIM2_TI2_MCO1: TIM2 TI2 is connected to MCO1 (*) + * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output (*) * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*) * * For TIM3, the parameter is one of the following values: * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO - * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output (*) - * @arg TIM_TIM3_TI1_MCO1: TIM3 TI2 is connected to MCO1 (*) - * @arg TIM_TIM3_TI1_TIM2_TI1: TIM3 TI2 is connected to TIM2 TI1 (*) - * @arg TIM_TIM3_TI1_HSE_1MHZ: TIM3 TI2 is connected to HSE_1MHZ (*) - * @arg TIM_TIM3_TI1_ETH_PPS TIM3 TI1 is connected to ETH PPS (*) + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM3_TI1_MCO1: TIM3 TI2 is connected to MCO1 (*) + * @arg TIM_TIM3_TI1_TIM2_TI1: TIM3 TI2 is connected to TIM2 TI1 (*) + * @arg TIM_TIM3_TI1_HSE_1MHZ: TIM3 TI2 is connected to HSE_1MHZ (*) + * @arg TIM_TIM3_TI1_ETH_PPS TIM3 TI1 is connected to ETH PPS (*) + * @arg TIM_TIM3_TI1_COMP1 TIM3 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM3_TI1_COMP2 TIM3 TI1 is connected to COMP2 output (*) + * @arg TIM_TIM3_TI1_PLAY1_OUT3 TIM3 TI1 is connected to PLAY1 output 3 (*) * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO - * @arg TIM_TIM3_TI2_CSI_128: TIM3 TI2 is connected to CSI_128 (*) - * @arg TIM_TIM3_TI2_MCO2: TIM3 TI2 is connected to MCO2 (*) - * @arg TIM_TIM3_TI2_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*) + * @arg TIM_TIM3_TI2_CSI_128: TIM3 TI2 is connected to CSI_128 (*) + * @arg TIM_TIM3_TI2_MCO2: TIM3 TI2 is connected to MCO2 (*) + * @arg TIM_TIM3_TI2_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*) + * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output (*) + * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output (*) * @arg TIM_TIM3_TI3_GPIO: TIM3 TI2 is connected to GPIO * @arg TIM_TIM3_TI4_GPIO: TIM3 TI2 is connected to GPIO * * For TIM4, the parameter is one of the following values: (**) * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO + * @arg TIM_TIM4_TI1_COMP1 TIM4 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM4_TI1_COMP2 TIM4 TI1 is connected to COMP2 output (*) * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO * * For TIM5, the parameter is one of the following values: (**) * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO + * @arg TIM_TIM5_TI1_COMP1 TIM5 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM5_TI1_COMP2 TIM5 TI1 is connected to COMP2 output (*) * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO * @arg TIM_TIM5_TI3_GPIO: TIM5 TI3 is connected to GPIO * @arg TIM_TIM5_TI4_GPIO: TIM5 TI4 is connected to GPIO * * For TIM8, the parameter is one of the following values: (**) * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO + * @arg TIM_TIM8_TI1_COMP1 TIM8 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM8_TI1_COMP2 TIM8 TI1 is connected to COMP2 output (*) * @arg TIM_TIM8_TI2_GPIO: TIM8 TI2 is connected to GPIO * @arg TIM_TIM8_TI3_GPIO: TIM8 TI3 is connected to GPIO * @arg TIM_TIM8_TI4_GPIO: TIM8 TI4 is connected to GPIO * * For TIM12, the parameter is one of the following values: (**) * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO + * @arg TIM_TIM12_TI1_COMP1 TIM12 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM12_TI1_COMP2 TIM12 TI1 is connected to COMP2 output (*) * @arg TIM_TIM12_TI1_HSI_1024: TIM12 TI1 is connected to HSI/1024 * @arg TIM_TIM12_TI1_CSI_128: TIM12 TI1 is connected to CSI/128 + * @arg TIM_TIM12_TI2_GPIO: TIM12 TI2 is connected to GPIO + * @arg TIM_TIM12_TI2_COMP2 TIM12 TI2 is connected to COMP2 output (*) * * For TIM13, the parameter is one of the following values: (**) - * @arg TIM_TIM12_TI1_GPIO: TIM13 TI1 is connected to GPIO + * @arg TIM_TIM13_TI1_GPIO: TIM13 TI1 is connected to GPIO + * @arg TIM_TIM13_TI1_I3C1_IBIACK TIM13 TI1 is connected to I3C1 IBI ACK (*) + * @arg TIM_TIM13_TI1_COMP1 TIM13 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM13_TI1_COMP2 TIM13 TI1 is connected to COMP2 output (*) * * For TIM14, the parameter is one of the following values: (**) * @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_TI1_I3C2_IBIACK TIM14 TI1 is connected to I3C2 IBI ACK (*) + * @arg TIM_TIM14_TI1_COMP1 TIM14 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM14_TI1_COMP2 TIM14 TI1 is connected to COMP2 output (*) * * For TIM15, the parameter can have the following values: (**) * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO @@ -2489,22 +2537,30 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE * @arg TIM_TIM15_TI1_CSI_128: TIM15 TI1 is connected to CSI/128 - * @arg TIM_TIM15_TI1_MCO: TIM15 TI1 is connected to MCO + * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2 + * @arg TIM_TIM15_TI1_COMP1 TIM15 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM15_TI1_COMP2 TIM15 TI1 is connected to COMP2 output (*) * @arg TIM_TIM15_TI2_GPIO: TIM15 TI1 is connected to GPIO * @arg TIM_TIM15_TI2_TIM2: TIM15 TI1 is connected to TIM2 * @arg TIM_TIM15_TI2_TIM3: TIM15 TI1 is connected to TIM3 * @arg TIM_TIM15_TI2_TIM4: TIM15 TI1 is connected to TIM4 + * @arg TIM_TIM15_TI2_COMP1 TIM15 TI2 is connected to COMP1 output (*) + * @arg TIM_TIM15_TI2_COMP2 TIM15 TI2 is connected to COMP2 output (*) * * For TIM16, the parameter is one of the following values: (**) * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTCWKUP + * @arg TIM_TIM16_TI1_COMP1 TIM16 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM16_TI1_COMP2 TIM16 TI1 is connected to COMP2 output (*) * * For TIM17, the parameter can have the following values: (**) * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ - * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO + * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1 + * @arg TIM_TIM17_TI1_COMP1 TIM17 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM17_TI1_COMP2 TIM17 TI1 is connected to COMP2 output (*) * * (*) Value not defined in all devices. \n * (**) Timer instance not available on all devices. \n diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c index ae35d5a845..241bd8f83b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c @@ -1130,12 +1130,14 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1227,12 +1229,14 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1312,12 +1316,14 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1389,12 +1395,14 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } +#endif /* USART_DMAREQUESTS_SW_WA */ if (!(IS_LPUART_INSTANCE(huart->Instance))) { /* Check that USART RTOEN bit is set */ @@ -1773,6 +1781,11 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) { @@ -1796,6 +1809,11 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) { @@ -1865,6 +1883,11 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) { @@ -1929,6 +1952,11 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) { @@ -2030,6 +2058,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) { @@ -2051,6 +2084,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) { @@ -2139,6 +2177,11 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) { @@ -2235,6 +2278,11 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) { @@ -2416,6 +2464,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) { @@ -2504,6 +2557,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -2526,6 +2585,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3697,6 +3778,12 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { huart->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } @@ -3749,6 +3836,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4547,6 +4640,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4711,6 +4805,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c index 551ad99fe2..f1aa6d9e93 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c @@ -576,7 +576,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -726,6 +726,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; @@ -845,6 +853,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c index 273c50b849..7effea0680 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -227,8 +227,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -240,7 +240,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -659,11 +659,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -760,12 +759,14 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } +#endif /* USART_DMAREQUESTS_SW_WA */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; @@ -864,12 +865,14 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the USART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } +#endif /* USART_DMAREQUESTS_SW_WA */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; @@ -986,6 +989,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const u /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { @@ -998,6 +1002,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const u CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } +#endif /* USART_DMAREQUESTS_SW_WA */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; @@ -1136,12 +1141,14 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8 /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } +#endif /* USART_DMAREQUESTS_SW_WA */ husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; husart->TxXferCount = Size; @@ -1227,12 +1234,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the USART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } +#endif /* USART_DMAREQUESTS_SW_WA */ husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->RxXferCount = Size; @@ -1347,6 +1356,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, cons /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { @@ -1359,6 +1369,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, cons CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } +#endif /* USART_DMAREQUESTS_SW_WA */ husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->RxXferCount = Size; @@ -2175,6 +2186,11 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (husart->hdmatx != NULL) { @@ -2198,6 +2214,11 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (husart->hdmarx != NULL) { @@ -2302,6 +2323,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (husart->hdmatx != NULL) { @@ -2323,6 +2349,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (husart->hdmarx != NULL) { @@ -2505,6 +2536,11 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Tx channel */ if (husart->hdmatx != NULL) { @@ -2834,6 +2870,12 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) if (husart->State == HAL_USART_STATE_BUSY_TX) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } @@ -2890,6 +2932,15 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ if (husart->State == HAL_USART_STATE_BUSY_RX) { #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) @@ -3176,7 +3227,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c index 2bfa7d796f..0016588ee8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c index 0be95e79f0..c2015166ee 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c @@ -1134,7 +1134,7 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusC * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1154,7 +1154,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pD /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1296,7 +1296,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pDa * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; @@ -1314,7 +1314,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1417,7 +1417,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const * of data and the fifo threshold should be aligned on word * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t data_size = hxspi->Instance->DLR + 1U; @@ -1496,7 +1496,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *cons if (status == HAL_OK) { hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -2858,9 +2858,6 @@ static void XSPI_DMACplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer on the XSPI side */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - /* Enable the XSPI transfer complete Interrupt */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); } @@ -2995,7 +2992,7 @@ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxsp { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hxspi->State = HAL_XSPI_STATE_ERROR; + hxspi->State = HAL_XSPI_STATE_READY; hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; return HAL_TIMEOUT; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c index 5029fdbcf2..58c008e9f5 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c @@ -81,17 +81,20 @@ ErrorStatus LL_EXTI_DeInit(void) { /* Interrupt mask register set to default reset values */ LL_EXTI_WriteReg(IMR1, 0xFFFE0000U); -#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) - LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); -#elif defined(STM32H533xx) +#if defined(STM32H533xx) || defined(STM32H523xx) LL_EXTI_WriteReg(IMR2, 0x07DBFFFFU); -#else +#elif defined(STM32H503xx) LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); -#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ +#else + LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); +#endif /* defined(STM32H533xx) || defined(STM32H523xx) */ /* Event mask register set to default reset values */ LL_EXTI_WriteReg(EMR1, 0x00000000U); LL_EXTI_WriteReg(EMR2, 0x00000000U); +#if defined(EXTI_EMR3_EM) + LL_EXTI_WriteReg(EMR3, 0x00000000U); +#endif /* EXTI_EMR3_EM */ /* Rising Trigger selection register set to default reset values */ LL_EXTI_WriteReg(RTSR1, 0x00000000U); @@ -259,6 +262,7 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) /* De-configure EXTI Lines in range from 32 to 63 */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + } return status; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c index cf03303498..e48e082906 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c @@ -61,7 +61,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -195,7 +195,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -383,7 +383,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -434,7 +434,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -583,7 +583,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -616,7 +616,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -647,7 +647,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -768,7 +768,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -856,7 +856,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -919,7 +919,7 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -1049,7 +1049,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c index 340ed846b4..efa633a2b3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_gpio.c @@ -31,7 +31,7 @@ */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) /** @addtogroup GPIO_LL * @{ @@ -166,6 +166,20 @@ ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI); } #endif /* GPIOI */ +#if defined(GPIOJ) + else if (GPIOx == GPIOJ) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOJ); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOJ); + } +#endif /* GPIOJ */ +#if defined(GPIOK) + else if (GPIOx == GPIOK) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOK); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOK); + } +#endif /* GPIOK */ else { status = ERROR; @@ -279,7 +293,8 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ + defined (GPIOK) ||*/ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_opamp.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_opamp.c index c69fb9239b..dd9522939e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_opamp.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_opamp.c @@ -65,8 +65,6 @@ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC) \ ) - - #define IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__) \ (((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0) \ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c index 2fdf9fd7ba..59aadb8861 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c @@ -138,7 +138,9 @@ #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) +#if defined(USB_DRD_FS) #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* USB_DRD_FS */ #define IS_LL_RCC_ADCDAC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADCDAC_CLKSOURCE)) @@ -2837,6 +2839,7 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) return rng_frequency; } +#if defined(USB_DRD_FS) /** * @brief Return USBx clock frequency * @param USBxSource This parameter can be one of the following values: @@ -2897,6 +2900,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) return usb_frequency; } +#endif /* USB_DRD_FS */ /** * @brief Return ADCxDAC clock frequency diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c index 5569f4c47e..22c6b2aca2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_ucpd.c @@ -112,7 +112,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) * the configuration information for the UCPD peripheral. * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct) +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Check the ucpd Instance UCPDx*/ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c index ddc27c6240..bcff169016 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c @@ -1151,7 +1151,14 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, } /* Clear device address, Endpoint number and Low Speed Endpoint fields */ - wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); + wChRegVal &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFU << 27)); /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | @@ -1200,6 +1207,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) if (hc->doublebuffer == 0U) { + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_RX_DTOG(USBx, phy_ch_num); + } + } + /* Set RX buffer count */ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } @@ -1257,6 +1276,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); } + + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_TX_DTOG(USBx, phy_ch_num); + } + } } #if (USE_USB_DOUBLE_BUFFER == 1U) else if (hc->ep_type == EP_TYPE_BULK) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c index 0b47a3d0df..c11c2a5662 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c @@ -41,9 +41,9 @@ * @{ */ #define UTILS_MAX_FREQUENCY_SCALE0 250000000U /*!< Maximum frequency for system clock at power scale0, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE1 180000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE2 130000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE3 80000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE1 200000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 150000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 100000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ @@ -64,31 +64,31 @@ #define UTILS_HSE_FREQUENCY_MAX 50000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to HCLK Frequency */ -#define UTILS_SCALE0_LATENCY0_FREQ 38000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */ -#define UTILS_SCALE0_LATENCY1_FREQ 76000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */ -#define UTILS_SCALE0_LATENCY2_FREQ 114000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */ -#define UTILS_SCALE0_LATENCY3_FREQ 152000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */ -#define UTILS_SCALE0_LATENCY4_FREQ 190000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */ +#define UTILS_SCALE0_LATENCY0_FREQ 42000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */ +#define UTILS_SCALE0_LATENCY1_FREQ 84000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */ +#define UTILS_SCALE0_LATENCY2_FREQ 126000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */ +#define UTILS_SCALE0_LATENCY3_FREQ 168000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */ +#define UTILS_SCALE0_LATENCY4_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */ #define UTILS_SCALE0_LATENCY5_FREQ 250000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */ -#define UTILS_SCALE1_LATENCY0_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ -#define UTILS_SCALE1_LATENCY1_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ -#define UTILS_SCALE1_LATENCY2_FREQ 96000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ -#define UTILS_SCALE1_LATENCY3_FREQ 128000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ -#define UTILS_SCALE1_LATENCY4_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ -#define UTILS_SCALE1_LATENCY5_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ - -#define UTILS_SCALE2_LATENCY0_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ -#define UTILS_SCALE2_LATENCY1_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ -#define UTILS_SCALE2_LATENCY2_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ -#define UTILS_SCALE2_LATENCY3_FREQ 106000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ -#define UTILS_SCALE2_LATENCY4_FREQ 130000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ - -#define UTILS_SCALE3_LATENCY0_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ -#define UTILS_SCALE3_LATENCY1_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ -#define UTILS_SCALE3_LATENCY2_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ -#define UTILS_SCALE3_LATENCY3_FREQ 65000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ -#define UTILS_SCALE3_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ +#define UTILS_SCALE1_LATENCY0_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ +#define UTILS_SCALE1_LATENCY1_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_FREQ 170000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_FREQ 200000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ + +#define UTILS_SCALE2_LATENCY0_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ +#define UTILS_SCALE2_LATENCY1_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE2_LATENCY3_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ +#define UTILS_SCALE2_LATENCY4_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ + +#define UTILS_SCALE3_LATENCY0_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ +#define UTILS_SCALE3_LATENCY1_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +#define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ +#define UTILS_SCALE3_LATENCY3_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ +#define UTILS_SCALE3_LATENCY4_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ /** * @} */ @@ -318,19 +318,19 @@ void LL_mDelay(uint32_t Delay) (++) | Latency | HCLK clock frequency (MHz) | (++) | |-----------------------------------------------------------------------------| (++) | | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 | - (++) | | 1.26 - 1.35V | 1.15 - 1.26V | 1.05 - 1.15V | 0,95 - 1,05V | + (++) | | 1.30 - 1.40V | 1.15 - 1.26V | 1.05 - 1.15V | 0,95 - 1,05V | (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |0WS(1 CPU cycles)| 0 < HCLK <= 38 | 0 < HCLK <= 32 | 0 < HCLK <= 26 | 0 < HCLK <= 16 | + (++) |0WS(1 CPU cycles)| 0 < HCLK <= 42 | 0 < HCLK <= 34 | 0 < HCLK <= 30 | 0 < HCLK <= 20 | (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |1WS(2 CPU cycles)| 38 < HCLK <= 76 | 32 < HCLK <= 64 | 26 < HCLK <= 50 | 16 < HCLK <= 32 | + (++) |1WS(2 CPU cycles)| 42 < HCLK <= 84 | 34 < HCLK <= 68 | 30 < HCLK <= 60 | 20 < HCLK <= 40 | (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |2WS(3 CPU cycles)| 76 < HCLK <= 114 | 64 < HCLK <= 96 | 50 < HCLK <= 80 | 32 < HCLK <= 50 | + (++) |2WS(3 CPU cycles)| 84 < HCLK <= 126 | 68 < HCLK <= 102 | 60 < HCLK <= 90 | 40 < HCLK <= 60 | (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |3WS(4 CPU cycles)| 114 < HCLK <= 152 | 96 < HCLK <= 128 | 80 < HCLK <= 106 | 50 < HCLK <= 65 | + (++) |3WS(4 CPU cycles)| 126 < HCLK <= 168 | 102 < HCLK <= 136| 90 < HCLK <= 120 | 60 < HCLK <= 80 | (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |4WS(5 CPU cycles)| 152 < HCLK <= 190| 128 < HCLK <= 160| 106 < HCLK <= 130| 65 < HCLK <= 80 | + (++) |4WS(5 CPU cycles)| 168 < HCLK <= 210| 136 < HCLK <= 170| 120 < HCLK <= 150| 80 < HCLK <= 100 | (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |5WS(6 CPU cycles)| 190 < HCLK <= 250| 160 < HCLK <= 180| NA | NA | + (++) |5WS(6 CPU cycles)| 210 < HCLK <= 250| 170 < HCLK <= 200| NA | NA | (++) +-----------------+-------------------+------------------+------------------+-------------------+ @endinternal @@ -674,31 +674,31 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) { if (HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ) { - /* 0 < HCLK <= 38 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ + /* 0 < HCLK <= 42 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ } else if ((HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ)) { - /* 38 < HCLK <=76 => 1WS (2 CPU cycles) */ + /* 42 < HCLK <=84 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ) { - /* 76 < HCLK <= 114 => 2WS (3 CPU cycles) */ + /* 84 < HCLK <= 126 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ) { - /* 114 < HCLK <= 152 => 3WS (4 CPU cycles) */ + /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */ latency = LL_FLASH_LATENCY_3; } else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ) { - /* 152 < HCLK <= 190 => 4WS (5 CPU cycles) */ + /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */ latency = LL_FLASH_LATENCY_4; } else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ) { - /* 190 < HCLK <= 250 => 5WS (6 CPU cycles) */ + /* 210 < HCLK <= 250 => 5WS (6 CPU cycles) */ latency = LL_FLASH_LATENCY_5; } else @@ -710,31 +710,31 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) { if (HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ) { - /* 0 < HCLK <= 32 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ + /* 0 < HCLK <= 34 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ } else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ) { - /* 32 < HCLK <=64 => 1WS (2 CPU cycles) */ + /* 34 < HCLK <=68 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ) { - /* 64 < HCLK <= 96 => 2WS (3 CPU cycles) */ + /* 68 < HCLK <= 102 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ) { - /* 96 < HCLK <= 128 => 3WS (4 CPU cycles) */ + /* 102 < HCLK <= 136 => 3WS (4 CPU cycles) */ latency = LL_FLASH_LATENCY_3; } else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ) { - /* 128 < HCLK <= 160 => 4WS (5 CPU cycles) */ + /* 136 < HCLK <= 170 => 4WS (5 CPU cycles) */ latency = LL_FLASH_LATENCY_4; } else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ) { - /* 160 < HCLK <= 150 => 5WS (6 CPU cycles) */ + /* 170 < HCLK <= 200 => 5WS (6 CPU cycles) */ latency = LL_FLASH_LATENCY_5; } else @@ -746,26 +746,26 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) { if (HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ) { - /* 0 < HCLK <= 26 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ + /* 0 < HCLK <= 30 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ } else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ) { - /* 26 < HCLK <= 50 => 1WS (2 CPU cycles) */ + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ) { - /* 50 < HCLK <= 80 => 2WS (3 CPU cycles) */ + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ) { - /* 80 < HCLK <= 106 => 3WS (4 CPU cycles) */ + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ latency = LL_FLASH_LATENCY_3; } else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ) { - /* 106 < HCLK <= 130 => 4WS (5 CPU cycles) */ + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ latency = LL_FLASH_LATENCY_4; } else @@ -777,26 +777,26 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) { if (HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) { - /* 0 < HCLK <= 16 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ + /* 0 < HCLK <= 20 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ } else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ) { - /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ) { - /* 32 < HCLK <= 50 => 2WS (3 CPU cycles) */ + /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ) { - /* 50 < HCLK <= 65 => 3WS (4 CPU cycles) */ + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ latency = LL_FLASH_LATENCY_3; } else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ) { - /* 65 < HCLK <= 80 => 4WS (5 CPU cycles) */ + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ latency = LL_FLASH_LATENCY_4; } else diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c index d4396b76d5..19d16d2dfc 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_util_i3c.c @@ -23,7 +23,7 @@ * @{ */ -/** @addtogroup I3C +/** @addtogroup UTILITY_I3C * @{ */ @@ -33,15 +33,16 @@ * @{ */ #define SEC210PSEC (uint64_t)100000000000 /*!< 10ps, to take two decimal float of ns calculation */ -#define TI3CH_MIN 3200U /*!< Open drain & push pull SCL high min, 32ns */ -#define TI3CH_OD_MAX 4100U /*!< Open drain SCL high max, 41 ns */ -#define TI3CL_OD_MIN 20000U /*!< Open drain SCL low min, 200 ns */ -#define TFMPL_OD_MIN 50000U /*!< Fast Mode Plus Open drain SCL low min, 500 ns */ -#define TFML_OD_MIN 130000U /*!< Fast Mode Open drain SCL low min, 1300 ns */ -#define TFM_MIN 250000U /*!< Fast Mode, period min for ti3cclk, 2.5us */ -#define TSM_MIN 1000000U /*!< Standard Mode, period min for ti3cclk, 10us */ -#define TI3C_CAS_MIN 3840U /*!< Time SCL after START min, 38.4 ns */ -#define TCAPA 35000U /*!< Capacitor effect Value measure on Nucleo around 350ns */ +#define TI3CH_MIN 3200U /*!< Open drain & push pull SCL high min, 32ns */ +#define TI3CH_OD_MAX 4100U /*!< Open drain SCL high max, 41 ns */ +#define TI3CL_OD_MIN 20000U /*!< Open drain SCL low min, 200 ns */ +#define TFMPL_OD_MIN 50000U /*!< Fast Mode Plus Open drain SCL low min, 500 ns */ +#define TFML_OD_MIN 130000U /*!< Fast Mode Open drain SCL low min, 1300 ns */ +#define TFM_MIN 250000U /*!< Fast Mode, period min for ti3cclk, 2.5us */ +#define TSM_MIN 1000000U /*!< Standard Mode, period min for ti3cclk, 10us */ +#define TI3C_CAS_MIN 3840U /*!< Time SCL after START min, 38.4 ns */ +#define TCAPA 35000U /*!< Capacitor effect Value measure on Nucleo around 350ns */ +#define I3C_FREQUENCY_MAX 257000000U /*!< Maximum I3C frequency */ /** * @} */ @@ -128,6 +129,17 @@ ErrorStatus I3C_CtrlTimingComputation(const I3C_CtrlTimingTypeDef *pInputTiming, uint32_t sdahold; /* Verify Parameters */ + if (pInputTiming->clockSrcFreq > I3C_FREQUENCY_MAX) + { + /* Above this frequency, some timing register parameters are over than field value */ + status = ERROR; + } + + if ((pInputTiming->busType != I3C_PURE_I3C_BUS) && (pInputTiming->busType != I3C_MIXED_BUS)) + { + status = ERROR; + } + if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U)) && (pInputTiming->busType == I3C_PURE_I3C_BUS)) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/_htmresc/mini-st.css b/system/Drivers/STM32H5xx_HAL_Driver/_htmresc/mini-st_2020.css similarity index 100% rename from system/Drivers/STM32H5xx_HAL_Driver/_htmresc/mini-st.css rename to system/Drivers/STM32H5xx_HAL_Driver/_htmresc/mini-st_2020.css diff --git a/system/Drivers/STM32H5xx_HAL_Driver/_htmresc/st_logo.png b/system/Drivers/STM32H5xx_HAL_Driver/_htmresc/st_logo_2020.png similarity index 100% rename from system/Drivers/STM32H5xx_HAL_Driver/_htmresc/st_logo.png rename to system/Drivers/STM32H5xx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 3f0d99d97c..8373ff7fb5 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.3.1 * STM32G0: 1.4.6 * STM32G4: 1.2.4 - * STM32H5: 1.2.0 + * STM32H5: 1.3.0 * STM32H7: 1.11.3 * STM32L0: 1.10.6 * STM32L1: 1.4.5