From 1d689324dbc72f9dd4ec79eb34e66b59cc6dd0f0 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 13 Oct 2023 16:43:11 +0200 Subject: [PATCH] :rocket: preparing release 1.9.0 --- CHANGELOG.md | 1 + docs/attrs.adoc | 2 +- rtl/core/neorv32_package.vhd | 2 +- sw/svd/neorv32.svd | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index cec47ca84..0bab5980b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date (*dd.mm.yyyy*) | Version | Comment | |:-------------------:|:-------:|:--------| +| 13.10.2023 | [**:rocket:1.9.0**](https://github.com/stnolting/neorv32/releases/tag/v1.9.0) | **New release** | | 13.10.2023 | 1.8.9.9 | minor hardware edits and optimizations; [#703](https://github.com/stnolting/neorv32/pull/703) | | 07.10.2023 | 1.8.9.8 | add "transfer done" flag to DMA; [#699](https://github.com/stnolting/neorv32/pull/699) | | 04.10.2023 | 1.8.9.7 | :warning: rework internal bus protocol; [#697](https://github.com/stnolting/neorv32/pull/697) | diff --git a/docs/attrs.adoc b/docs/attrs.adoc index d87cfcd34..d0ed66a78 100644 --- a/docs/attrs.adoc +++ b/docs/attrs.adoc @@ -1,7 +1,7 @@ :author: by stnolting :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. -:revnumber: v1.8.9 +:revnumber: v1.9.0 :doctype: book :sectnums: :stem: diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index c44592214..06b2402c7 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -59,7 +59,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080909"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090000"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width, do not change! diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index cd5e4fd26..a1939a551 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.8.9 + 1.9.0 The NEORV32 RISC-V Processor