From b08a158c362b7d86de90c334f7de22ac2921c4fe Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 14 Jan 2022 05:52:17 +0100 Subject: [PATCH 1/4] [sw/lib] minor comment edits --- sw/lib/include/neorv32.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sw/lib/include/neorv32.h b/sw/lib/include/neorv32.h index 0fc3926a1..3a6d214fa 100644 --- a/sw/lib/include/neorv32.h +++ b/sw/lib/include/neorv32.h @@ -1165,8 +1165,8 @@ enum NEORV32_WDT_CTRL_enum { /**@{*/ /** GPIO module prototype */ typedef struct __attribute__((packed,aligned(4))) { - const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit */ - const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit */ + const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit, read-only */ + const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit, read-only */ uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */ uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */ } neorv32_gpio_t; @@ -1234,7 +1234,7 @@ enum NEORV32_NEOLED_CTRL_enum { * @name IO Device: System Configuration Information Memory (SYSINFO) **************************************************************************/ /**@{*/ -/** SYSINFO module prototype */ +/** SYSINFO module prototype - whole module is read-only */ typedef struct __attribute__((packed,aligned(4))) { const uint32_t CLK; /**< offset 0: clock speed in Hz */ const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */ From 8303255765778151be839d577ded740a29f82c0f Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 14 Jan 2022 05:53:12 +0100 Subject: [PATCH 2/4] [rtl/core] GPIO.input is read-only Any write access to the INPUT register will raise a bus exception. --- rtl/core/neorv32_gpio.vhd | 15 +++++++++------ rtl/core/neorv32_package.vhd | 3 ++- rtl/core/neorv32_top.vhd | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/rtl/core/neorv32_gpio.vhd b/rtl/core/neorv32_gpio.vhd index db6dbe3c1..21fdd578d 100644 --- a/rtl/core/neorv32_gpio.vhd +++ b/rtl/core/neorv32_gpio.vhd @@ -1,11 +1,12 @@ -- ################################################################################################# -- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> # -- # ********************************************************************************************* # --- # 64-bit general purpose parallel input & output port unit. # +-- # 64-bit general purpose parallel input & output port unit. Input/outputs are split into two # +-- # 32-bit memory-mapped registers each. # -- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # @@ -51,6 +52,7 @@ entity neorv32_gpio is data_i : in std_ulogic_vector(31 downto 0); -- data in data_o : out std_ulogic_vector(31 downto 0); -- data out ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error -- parallel io -- gpio_o : out std_ulogic_vector(63 downto 0); gpio_i : in std_ulogic_vector(63 downto 0) @@ -70,8 +72,8 @@ architecture neorv32_gpio_rtl of neorv32_gpio is signal rden : std_ulogic; -- read enable -- accessible regs -- - signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/- - signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w + signal din_hi, din_lo : std_ulogic_vector(31 downto 0); -- r/-: parallel input hi/lo + signal dout_hi, dout_lo : std_ulogic_vector(31 downto 0); -- r/w: parallel output hi/lo begin @@ -89,7 +91,8 @@ begin begin if rising_edge(clk_i) then -- bus handshake -- - ack_o <= wren or rden; + ack_o <= (wren and addr(3)) or rden; + err_o <= wren and (not addr(3)); -- INPUT registers are read only! -- write access -- if (wren = '1') then @@ -101,7 +104,7 @@ begin end if; end if; - -- input buffer -- + -- input buffer (prevent metastability) -- din_lo <= gpio_i(31 downto 00); din_hi <= gpio_i(63 downto 32); diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 617eb999b..2ea74f6e0 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -64,7 +64,7 @@ package neorv32_package is -- Architecture Constants (do not modify!) ------------------------------------------------ -- ------------------------------------------------------------------------------------------- constant data_width_c : natural := 32; -- native data path width - do not change! - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060508"; -- no touchy! + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060509"; -- no touchy! constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! -- Check if we're inside the Matrix ------------------------------------------------------- @@ -1638,6 +1638,7 @@ package neorv32_package is data_i : in std_ulogic_vector(31 downto 0); -- data in data_o : out std_ulogic_vector(31 downto 0); -- data out ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error -- parallel io -- gpio_o : out std_ulogic_vector(63 downto 0); gpio_i : in std_ulogic_vector(63 downto 0) diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index d85765c32..37d873f9d 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -1000,11 +1000,11 @@ begin data_i => p_bus.wdata, -- data in data_o => resp_bus(RESP_GPIO).rdata, -- data out ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge + err_o => resp_bus(RESP_GPIO).err, -- transfer error -- parallel io -- gpio_o => gpio_o, gpio_i => gpio_i ); - resp_bus(RESP_GPIO).err <= '0'; -- no access error possible end generate; neorv32_gpio_inst_false: From c5c630de396c308f9ace36a5790af4ccc45c0f86 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 14 Jan 2022 06:01:12 +0100 Subject: [PATCH 3/4] [docs/datasheet] GPIO: updated r/w capabilities --- docs/datasheet/soc_gpio.adoc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/docs/datasheet/soc_gpio.adoc b/docs/datasheet/soc_gpio.adoc index 7e81e0820..c008ab98c 100644 --- a/docs/datasheet/soc_gpio.adoc +++ b/docs/datasheet/soc_gpio.adoc @@ -19,20 +19,25 @@ output port. These ports can be used chip-externally (for example to drive statu or chip-internally to provide control signals for other IP modules. The component is disabled for implementation when the _IO_GPIO_EN_ generic is set _false_. In this case the GPIO output port `gpio_o` is tied to all-zero. -.Access atomicity +.Access Atomicity [NOTE] The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot be performed within a single clock cycle. +.INPUT is read-only +[NOTE] +Write accesses to the `NEORV32_GPIO.INPUT_LO` and `NEORV32_GPIO.INPUT_HI` registers will raise a store bus +error exception. The BUSKEEPER will indicate a "DEVICE_ERR" in this case. + .GPIO unit register map (`struct NEORV32_GPIO`) [cols="<2,<2,^1,^1,<6"] [options="header",grid="rows"] |======================= -| Address | Name [C] | Bit(s) | R/W | Function -| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0 (write accesses are ignored) -| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32 (write accesses are ignored) +| Address | Name [C] | Bit(s) | R/W | Function +| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0 +| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32 | `0xffffffc8` | `NEORV32_GPIO.OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0 | `0xffffffcc` | `NEORV32_GPIO.OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32 |======================= From 3dca6f741838cae061b992906270e8f180def6a4 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 14 Jan 2022 06:02:59 +0100 Subject: [PATCH 4/4] [CHANGELOG] added v1.6.5.9 --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 496d60f0a..03a1d117b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,6 +26,7 @@ defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/ | Date (*dd.mm.yyyy*) | Version | Comment | |:----------:|:-------:|:--------| +| 14.01.2022 | 1.6.5.9 | **GPIO** module: write accesses to the GPIO module's "input" registers will now raise a bus exception; [PR #255](https://github.com/stnolting/neorv32/pull/255) | | 11.01.2022 | 1.6.5.8 | minor rtl code clean-ups and edits in `rtl/core`; any write access to the SYSINFO module will now show up as a BUSKEEPER's "DEVICE_ERR" | | 08.01.2022 | 1.6.5.7 | :bug: fixed bug in BUSKEEPER's error type logic (introduced in version `1.6.5.4`); removed "unexpected ERR/ACK" error codes; [PR #253](https://github.com/stnolting/neorv32/pull/253) | | 07.01.2022 | 1.6.5.6 | :sparkles: **XIP & SPI: added high-speed SPI mode** (SPI clocking at half of the processor clock), see [PR #251](https://github.com/stnolting/neorv32/pull/251) |