{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":490753562,"defaultBranch":"main","name":"Analog-Signal-Interfacing-and-Filtering-using-FPGA-in-VHDL","ownerLogin":"sunnyiisc","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2022-05-10T15:19:48.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/47363228?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1653135012.700361","currentOid":""},"activityList":{"items":[],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":null,"startCursor":null,"endCursor":null}},"title":"Activity ยท sunnyiisc/Analog-Signal-Interfacing-and-Filtering-using-FPGA-in-VHDL"}